1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
9 struct mdp5_cfg_handler {
11 struct mdp5_cfg config;
14 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
15 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
17 static const struct mdp5_cfg_hw msm8x74v1_config = {
28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
29 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
30 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
41 .caps = MDP_PIPE_CAP_HFLIP |
49 .base = { 0x01d00, 0x02100, 0x02500 },
50 .caps = MDP_PIPE_CAP_HFLIP |
57 .base = { 0x02900, 0x02d00 },
58 .caps = MDP_PIPE_CAP_HFLIP |
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
66 { .id = 0, .pp = 0, .dspp = 0,
67 .caps = MDP_LM_CAP_DISPLAY, },
68 { .id = 1, .pp = 1, .dspp = 1,
69 .caps = MDP_LM_CAP_DISPLAY, },
70 { .id = 2, .pp = 2, .dspp = 2,
71 .caps = MDP_LM_CAP_DISPLAY, },
72 { .id = 3, .pp = -1, .dspp = -1,
73 .caps = MDP_LM_CAP_WB },
74 { .id = 4, .pp = -1, .dspp = -1,
75 .caps = MDP_LM_CAP_WB },
83 .base = { 0x04500, 0x04900, 0x04d00 },
87 .base = { 0x21a00, 0x21b00, 0x21c00 },
90 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
99 .ab_inefficiency = 200,
100 .ib_inefficiency = 120,
101 .clk_inefficiency = 125
103 .max_clk = 200000000,
106 static const struct mdp5_cfg_hw msm8x74v2_config = {
110 .caps = MDP_CAP_SMP |
117 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
118 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
119 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
124 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
125 .flush_hw_mask = 0x0003ffff,
129 .base = { 0x01100, 0x01500, 0x01900 },
130 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
131 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
132 MDP_PIPE_CAP_DECIMATION,
136 .base = { 0x01d00, 0x02100, 0x02500 },
137 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
138 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
142 .base = { 0x02900, 0x02d00 },
143 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
147 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
149 { .id = 0, .pp = 0, .dspp = 0,
150 .caps = MDP_LM_CAP_DISPLAY, },
151 { .id = 1, .pp = 1, .dspp = 1,
152 .caps = MDP_LM_CAP_DISPLAY, },
153 { .id = 2, .pp = 2, .dspp = 2,
154 .caps = MDP_LM_CAP_DISPLAY, },
155 { .id = 3, .pp = -1, .dspp = -1,
156 .caps = MDP_LM_CAP_WB, },
157 { .id = 4, .pp = -1, .dspp = -1,
158 .caps = MDP_LM_CAP_WB, },
162 .max_height = 0xFFFF,
166 .base = { 0x04500, 0x04900, 0x04d00 },
170 .base = { 0x13000, 0x13200 },
174 .base = { 0x12c00, 0x12d00, 0x12e00 },
177 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
186 .ab_inefficiency = 200,
187 .ib_inefficiency = 120,
188 .clk_inefficiency = 125
190 .max_clk = 320000000,
193 static const struct mdp5_cfg_hw apq8084_config = {
197 .caps = MDP_CAP_SMP |
205 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
206 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
207 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
208 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
209 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
211 .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
213 /* Two SMP blocks are statically tied to RGB pipes: */
214 [16] = 2, [17] = 2, [18] = 2, [22] = 2,
219 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
220 .flush_hw_mask = 0x003fffff,
224 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
225 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
226 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
227 MDP_PIPE_CAP_DECIMATION,
231 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
232 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
233 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
237 .base = { 0x03100, 0x03500 },
238 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
242 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
244 { .id = 0, .pp = 0, .dspp = 0,
245 .caps = MDP_LM_CAP_DISPLAY |
247 { .id = 1, .pp = 1, .dspp = 1,
248 .caps = MDP_LM_CAP_DISPLAY, },
249 { .id = 2, .pp = 2, .dspp = 2,
250 .caps = MDP_LM_CAP_DISPLAY |
252 { .id = 3, .pp = -1, .dspp = -1,
253 .caps = MDP_LM_CAP_WB, },
254 { .id = 4, .pp = -1, .dspp = -1,
255 .caps = MDP_LM_CAP_WB, },
256 { .id = 5, .pp = 3, .dspp = 3,
257 .caps = MDP_LM_CAP_DISPLAY, },
261 .max_height = 0xFFFF,
265 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
270 .base = { 0x13400, 0x13600, 0x13800 },
274 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
277 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
286 .ab_inefficiency = 200,
287 .ib_inefficiency = 120,
288 .clk_inefficiency = 105
290 .max_clk = 320000000,
293 static const struct mdp5_cfg_hw msm8x16_config = {
298 .caps = MDP_CAP_SMP |
305 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
306 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
311 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
312 .flush_hw_mask = 0x4003ffff,
317 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
318 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
319 MDP_PIPE_CAP_DECIMATION,
323 .base = { 0x14000, 0x16000 },
324 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
325 MDP_PIPE_CAP_DECIMATION,
330 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
333 .count = 2, /* LM0 and LM3 */
334 .base = { 0x44000, 0x47000 },
336 { .id = 0, .pp = 0, .dspp = 0,
337 .caps = MDP_LM_CAP_DISPLAY, },
338 { .id = 3, .pp = -1, .dspp = -1,
339 .caps = MDP_LM_CAP_WB },
343 .max_height = 0xFFFF,
351 .base = { 0x00000, 0x6a800 },
358 .ab_inefficiency = 100,
359 .ib_inefficiency = 200,
360 .clk_inefficiency = 105
362 .max_clk = 320000000,
365 static const struct mdp5_cfg_hw msm8x36_config = {
370 .caps = MDP_CAP_SMP |
377 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
378 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
383 .base = { 0x01000, 0x01200, 0x01400 },
384 .flush_hw_mask = 0x4003ffff,
389 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
390 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
391 MDP_PIPE_CAP_DECIMATION,
395 .base = { 0x14000, 0x16000 },
396 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
397 MDP_PIPE_CAP_DECIMATION,
402 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
406 .base = { 0x44000, 0x47000 },
408 { .id = 0, .pp = 0, .dspp = 0,
409 .caps = MDP_LM_CAP_DISPLAY, },
410 { .id = 1, .pp = -1, .dspp = -1,
411 .caps = MDP_LM_CAP_WB, },
415 .max_height = 0xFFFF,
430 .base = { 0x00000, 0x6a800, 0x6b000 },
438 .ab_inefficiency = 100,
439 .ib_inefficiency = 200,
440 .clk_inefficiency = 105
442 .max_clk = 366670000,
445 static const struct mdp5_cfg_hw msm8x94_config = {
449 .caps = MDP_CAP_SMP |
457 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
458 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
459 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
460 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
461 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
463 .reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
465 [1] = 1, [4] = 1, [7] = 1, [19] = 1,
466 [16] = 5, [17] = 5, [18] = 5, [22] = 5,
471 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
472 .flush_hw_mask = 0xf0ffffff,
476 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
477 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
478 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
479 MDP_PIPE_CAP_DECIMATION,
483 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
484 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
485 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
489 .base = { 0x24000, 0x26000 },
490 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
494 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
496 { .id = 0, .pp = 0, .dspp = 0,
497 .caps = MDP_LM_CAP_DISPLAY |
499 { .id = 1, .pp = 1, .dspp = 1,
500 .caps = MDP_LM_CAP_DISPLAY, },
501 { .id = 2, .pp = 2, .dspp = 2,
502 .caps = MDP_LM_CAP_DISPLAY |
504 { .id = 3, .pp = -1, .dspp = -1,
505 .caps = MDP_LM_CAP_WB, },
506 { .id = 4, .pp = -1, .dspp = -1,
507 .caps = MDP_LM_CAP_WB, },
508 { .id = 5, .pp = 3, .dspp = 3,
509 .caps = MDP_LM_CAP_DISPLAY, },
513 .max_height = 0xFFFF,
517 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
522 .base = { 0x78000, 0x78800, 0x79000 },
526 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
529 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
538 .ab_inefficiency = 100,
539 .ib_inefficiency = 100,
540 .clk_inefficiency = 105
542 .max_clk = 400000000,
545 static const struct mdp5_cfg_hw msm8x96_config = {
549 .caps = MDP_CAP_DSC |
556 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
557 .flush_hw_mask = 0xf4ffffff,
561 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
562 .caps = MDP_PIPE_CAP_HFLIP |
566 MDP_PIPE_CAP_DECIMATION |
567 MDP_PIPE_CAP_SW_PIX_EXT |
572 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
573 .caps = MDP_PIPE_CAP_HFLIP |
576 MDP_PIPE_CAP_DECIMATION |
577 MDP_PIPE_CAP_SW_PIX_EXT |
582 .base = { 0x24000, 0x26000 },
583 .caps = MDP_PIPE_CAP_HFLIP |
585 MDP_PIPE_CAP_SW_PIX_EXT |
590 .base = { 0x34000, 0x36000 },
591 .caps = MDP_PIPE_CAP_HFLIP |
593 MDP_PIPE_CAP_SW_PIX_EXT |
594 MDP_PIPE_CAP_CURSOR |
600 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
602 { .id = 0, .pp = 0, .dspp = 0,
603 .caps = MDP_LM_CAP_DISPLAY |
605 { .id = 1, .pp = 1, .dspp = 1,
606 .caps = MDP_LM_CAP_DISPLAY, },
607 { .id = 2, .pp = 2, .dspp = -1,
608 .caps = MDP_LM_CAP_DISPLAY |
610 { .id = 3, .pp = -1, .dspp = -1,
611 .caps = MDP_LM_CAP_WB, },
612 { .id = 4, .pp = -1, .dspp = -1,
613 .caps = MDP_LM_CAP_WB, },
614 { .id = 5, .pp = 3, .dspp = -1,
615 .caps = MDP_LM_CAP_DISPLAY, },
619 .max_height = 0xFFFF,
623 .base = { 0x54000, 0x56000 },
627 .base = { 0x78000, 0x78800, 0x79000 },
631 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
639 .base = { 0x80000, 0x80400 },
642 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
651 .ab_inefficiency = 100,
652 .ib_inefficiency = 200,
653 .clk_inefficiency = 105
655 .max_clk = 412500000,
658 const struct mdp5_cfg_hw msm8x76_config = {
662 .caps = MDP_CAP_SMP |
669 .base = { 0x01000, 0x01200, 0x01400 },
670 .flush_hw_mask = 0xffffffff,
676 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
678 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
683 .base = { 0x04000, 0x06000 },
684 .caps = MDP_PIPE_CAP_HFLIP |
688 MDP_PIPE_CAP_DECIMATION |
689 MDP_PIPE_CAP_SW_PIX_EXT |
694 .base = { 0x14000, 0x16000 },
695 .caps = MDP_PIPE_CAP_HFLIP |
697 MDP_PIPE_CAP_DECIMATION |
698 MDP_PIPE_CAP_SW_PIX_EXT |
704 .caps = MDP_PIPE_CAP_HFLIP |
706 MDP_PIPE_CAP_SW_PIX_EXT |
712 .caps = MDP_PIPE_CAP_HFLIP |
714 MDP_PIPE_CAP_SW_PIX_EXT |
715 MDP_PIPE_CAP_CURSOR |
720 .base = { 0x44000, 0x45000 },
722 { .id = 0, .pp = 0, .dspp = 0,
723 .caps = MDP_LM_CAP_DISPLAY, },
724 { .id = 1, .pp = -1, .dspp = -1,
725 .caps = MDP_LM_CAP_WB },
729 .max_height = 0xFFFF,
738 .base = { 0x70000, 0x70800, 0x72000 },
742 .base = { 0x80000, 0x80400 },
745 .base = { 0x6a000, 0x6a800, 0x6b000 },
752 .max_clk = 360000000,
755 static const struct mdp5_cfg_hw msm8917_config = {
763 .base = { 0x01000, 0x01200, 0x01400 },
764 .flush_hw_mask = 0xffffffff,
769 .caps = MDP_PIPE_CAP_HFLIP |
773 MDP_PIPE_CAP_DECIMATION |
774 MDP_PIPE_CAP_SW_PIX_EXT |
779 .base = { 0x14000, 0x16000 },
780 .caps = MDP_PIPE_CAP_HFLIP |
782 MDP_PIPE_CAP_DECIMATION |
783 MDP_PIPE_CAP_SW_PIX_EXT |
789 .caps = MDP_PIPE_CAP_HFLIP |
791 MDP_PIPE_CAP_SW_PIX_EXT |
797 .caps = MDP_PIPE_CAP_HFLIP |
799 MDP_PIPE_CAP_SW_PIX_EXT |
800 MDP_PIPE_CAP_CURSOR |
806 .base = { 0x44000, 0x45000 },
808 { .id = 0, .pp = 0, .dspp = 0,
809 .caps = MDP_LM_CAP_DISPLAY, },
810 { .id = 1, .pp = -1, .dspp = -1,
811 .caps = MDP_LM_CAP_WB },
815 .max_height = 0xFFFF,
831 .base = { 0x6a000, 0x6a800 },
837 .max_clk = 320000000,
840 static const struct mdp5_cfg_hw msm8998_config = {
844 .caps = MDP_CAP_DSC |
851 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
852 .flush_hw_mask = 0xf7ffffff,
856 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
857 .caps = MDP_PIPE_CAP_HFLIP |
861 MDP_PIPE_CAP_DECIMATION |
862 MDP_PIPE_CAP_SW_PIX_EXT |
867 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
868 .caps = MDP_PIPE_CAP_HFLIP |
871 MDP_PIPE_CAP_DECIMATION |
872 MDP_PIPE_CAP_SW_PIX_EXT |
876 .count = 2, /* driver supports max of 2 currently */
877 .base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
878 .caps = MDP_PIPE_CAP_HFLIP |
880 MDP_PIPE_CAP_SW_PIX_EXT |
885 .base = { 0x34000, 0x36000 },
886 .caps = MDP_PIPE_CAP_HFLIP |
888 MDP_PIPE_CAP_SW_PIX_EXT |
889 MDP_PIPE_CAP_CURSOR |
895 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
897 { .id = 0, .pp = 0, .dspp = 0,
898 .caps = MDP_LM_CAP_DISPLAY |
900 { .id = 1, .pp = 1, .dspp = 1,
901 .caps = MDP_LM_CAP_DISPLAY, },
902 { .id = 2, .pp = 2, .dspp = -1,
903 .caps = MDP_LM_CAP_DISPLAY |
905 { .id = 3, .pp = -1, .dspp = -1,
906 .caps = MDP_LM_CAP_WB, },
907 { .id = 4, .pp = -1, .dspp = -1,
908 .caps = MDP_LM_CAP_WB, },
909 { .id = 5, .pp = 3, .dspp = -1,
910 .caps = MDP_LM_CAP_DISPLAY, },
914 .max_height = 0xFFFF,
918 .base = { 0x54000, 0x56000 },
922 .base = { 0x78000, 0x78800, 0x79000 },
926 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
934 .base = { 0x80000, 0x80400 },
937 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
945 .max_clk = 412500000,
948 static const struct mdp5_cfg_hw sdm630_config = {
952 .caps = MDP_CAP_CDM |
958 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
959 .flush_hw_mask = 0xf4ffffff,
964 .caps = MDP_PIPE_CAP_HFLIP |
968 MDP_PIPE_CAP_DECIMATION |
969 MDP_PIPE_CAP_SW_PIX_EXT |
974 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
975 .caps = MDP_PIPE_CAP_HFLIP |
978 MDP_PIPE_CAP_DECIMATION |
979 MDP_PIPE_CAP_SW_PIX_EXT |
983 .count = 2, /* driver supports max of 2 currently */
984 .base = { 0x24000, 0x26000, 0x28000 },
985 .caps = MDP_PIPE_CAP_HFLIP |
987 MDP_PIPE_CAP_SW_PIX_EXT |
993 .caps = MDP_PIPE_CAP_HFLIP |
995 MDP_PIPE_CAP_SW_PIX_EXT |
996 MDP_PIPE_CAP_CURSOR |
1002 .base = { 0x44000, 0x46000 },
1004 { .id = 0, .pp = 0, .dspp = 0,
1005 .caps = MDP_LM_CAP_DISPLAY |
1007 { .id = 1, .pp = 1, .dspp = -1,
1008 .caps = MDP_LM_CAP_WB, },
1012 .max_height = 0xFFFF,
1016 .base = { 0x54000 },
1020 .base = { 0x78000, 0x78800 },
1024 .base = { 0x70000, 0x71000, 0x72000 },
1028 .base = { 0x79200 },
1031 .base = { 0x6a000, 0x6a800 },
1033 [0] = INTF_DISABLED,
1037 .max_clk = 412500000,
1040 static const struct mdp5_cfg_hw sdm660_config = {
1044 .caps = MDP_CAP_DSC |
1051 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1052 .flush_hw_mask = 0xf4ffffff,
1056 .base = { 0x04000, 0x6000 },
1057 .caps = MDP_PIPE_CAP_HFLIP |
1058 MDP_PIPE_CAP_VFLIP |
1059 MDP_PIPE_CAP_SCALE |
1061 MDP_PIPE_CAP_DECIMATION |
1062 MDP_PIPE_CAP_SW_PIX_EXT |
1067 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1068 .caps = MDP_PIPE_CAP_HFLIP |
1069 MDP_PIPE_CAP_VFLIP |
1070 MDP_PIPE_CAP_SCALE |
1071 MDP_PIPE_CAP_DECIMATION |
1072 MDP_PIPE_CAP_SW_PIX_EXT |
1076 .count = 2, /* driver supports max of 2 currently */
1077 .base = { 0x24000, 0x26000, 0x28000 },
1078 .caps = MDP_PIPE_CAP_HFLIP |
1079 MDP_PIPE_CAP_VFLIP |
1080 MDP_PIPE_CAP_SW_PIX_EXT |
1085 .base = { 0x34000 },
1086 .caps = MDP_PIPE_CAP_HFLIP |
1087 MDP_PIPE_CAP_VFLIP |
1088 MDP_PIPE_CAP_SW_PIX_EXT |
1089 MDP_PIPE_CAP_CURSOR |
1095 .base = { 0x44000, 0x45000, 0x46000, 0x49000 },
1097 { .id = 0, .pp = 0, .dspp = 0,
1098 .caps = MDP_LM_CAP_DISPLAY |
1100 { .id = 1, .pp = 1, .dspp = 1,
1101 .caps = MDP_LM_CAP_DISPLAY, },
1102 { .id = 2, .pp = 2, .dspp = -1,
1103 .caps = MDP_LM_CAP_DISPLAY |
1105 { .id = 3, .pp = 3, .dspp = -1,
1106 .caps = MDP_LM_CAP_WB, },
1110 .max_height = 0xFFFF,
1114 .base = { 0x54000, 0x56000 },
1118 .base = { 0x78000, 0x78800 },
1122 .base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 },
1126 .base = { 0x79200 },
1130 .base = { 0x80000, 0x80400 },
1133 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 },
1135 [0] = INTF_DISABLED,
1141 .max_clk = 412500000,
1144 static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
1145 { .revision = 0, .config = { .hw = &msm8x74v1_config } },
1146 { .revision = 2, .config = { .hw = &msm8x74v2_config } },
1147 { .revision = 3, .config = { .hw = &apq8084_config } },
1148 { .revision = 6, .config = { .hw = &msm8x16_config } },
1149 { .revision = 8, .config = { .hw = &msm8x36_config } },
1150 { .revision = 9, .config = { .hw = &msm8x94_config } },
1151 { .revision = 7, .config = { .hw = &msm8x96_config } },
1152 { .revision = 11, .config = { .hw = &msm8x76_config } },
1153 { .revision = 15, .config = { .hw = &msm8917_config } },
1156 static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
1157 { .revision = 0, .config = { .hw = &msm8998_config } },
1158 { .revision = 2, .config = { .hw = &sdm660_config } },
1159 { .revision = 3, .config = { .hw = &sdm630_config } },
1162 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
1164 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
1166 return cfg_handler->config.hw;
1169 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
1171 return &cfg_handler->config;
1174 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
1176 return cfg_handler->revision;
1179 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
1184 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
1185 uint32_t major, uint32_t minor)
1187 struct drm_device *dev = mdp5_kms->dev;
1188 struct platform_device *pdev = to_platform_device(dev->dev);
1189 struct mdp5_cfg_handler *cfg_handler;
1190 const struct mdp5_cfg_handler *cfg_handlers;
1191 struct mdp5_cfg_platform *pconfig;
1192 int i, ret = 0, num_handlers;
1194 cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
1195 if (unlikely(!cfg_handler)) {
1202 cfg_handlers = cfg_handlers_v1;
1203 num_handlers = ARRAY_SIZE(cfg_handlers_v1);
1206 cfg_handlers = cfg_handlers_v3;
1207 num_handlers = ARRAY_SIZE(cfg_handlers_v3);
1210 DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
1216 /* only after mdp5_cfg global pointer's init can we access the hw */
1217 for (i = 0; i < num_handlers; i++) {
1218 if (cfg_handlers[i].revision != minor)
1220 mdp5_cfg = cfg_handlers[i].config.hw;
1224 if (unlikely(!mdp5_cfg)) {
1225 DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
1231 cfg_handler->revision = minor;
1232 cfg_handler->config.hw = mdp5_cfg;
1234 pconfig = mdp5_get_config(pdev);
1235 memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
1237 DBG("MDP5: %s hw config selected", mdp5_cfg->name);
1243 mdp5_cfg_destroy(cfg_handler);
1245 return ERR_PTR(ret);
1248 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
1250 static struct mdp5_cfg_platform config = {};
1252 config.iommu = iommu_domain_alloc(&platform_bus_type);