drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

   1 /*
   2  * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
  20
  21 #include <linux/debugfs.h>
  22 #include <linux/dma-buf.h>
  23
  24 #include <drm/drm_atomic_uapi.h>
  25
  26 #include "msm_drv.h"
  27 #include "dpu_kms.h"
  28 #include "dpu_formats.h"
  29 #include "dpu_hw_sspp.h"
  30 #include "dpu_hw_catalog_format.h"
  31 #include "dpu_trace.h"
  32 #include "dpu_crtc.h"
  33 #include "dpu_vbif.h"
  34 #include "dpu_plane.h"
  35
  36 #define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\
  37                 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  38
  39 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
  40                 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  41
  42 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  43 #define PHASE_STEP_SHIFT        21
  44 #define PHASE_STEP_UNIT_SCALE   ((int) (1 << PHASE_STEP_SHIFT))
  45 #define PHASE_RESIDUAL          15
  46
  47 #define SHARP_STRENGTH_DEFAULT  32
  48 #define SHARP_EDGE_THR_DEFAULT  112
  49 #define SHARP_SMOOTH_THR_DEFAULT        8
  50 #define SHARP_NOISE_THR_DEFAULT 2
  51
  52 #define DPU_NAME_SIZE  12
  53
  54 #define DPU_PLANE_COLOR_FILL_FLAG       BIT(31)
  55 #define DPU_ZPOS_MAX 255
  56
  57 /* multirect rect index */
  58 enum {
  59         R0,
  60         R1,
  61         R_MAX
  62 };
  63
  64 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
  65 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
  66
  67 #define DEFAULT_REFRESH_RATE    60
  68
  69 /**
  70  * enum dpu_plane_qos - Different qos configurations for each pipe
  71  *
  72  * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  73  * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  74  *      this configuration is mutually exclusive from VBLANK_CTRL.
  75  * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  76  */
  77 enum dpu_plane_qos {
  78         DPU_PLANE_QOS_VBLANK_CTRL = BIT(0),
  79         DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  80         DPU_PLANE_QOS_PANIC_CTRL = BIT(2),
  81 };
  82
  83 /*
  84  * struct dpu_plane - local dpu plane structure
  85  * @aspace: address space pointer
  86  * @csc_ptr: Points to dpu_csc_cfg structure to use for current
  87  * @mplane_list: List of multirect planes of the same pipe
  88  * @catalog: Points to dpu catalog structure
  89  * @revalidate: force revalidation of all the plane properties
  90  */
  91 struct dpu_plane {
  92         struct drm_plane base;
  93
  94         struct mutex lock;
  95
  96         enum dpu_sspp pipe;
  97         uint32_t features;      /* capabilities from catalog */
  98
  99         struct dpu_hw_pipe *pipe_hw;
 100         struct dpu_hw_pipe_cfg pipe_cfg;
 101         struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
 102         uint32_t color_fill;
 103         bool is_error;
 104         bool is_rt_pipe;
 105         bool is_virtual;
 106         struct list_head mplane_list;
 107         struct dpu_mdss_cfg *catalog;
 108
 109         struct dpu_csc_cfg *csc_ptr;
 110
 111         const struct dpu_sspp_sub_blks *pipe_sblk;
 112         char pipe_name[DPU_NAME_SIZE];
 113
 114         /* debugfs related stuff */
 115         struct dentry *debugfs_root;
 116         struct dpu_debugfs_regset32 debugfs_src;
 117         struct dpu_debugfs_regset32 debugfs_scaler;
 118         struct dpu_debugfs_regset32 debugfs_csc;
 119         bool debugfs_default_scale;
 120 };
 121
 122 static const uint64_t supported_format_modifiers[] = {
 123         DRM_FORMAT_MOD_QCOM_COMPRESSED,
 124         DRM_FORMAT_MOD_LINEAR,
 125         DRM_FORMAT_MOD_INVALID
 126 };
 127
 128 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
 129
 130 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
 131 {
 132         struct msm_drm_private *priv = plane->dev->dev_private;
 133
 134         return to_dpu_kms(priv->kms);
 135 }
 136
 137 /**
 138  * _dpu_plane_calc_fill_level - calculate fill level of the given source format
 139  * @plane:              Pointer to drm plane
 140  * @fmt:                Pointer to source buffer format
 141  * @src_wdith:          width of source buffer
 142  * Return: fill level corresponding to the source buffer/format or 0 if error
 143  */
 144 static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
 145                 const struct dpu_format *fmt, u32 src_width)
 146 {
 147         struct dpu_plane *pdpu, *tmp;
 148         struct dpu_plane_state *pstate;
 149         u32 fixed_buff_size;
 150         u32 total_fl;
 151
 152         if (!fmt || !plane->state || !src_width || !fmt->bpp) {
 153                 DPU_ERROR("invalid arguments\n");
 154                 return 0;
 155         }
 156
 157         pdpu = to_dpu_plane(plane);
 158         pstate = to_dpu_plane_state(plane->state);
 159         fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size;
 160
 161         list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
 162                 if (!tmp->base.state->visible)
 163                         continue;
 164                 DPU_DEBUG("plane%d/%d src_width:%d/%d\n",
 165                                 pdpu->base.base.id, tmp->base.base.id,
 166                                 src_width,
 167                                 drm_rect_width(&tmp->pipe_cfg.src_rect));
 168                 src_width = max_t(u32, src_width,
 169                                   drm_rect_width(&tmp->pipe_cfg.src_rect));
 170         }
 171
 172         if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
 173                 if (fmt->chroma_sample == DPU_CHROMA_420) {
 174                         /* NV12 */
 175                         total_fl = (fixed_buff_size / 2) /
 176                                 ((src_width + 32) * fmt->bpp);
 177                 } else {
 178                         /* non NV12 */
 179                         total_fl = (fixed_buff_size / 2) * 2 /
 180                                 ((src_width + 32) * fmt->bpp);
 181                 }
 182         } else {
 183                 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
 184                         total_fl = (fixed_buff_size / 2) * 2 /
 185                                 ((src_width + 32) * fmt->bpp);
 186                 } else {
 187                         total_fl = (fixed_buff_size) * 2 /
 188                                 ((src_width + 32) * fmt->bpp);
 189                 }
 190         }
 191
 192         DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
 193                         plane->base.id, pdpu->pipe - SSPP_VIG0,
 194                         (char *)&fmt->base.pixel_format,
 195                         src_width, total_fl);
 196
 197         return total_fl;
 198 }
 199
 200 /**
 201  * _dpu_plane_get_qos_lut - get LUT mapping based on fill level
 202  * @tbl:                Pointer to LUT table
 203  * @total_fl:           fill level
 204  * Return: LUT setting corresponding to the fill level
 205  */
 206 static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
 207                 u32 total_fl)
 208 {
 209         int i;
 210
 211         if (!tbl || !tbl->nentry || !tbl->entries)
 212                 return 0;
 213
 214         for (i = 0; i < tbl->nentry; i++)
 215                 if (total_fl <= tbl->entries[i].fl)
 216                         return tbl->entries[i].lut;
 217
 218         /* if last fl is zero, use as default */
 219         if (!tbl->entries[i-1].fl)
 220                 return tbl->entries[i-1].lut;
 221
 222         return 0;
 223 }
 224
 225 /**
 226  * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
 227  * @plane:              Pointer to drm plane
 228  * @fb:                 Pointer to framebuffer associated with the given plane
 229  */
 230 static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
 231                 struct drm_framebuffer *fb)
 232 {
 233         struct dpu_plane *pdpu = to_dpu_plane(plane);
 234         const struct dpu_format *fmt = NULL;
 235         u64 qos_lut;
 236         u32 total_fl = 0, lut_usage;
 237
 238         if (!pdpu->is_rt_pipe) {
 239                 lut_usage = DPU_QOS_LUT_USAGE_NRT;
 240         } else {
 241                 fmt = dpu_get_dpu_format_ext(
 242                                 fb->format->format,
 243                                 fb->modifier);
 244                 total_fl = _dpu_plane_calc_fill_level(plane, fmt,
 245                                 drm_rect_width(&pdpu->pipe_cfg.src_rect));
 246
 247                 if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
 248                         lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
 249                 else
 250                         lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
 251         }
 252
 253         qos_lut = _dpu_plane_get_qos_lut(
 254                         &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
 255
 256         pdpu->pipe_qos_cfg.creq_lut = qos_lut;
 257
 258         trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
 259                         (fmt) ? fmt->base.pixel_format : 0,
 260                         pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
 261
 262         DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
 263                         plane->base.id,
 264                         pdpu->pipe - SSPP_VIG0,
 265                         fmt ? (char *)&fmt->base.pixel_format : NULL,
 266                         pdpu->is_rt_pipe, total_fl, qos_lut);
 267
 268         pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg);
 269 }
 270
 271 /**
 272  * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane
 273  * @plane:              Pointer to drm plane
 274  * @fb:                 Pointer to framebuffer associated with the given plane
 275  */
 276 static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
 277                 struct drm_framebuffer *fb)
 278 {
 279         struct dpu_plane *pdpu = to_dpu_plane(plane);
 280         const struct dpu_format *fmt = NULL;
 281         u32 danger_lut, safe_lut;
 282
 283         if (!pdpu->is_rt_pipe) {
 284                 danger_lut = pdpu->catalog->perf.danger_lut_tbl
 285                                 [DPU_QOS_LUT_USAGE_NRT];
 286                 safe_lut = pdpu->catalog->perf.safe_lut_tbl
 287                                 [DPU_QOS_LUT_USAGE_NRT];
 288         } else {
 289                 fmt = dpu_get_dpu_format_ext(
 290                                 fb->format->format,
 291                                 fb->modifier);
 292
 293                 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) {
 294                         danger_lut = pdpu->catalog->perf.danger_lut_tbl
 295                                         [DPU_QOS_LUT_USAGE_LINEAR];
 296                         safe_lut = pdpu->catalog->perf.safe_lut_tbl
 297                                         [DPU_QOS_LUT_USAGE_LINEAR];
 298                 } else {
 299                         danger_lut = pdpu->catalog->perf.danger_lut_tbl
 300                                         [DPU_QOS_LUT_USAGE_MACROTILE];
 301                         safe_lut = pdpu->catalog->perf.safe_lut_tbl
 302                                         [DPU_QOS_LUT_USAGE_MACROTILE];
 303                 }
 304         }
 305
 306         pdpu->pipe_qos_cfg.danger_lut = danger_lut;
 307         pdpu->pipe_qos_cfg.safe_lut = safe_lut;
 308
 309         trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
 310                         (fmt) ? fmt->base.pixel_format : 0,
 311                         (fmt) ? fmt->fetch_mode : 0,
 312                         pdpu->pipe_qos_cfg.danger_lut,
 313                         pdpu->pipe_qos_cfg.safe_lut);
 314
 315         DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
 316                 plane->base.id,
 317                 pdpu->pipe - SSPP_VIG0,
 318                 fmt ? (char *)&fmt->base.pixel_format : NULL,
 319                 fmt ? fmt->fetch_mode : -1,
 320                 pdpu->pipe_qos_cfg.danger_lut,
 321                 pdpu->pipe_qos_cfg.safe_lut);
 322
 323         pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
 324                         &pdpu->pipe_qos_cfg);
 325 }
 326
 327 /**
 328  * _dpu_plane_set_qos_ctrl - set QoS control of the given plane
 329  * @plane:              Pointer to drm plane
 330  * @enable:             true to enable QoS control
 331  * @flags:              QoS control mode (enum dpu_plane_qos)
 332  */
 333 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
 334         bool enable, u32 flags)
 335 {
 336         struct dpu_plane *pdpu = to_dpu_plane(plane);
 337
 338         if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
 339                 pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
 340                 pdpu->pipe_qos_cfg.danger_vblank =
 341                                 pdpu->pipe_sblk->danger_vblank;
 342                 pdpu->pipe_qos_cfg.vblank_en = enable;
 343         }
 344
 345         if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) {
 346                 /* this feature overrules previous VBLANK_CTRL */
 347                 pdpu->pipe_qos_cfg.vblank_en = false;
 348                 pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
 349         }
 350
 351         if (flags & DPU_PLANE_QOS_PANIC_CTRL)
 352                 pdpu->pipe_qos_cfg.danger_safe_en = enable;
 353
 354         if (!pdpu->is_rt_pipe) {
 355                 pdpu->pipe_qos_cfg.vblank_en = false;
 356                 pdpu->pipe_qos_cfg.danger_safe_en = false;
 357         }
 358
 359         DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
 360                 plane->base.id,
 361                 pdpu->pipe - SSPP_VIG0,
 362                 pdpu->pipe_qos_cfg.danger_safe_en,
 363                 pdpu->pipe_qos_cfg.vblank_en,
 364                 pdpu->pipe_qos_cfg.creq_vblank,
 365                 pdpu->pipe_qos_cfg.danger_vblank,
 366                 pdpu->is_rt_pipe);
 367
 368         pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
 369                         &pdpu->pipe_qos_cfg);
 370 }
 371
 372 /**
 373  * _dpu_plane_set_ot_limit - set OT limit for the given plane
 374  * @plane:              Pointer to drm plane
 375  * @crtc:               Pointer to drm crtc
 376  */
 377 static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
 378                 struct drm_crtc *crtc)
 379 {
 380         struct dpu_plane *pdpu = to_dpu_plane(plane);
 381         struct dpu_vbif_set_ot_params ot_params;
 382         struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
 383
 384         memset(&ot_params, 0, sizeof(ot_params));
 385         ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
 386         ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
 387         ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
 388         ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
 389         ot_params.is_wfd = !pdpu->is_rt_pipe;
 390         ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
 391         ot_params.vbif_idx = VBIF_RT;
 392         ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
 393         ot_params.rd = true;
 394
 395         dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
 396 }
 397
 398 /**
 399  * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane
 400  * @plane:              Pointer to drm plane
 401  */
 402 static void _dpu_plane_set_qos_remap(struct drm_plane *plane)
 403 {
 404         struct dpu_plane *pdpu = to_dpu_plane(plane);
 405         struct dpu_vbif_set_qos_params qos_params;
 406         struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
 407
 408         memset(&qos_params, 0, sizeof(qos_params));
 409         qos_params.vbif_idx = VBIF_RT;
 410         qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl;
 411         qos_params.xin_id = pdpu->pipe_hw->cap->xin_id;
 412         qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0;
 413         qos_params.is_rt = pdpu->is_rt_pipe;
 414
 415         DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
 416                         plane->base.id, qos_params.num,
 417                         qos_params.vbif_idx,
 418                         qos_params.xin_id, qos_params.is_rt,
 419                         qos_params.clk_ctrl);
 420
 421         dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
 422 }
 423
 424 static void _dpu_plane_set_scanout(struct drm_plane *plane,
 425                 struct dpu_plane_state *pstate,
 426                 struct dpu_hw_pipe_cfg *pipe_cfg,
 427                 struct drm_framebuffer *fb)
 428 {
 429         struct dpu_plane *pdpu = to_dpu_plane(plane);
 430         struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
 431         struct msm_gem_address_space *aspace = kms->base.aspace;
 432         int ret;
 433
 434         ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout);
 435         if (ret == -EAGAIN)
 436                 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n");
 437         else if (ret)
 438                 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
 439         else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
 440                 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
 441                                             &pipe_cfg->layout,
 442                                             pstate->multirect_index);
 443                 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
 444                                                 pstate->multirect_index);
 445         }
 446 }
 447
 448 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
 449                 struct dpu_plane_state *pstate,
 450                 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
 451                 struct dpu_hw_scaler3_cfg *scale_cfg,
 452                 const struct dpu_format *fmt,
 453                 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
 454 {
 455         uint32_t i;
 456
 457         memset(scale_cfg, 0, sizeof(*scale_cfg));
 458         memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));
 459
 460         scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
 461                 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
 462         scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
 463                 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);
 464
 465
 466         scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] =
 467                 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v;
 468         scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] =
 469                 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h;
 470
 471         scale_cfg->phase_step_x[DPU_SSPP_COMP_2] =
 472                 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2];
 473         scale_cfg->phase_step_y[DPU_SSPP_COMP_2] =
 474                 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2];
 475
 476         scale_cfg->phase_step_x[DPU_SSPP_COMP_3] =
 477                 scale_cfg->phase_step_x[DPU_SSPP_COMP_0];
 478         scale_cfg->phase_step_y[DPU_SSPP_COMP_3] =
 479                 scale_cfg->phase_step_y[DPU_SSPP_COMP_0];
 480
 481         for (i = 0; i < DPU_MAX_PLANES; i++) {
 482                 scale_cfg->src_width[i] = src_w;
 483                 scale_cfg->src_height[i] = src_h;
 484                 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
 485                         scale_cfg->src_width[i] /= chroma_subsmpl_h;
 486                         scale_cfg->src_height[i] /= chroma_subsmpl_v;
 487                 }
 488                 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
 489                 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
 490                 pstate->pixel_ext.num_ext_pxls_top[i] =
 491                         scale_cfg->src_height[i];
 492                 pstate->pixel_ext.num_ext_pxls_left[i] =
 493                         scale_cfg->src_width[i];
 494         }
 495         if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
 496                 && (src_w == dst_w))
 497                 return;
 498
 499         scale_cfg->dst_width = dst_w;
 500         scale_cfg->dst_height = dst_h;
 501         scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL;
 502         scale_cfg->uv_filter_cfg = DPU_SCALE_BIL;
 503         scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL;
 504         scale_cfg->lut_flag = 0;
 505         scale_cfg->blend_cfg = 1;
 506         scale_cfg->enable = 1;
 507 }
 508
 509 static void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
 510 {
 511         static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
 512                 {
 513                         /* S15.16 format */
 514                         0x00012A00, 0x00000000, 0x00019880,
 515                         0x00012A00, 0xFFFF9B80, 0xFFFF3000,
 516                         0x00012A00, 0x00020480, 0x00000000,
 517                 },
 518                 /* signed bias */
 519                 { 0xfff0, 0xff80, 0xff80,},
 520                 { 0x0, 0x0, 0x0,},
 521                 /* unsigned clamp */
 522                 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
 523                 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
 524         };
 525         static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
 526                 {
 527                         /* S15.16 format */
 528                         0x00012A00, 0x00000000, 0x00019880,
 529                         0x00012A00, 0xFFFF9B80, 0xFFFF3000,
 530                         0x00012A00, 0x00020480, 0x00000000,
 531                         },
 532                 /* signed bias */
 533                 { 0xffc0, 0xfe00, 0xfe00,},
 534                 { 0x0, 0x0, 0x0,},
 535                 /* unsigned clamp */
 536                 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
 537                 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
 538         };
 539
 540         if (!pdpu) {
 541                 DPU_ERROR("invalid plane\n");
 542                 return;
 543         }
 544
 545         if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
 546                 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L;
 547         else
 548                 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L;
 549
 550         DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
 551                         pdpu->csc_ptr->csc_mv[0],
 552                         pdpu->csc_ptr->csc_mv[1],
 553                         pdpu->csc_ptr->csc_mv[2]);
 554 }
 555
 556 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
 557                 struct dpu_plane_state *pstate,
 558                 const struct dpu_format *fmt, bool color_fill)
 559 {
 560         uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
 561
 562         /* don't chroma subsample if decimating */
 563         chroma_subsmpl_h =
 564                 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
 565         chroma_subsmpl_v =
 566                 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
 567
 568         /* update scaler. calculate default config for QSEED3 */
 569         _dpu_plane_setup_scaler3(pdpu, pstate,
 570                         drm_rect_width(&pdpu->pipe_cfg.src_rect),
 571                         drm_rect_height(&pdpu->pipe_cfg.src_rect),
 572                         drm_rect_width(&pdpu->pipe_cfg.dst_rect),
 573                         drm_rect_height(&pdpu->pipe_cfg.dst_rect),
 574                         &pstate->scaler3_cfg, fmt,
 575                         chroma_subsmpl_h, chroma_subsmpl_v);
 576 }
 577
 578 /**
 579  * _dpu_plane_color_fill - enables color fill on plane
 580  * @pdpu:   Pointer to DPU plane object
 581  * @color:  RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
 582  * @alpha:  8-bit fill alpha value, 255 selects 100% alpha
 583  * Returns: 0 on success
 584  */
 585 static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
 586                 uint32_t color, uint32_t alpha)
 587 {
 588         const struct dpu_format *fmt;
 589         const struct drm_plane *plane = &pdpu->base;
 590         struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
 591
 592         DPU_DEBUG_PLANE(pdpu, "\n");
 593
 594         /*
 595          * select fill format to match user property expectation,
 596          * h/w only supports RGB variants
 597          */
 598         fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
 599
 600         /* update sspp */
 601         if (fmt && pdpu->pipe_hw->ops.setup_solidfill) {
 602                 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw,
 603                                 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
 604                                 pstate->multirect_index);
 605
 606                 /* override scaler/decimation if solid fill */
 607                 pdpu->pipe_cfg.src_rect.x1 = 0;
 608                 pdpu->pipe_cfg.src_rect.y1 = 0;
 609                 pdpu->pipe_cfg.src_rect.x2 =
 610                         drm_rect_width(&pdpu->pipe_cfg.dst_rect);
 611                 pdpu->pipe_cfg.src_rect.y2 =
 612                         drm_rect_height(&pdpu->pipe_cfg.dst_rect);
 613                 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true);
 614
 615                 if (pdpu->pipe_hw->ops.setup_format)
 616                         pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
 617                                         fmt, DPU_SSPP_SOLID_FILL,
 618                                         pstate->multirect_index);
 619
 620                 if (pdpu->pipe_hw->ops.setup_rects)
 621                         pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
 622                                         &pdpu->pipe_cfg,
 623                                         pstate->multirect_index);
 624
 625                 if (pdpu->pipe_hw->ops.setup_pe)
 626                         pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
 627                                         &pstate->pixel_ext);
 628
 629                 if (pdpu->pipe_hw->ops.setup_scaler &&
 630                                 pstate->multirect_index != DPU_SSPP_RECT_1)
 631                         pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
 632                                         &pdpu->pipe_cfg, &pstate->pixel_ext,
 633                                         &pstate->scaler3_cfg);
 634         }
 635
 636         return 0;
 637 }
 638
 639 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
 640 {
 641         struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
 642
 643         pstate->multirect_index = DPU_SSPP_RECT_SOLO;
 644         pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
 645 }
 646
 647 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
 648 {
 649         struct dpu_plane_state *pstate[R_MAX];
 650         const struct drm_plane_state *drm_state[R_MAX];
 651         struct drm_rect src[R_MAX], dst[R_MAX];
 652         struct dpu_plane *dpu_plane[R_MAX];
 653         const struct dpu_format *fmt[R_MAX];
 654         int i, buffer_lines;
 655         unsigned int max_tile_height = 1;
 656         bool parallel_fetch_qualified = true;
 657         bool has_tiled_rect = false;
 658
 659         for (i = 0; i < R_MAX; i++) {
 660                 const struct msm_format *msm_fmt;
 661
 662                 drm_state[i] = i ? plane->r1 : plane->r0;
 663                 msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
 664                 fmt[i] = to_dpu_format(msm_fmt);
 665
 666                 if (DPU_FORMAT_IS_UBWC(fmt[i])) {
 667                         has_tiled_rect = true;
 668                         if (fmt[i]->tile_height > max_tile_height)
 669                                 max_tile_height = fmt[i]->tile_height;
 670                 }
 671         }
 672
 673         for (i = 0; i < R_MAX; i++) {
 674                 int width_threshold;
 675
 676                 pstate[i] = to_dpu_plane_state(drm_state[i]);
 677                 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane);
 678
 679                 if (pstate[i] == NULL) {
 680                         DPU_ERROR("DPU plane state of plane id %d is NULL\n",
 681                                 drm_state[i]->plane->base.id);
 682                         return -EINVAL;
 683                 }
 684
 685                 src[i].x1 = drm_state[i]->src_x >> 16;
 686                 src[i].y1 = drm_state[i]->src_y >> 16;
 687                 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16);
 688                 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16);
 689
 690                 dst[i] = drm_plane_state_dest(drm_state[i]);
 691
 692                 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 ||
 693                     drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) {
 694                         DPU_ERROR_PLANE(dpu_plane[i],
 695                                 "scaling is not supported in multirect mode\n");
 696                         return -EINVAL;
 697                 }
 698
 699                 if (DPU_FORMAT_IS_YUV(fmt[i])) {
 700                         DPU_ERROR_PLANE(dpu_plane[i],
 701                                 "Unsupported format for multirect mode\n");
 702                         return -EINVAL;
 703                 }
 704
 705                 /**
 706                  * SSPP PD_MEM is split half - one for each RECT.
 707                  * Tiled formats need 5 lines of buffering while fetching
 708                  * whereas linear formats need only 2 lines.
 709                  * So we cannot support more than half of the supported SSPP
 710                  * width for tiled formats.
 711                  */
 712                 width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth;
 713                 if (has_tiled_rect)
 714                         width_threshold /= 2;
 715
 716                 if (parallel_fetch_qualified &&
 717                     drm_rect_width(&src[i]) > width_threshold)
 718                         parallel_fetch_qualified = false;
 719
 720         }
 721
 722         /* Validate RECT's and set the mode */
 723
 724         /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */
 725         if (parallel_fetch_qualified) {
 726                 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
 727                 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
 728
 729                 goto done;
 730         }
 731
 732         /* TIME_MX Mode */
 733         buffer_lines = 2 * max_tile_height;
 734
 735         if (dst[R1].y1 >= dst[R0].y2 + buffer_lines ||
 736             dst[R0].y1 >= dst[R1].y2 + buffer_lines) {
 737                 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
 738                 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
 739         } else {
 740                 DPU_ERROR(
 741                         "No multirect mode possible for the planes (%d - %d)\n",
 742                         drm_state[R0]->plane->base.id,
 743                         drm_state[R1]->plane->base.id);
 744                 return -EINVAL;
 745         }
 746
 747 done:
 748         if (dpu_plane[R0]->is_virtual) {
 749                 pstate[R0]->multirect_index = DPU_SSPP_RECT_1;
 750                 pstate[R1]->multirect_index = DPU_SSPP_RECT_0;
 751         } else {
 752                 pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
 753                 pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
 754         };
 755
 756         DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n",
 757                 pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
 758         DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n",
 759                 pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
 760         return 0;
 761 }
 762
 763 /**
 764  * dpu_plane_get_ctl_flush - get control flush for the given plane
 765  * @plane: Pointer to drm plane structure
 766  * @ctl: Pointer to hardware control driver
 767  * @flush_sspp: Pointer to sspp flush control word
 768  */
 769 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
 770                 u32 *flush_sspp)
 771 {
 772         *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane));
 773 }
 774
 775 static int dpu_plane_prepare_fb(struct drm_plane *plane,
 776                 struct drm_plane_state *new_state)
 777 {
 778         struct drm_framebuffer *fb = new_state->fb;
 779         struct dpu_plane *pdpu = to_dpu_plane(plane);
 780         struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
 781         struct dpu_hw_fmt_layout layout;
 782         struct drm_gem_object *obj;
 783         struct dma_fence *fence;
 784         struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
 785         int ret;
 786
 787         if (!new_state->fb)
 788                 return 0;
 789
 790         DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
 791
 792         /* cache aspace */
 793         pstate->aspace = kms->base.aspace;
 794
 795         /*
 796          * TODO: Need to sort out the msm_framebuffer_prepare() call below so
 797          *       we can use msm_atomic_prepare_fb() instead of doing the
 798          *       implicit fence and fb prepare by hand here.
 799          */
 800         obj = msm_framebuffer_bo(new_state->fb, 0);
 801         fence = reservation_object_get_excl_rcu(obj->resv);
 802         if (fence)
 803                 drm_atomic_set_fence_for_plane(new_state, fence);
 804
 805         if (pstate->aspace) {
 806                 ret = msm_framebuffer_prepare(new_state->fb,
 807                                 pstate->aspace);
 808                 if (ret) {
 809                         DPU_ERROR("failed to prepare framebuffer\n");
 810                         return ret;
 811                 }
 812         }
 813
 814         /* validate framebuffer layout before commit */
 815         ret = dpu_format_populate_layout(pstate->aspace,
 816                         new_state->fb, &layout);
 817         if (ret) {
 818                 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
 819                 return ret;
 820         }
 821
 822         return 0;
 823 }
 824
 825 static void dpu_plane_cleanup_fb(struct drm_plane *plane,
 826                 struct drm_plane_state *old_state)
 827 {
 828         struct dpu_plane *pdpu = to_dpu_plane(plane);
 829         struct dpu_plane_state *old_pstate;
 830
 831         if (!old_state || !old_state->fb)
 832                 return;
 833
 834         old_pstate = to_dpu_plane_state(old_state);
 835
 836         DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
 837
 838         msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
 839 }
 840
 841 static bool dpu_plane_validate_src(struct drm_rect *src,
 842                                    struct drm_rect *fb_rect,
 843                                    uint32_t min_src_size)
 844 {
 845         /* Ensure fb size is supported */
 846         if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH ||
 847             drm_rect_height(fb_rect) > MAX_IMG_HEIGHT)
 848                 return false;
 849
 850         /* Ensure src rect is above the minimum size */
 851         if (drm_rect_width(src) < min_src_size ||
 852             drm_rect_height(src) < min_src_size)
 853                 return false;
 854
 855         /* Ensure src is fully encapsulated in fb */
 856         return drm_rect_intersect(fb_rect, src) &&
 857                 drm_rect_equals(fb_rect, src);
 858 }
 859
 860 static int dpu_plane_atomic_check(struct drm_plane *plane,
 861                                   struct drm_plane_state *state)
 862 {
 863         int ret = 0, min_scale;
 864         struct dpu_plane *pdpu = to_dpu_plane(plane);
 865         const struct drm_crtc_state *crtc_state = NULL;
 866         const struct dpu_format *fmt;
 867         struct drm_rect src, dst, fb_rect = { 0 };
 868         uint32_t min_src_size, max_linewidth;
 869
 870         if (state->crtc)
 871                 crtc_state = drm_atomic_get_new_crtc_state(state->state,
 872                                                            state->crtc);
 873
 874         min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale);
 875         ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale,
 876                                           pdpu->pipe_sblk->maxupscale << 16,
 877                                           true, true);
 878         if (ret) {
 879                 DPU_ERROR_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
 880                 return ret;
 881         }
 882         if (!state->visible)
 883                 return 0;
 884
 885         src.x1 = state->src_x >> 16;
 886         src.y1 = state->src_y >> 16;
 887         src.x2 = src.x1 + (state->src_w >> 16);
 888         src.y2 = src.y1 + (state->src_h >> 16);
 889
 890         dst = drm_plane_state_dest(state);
 891
 892         fb_rect.x2 = state->fb->width;
 893         fb_rect.y2 = state->fb->height;
 894
 895         max_linewidth = pdpu->pipe_sblk->common->maxlinewidth;
 896
 897         fmt = to_dpu_format(msm_framebuffer_format(state->fb));
 898
 899         min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
 900
 901         if (DPU_FORMAT_IS_YUV(fmt) &&
 902                 (!(pdpu->features & DPU_SSPP_SCALER) ||
 903                  !(pdpu->features & (BIT(DPU_SSPP_CSC)
 904                  | BIT(DPU_SSPP_CSC_10BIT))))) {
 905                 DPU_ERROR_PLANE(pdpu,
 906                                 "plane doesn't have scaler/csc for yuv\n");
 907                 return -EINVAL;
 908
 909         /* check src bounds */
 910         } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
 911                 DPU_ERROR_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
 912                                 DRM_RECT_ARG(&src));
 913                 return -E2BIG;
 914
 915         /* valid yuv image */
 916         } else if (DPU_FORMAT_IS_YUV(fmt) &&
 917                    (src.x1 & 0x1 || src.y1 & 0x1 ||
 918                     drm_rect_width(&src) & 0x1 ||
 919                     drm_rect_height(&src) & 0x1)) {
 920                 DPU_ERROR_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
 921                                 DRM_RECT_ARG(&src));
 922                 return -EINVAL;
 923
 924         /* min dst support */
 925         } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) {
 926                 DPU_ERROR_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
 927                                 DRM_RECT_ARG(&dst));
 928                 return -EINVAL;
 929
 930         /* check decimated source width */
 931         } else if (drm_rect_width(&src) > max_linewidth) {
 932                 DPU_ERROR_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
 933                                 DRM_RECT_ARG(&src), max_linewidth);
 934                 return -E2BIG;
 935         }
 936
 937         return 0;
 938 }
 939
 940 void dpu_plane_flush(struct drm_plane *plane)
 941 {
 942         struct dpu_plane *pdpu;
 943         struct dpu_plane_state *pstate;
 944
 945         if (!plane || !plane->state) {
 946                 DPU_ERROR("invalid plane\n");
 947                 return;
 948         }
 949
 950         pdpu = to_dpu_plane(plane);
 951         pstate = to_dpu_plane_state(plane->state);
 952
 953         /*
 954          * These updates have to be done immediately before the plane flush
 955          * timing, and may not be moved to the atomic_update/mode_set functions.
 956          */
 957         if (pdpu->is_error)
 958                 /* force white frame with 100% alpha pipe output on error */
 959                 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
 960         else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
 961                 /* force 100% alpha */
 962                 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
 963         else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc)
 964                 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr);
 965
 966         /* flag h/w flush complete */
 967         if (plane->state)
 968                 pstate->pending = false;
 969 }
 970
 971 /**
 972  * dpu_plane_set_error: enable/disable error condition
 973  * @plane: pointer to drm_plane structure
 974  */
 975 void dpu_plane_set_error(struct drm_plane *plane, bool error)
 976 {
 977         struct dpu_plane *pdpu;
 978
 979         if (!plane)
 980                 return;
 981
 982         pdpu = to_dpu_plane(plane);
 983         pdpu->is_error = error;
 984 }
 985
 986 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 987 {
 988         uint32_t src_flags;
 989         struct dpu_plane *pdpu = to_dpu_plane(plane);
 990         struct drm_plane_state *state = plane->state;
 991         struct dpu_plane_state *pstate = to_dpu_plane_state(state);
 992         struct drm_crtc *crtc = state->crtc;
 993         struct drm_framebuffer *fb = state->fb;
 994         const struct dpu_format *fmt =
 995                 to_dpu_format(msm_framebuffer_format(fb));
 996
 997         memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
 998
 999         _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);
1000
1001         pstate->pending = true;
1002
1003         pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
1004         _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1005
1006         DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1007                         ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
1008                         crtc->base.id, DRM_RECT_ARG(&state->dst),
1009                         (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
1010
1011         pdpu->pipe_cfg.src_rect = state->src;
1012
1013         /* state->src is 16.16, src_rect is not */
1014         pdpu->pipe_cfg.src_rect.x1 >>= 16;
1015         pdpu->pipe_cfg.src_rect.x2 >>= 16;
1016         pdpu->pipe_cfg.src_rect.y1 >>= 16;
1017         pdpu->pipe_cfg.src_rect.y2 >>= 16;
1018
1019         pdpu->pipe_cfg.dst_rect = state->dst;
1020
1021         _dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
1022
1023         /* override for color fill */
1024         if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1025                 /* skip remaining processing on color fill */
1026                 return;
1027         }
1028
1029         if (pdpu->pipe_hw->ops.setup_rects) {
1030                 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
1031                                 &pdpu->pipe_cfg,
1032                                 pstate->multirect_index);
1033         }
1034
1035         if (pdpu->pipe_hw->ops.setup_pe &&
1036                         (pstate->multirect_index != DPU_SSPP_RECT_1))
1037                 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
1038                                 &pstate->pixel_ext);
1039
1040         /**
1041          * when programmed in multirect mode, scalar block will be
1042          * bypassed. Still we need to update alpha and bitwidth
1043          * ONLY for RECT0
1044          */
1045         if (pdpu->pipe_hw->ops.setup_scaler &&
1046                         pstate->multirect_index != DPU_SSPP_RECT_1)
1047                 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
1048                                 &pdpu->pipe_cfg, &pstate->pixel_ext,
1049                                 &pstate->scaler3_cfg);
1050
1051         if (pdpu->pipe_hw->ops.setup_multirect)
1052                 pdpu->pipe_hw->ops.setup_multirect(
1053                                 pdpu->pipe_hw,
1054                                 pstate->multirect_index,
1055                                 pstate->multirect_mode);
1056
1057         if (pdpu->pipe_hw->ops.setup_format) {
1058                 src_flags = 0x0;
1059
1060                 /* update format */
1061                 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
1062                                 pstate->multirect_index);
1063
1064                 if (pdpu->pipe_hw->ops.setup_cdp) {
1065                         struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
1066
1067                         memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
1068
1069                         cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
1070                                         [DPU_PERF_CDP_USAGE_RT].rd_enable;
1071                         cdp_cfg->ubwc_meta_enable =
1072                                         DPU_FORMAT_IS_UBWC(fmt);
1073                         cdp_cfg->tile_amortize_enable =
1074                                         DPU_FORMAT_IS_UBWC(fmt) ||
1075                                         DPU_FORMAT_IS_TILE(fmt);
1076                         cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
1077
1078                         pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
1079                 }
1080
1081                 /* update csc */
1082                 if (DPU_FORMAT_IS_YUV(fmt))
1083                         _dpu_plane_setup_csc(pdpu);
1084                 else
1085                         pdpu->csc_ptr = 0;
1086         }
1087
1088         _dpu_plane_set_qos_lut(plane, fb);
1089         _dpu_plane_set_danger_lut(plane, fb);
1090
1091         if (plane->type != DRM_PLANE_TYPE_CURSOR) {
1092                 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
1093                 _dpu_plane_set_ot_limit(plane, crtc);
1094         }
1095
1096         _dpu_plane_set_qos_remap(plane);
1097 }
1098
1099 static void _dpu_plane_atomic_disable(struct drm_plane *plane)
1100 {
1101         struct dpu_plane *pdpu = to_dpu_plane(plane);
1102         struct drm_plane_state *state = plane->state;
1103         struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1104
1105         trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane),
1106                                 pstate->multirect_mode);
1107
1108         pstate->pending = true;
1109
1110         if (is_dpu_plane_virtual(plane) &&
1111                         pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect)
1112                 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw,
1113                                 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE);
1114 }
1115
1116 static void dpu_plane_atomic_update(struct drm_plane *plane,
1117                                 struct drm_plane_state *old_state)
1118 {
1119         struct dpu_plane *pdpu = to_dpu_plane(plane);
1120         struct drm_plane_state *state = plane->state;
1121
1122         pdpu->is_error = false;
1123
1124         DPU_DEBUG_PLANE(pdpu, "\n");
1125
1126         if (!state->visible) {
1127                 _dpu_plane_atomic_disable(plane);
1128         } else {
1129                 dpu_plane_sspp_atomic_update(plane);
1130         }
1131 }
1132
1133 void dpu_plane_restore(struct drm_plane *plane)
1134 {
1135         struct dpu_plane *pdpu;
1136
1137         if (!plane || !plane->state) {
1138                 DPU_ERROR("invalid plane\n");
1139                 return;
1140         }
1141
1142         pdpu = to_dpu_plane(plane);
1143
1144         DPU_DEBUG_PLANE(pdpu, "\n");
1145
1146         /* last plane state is same as current state */
1147         dpu_plane_atomic_update(plane, plane->state);
1148 }
1149
1150 static void dpu_plane_destroy(struct drm_plane *plane)
1151 {
1152         struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;
1153
1154         DPU_DEBUG_PLANE(pdpu, "\n");
1155
1156         if (pdpu) {
1157                 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
1158
1159                 mutex_destroy(&pdpu->lock);
1160
1161                 /* this will destroy the states as well */
1162                 drm_plane_cleanup(plane);
1163
1164                 dpu_hw_sspp_destroy(pdpu->pipe_hw);
1165
1166                 kfree(pdpu);
1167         }
1168 }
1169
1170 static void dpu_plane_destroy_state(struct drm_plane *plane,
1171                 struct drm_plane_state *state)
1172 {
1173         __drm_atomic_helper_plane_destroy_state(state);
1174         kfree(to_dpu_plane_state(state));
1175 }
1176
1177 static struct drm_plane_state *
1178 dpu_plane_duplicate_state(struct drm_plane *plane)
1179 {
1180         struct dpu_plane *pdpu;
1181         struct dpu_plane_state *pstate;
1182         struct dpu_plane_state *old_state;
1183
1184         if (!plane) {
1185                 DPU_ERROR("invalid plane\n");
1186                 return NULL;
1187         } else if (!plane->state) {
1188                 DPU_ERROR("invalid plane state\n");
1189                 return NULL;
1190         }
1191
1192         old_state = to_dpu_plane_state(plane->state);
1193         pdpu = to_dpu_plane(plane);
1194         pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1195         if (!pstate) {
1196                 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1197                 return NULL;
1198         }
1199
1200         DPU_DEBUG_PLANE(pdpu, "\n");
1201
1202         pstate->pending = false;
1203
1204         __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
1205
1206         return &pstate->base;
1207 }
1208
1209 static void dpu_plane_reset(struct drm_plane *plane)
1210 {
1211         struct dpu_plane *pdpu;
1212         struct dpu_plane_state *pstate;
1213
1214         if (!plane) {
1215                 DPU_ERROR("invalid plane\n");
1216                 return;
1217         }
1218
1219         pdpu = to_dpu_plane(plane);
1220         DPU_DEBUG_PLANE(pdpu, "\n");
1221
1222         /* remove previous state, if present */
1223         if (plane->state) {
1224                 dpu_plane_destroy_state(plane, plane->state);
1225                 plane->state = 0;
1226         }
1227
1228         pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
1229         if (!pstate) {
1230                 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1231                 return;
1232         }
1233
1234         pstate->base.plane = plane;
1235
1236         plane->state = &pstate->base;
1237 }
1238
1239 #ifdef CONFIG_DEBUG_FS
1240 static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
1241 {
1242         struct dpu_plane *pdpu = to_dpu_plane(plane);
1243         struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1244
1245         if (!pdpu->is_rt_pipe)
1246                 return;
1247
1248         pm_runtime_get_sync(&dpu_kms->pdev->dev);
1249         _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
1250         pm_runtime_put_sync(&dpu_kms->pdev->dev);
1251 }
1252
1253 static ssize_t _dpu_plane_danger_read(struct file *file,
1254                         char __user *buff, size_t count, loff_t *ppos)
1255 {
1256         struct dpu_kms *kms = file->private_data;
1257         int len;
1258         char buf[40];
1259
1260         len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
1261
1262         return simple_read_from_buffer(buff, count, ppos, buf, len);
1263 }
1264
1265 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
1266 {
1267         struct drm_plane *plane;
1268
1269         drm_for_each_plane(plane, kms->dev) {
1270                 if (plane->fb && plane->state) {
1271                         dpu_plane_danger_signal_ctrl(plane, enable);
1272                         DPU_DEBUG("plane:%d img:%dx%d ",
1273                                 plane->base.id, plane->fb->width,
1274                                 plane->fb->height);
1275                         DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
1276                                 plane->state->src_x >> 16,
1277                                 plane->state->src_y >> 16,
1278                                 plane->state->src_w >> 16,
1279                                 plane->state->src_h >> 16,
1280                                 plane->state->crtc_x, plane->state->crtc_y,
1281                                 plane->state->crtc_w, plane->state->crtc_h);
1282                 } else {
1283                         DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
1284                 }
1285         }
1286 }
1287
1288 static ssize_t _dpu_plane_danger_write(struct file *file,
1289                     const char __user *user_buf, size_t count, loff_t *ppos)
1290 {
1291         struct dpu_kms *kms = file->private_data;
1292         int disable_panic;
1293         int ret;
1294
1295         ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
1296         if (ret)
1297                 return ret;
1298
1299         if (disable_panic) {
1300                 /* Disable panic signal for all active pipes */
1301                 DPU_DEBUG("Disabling danger:\n");
1302                 _dpu_plane_set_danger_state(kms, false);
1303                 kms->has_danger_ctrl = false;
1304         } else {
1305                 /* Enable panic signal for all active pipes */
1306                 DPU_DEBUG("Enabling danger:\n");
1307                 kms->has_danger_ctrl = true;
1308                 _dpu_plane_set_danger_state(kms, true);
1309         }
1310
1311         return count;
1312 }
1313
1314 static const struct file_operations dpu_plane_danger_enable = {
1315         .open = simple_open,
1316         .read = _dpu_plane_danger_read,
1317         .write = _dpu_plane_danger_write,
1318 };
1319
1320 static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1321 {
1322         struct dpu_plane *pdpu = to_dpu_plane(plane);
1323         struct dpu_kms *kms = _dpu_plane_get_kms(plane);
1324         const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
1325         const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
1326
1327         /* create overall sub-directory for the pipe */
1328         pdpu->debugfs_root =
1329                 debugfs_create_dir(pdpu->pipe_name,
1330                                 plane->dev->primary->debugfs_root);
1331
1332         if (!pdpu->debugfs_root)
1333                 return -ENOMEM;
1334
1335         /* don't error check these */
1336         debugfs_create_x32("features", 0600,
1337                         pdpu->debugfs_root, &pdpu->features);
1338
1339         /* add register dump support */
1340         dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
1341                         sblk->src_blk.base + cfg->base,
1342                         sblk->src_blk.len,
1343                         kms);
1344         dpu_debugfs_create_regset32("src_blk", 0400,
1345                         pdpu->debugfs_root, &pdpu->debugfs_src);
1346
1347         if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
1348                         cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) {
1349                 dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
1350                                 sblk->scaler_blk.base + cfg->base,
1351                                 sblk->scaler_blk.len,
1352                                 kms);
1353                 dpu_debugfs_create_regset32("scaler_blk", 0400,
1354                                 pdpu->debugfs_root,
1355                                 &pdpu->debugfs_scaler);
1356                 debugfs_create_bool("default_scaling",
1357                                 0600,
1358                                 pdpu->debugfs_root,
1359                                 &pdpu->debugfs_default_scale);
1360         }
1361
1362         if (cfg->features & BIT(DPU_SSPP_CSC) ||
1363                         cfg->features & BIT(DPU_SSPP_CSC_10BIT)) {
1364                 dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
1365                                 sblk->csc_blk.base + cfg->base,
1366                                 sblk->csc_blk.len,
1367                                 kms);
1368                 dpu_debugfs_create_regset32("csc_blk", 0400,
1369                                 pdpu->debugfs_root, &pdpu->debugfs_csc);
1370         }
1371
1372         debugfs_create_u32("xin_id",
1373                         0400,
1374                         pdpu->debugfs_root,
1375                         (u32 *) &cfg->xin_id);
1376         debugfs_create_u32("clk_ctrl",
1377                         0400,
1378                         pdpu->debugfs_root,
1379                         (u32 *) &cfg->clk_ctrl);
1380         debugfs_create_x32("creq_vblank",
1381                         0600,
1382                         pdpu->debugfs_root,
1383                         (u32 *) &sblk->creq_vblank);
1384         debugfs_create_x32("danger_vblank",
1385                         0600,
1386                         pdpu->debugfs_root,
1387                         (u32 *) &sblk->danger_vblank);
1388
1389         debugfs_create_file("disable_danger",
1390                         0600,
1391                         pdpu->debugfs_root,
1392                         kms, &dpu_plane_danger_enable);
1393
1394         return 0;
1395 }
1396 #else
1397 static int _dpu_plane_init_debugfs(struct drm_plane *plane)
1398 {
1399         return 0;
1400 }
1401 #endif
1402
1403 static int dpu_plane_late_register(struct drm_plane *plane)
1404 {
1405         return _dpu_plane_init_debugfs(plane);
1406 }
1407
1408 static void dpu_plane_early_unregister(struct drm_plane *plane)
1409 {
1410         struct dpu_plane *pdpu = to_dpu_plane(plane);
1411
1412         debugfs_remove_recursive(pdpu->debugfs_root);
1413 }
1414
1415 static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
1416                 uint32_t format, uint64_t modifier)
1417 {
1418         if (modifier == DRM_FORMAT_MOD_LINEAR)
1419                 return true;
1420
1421         if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) {
1422                 int i;
1423                 for (i = 0; i < ARRAY_SIZE(qcom_compressed_supported_formats); i++) {
1424                         if (format == qcom_compressed_supported_formats[i])
1425                                 return true;
1426                 }
1427         }
1428
1429         return false;
1430 }
1431
1432 static const struct drm_plane_funcs dpu_plane_funcs = {
1433                 .update_plane = drm_atomic_helper_update_plane,
1434                 .disable_plane = drm_atomic_helper_disable_plane,
1435                 .destroy = dpu_plane_destroy,
1436                 .reset = dpu_plane_reset,
1437                 .atomic_duplicate_state = dpu_plane_duplicate_state,
1438                 .atomic_destroy_state = dpu_plane_destroy_state,
1439                 .late_register = dpu_plane_late_register,
1440                 .early_unregister = dpu_plane_early_unregister,
1441                 .format_mod_supported = dpu_plane_format_mod_supported,
1442 };
1443
1444 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
1445                 .prepare_fb = dpu_plane_prepare_fb,
1446                 .cleanup_fb = dpu_plane_cleanup_fb,
1447                 .atomic_check = dpu_plane_atomic_check,
1448                 .atomic_update = dpu_plane_atomic_update,
1449 };
1450
1451 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane)
1452 {
1453         return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE;
1454 }
1455
1456 bool is_dpu_plane_virtual(struct drm_plane *plane)
1457 {
1458         return plane ? to_dpu_plane(plane)->is_virtual : false;
1459 }
1460
1461 /* initialize plane */
1462 struct drm_plane *dpu_plane_init(struct drm_device *dev,
1463                 uint32_t pipe, enum drm_plane_type type,
1464                 unsigned long possible_crtcs, u32 master_plane_id)
1465 {
1466         struct drm_plane *plane = NULL, *master_plane = NULL;
1467         const uint32_t *format_list;
1468         struct dpu_plane *pdpu;
1469         struct msm_drm_private *priv = dev->dev_private;
1470         struct dpu_kms *kms = to_dpu_kms(priv->kms);
1471         int zpos_max = DPU_ZPOS_MAX;
1472         uint32_t num_formats;
1473         int ret = -EINVAL;
1474
1475         /* create and zero local structure */
1476         pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL);
1477         if (!pdpu) {
1478                 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe);
1479                 ret = -ENOMEM;
1480                 return ERR_PTR(ret);
1481         }
1482
1483         /* cache local stuff for later */
1484         plane = &pdpu->base;
1485         pdpu->pipe = pipe;
1486         pdpu->is_virtual = (master_plane_id != 0);
1487         INIT_LIST_HEAD(&pdpu->mplane_list);
1488         master_plane = drm_plane_find(dev, NULL, master_plane_id);
1489         if (master_plane) {
1490                 struct dpu_plane *mpdpu = to_dpu_plane(master_plane);
1491
1492                 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list);
1493         }
1494
1495         /* initialize underlying h/w driver */
1496         pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog,
1497                                                         master_plane_id != 0);
1498         if (IS_ERR(pdpu->pipe_hw)) {
1499                 DPU_ERROR("[%u]SSPP init failed\n", pipe);
1500                 ret = PTR_ERR(pdpu->pipe_hw);
1501                 goto clean_plane;
1502         } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) {
1503                 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
1504                 goto clean_sspp;
1505         }
1506
1507         /* cache features mask for later */
1508         pdpu->features = pdpu->pipe_hw->cap->features;
1509         pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
1510         if (!pdpu->pipe_sblk) {
1511                 DPU_ERROR("[%u]invalid sblk\n", pipe);
1512                 goto clean_sspp;
1513         }
1514
1515         if (pdpu->is_virtual) {
1516                 format_list = pdpu->pipe_sblk->virt_format_list;
1517                 num_formats = pdpu->pipe_sblk->virt_num_formats;
1518         }
1519         else {
1520                 format_list = pdpu->pipe_sblk->format_list;
1521                 num_formats = pdpu->pipe_sblk->num_formats;
1522         }
1523
1524         ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
1525                                 format_list, num_formats,
1526                                 supported_format_modifiers, type, NULL);
1527         if (ret)
1528                 goto clean_sspp;
1529
1530         pdpu->catalog = kms->catalog;
1531
1532         if (kms->catalog->mixer_count &&
1533                 kms->catalog->mixer[0].sblk->maxblendstages) {
1534                 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
1535                 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
1536                         zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
1537         }
1538
1539         ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
1540         if (ret)
1541                 DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
1542
1543         /* success! finalize initialization */
1544         drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
1545
1546         /* save user friendly pipe name for later */
1547         snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id);
1548
1549         mutex_init(&pdpu->lock);
1550
1551         DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name,
1552                                         pipe, plane->base.id, master_plane_id);
1553         return plane;
1554
1555 clean_sspp:
1556         if (pdpu && pdpu->pipe_hw)
1557                 dpu_hw_sspp_destroy(pdpu->pipe_hw);
1558 clean_plane:
1559         kfree(pdpu);
1560         return ERR_PTR(ret);
1561 }