1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
10 #include <linux/debugfs.h>
11 #include <linux/dma-buf.h>
12 #include <linux/of_irq.h>
14 #include <drm/drm_crtc.h>
15 #include <drm/drm_file.h>
22 #include "dpu_core_irq.h"
23 #include "dpu_formats.h"
24 #include "dpu_hw_vbif.h"
26 #include "dpu_encoder.h"
27 #include "dpu_plane.h"
30 #define CREATE_TRACE_POINTS
31 #include "dpu_trace.h"
34 * To enable overall DRM driver logging
35 * # echo 0x2 > /sys/module/drm/parameters/debug
37 * To enable DRM driver h/w logging
38 * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
40 * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_)
42 #define DPU_DEBUGFS_DIR "msm_dpu"
43 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
45 static int dpu_kms_hw_init(struct msm_kms *kms);
46 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
48 static unsigned long dpu_iomap_size(struct platform_device *pdev,
53 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
55 DRM_ERROR("failed to get memory resource: %s\n", name);
59 return resource_size(res);
62 #ifdef CONFIG_DEBUG_FS
63 static int _dpu_danger_signal_status(struct seq_file *s,
66 struct dpu_kms *kms = (struct dpu_kms *)s->private;
67 struct dpu_danger_safe_status status;
71 DPU_ERROR("invalid arg(s)\n");
75 memset(&status, 0, sizeof(struct dpu_danger_safe_status));
77 pm_runtime_get_sync(&kms->pdev->dev);
79 seq_puts(s, "\nDanger signal status:\n");
80 if (kms->hw_mdp->ops.get_danger_status)
81 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
84 seq_puts(s, "\nSafe signal status:\n");
85 if (kms->hw_mdp->ops.get_danger_status)
86 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
89 pm_runtime_put_sync(&kms->pdev->dev);
91 seq_printf(s, "MDP : 0x%x\n", status.mdp);
93 for (i = SSPP_VIG0; i < SSPP_MAX; i++)
94 seq_printf(s, "SSPP%d : 0x%x \t", i - SSPP_VIG0,
101 #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix) \
102 static int __prefix ## _open(struct inode *inode, struct file *file) \
104 return single_open(file, __prefix ## _show, inode->i_private); \
106 static const struct file_operations __prefix ## _fops = { \
107 .owner = THIS_MODULE, \
108 .open = __prefix ## _open, \
109 .release = single_release, \
111 .llseek = seq_lseek, \
114 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v)
116 return _dpu_danger_signal_status(s, true);
118 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_danger_stats);
120 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
122 return _dpu_danger_signal_status(s, false);
124 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_debugfs_safe_stats);
126 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
127 struct dentry *parent)
129 struct dentry *entry = debugfs_create_dir("danger", parent);
131 debugfs_create_file("danger_status", 0600, entry,
132 dpu_kms, &dpu_debugfs_danger_stats_fops);
133 debugfs_create_file("safe_status", 0600, entry,
134 dpu_kms, &dpu_debugfs_safe_stats_fops);
137 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
139 struct dpu_debugfs_regset32 *regset = s->private;
140 struct dpu_kms *dpu_kms = regset->dpu_kms;
147 base = dpu_kms->mmio + regset->offset;
149 /* insert padding spaces, if needed */
150 if (regset->offset & 0xF) {
151 seq_printf(s, "[%x]", regset->offset & ~0xF);
152 for (i = 0; i < (regset->offset & 0xF); i += 4)
156 pm_runtime_get_sync(&dpu_kms->pdev->dev);
158 /* main register output */
159 for (i = 0; i < regset->blk_len; i += 4) {
160 addr = regset->offset + i;
161 if ((addr & 0xF) == 0x0)
162 seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
163 seq_printf(s, " %08x", readl_relaxed(base + i));
166 pm_runtime_put_sync(&dpu_kms->pdev->dev);
171 static int dpu_debugfs_open_regset32(struct inode *inode,
174 return single_open(file, _dpu_debugfs_show_regset32, inode->i_private);
177 static const struct file_operations dpu_fops_regset32 = {
178 .open = dpu_debugfs_open_regset32,
181 .release = single_release,
184 void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
185 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
188 regset->offset = offset;
189 regset->blk_len = length;
190 regset->dpu_kms = dpu_kms;
194 void dpu_debugfs_create_regset32(const char *name, umode_t mode,
195 void *parent, struct dpu_debugfs_regset32 *regset)
197 if (!name || !regset || !regset->dpu_kms || !regset->blk_len)
200 /* make sure offset is a multiple of 4 */
201 regset->offset = round_down(regset->offset, 4);
203 debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32);
206 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
208 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
209 void *p = dpu_hw_util_get_log_mask_ptr();
210 struct dentry *entry;
215 entry = debugfs_create_dir("debug", minor->debugfs_root);
217 debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p);
219 dpu_debugfs_danger_init(dpu_kms, entry);
220 dpu_debugfs_vbif_init(dpu_kms, entry);
221 dpu_debugfs_core_irq_init(dpu_kms, entry);
223 return dpu_core_perf_debugfs_init(dpu_kms, entry);
227 /* Global/shared object state funcs */
230 * This is a helper that returns the private state currently in operation.
231 * Note that this would return the "old_state" if called in the atomic check
232 * path, and the "new_state" after the atomic swap has been done.
234 struct dpu_global_state *
235 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms)
237 return to_dpu_global_state(dpu_kms->global_state.state);
241 * This acquires the modeset lock set aside for global state, creates
242 * a new duplicated private object state.
244 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s)
246 struct msm_drm_private *priv = s->dev->dev_private;
247 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
248 struct drm_private_state *priv_state;
251 ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx);
255 priv_state = drm_atomic_get_private_obj_state(s,
256 &dpu_kms->global_state);
257 if (IS_ERR(priv_state))
258 return ERR_CAST(priv_state);
260 return to_dpu_global_state(priv_state);
263 static struct drm_private_state *
264 dpu_kms_global_duplicate_state(struct drm_private_obj *obj)
266 struct dpu_global_state *state;
268 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
272 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
277 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
278 struct drm_private_state *state)
280 struct dpu_global_state *dpu_state = to_dpu_global_state(state);
285 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
286 .atomic_duplicate_state = dpu_kms_global_duplicate_state,
287 .atomic_destroy_state = dpu_kms_global_destroy_state,
290 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
292 struct dpu_global_state *state;
294 drm_modeset_lock_init(&dpu_kms->global_state_lock);
296 state = kzalloc(sizeof(*state), GFP_KERNEL);
300 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
302 &dpu_kms_global_state_funcs);
306 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
308 return dpu_crtc_vblank(crtc, true);
311 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
313 dpu_crtc_vblank(crtc, false);
316 static void dpu_kms_enable_commit(struct msm_kms *kms)
318 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
319 pm_runtime_get_sync(&dpu_kms->pdev->dev);
322 static void dpu_kms_disable_commit(struct msm_kms *kms)
324 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
325 pm_runtime_put_sync(&dpu_kms->pdev->dev);
328 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc)
330 struct drm_encoder *encoder;
332 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
335 if (dpu_encoder_vsync_time(encoder, &vsync_time) == 0)
342 static void dpu_kms_prepare_commit(struct msm_kms *kms,
343 struct drm_atomic_state *state)
345 struct drm_crtc *crtc;
346 struct drm_crtc_state *crtc_state;
347 struct drm_encoder *encoder;
353 /* Call prepare_commit for all affected encoders */
354 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
355 drm_for_each_encoder_mask(encoder, crtc->dev,
356 crtc_state->encoder_mask) {
357 dpu_encoder_prepare_commit(encoder);
362 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
364 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
365 struct drm_crtc *crtc;
367 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) {
368 if (!crtc->state->active)
371 trace_dpu_kms_commit(DRMID(crtc));
372 dpu_crtc_commit_kickoff(crtc);
377 * Override the encoder enable since we need to setup the inline rotator and do
378 * some crtc magic before enabling any bridge that might be present.
380 void dpu_kms_encoder_enable(struct drm_encoder *encoder)
382 const struct drm_encoder_helper_funcs *funcs = encoder->helper_private;
383 struct drm_device *dev = encoder->dev;
384 struct drm_crtc *crtc;
386 /* Forward this enable call to the commit hook */
387 if (funcs && funcs->commit)
388 funcs->commit(encoder);
390 drm_for_each_crtc(crtc, dev) {
391 if (!(crtc->state->encoder_mask & drm_encoder_mask(encoder)))
394 trace_dpu_kms_enc_enable(DRMID(crtc));
398 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
400 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
401 struct drm_crtc *crtc;
403 DPU_ATRACE_BEGIN("kms_complete_commit");
405 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
406 dpu_crtc_complete_commit(crtc);
408 DPU_ATRACE_END("kms_complete_commit");
411 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
412 struct drm_crtc *crtc)
414 struct drm_encoder *encoder;
415 struct drm_device *dev;
418 if (!kms || !crtc || !crtc->state) {
419 DPU_ERROR("invalid params\n");
425 if (!crtc->state->enable) {
426 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
430 if (!crtc->state->active) {
431 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
435 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
436 if (encoder->crtc != crtc)
439 * Wait for post-flush if necessary to delay before
440 * plane_cleanup. For example, wait for vsync in case of video
441 * mode panels. This may be a no-op for command mode panels.
443 trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
444 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
445 if (ret && ret != -EWOULDBLOCK) {
446 DPU_ERROR("wait for commit done returned %d\n", ret);
452 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
454 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
455 struct drm_crtc *crtc;
457 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
458 dpu_kms_wait_for_commit_done(kms, crtc);
461 static int _dpu_kms_initialize_dsi(struct drm_device *dev,
462 struct msm_drm_private *priv,
463 struct dpu_kms *dpu_kms)
465 struct drm_encoder *encoder = NULL;
468 if (!(priv->dsi[0] || priv->dsi[1]))
471 /*TODO: Support two independent DSI connectors */
472 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI);
473 if (IS_ERR(encoder)) {
474 DPU_ERROR("encoder init failed for dsi display\n");
475 return PTR_ERR(encoder);
478 priv->encoders[priv->num_encoders++] = encoder;
480 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
484 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
486 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
496 * _dpu_kms_setup_displays - create encoders, bridges and connectors
497 * for underlying displays
498 * @dev: Pointer to drm device structure
499 * @priv: Pointer to private drm device data
500 * @dpu_kms: Pointer to dpu kms structure
501 * Returns: Zero on success
503 static int _dpu_kms_setup_displays(struct drm_device *dev,
504 struct msm_drm_private *priv,
505 struct dpu_kms *dpu_kms)
508 * Extend this function to initialize other
512 return _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
515 static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms)
517 struct msm_drm_private *priv;
520 priv = dpu_kms->dev->dev_private;
522 for (i = 0; i < priv->num_crtcs; i++)
523 priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
526 for (i = 0; i < priv->num_planes; i++)
527 priv->planes[i]->funcs->destroy(priv->planes[i]);
528 priv->num_planes = 0;
530 for (i = 0; i < priv->num_connectors; i++)
531 priv->connectors[i]->funcs->destroy(priv->connectors[i]);
532 priv->num_connectors = 0;
534 for (i = 0; i < priv->num_encoders; i++)
535 priv->encoders[i]->funcs->destroy(priv->encoders[i]);
536 priv->num_encoders = 0;
539 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
541 struct drm_device *dev;
542 struct drm_plane *primary_planes[MAX_PLANES], *plane;
543 struct drm_plane *cursor_planes[MAX_PLANES] = { NULL };
544 struct drm_crtc *crtc;
546 struct msm_drm_private *priv;
547 struct dpu_mdss_cfg *catalog;
549 int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
552 priv = dev->dev_private;
553 catalog = dpu_kms->catalog;
556 * Create encoder and query display drivers to create
557 * bridges and connectors
559 ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);
563 max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
565 /* Create the planes, keeping track of one primary/cursor per crtc */
566 for (i = 0; i < catalog->sspp_count; i++) {
567 enum drm_plane_type type;
569 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
570 && cursor_planes_idx < max_crtc_count)
571 type = DRM_PLANE_TYPE_CURSOR;
572 else if (primary_planes_idx < max_crtc_count)
573 type = DRM_PLANE_TYPE_PRIMARY;
575 type = DRM_PLANE_TYPE_OVERLAY;
577 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
578 type, catalog->sspp[i].features,
579 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR));
581 plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
582 (1UL << max_crtc_count) - 1, 0);
584 DPU_ERROR("dpu_plane_init failed\n");
585 ret = PTR_ERR(plane);
588 priv->planes[priv->num_planes++] = plane;
590 if (type == DRM_PLANE_TYPE_CURSOR)
591 cursor_planes[cursor_planes_idx++] = plane;
592 else if (type == DRM_PLANE_TYPE_PRIMARY)
593 primary_planes[primary_planes_idx++] = plane;
596 max_crtc_count = min(max_crtc_count, primary_planes_idx);
598 /* Create one CRTC per encoder */
599 for (i = 0; i < max_crtc_count; i++) {
600 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
605 priv->crtcs[priv->num_crtcs++] = crtc;
608 /* All CRTCs are compatible with all encoders */
609 for (i = 0; i < priv->num_encoders; i++)
610 priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
614 _dpu_kms_drm_obj_destroy(dpu_kms);
618 static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
619 struct drm_encoder *encoder)
624 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
628 if (dpu_kms->hw_intr)
629 dpu_hw_intr_destroy(dpu_kms->hw_intr);
630 dpu_kms->hw_intr = NULL;
632 /* safe to call these more than once during shutdown */
633 _dpu_kms_mmu_destroy(dpu_kms);
635 if (dpu_kms->catalog) {
636 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
637 u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
639 if ((vbif_idx < VBIF_MAX) && dpu_kms->hw_vbif[vbif_idx])
640 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[vbif_idx]);
644 if (dpu_kms->rm_init)
645 dpu_rm_destroy(&dpu_kms->rm);
646 dpu_kms->rm_init = false;
648 if (dpu_kms->catalog)
649 dpu_hw_catalog_deinit(dpu_kms->catalog);
650 dpu_kms->catalog = NULL;
652 if (dpu_kms->vbif[VBIF_NRT])
653 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]);
654 dpu_kms->vbif[VBIF_NRT] = NULL;
656 if (dpu_kms->vbif[VBIF_RT])
657 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
658 dpu_kms->vbif[VBIF_RT] = NULL;
661 dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
662 dpu_kms->hw_mdp = NULL;
665 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
666 dpu_kms->mmio = NULL;
669 static void dpu_kms_destroy(struct msm_kms *kms)
671 struct dpu_kms *dpu_kms;
674 DPU_ERROR("invalid kms\n");
678 dpu_kms = to_dpu_kms(kms);
680 _dpu_kms_hw_destroy(dpu_kms);
683 static void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
684 struct drm_encoder *encoder,
687 struct msm_display_info info;
688 struct msm_drm_private *priv = encoder->dev->dev_private;
691 memset(&info, 0, sizeof(info));
693 info.intf_type = encoder->encoder_type;
694 info.capabilities = cmd_mode ? MSM_DISPLAY_CAP_CMD_MODE :
695 MSM_DISPLAY_CAP_VID_MODE;
697 /* TODO: No support for DSI swap */
698 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
700 info.h_tile_instance[info.num_of_h_tiles] = i;
701 info.num_of_h_tiles++;
705 rc = dpu_encoder_setup(encoder->dev, encoder, &info);
707 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
708 encoder->base.id, rc);
711 static irqreturn_t dpu_irq(struct msm_kms *kms)
713 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
715 return dpu_core_irq(dpu_kms);
718 static void dpu_irq_preinstall(struct msm_kms *kms)
720 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
722 dpu_core_irq_preinstall(dpu_kms);
725 static void dpu_irq_uninstall(struct msm_kms *kms)
727 struct dpu_kms *dpu_kms = to_dpu_kms(kms);
729 dpu_core_irq_uninstall(dpu_kms);
732 static const struct msm_kms_funcs kms_funcs = {
733 .hw_init = dpu_kms_hw_init,
734 .irq_preinstall = dpu_irq_preinstall,
735 .irq_uninstall = dpu_irq_uninstall,
737 .enable_commit = dpu_kms_enable_commit,
738 .disable_commit = dpu_kms_disable_commit,
739 .vsync_time = dpu_kms_vsync_time,
740 .prepare_commit = dpu_kms_prepare_commit,
741 .flush_commit = dpu_kms_flush_commit,
742 .wait_flush = dpu_kms_wait_flush,
743 .complete_commit = dpu_kms_complete_commit,
744 .enable_vblank = dpu_kms_enable_vblank,
745 .disable_vblank = dpu_kms_disable_vblank,
746 .check_modified_format = dpu_format_check_modified_format,
747 .get_format = dpu_get_msm_format,
748 .round_pixclk = dpu_kms_round_pixclk,
749 .destroy = dpu_kms_destroy,
750 .set_encoder_mode = _dpu_kms_set_encoder_mode,
751 #ifdef CONFIG_DEBUG_FS
752 .debugfs_init = dpu_kms_debugfs_init,
756 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
760 if (!dpu_kms->base.aspace)
763 mmu = dpu_kms->base.aspace->mmu;
765 mmu->funcs->detach(mmu);
766 msm_gem_address_space_put(dpu_kms->base.aspace);
768 dpu_kms->base.aspace = NULL;
771 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
773 struct iommu_domain *domain;
774 struct msm_gem_address_space *aspace;
777 domain = iommu_domain_alloc(&platform_bus_type);
781 mmu = msm_iommu_new(dpu_kms->dev->dev, domain);
782 aspace = msm_gem_address_space_create(mmu, "dpu1",
783 0x1000, 0x100000000 - 0x1000);
785 if (IS_ERR(aspace)) {
786 mmu->funcs->destroy(mmu);
787 return PTR_ERR(aspace);
790 dpu_kms->base.aspace = aspace;
794 static struct dss_clk *_dpu_kms_get_clk(struct dpu_kms *dpu_kms,
797 struct dss_module_power *mp = &dpu_kms->mp;
800 for (i = 0; i < mp->num_clk; i++) {
801 if (!strcmp(mp->clk_config[i].clk_name, clock_name))
802 return &mp->clk_config[i];
808 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
812 clk = _dpu_kms_get_clk(dpu_kms, clock_name);
816 return clk_get_rate(clk->clk);
819 static int dpu_kms_hw_init(struct msm_kms *kms)
821 struct dpu_kms *dpu_kms;
822 struct drm_device *dev;
826 DPU_ERROR("invalid kms\n");
830 dpu_kms = to_dpu_kms(kms);
833 rc = dpu_kms_global_obj_init(dpu_kms);
837 atomic_set(&dpu_kms->bandwidth_ref, 0);
839 dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp", "mdp");
840 if (IS_ERR(dpu_kms->mmio)) {
841 rc = PTR_ERR(dpu_kms->mmio);
842 DPU_ERROR("mdp register memory map failed: %d\n", rc);
843 dpu_kms->mmio = NULL;
846 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
847 dpu_kms->mmio_len = dpu_iomap_size(dpu_kms->pdev, "mdp");
849 dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif", "vbif");
850 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
851 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
852 DPU_ERROR("vbif register memory map failed: %d\n", rc);
853 dpu_kms->vbif[VBIF_RT] = NULL;
856 dpu_kms->vbif_len[VBIF_RT] = dpu_iomap_size(dpu_kms->pdev, "vbif");
857 dpu_kms->vbif[VBIF_NRT] = msm_ioremap(dpu_kms->pdev, "vbif_nrt", "vbif_nrt");
858 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
859 dpu_kms->vbif[VBIF_NRT] = NULL;
860 DPU_DEBUG("VBIF NRT is not defined");
862 dpu_kms->vbif_len[VBIF_NRT] = dpu_iomap_size(dpu_kms->pdev,
866 dpu_kms->reg_dma = msm_ioremap(dpu_kms->pdev, "regdma", "regdma");
867 if (IS_ERR(dpu_kms->reg_dma)) {
868 dpu_kms->reg_dma = NULL;
869 DPU_DEBUG("REG_DMA is not defined");
871 dpu_kms->reg_dma_len = dpu_iomap_size(dpu_kms->pdev, "regdma");
874 pm_runtime_get_sync(&dpu_kms->pdev->dev);
876 dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
878 pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev);
880 dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev);
881 if (IS_ERR_OR_NULL(dpu_kms->catalog)) {
882 rc = PTR_ERR(dpu_kms->catalog);
883 if (!dpu_kms->catalog)
885 DPU_ERROR("catalog init failed: %d\n", rc);
886 dpu_kms->catalog = NULL;
891 * Now we need to read the HW catalog and initialize resources such as
892 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
894 rc = _dpu_kms_mmu_init(dpu_kms);
896 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc);
900 rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
902 DPU_ERROR("rm init failed: %d\n", rc);
906 dpu_kms->rm_init = true;
908 dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
910 if (IS_ERR(dpu_kms->hw_mdp)) {
911 rc = PTR_ERR(dpu_kms->hw_mdp);
912 DPU_ERROR("failed to get hw_mdp: %d\n", rc);
913 dpu_kms->hw_mdp = NULL;
917 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
918 u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
920 dpu_kms->hw_vbif[i] = dpu_hw_vbif_init(vbif_idx,
921 dpu_kms->vbif[vbif_idx], dpu_kms->catalog);
922 if (IS_ERR_OR_NULL(dpu_kms->hw_vbif[vbif_idx])) {
923 rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]);
924 if (!dpu_kms->hw_vbif[vbif_idx])
926 DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
927 dpu_kms->hw_vbif[vbif_idx] = NULL;
932 rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog,
933 _dpu_kms_get_clk(dpu_kms, "core"));
935 DPU_ERROR("failed to init perf %d\n", rc);
939 dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog);
940 if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) {
941 rc = PTR_ERR(dpu_kms->hw_intr);
942 DPU_ERROR("hw_intr init failed: %d\n", rc);
943 dpu_kms->hw_intr = NULL;
944 goto hw_intr_init_err;
947 dev->mode_config.min_width = 0;
948 dev->mode_config.min_height = 0;
951 * max crtc width is equal to the max mixer width * 2 and max height is
954 dev->mode_config.max_width =
955 dpu_kms->catalog->caps->max_mixer_width * 2;
956 dev->mode_config.max_height = 4096;
959 * Support format modifiers for compression etc.
961 dev->mode_config.allow_fb_modifiers = true;
964 * _dpu_kms_drm_obj_init should create the DRM related objects
965 * i.e. CRTCs, planes, encoders, connectors and so forth
967 rc = _dpu_kms_drm_obj_init(dpu_kms);
969 DPU_ERROR("modeset init failed: %d\n", rc);
970 goto drm_obj_init_err;
973 dpu_vbif_init_memtypes(dpu_kms);
975 pm_runtime_put_sync(&dpu_kms->pdev->dev);
980 dpu_core_perf_destroy(&dpu_kms->perf);
984 pm_runtime_put_sync(&dpu_kms->pdev->dev);
986 _dpu_kms_hw_destroy(dpu_kms);
991 struct msm_kms *dpu_kms_init(struct drm_device *dev)
993 struct msm_drm_private *priv;
994 struct dpu_kms *dpu_kms;
998 DPU_ERROR("drm device node invalid\n");
999 return ERR_PTR(-EINVAL);
1002 priv = dev->dev_private;
1003 dpu_kms = to_dpu_kms(priv->kms);
1005 irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0);
1007 DPU_ERROR("failed to get irq: %d\n", irq);
1008 return ERR_PTR(irq);
1010 dpu_kms->base.irq = irq;
1012 return &dpu_kms->base;
1015 static int dpu_bind(struct device *dev, struct device *master, void *data)
1017 struct drm_device *ddev = dev_get_drvdata(master);
1018 struct platform_device *pdev = to_platform_device(dev);
1019 struct msm_drm_private *priv = ddev->dev_private;
1020 struct dpu_kms *dpu_kms;
1021 struct dss_module_power *mp;
1024 dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);
1029 ret = msm_dss_parse_clock(pdev, mp);
1031 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
1035 platform_set_drvdata(pdev, dpu_kms);
1037 msm_kms_init(&dpu_kms->base, &kms_funcs);
1038 dpu_kms->dev = ddev;
1039 dpu_kms->pdev = pdev;
1041 pm_runtime_enable(&pdev->dev);
1042 dpu_kms->rpm_enabled = true;
1044 priv->kms = &dpu_kms->base;
1048 static void dpu_unbind(struct device *dev, struct device *master, void *data)
1050 struct platform_device *pdev = to_platform_device(dev);
1051 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
1052 struct dss_module_power *mp = &dpu_kms->mp;
1054 msm_dss_put_clk(mp->clk_config, mp->num_clk);
1055 devm_kfree(&pdev->dev, mp->clk_config);
1058 if (dpu_kms->rpm_enabled)
1059 pm_runtime_disable(&pdev->dev);
1062 static const struct component_ops dpu_ops = {
1064 .unbind = dpu_unbind,
1067 static int dpu_dev_probe(struct platform_device *pdev)
1069 return component_add(&pdev->dev, &dpu_ops);
1072 static int dpu_dev_remove(struct platform_device *pdev)
1074 component_del(&pdev->dev, &dpu_ops);
1078 static int __maybe_unused dpu_runtime_suspend(struct device *dev)
1081 struct platform_device *pdev = to_platform_device(dev);
1082 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
1083 struct dss_module_power *mp = &dpu_kms->mp;
1085 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
1087 DPU_ERROR("clock disable failed rc:%d\n", rc);
1092 static int __maybe_unused dpu_runtime_resume(struct device *dev)
1095 struct platform_device *pdev = to_platform_device(dev);
1096 struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
1097 struct drm_encoder *encoder;
1098 struct drm_device *ddev;
1099 struct dss_module_power *mp = &dpu_kms->mp;
1101 ddev = dpu_kms->dev;
1102 rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
1104 DPU_ERROR("clock enable failed rc:%d\n", rc);
1108 dpu_vbif_init_memtypes(dpu_kms);
1110 drm_for_each_encoder(encoder, ddev)
1111 dpu_encoder_virt_runtime_resume(encoder);
1116 static const struct dev_pm_ops dpu_pm_ops = {
1117 SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
1120 static const struct of_device_id dpu_dt_match[] = {
1121 { .compatible = "qcom,sdm845-dpu", },
1122 { .compatible = "qcom,sc7180-dpu", },
1125 MODULE_DEVICE_TABLE(of, dpu_dt_match);
1127 static struct platform_driver dpu_driver = {
1128 .probe = dpu_dev_probe,
1129 .remove = dpu_dev_remove,
1132 .of_match_table = dpu_dt_match,
1137 void __init msm_dpu_register(void)
1139 platform_driver_register(&dpu_driver);
1142 void __exit msm_dpu_unregister(void)
1144 platform_driver_unregister(&dpu_driver);