1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
8 #include <linux/kernel.h>
13 #define DPU_DBG_NAME "dpu"
17 #ifndef DPU_CSC_MATRIX_COEFF_SIZE
18 #define DPU_CSC_MATRIX_COEFF_SIZE 9
21 #ifndef DPU_CSC_CLAMP_SIZE
22 #define DPU_CSC_CLAMP_SIZE 6
25 #ifndef DPU_CSC_BIAS_SIZE
26 #define DPU_CSC_BIAS_SIZE 3
29 #ifndef DPU_MAX_PLANES
30 #define DPU_MAX_PLANES 4
33 #define PIPES_PER_STAGE 2
34 #ifndef DPU_MAX_DE_CURVES
35 #define DPU_MAX_DE_CURVES 3
38 enum dpu_format_flags {
39 DPU_FORMAT_FLAG_YUV_BIT,
40 DPU_FORMAT_FLAG_DX_BIT,
41 DPU_FORMAT_FLAG_COMPRESSED_BIT,
42 DPU_FORMAT_FLAG_BIT_MAX,
45 #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT)
46 #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT)
47 #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
48 #define DPU_FORMAT_IS_YUV(X) \
49 (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
50 #define DPU_FORMAT_IS_DX(X) \
51 (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
52 #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR)
53 #define DPU_FORMAT_IS_TILE(X) \
54 (((X)->fetch_mode == DPU_FETCH_UBWC) && \
55 !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
56 #define DPU_FORMAT_IS_UBWC(X) \
57 (((X)->fetch_mode == DPU_FETCH_UBWC) && \
58 test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
60 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
61 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
62 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
63 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0)
64 #define DPU_BLEND_FG_INV_ALPHA (1 << 2)
65 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3)
66 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4)
67 #define DPU_BLEND_FG_TRANSP_EN (1 << 5)
68 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8)
69 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8)
70 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8)
71 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8)
72 #define DPU_BLEND_BG_INV_ALPHA (1 << 10)
73 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11)
74 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12)
75 #define DPU_BLEND_BG_TRANSP_EN (1 << 13)
77 #define DPU_VSYNC0_SOURCE_GPIO 0
78 #define DPU_VSYNC1_SOURCE_GPIO 1
79 #define DPU_VSYNC2_SOURCE_GPIO 2
80 #define DPU_VSYNC_SOURCE_INTF_0 3
81 #define DPU_VSYNC_SOURCE_INTF_1 4
82 #define DPU_VSYNC_SOURCE_INTF_2 5
83 #define DPU_VSYNC_SOURCE_INTF_3 6
84 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11
85 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12
86 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13
87 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14
88 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15
90 enum dpu_hw_blk_type {
221 * Historically these values correspond to the values written to the
222 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP
223 * generations this register is NOP, but we keep the values for historical
231 /* old eDP found on 8x74 and 8x84 */
233 /* both DP and eDP, handled by the new DP driver */
236 /* virtual interfaces */
284 * DPU HW,Component order color map
294 * enum dpu_plane_type - defines how the color component pixel packing
295 * @DPU_PLANE_INTERLEAVED : Color components in single plane
296 * @DPU_PLANE_PLANAR : Color component in separate planes
297 * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
299 enum dpu_plane_type {
300 DPU_PLANE_INTERLEAVED,
302 DPU_PLANE_PSEUDO_PLANAR,
306 * enum dpu_chroma_samp_type - chroma sub-samplng type
307 * @DPU_CHROMA_RGB : No chroma subsampling
308 * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled
309 * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled
310 * @DPU_CHROMA_420 : 420 subsampling
312 enum dpu_chroma_samp_type {
320 * dpu_fetch_type - Defines How DPU HW fetches data
321 * @DPU_FETCH_LINEAR : fetch is line by line
322 * @DPU_FETCH_TILE : fetches data in Z order from a tile
323 * @DPU_FETCH_UBWC : fetch and decompress data
325 enum dpu_fetch_type {
332 * Value of enum chosen to fit the number of bits
333 * expected by the HW programming.
336 COLOR_ALPHA_1BIT = 0,
337 COLOR_ALPHA_4BIT = 1,
339 COLOR_5BIT = 1, /* No 5-bit Alpha */
340 COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
341 COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
345 * enum dpu_3d_blend_mode
346 * Desribes how the 3d data is blended
347 * @BLEND_3D_NONE : 3d blending not enabled
348 * @BLEND_3D_FRAME_INT : Frame interleaving
349 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving
350 * @BLEND_3D_V_ROW_INT : vertical row interleaving
351 * @BLEND_3D_COL_INT : column interleaving
354 enum dpu_3d_blend_mode {
363 /** struct dpu_format - defines the format configuration which
364 * allows DPU HW to correctly fetch and decode the format
365 * @base: base msm_format structure containing fourcc code
366 * @fetch_planes: how the color components are packed in pixel format
367 * @element: element color ordering
368 * @bits: element bit widths
369 * @chroma_sample: chroma sub-samplng type
370 * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
371 * @unpack_tight: 0 for loose, 1 for tight
372 * @unpack_count: 0 = 1 component, 1 = 2 component
373 * @bpp: bytes per pixel
374 * @alpha_enable: whether the format has an alpha channel
375 * @num_planes: number of planes (including meta data planes)
376 * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
377 * @flag: usage bit flags
378 * @tile_width: format tile width
379 * @tile_height: format tile height
382 struct msm_format base;
383 enum dpu_plane_type fetch_planes;
384 u8 element[DPU_MAX_PLANES];
385 u8 bits[DPU_MAX_PLANES];
386 enum dpu_chroma_samp_type chroma_sample;
393 enum dpu_fetch_type fetch_mode;
394 DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
398 #define to_dpu_format(x) container_of(x, struct dpu_format, base)
401 * struct dpu_hw_fmt_layout - format information of the source pixel data
402 * @format: pixel format parameters
403 * @num_planes: number of planes (including meta data planes)
404 * @width: image width
405 * @height: image height
406 * @total_size: total size in bytes
407 * @plane_addr: address of each plane
408 * @plane_size: length of each plane
409 * @plane_pitch: pitch of each plane
411 struct dpu_hw_fmt_layout {
412 const struct dpu_format *format;
417 uint32_t plane_addr[DPU_MAX_PLANES];
418 uint32_t plane_size[DPU_MAX_PLANES];
419 uint32_t plane_pitch[DPU_MAX_PLANES];
423 /* matrix coefficients in S15.16 format */
424 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE];
425 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE];
426 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE];
427 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE];
428 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE];
432 * struct dpu_mdss_color - mdss color description
438 struct dpu_mdss_color {
446 * Define bit masks for h/w logging.
448 #define DPU_DBG_MASK_NONE (1 << 0)
449 #define DPU_DBG_MASK_INTF (1 << 1)
450 #define DPU_DBG_MASK_LM (1 << 2)
451 #define DPU_DBG_MASK_CTL (1 << 3)
452 #define DPU_DBG_MASK_PINGPONG (1 << 4)
453 #define DPU_DBG_MASK_SSPP (1 << 5)
454 #define DPU_DBG_MASK_WB (1 << 6)
455 #define DPU_DBG_MASK_TOP (1 << 7)
456 #define DPU_DBG_MASK_VBIF (1 << 8)
457 #define DPU_DBG_MASK_ROT (1 << 9)
458 #define DPU_DBG_MASK_DSPP (1 << 10)
459 #define DPU_DBG_MASK_DSC (1 << 11)
461 #endif /* _DPU_HW_MDSS_H */