drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
   3  */
   4
   5 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   6 #include "dpu_encoder_phys.h"
   7 #include "dpu_hw_interrupts.h"
   8 #include "dpu_hw_merge3d.h"
   9 #include "dpu_core_irq.h"
  10 #include "dpu_formats.h"
  11 #include "dpu_trace.h"
  12 #include "disp/msm_disp_snapshot.h"
  13
  14 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
  15                 (e) && (e)->parent ? \
  16                 (e)->parent->base.id : -1, \
  17                 (e) && (e)->hw_intf ? \
  18                 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
  19
  20 #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
  21                 (e) && (e)->parent ? \
  22                 (e)->parent->base.id : -1, \
  23                 (e) && (e)->hw_intf ? \
  24                 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
  25
  26 #define to_dpu_encoder_phys_vid(x) \
  27         container_of(x, struct dpu_encoder_phys_vid, base)
  28
  29 static bool dpu_encoder_phys_vid_is_master(
  30                 struct dpu_encoder_phys *phys_enc)
  31 {
  32         bool ret = false;
  33
  34         if (phys_enc->split_role != ENC_ROLE_SLAVE)
  35                 ret = true;
  36
  37         return ret;
  38 }
  39
  40 static void drm_mode_to_intf_timing_params(
  41                 const struct dpu_encoder_phys *phys_enc,
  42                 const struct drm_display_mode *mode,
  43                 struct intf_timing_params *timing)
  44 {
  45         memset(timing, 0, sizeof(*timing));
  46
  47         if ((mode->htotal < mode->hsync_end)
  48                         || (mode->hsync_start < mode->hdisplay)
  49                         || (mode->vtotal < mode->vsync_end)
  50                         || (mode->vsync_start < mode->vdisplay)
  51                         || (mode->hsync_end < mode->hsync_start)
  52                         || (mode->vsync_end < mode->vsync_start)) {
  53                 DPU_ERROR(
  54                     "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
  55                                 mode->hsync_start, mode->hsync_end,
  56                                 mode->htotal, mode->hdisplay);
  57                 DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
  58                                 mode->vsync_start, mode->vsync_end,
  59                                 mode->vtotal, mode->vdisplay);
  60                 return;
  61         }
  62
  63         /*
  64          * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
  65          *  Active Region      Front Porch   Sync   Back Porch
  66          * <-----------------><------------><-----><----------->
  67          * <- [hv]display --->
  68          * <--------- [hv]sync_start ------>
  69          * <----------------- [hv]sync_end ------->
  70          * <---------------------------- [hv]total ------------->
  71          */
  72         timing->width = mode->hdisplay; /* active width */
  73         timing->height = mode->vdisplay;        /* active height */
  74         timing->xres = timing->width;
  75         timing->yres = timing->height;
  76         timing->h_back_porch = mode->htotal - mode->hsync_end;
  77         timing->h_front_porch = mode->hsync_start - mode->hdisplay;
  78         timing->v_back_porch = mode->vtotal - mode->vsync_end;
  79         timing->v_front_porch = mode->vsync_start - mode->vdisplay;
  80         timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
  81         timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
  82         timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
  83         timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
  84         timing->border_clr = 0;
  85         timing->underflow_clr = 0xff;
  86         timing->hsync_skew = mode->hskew;
  87
  88         /* DSI controller cannot handle active-low sync signals. */
  89         if (phys_enc->hw_intf->cap->type == INTF_DSI) {
  90                 timing->hsync_polarity = 0;
  91                 timing->vsync_polarity = 0;
  92         }
  93
  94         /* for DP/EDP, Shift timings to align it to bottom right */
  95         if (phys_enc->hw_intf->cap->type == INTF_DP) {
  96                 timing->h_back_porch += timing->h_front_porch;
  97                 timing->h_front_porch = 0;
  98                 timing->v_back_porch += timing->v_front_porch;
  99                 timing->v_front_porch = 0;
 100         }
 101
 102         timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
 103
 104         /*
 105          * for DP, divide the horizonal parameters by 2 when
 106          * widebus is enabled
 107          */
 108         if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
 109                 timing->width = timing->width >> 1;
 110                 timing->xres = timing->xres >> 1;
 111                 timing->h_back_porch = timing->h_back_porch >> 1;
 112                 timing->h_front_porch = timing->h_front_porch >> 1;
 113                 timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
 114         }
 115 }
 116
 117 static u32 get_horizontal_total(const struct intf_timing_params *timing)
 118 {
 119         u32 active = timing->xres;
 120         u32 inactive =
 121             timing->h_back_porch + timing->h_front_porch +
 122             timing->hsync_pulse_width;
 123         return active + inactive;
 124 }
 125
 126 static u32 get_vertical_total(const struct intf_timing_params *timing)
 127 {
 128         u32 active = timing->yres;
 129         u32 inactive =
 130             timing->v_back_porch + timing->v_front_porch +
 131             timing->vsync_pulse_width;
 132         return active + inactive;
 133 }
 134
 135 /*
 136  * programmable_fetch_get_num_lines:
 137  *      Number of fetch lines in vertical front porch
 138  * @timing: Pointer to the intf timing information for the requested mode
 139  *
 140  * Returns the number of fetch lines in vertical front porch at which mdp
 141  * can start fetching the next frame.
 142  *
 143  * Number of needed prefetch lines is anything that cannot be absorbed in the
 144  * start of frame time (back porch + vsync pulse width).
 145  *
 146  * Some panels have very large VFP, however we only need a total number of
 147  * lines based on the chip worst case latencies.
 148  */
 149 static u32 programmable_fetch_get_num_lines(
 150                 struct dpu_encoder_phys *phys_enc,
 151                 const struct intf_timing_params *timing)
 152 {
 153         u32 worst_case_needed_lines =
 154             phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
 155         u32 start_of_frame_lines =
 156             timing->v_back_porch + timing->vsync_pulse_width;
 157         u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
 158         u32 actual_vfp_lines = 0;
 159
 160         /* Fetch must be outside active lines, otherwise undefined. */
 161         if (start_of_frame_lines >= worst_case_needed_lines) {
 162                 DPU_DEBUG_VIDENC(phys_enc,
 163                                 "prog fetch is not needed, large vbp+vsw\n");
 164                 actual_vfp_lines = 0;
 165         } else if (timing->v_front_porch < needed_vfp_lines) {
 166                 /* Warn fetch needed, but not enough porch in panel config */
 167                 pr_warn_once
 168                         ("low vbp+vfp may lead to perf issues in some cases\n");
 169                 DPU_DEBUG_VIDENC(phys_enc,
 170                                 "less vfp than fetch req, using entire vfp\n");
 171                 actual_vfp_lines = timing->v_front_porch;
 172         } else {
 173                 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
 174                 actual_vfp_lines = needed_vfp_lines;
 175         }
 176
 177         DPU_DEBUG_VIDENC(phys_enc,
 178                 "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
 179                 timing->v_front_porch, timing->v_back_porch,
 180                 timing->vsync_pulse_width);
 181         DPU_DEBUG_VIDENC(phys_enc,
 182                 "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
 183                 worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
 184
 185         return actual_vfp_lines;
 186 }
 187
 188 /*
 189  * programmable_fetch_config: Programs HW to prefetch lines by offsetting
 190  *      the start of fetch into the vertical front porch for cases where the
 191  *      vsync pulse width and vertical back porch time is insufficient
 192  *
 193  *      Gets # of lines to pre-fetch, then calculate VSYNC counter value.
 194  *      HW layer requires VSYNC counter of first pixel of tgt VFP line.
 195  *
 196  * @timing: Pointer to the intf timing information for the requested mode
 197  */
 198 static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
 199                                       const struct intf_timing_params *timing)
 200 {
 201         struct intf_prog_fetch f = { 0 };
 202         u32 vfp_fetch_lines = 0;
 203         u32 horiz_total = 0;
 204         u32 vert_total = 0;
 205         u32 vfp_fetch_start_vsync_counter = 0;
 206         unsigned long lock_flags;
 207
 208         if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
 209                 return;
 210
 211         vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
 212         if (vfp_fetch_lines) {
 213                 vert_total = get_vertical_total(timing);
 214                 horiz_total = get_horizontal_total(timing);
 215                 vfp_fetch_start_vsync_counter =
 216                     (vert_total - vfp_fetch_lines) * horiz_total + 1;
 217                 f.enable = 1;
 218                 f.fetch_start = vfp_fetch_start_vsync_counter;
 219         }
 220
 221         DPU_DEBUG_VIDENC(phys_enc,
 222                 "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
 223                 vfp_fetch_lines, vfp_fetch_start_vsync_counter);
 224
 225         spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 226         phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
 227         spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 228 }
 229
 230 static void dpu_encoder_phys_vid_setup_timing_engine(
 231                 struct dpu_encoder_phys *phys_enc)
 232 {
 233         struct drm_display_mode mode;
 234         struct intf_timing_params timing_params = { 0 };
 235         const struct dpu_format *fmt = NULL;
 236         u32 fmt_fourcc = DRM_FORMAT_RGB888;
 237         unsigned long lock_flags;
 238         struct dpu_hw_intf_cfg intf_cfg = { 0 };
 239
 240         drm_mode_init(&mode, &phys_enc->cached_mode);
 241
 242         if (!phys_enc->hw_ctl->ops.setup_intf_cfg) {
 243                 DPU_ERROR("invalid encoder %d\n", phys_enc != NULL);
 244                 return;
 245         }
 246
 247         if (!phys_enc->hw_intf->ops.setup_timing_gen) {
 248                 DPU_ERROR("timing engine setup is not supported\n");
 249                 return;
 250         }
 251
 252         DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
 253         drm_mode_debug_printmodeline(&mode);
 254
 255         if (phys_enc->split_role != ENC_ROLE_SOLO) {
 256                 mode.hdisplay >>= 1;
 257                 mode.htotal >>= 1;
 258                 mode.hsync_start >>= 1;
 259                 mode.hsync_end >>= 1;
 260
 261                 DPU_DEBUG_VIDENC(phys_enc,
 262                         "split_role %d, halve horizontal %d %d %d %d\n",
 263                         phys_enc->split_role,
 264                         mode.hdisplay, mode.htotal,
 265                         mode.hsync_start, mode.hsync_end);
 266         }
 267
 268         drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
 269
 270         fmt = dpu_get_dpu_format(fmt_fourcc);
 271         DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
 272
 273         intf_cfg.intf = phys_enc->hw_intf->idx;
 274         intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
 275         intf_cfg.stream_sel = 0; /* Don't care value for video mode */
 276         intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
 277         intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
 278         if (phys_enc->hw_pp->merge_3d)
 279                 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
 280
 281         spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 282         phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
 283                         &timing_params, fmt);
 284         phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
 285
 286         /* setup which pp blk will connect to this intf */
 287         if (phys_enc->hw_intf->ops.bind_pingpong_blk)
 288                 phys_enc->hw_intf->ops.bind_pingpong_blk(
 289                                 phys_enc->hw_intf,
 290                                 true,
 291                                 phys_enc->hw_pp->idx);
 292
 293         if (phys_enc->hw_pp->merge_3d)
 294                 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);
 295
 296         spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 297
 298         programmable_fetch_config(phys_enc, &timing_params);
 299 }
 300
 301 static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
 302 {
 303         struct dpu_encoder_phys *phys_enc = arg;
 304         struct dpu_hw_ctl *hw_ctl;
 305         unsigned long lock_flags;
 306         u32 flush_register = 0;
 307
 308         hw_ctl = phys_enc->hw_ctl;
 309
 310         DPU_ATRACE_BEGIN("vblank_irq");
 311
 312         dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
 313
 314         atomic_read(&phys_enc->pending_kickoff_cnt);
 315
 316         /*
 317          * only decrement the pending flush count if we've actually flushed
 318          * hardware. due to sw irq latency, vblank may have already happened
 319          * so we need to double-check with hw that it accepted the flush bits
 320          */
 321         spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 322         if (hw_ctl->ops.get_flush_register)
 323                 flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
 324
 325         if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
 326                 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
 327         spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 328
 329         /* Signal any waiting atomic commit thread */
 330         wake_up_all(&phys_enc->pending_kickoff_wq);
 331
 332         dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
 333                         DPU_ENCODER_FRAME_EVENT_DONE);
 334
 335         DPU_ATRACE_END("vblank_irq");
 336 }
 337
 338 static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
 339 {
 340         struct dpu_encoder_phys *phys_enc = arg;
 341
 342         dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);
 343 }
 344
 345 static bool dpu_encoder_phys_vid_needs_single_flush(
 346                 struct dpu_encoder_phys *phys_enc)
 347 {
 348         return phys_enc->split_role != ENC_ROLE_SOLO;
 349 }
 350
 351 static void dpu_encoder_phys_vid_atomic_mode_set(
 352                 struct dpu_encoder_phys *phys_enc,
 353                 struct drm_crtc_state *crtc_state,
 354                 struct drm_connector_state *conn_state)
 355 {
 356         phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
 357
 358         phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
 359 }
 360
 361 static int dpu_encoder_phys_vid_control_vblank_irq(
 362                 struct dpu_encoder_phys *phys_enc,
 363                 bool enable)
 364 {
 365         int ret = 0;
 366         int refcount;
 367
 368         refcount = atomic_read(&phys_enc->vblank_refcount);
 369
 370         /* Slave encoders don't report vblank */
 371         if (!dpu_encoder_phys_vid_is_master(phys_enc))
 372                 goto end;
 373
 374         /* protect against negative */
 375         if (!enable && refcount == 0) {
 376                 ret = -EINVAL;
 377                 goto end;
 378         }
 379
 380         DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
 381                       atomic_read(&phys_enc->vblank_refcount));
 382
 383         if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
 384                 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms,
 385                                 phys_enc->irq[INTR_IDX_VSYNC],
 386                                 dpu_encoder_phys_vid_vblank_irq,
 387                                 phys_enc);
 388         else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
 389                 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
 390                                 phys_enc->irq[INTR_IDX_VSYNC]);
 391
 392 end:
 393         if (ret) {
 394                 DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
 395                           DRMID(phys_enc->parent),
 396                           phys_enc->hw_intf->idx - INTF_0, ret, enable,
 397                           refcount);
 398         }
 399         return ret;
 400 }
 401
 402 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
 403 {
 404         struct dpu_hw_ctl *ctl;
 405
 406         ctl = phys_enc->hw_ctl;
 407
 408         DPU_DEBUG_VIDENC(phys_enc, "\n");
 409
 410         if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
 411                 return;
 412
 413         dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
 414
 415         dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
 416
 417         /*
 418          * For single flush cases (dual-ctl or pp-split), skip setting the
 419          * flush bit for the slave intf, since both intfs use same ctl
 420          * and HW will only flush the master.
 421          */
 422         if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&
 423                 !dpu_encoder_phys_vid_is_master(phys_enc))
 424                 goto skip_flush;
 425
 426         ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
 427         if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
 428                 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);
 429
 430 skip_flush:
 431         DPU_DEBUG_VIDENC(phys_enc,
 432                 "update pending flush ctl %d intf %d\n",
 433                 ctl->idx - CTL_0, phys_enc->hw_intf->idx);
 434
 435         atomic_set(&phys_enc->underrun_cnt, 0);
 436
 437         /* ctl_flush & timing engine enable will be triggered by framework */
 438         if (phys_enc->enable_state == DPU_ENC_DISABLED)
 439                 phys_enc->enable_state = DPU_ENC_ENABLING;
 440 }
 441
 442 static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc)
 443 {
 444         DPU_DEBUG_VIDENC(phys_enc, "\n");
 445         kfree(phys_enc);
 446 }
 447
 448 static int dpu_encoder_phys_vid_wait_for_vblank(
 449                 struct dpu_encoder_phys *phys_enc)
 450 {
 451         struct dpu_encoder_wait_info wait_info;
 452         int ret;
 453
 454         wait_info.wq = &phys_enc->pending_kickoff_wq;
 455         wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
 456         wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 457
 458         if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
 459                 return 0;
 460         }
 461
 462         /* Wait for kickoff to complete */
 463         ret = dpu_encoder_helper_wait_for_irq(phys_enc,
 464                         phys_enc->irq[INTR_IDX_VSYNC],
 465                         dpu_encoder_phys_vid_vblank_irq,
 466                         &wait_info);
 467
 468         if (ret == -ETIMEDOUT) {
 469                 dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
 470         }
 471
 472         return ret;
 473 }
 474
 475 static int dpu_encoder_phys_vid_wait_for_commit_done(
 476                 struct dpu_encoder_phys *phys_enc)
 477 {
 478         struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
 479         int ret;
 480
 481         if (!hw_ctl)
 482                 return 0;
 483
 484         ret = wait_event_timeout(phys_enc->pending_kickoff_wq,
 485                 (hw_ctl->ops.get_flush_register(hw_ctl) == 0),
 486                 msecs_to_jiffies(50));
 487         if (ret <= 0) {
 488                 DPU_ERROR("vblank timeout\n");
 489                 return -ETIMEDOUT;
 490         }
 491
 492         return 0;
 493 }
 494
 495 static void dpu_encoder_phys_vid_prepare_for_kickoff(
 496                 struct dpu_encoder_phys *phys_enc)
 497 {
 498         struct dpu_hw_ctl *ctl;
 499         int rc;
 500         struct drm_encoder *drm_enc;
 501
 502         drm_enc = phys_enc->parent;
 503
 504         ctl = phys_enc->hw_ctl;
 505         if (!ctl->ops.wait_reset_status)
 506                 return;
 507
 508         /*
 509          * hw supports hardware initiated ctl reset, so before we kickoff a new
 510          * frame, need to check and wait for hw initiated ctl reset completion
 511          */
 512         rc = ctl->ops.wait_reset_status(ctl);
 513         if (rc) {
 514                 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
 515                                 ctl->idx, rc);
 516                 msm_disp_snapshot_state(drm_enc->dev);
 517                 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
 518                                 phys_enc->irq[INTR_IDX_VSYNC]);
 519         }
 520 }
 521
 522 static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
 523 {
 524         unsigned long lock_flags;
 525         int ret;
 526
 527         if (!phys_enc->parent || !phys_enc->parent->dev) {
 528                 DPU_ERROR("invalid encoder/device\n");
 529                 return;
 530         }
 531
 532         if (!phys_enc->hw_intf) {
 533                 DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
 534                                 phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
 535                 return;
 536         }
 537
 538         if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
 539                 return;
 540
 541         if (phys_enc->enable_state == DPU_ENC_DISABLED) {
 542                 DPU_ERROR("already disabled\n");
 543                 return;
 544         }
 545
 546         spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 547         phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
 548         if (dpu_encoder_phys_vid_is_master(phys_enc))
 549                 dpu_encoder_phys_inc_pending(phys_enc);
 550         spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 551
 552         /*
 553          * Wait for a vsync so we know the ENABLE=0 latched before
 554          * the (connector) source of the vsync's gets disabled,
 555          * otherwise we end up in a funny state if we re-enable
 556          * before the disable latches, which results that some of
 557          * the settings changes for the new modeset (like new
 558          * scanout buffer) don't latch properly..
 559          */
 560         if (dpu_encoder_phys_vid_is_master(phys_enc)) {
 561                 ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
 562                 if (ret) {
 563                         atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 564                         DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
 565                                   DRMID(phys_enc->parent),
 566                                   phys_enc->hw_intf->idx - INTF_0, ret);
 567                 }
 568         }
 569
 570         phys_enc->enable_state = DPU_ENC_DISABLED;
 571 }
 572
 573 static void dpu_encoder_phys_vid_handle_post_kickoff(
 574                 struct dpu_encoder_phys *phys_enc)
 575 {
 576         unsigned long lock_flags;
 577
 578         /*
 579          * Video mode must flush CTL before enabling timing engine
 580          * Video encoders need to turn on their interfaces now
 581          */
 582         if (phys_enc->enable_state == DPU_ENC_ENABLING) {
 583                 trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
 584                                     phys_enc->hw_intf->idx - INTF_0);
 585                 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 586                 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
 587                 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 588                 phys_enc->enable_state = DPU_ENC_ENABLED;
 589         }
 590 }
 591
 592 static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
 593                 bool enable)
 594 {
 595         int ret;
 596
 597         trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
 598                             phys_enc->hw_intf->idx - INTF_0,
 599                             enable,
 600                             atomic_read(&phys_enc->vblank_refcount));
 601
 602         if (enable) {
 603                 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
 604                 if (WARN_ON(ret))
 605                         return;
 606
 607                 dpu_core_irq_register_callback(phys_enc->dpu_kms,
 608                                 phys_enc->irq[INTR_IDX_UNDERRUN],
 609                                 dpu_encoder_phys_vid_underrun_irq,
 610                                 phys_enc);
 611         } else {
 612                 dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
 613                 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
 614                                 phys_enc->irq[INTR_IDX_UNDERRUN]);
 615         }
 616 }
 617
 618 static int dpu_encoder_phys_vid_get_line_count(
 619                 struct dpu_encoder_phys *phys_enc)
 620 {
 621         if (!dpu_encoder_phys_vid_is_master(phys_enc))
 622                 return -EINVAL;
 623
 624         if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
 625                 return -EINVAL;
 626
 627         return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
 628 }
 629
 630 static int dpu_encoder_phys_vid_get_frame_count(
 631                 struct dpu_encoder_phys *phys_enc)
 632 {
 633         struct intf_status s = {0};
 634         u32 fetch_start = 0;
 635         struct drm_display_mode mode;
 636
 637         drm_mode_init(&mode, &phys_enc->cached_mode);
 638
 639         if (!dpu_encoder_phys_vid_is_master(phys_enc))
 640                 return -EINVAL;
 641
 642         if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status)
 643                 return -EINVAL;
 644
 645         phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s);
 646
 647         if (s.is_prog_fetch_en && s.is_en) {
 648                 fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay);
 649                 if ((s.line_count > fetch_start) &&
 650                         (s.line_count <= mode.vtotal))
 651                         return s.frame_count + 1;
 652         }
 653
 654         return s.frame_count;
 655 }
 656
 657 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
 658 {
 659         ops->is_master = dpu_encoder_phys_vid_is_master;
 660         ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;
 661         ops->enable = dpu_encoder_phys_vid_enable;
 662         ops->disable = dpu_encoder_phys_vid_disable;
 663         ops->destroy = dpu_encoder_phys_vid_destroy;
 664         ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
 665         ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
 666         ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;
 667         ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;
 668         ops->irq_control = dpu_encoder_phys_vid_irq_control;
 669         ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
 670         ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
 671         ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
 672         ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
 673         ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count;
 674 }
 675
 676 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 677                 struct dpu_enc_phys_init_params *p)
 678 {
 679         struct dpu_encoder_phys *phys_enc = NULL;
 680         int i;
 681
 682         if (!p) {
 683                 DPU_ERROR("failed to create encoder due to invalid parameter\n");
 684                 return ERR_PTR(-EINVAL);
 685         }
 686
 687         phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL);
 688         if (!phys_enc) {
 689                 DPU_ERROR("failed to create encoder due to memory allocation error\n");
 690                 return ERR_PTR(-ENOMEM);
 691         }
 692
 693         phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
 694         phys_enc->intf_idx = p->intf_idx;
 695
 696         DPU_DEBUG_VIDENC(phys_enc, "\n");
 697
 698         dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
 699         phys_enc->parent = p->parent;
 700         phys_enc->dpu_kms = p->dpu_kms;
 701         phys_enc->split_role = p->split_role;
 702         phys_enc->intf_mode = INTF_MODE_VIDEO;
 703         phys_enc->enc_spinlock = p->enc_spinlock;
 704         for (i = 0; i < ARRAY_SIZE(phys_enc->irq); i++)
 705                 phys_enc->irq[i] = -EINVAL;
 706
 707         atomic_set(&phys_enc->vblank_refcount, 0);
 708         atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 709         init_waitqueue_head(&phys_enc->pending_kickoff_wq);
 710         phys_enc->enable_state = DPU_ENC_DISABLED;
 711
 712         DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx);
 713
 714         return phys_enc;
 715 }