1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
6 #ifndef __DPU_ENCODER_PHYS_H__
7 #define __DPU_ENCODER_PHYS_H__
9 #include <linux/jiffies.h>
12 #include "dpu_hw_intf.h"
13 #include "dpu_hw_pingpong.h"
14 #include "dpu_hw_ctl.h"
15 #include "dpu_hw_top.h"
16 #include "dpu_encoder.h"
19 #define DPU_ENCODER_NAME_MAX 16
21 /* wait for at most 2 vsync for lowest refresh rate (24hz) */
22 #define KICKOFF_TIMEOUT_MS 84
23 #define KICKOFF_TIMEOUT_JIFFIES msecs_to_jiffies(KICKOFF_TIMEOUT_MS)
26 * enum dpu_enc_split_role - Role this physical encoder will play in a
27 * split-panel configuration, where one panel is master, and others slaves.
28 * Masters have extra responsibilities, like managing the VBLANK IRQ.
29 * @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master.
30 * @ENC_ROLE_MASTER: This encoder is the master of a split panel config.
31 * @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config.
33 enum dpu_enc_split_role {
40 * enum dpu_enc_enable_state - current enabled state of the physical encoder
41 * @DPU_ENC_DISABLING: Encoder transitioning to disable state
42 * Events bounding transition are encoder type specific
43 * @DPU_ENC_DISABLED: Encoder is disabled
44 * @DPU_ENC_ENABLING: Encoder transitioning to enabled
45 * Events bounding transition are encoder type specific
46 * @DPU_ENC_ENABLED: Encoder is enabled
47 * @DPU_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset
48 * to recover from a previous error
50 enum dpu_enc_enable_state {
55 DPU_ENC_ERR_NEEDS_HW_RESET
58 struct dpu_encoder_phys;
61 * struct dpu_encoder_virt_ops - Interface the containing virtual encoder
62 * provides for the physical encoders to use to callback.
63 * @handle_vblank_virt: Notify virtual encoder of vblank IRQ reception
64 * Note: This is called from IRQ handler context.
65 * @handle_underrun_virt: Notify virtual encoder of underrun IRQ reception
66 * Note: This is called from IRQ handler context.
67 * @handle_frame_done: Notify virtual encoder that this phys encoder
68 * completes last request frame.
70 struct dpu_encoder_virt_ops {
71 void (*handle_vblank_virt)(struct drm_encoder *,
72 struct dpu_encoder_phys *phys);
73 void (*handle_underrun_virt)(struct drm_encoder *,
74 struct dpu_encoder_phys *phys);
75 void (*handle_frame_done)(struct drm_encoder *,
76 struct dpu_encoder_phys *phys, u32 event);
80 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to
81 * the containing virtual encoder.
82 * @late_register: DRM Call. Add Userspace interfaces, debugfs.
83 * @prepare_commit: MSM Atomic Call, start of atomic commit sequence
84 * @is_master: Whether this phys_enc is the current master
85 * encoder. Can be switched at enable time. Based
86 * on split_role and current mode (CMD/VID).
87 * @atomic_mode_set: DRM Call. Set a DRM mode.
88 * This likely caches the mode, for use at enable.
89 * @enable: DRM Call. Enable a DRM mode.
90 * @disable: DRM Call. Disable mode.
91 * @atomic_check: DRM Call. Atomic check new DRM state.
92 * @destroy: DRM Call. Destroy and release resources.
93 * @control_vblank_irq Register/Deregister for VBLANK IRQ
94 * @wait_for_commit_done: Wait for hardware to have flushed the
95 * current pending frames to hardware
96 * @wait_for_tx_complete: Wait for hardware to transfer the pixels
98 * @wait_for_vblank: Wait for VBLANK, for sub-driver internal use
99 * @prepare_for_kickoff: Do any work necessary prior to a kickoff
100 * For CMD encoder, may wait for previous tx done
101 * @handle_post_kickoff: Do any work necessary post-kickoff work
102 * @trigger_start: Process start event on physical encoder
103 * @needs_single_flush: Whether encoder slaves need to be flushed
104 * @irq_control: Handler to enable/disable all the encoder IRQs
105 * @prepare_idle_pc: phys encoder can update the vsync_enable status
106 * on idle power collapse prepare
107 * @restore: Restore all the encoder configs.
108 * @get_line_count: Obtain current vertical line count
111 struct dpu_encoder_phys_ops {
112 int (*late_register)(struct dpu_encoder_phys *encoder,
113 struct dentry *debugfs_root);
114 void (*prepare_commit)(struct dpu_encoder_phys *encoder);
115 bool (*is_master)(struct dpu_encoder_phys *encoder);
116 void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
117 struct drm_crtc_state *crtc_state,
118 struct drm_connector_state *conn_state);
119 void (*enable)(struct dpu_encoder_phys *encoder);
120 void (*disable)(struct dpu_encoder_phys *encoder);
121 int (*atomic_check)(struct dpu_encoder_phys *encoder,
122 struct drm_crtc_state *crtc_state,
123 struct drm_connector_state *conn_state);
124 void (*destroy)(struct dpu_encoder_phys *encoder);
125 int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
126 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
127 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
128 int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
129 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
130 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
131 void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
132 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
133 void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
134 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
135 void (*restore)(struct dpu_encoder_phys *phys);
136 int (*get_line_count)(struct dpu_encoder_phys *phys);
137 int (*get_frame_count)(struct dpu_encoder_phys *phys);
141 * enum dpu_intr_idx - dpu encoder interrupt index
142 * @INTR_IDX_VSYNC: Vsync interrupt for video mode panel
143 * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel
144 * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel
145 * @INTR_IDX_RDPTR: Readpointer done unterrupt for cmd mode panel
157 * dpu_encoder_irq - tracking structure for interrupts
158 * @name: string name of interrupt
159 * @intr_idx: Encoder interrupt enumeration
160 * @irq_idx: IRQ interface lookup index from DPU IRQ framework
161 * will be -EINVAL if IRQ is not registered
162 * @irq_cb: interrupt callback
164 struct dpu_encoder_irq {
166 enum dpu_intr_idx intr_idx;
168 struct dpu_irq_callback cb;
172 * struct dpu_encoder_phys - physical encoder that drives a single INTF block
173 * tied to a specific panel / sub-panel. Abstract type, sub-classed by
174 * phys_vid or phys_cmd for video mode or command mode encs respectively.
175 * @parent: Pointer to the containing virtual encoder
176 * @ops: Operations exposed to the virtual encoder
177 * @parent_ops: Callbacks exposed by the parent to the phys_enc
178 * @hw_mdptop: Hardware interface to the top registers
179 * @hw_ctl: Hardware interface to the ctl registers
180 * @hw_pp: Hardware interface to the ping pong registers
181 * @hw_intf: Hardware interface to the intf registers
182 * @dpu_kms: Pointer to the dpu_kms top level
183 * @cached_mode: DRM mode cached at mode_set time, acted on in enable
184 * @enabled: Whether the encoder has enabled and running a mode
185 * @split_role: Role to play in a split-panel configuration
186 * @intf_mode: Interface mode
187 * @intf_idx: Interface index on dpu hardware
188 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
189 * @enable_state: Enable state tracking
190 * @vblank_refcount: Reference count of vblank request
191 * @vsync_cnt: Vsync count for the physical encoder
192 * @underrun_cnt: Underrun count for the physical encoder
193 * @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs
194 * vs. the number of done/vblank irqs. Should hover
195 * between 0-2 Incremented when a new kickoff is
196 * scheduled. Decremented in irq handler
197 * @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start
199 * @pending_kickoff_wq: Wait queue for blocking until kickoff completes
200 * @irq: IRQ tracking structures
202 struct dpu_encoder_phys {
203 struct drm_encoder *parent;
204 struct dpu_encoder_phys_ops ops;
205 const struct dpu_encoder_virt_ops *parent_ops;
206 struct dpu_hw_mdp *hw_mdptop;
207 struct dpu_hw_ctl *hw_ctl;
208 struct dpu_hw_pingpong *hw_pp;
209 struct dpu_hw_intf *hw_intf;
210 struct dpu_kms *dpu_kms;
211 struct drm_display_mode cached_mode;
212 enum dpu_enc_split_role split_role;
213 enum dpu_intf_mode intf_mode;
214 enum dpu_intf intf_idx;
215 spinlock_t *enc_spinlock;
216 enum dpu_enc_enable_state enable_state;
217 atomic_t vblank_refcount;
219 atomic_t underrun_cnt;
220 atomic_t pending_ctlstart_cnt;
221 atomic_t pending_kickoff_cnt;
222 wait_queue_head_t pending_kickoff_wq;
223 struct dpu_encoder_irq irq[INTR_IDX_MAX];
226 static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)
228 atomic_inc_return(&phys->pending_ctlstart_cnt);
229 return atomic_inc_return(&phys->pending_kickoff_cnt);
233 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
234 * mode specific operations
235 * @base: Baseclass physical encoder structure
236 * @intf_idx: Intf Block index used by this phys encoder
237 * @stream_sel: Stream selection for multi-stream interfaces
238 * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt
239 * after ctl_start instead of before next frame kickoff
240 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors
241 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
242 * @pending_vblank_wq: Wait queue for blocking until VBLANK received
244 struct dpu_encoder_phys_cmd {
245 struct dpu_encoder_phys base;
247 bool serialize_wait4pp;
248 int pp_timeout_report_cnt;
249 atomic_t pending_vblank_cnt;
250 wait_queue_head_t pending_vblank_wq;
254 * struct dpu_enc_phys_init_params - initialization parameters for phys encs
255 * @dpu_kms: Pointer to the dpu_kms top level
256 * @parent: Pointer to the containing virtual encoder
257 * @parent_ops: Callbacks exposed by the parent to the phys_enc
258 * @split_role: Role to play in a split-panel configuration
259 * @intf_idx: Interface index this phys_enc will control
260 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
262 struct dpu_enc_phys_init_params {
263 struct dpu_kms *dpu_kms;
264 struct drm_encoder *parent;
265 const struct dpu_encoder_virt_ops *parent_ops;
266 enum dpu_enc_split_role split_role;
267 enum dpu_intf intf_idx;
268 spinlock_t *enc_spinlock;
272 * dpu_encoder_wait_info - container for passing arguments to irq wait functions
273 * @wq: wait queue structure
274 * @atomic_cnt: wait until atomic_cnt equals zero
275 * @timeout_ms: timeout value in milliseconds
277 struct dpu_encoder_wait_info {
278 wait_queue_head_t *wq;
279 atomic_t *atomic_cnt;
284 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder
285 * @p: Pointer to init params structure
286 * Return: Error code or newly allocated encoder
288 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
289 struct dpu_enc_phys_init_params *p);
292 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder
293 * @p: Pointer to init params structure
294 * Return: Error code or newly allocated encoder
296 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
297 struct dpu_enc_phys_init_params *p);
300 * dpu_encoder_helper_trigger_start - control start helper function
301 * This helper function may be optionally specified by physical
302 * encoders if they require ctl_start triggering.
303 * @phys_enc: Pointer to physical encoder structure
305 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
307 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
308 struct dpu_encoder_phys *phys_enc)
310 struct dpu_crtc_state *dpu_cstate;
312 if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
313 return BLEND_3D_NONE;
315 dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
317 if (phys_enc->split_role == ENC_ROLE_SOLO &&
318 dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
319 return BLEND_3D_H_ROW_INT;
321 return BLEND_3D_NONE;
325 * dpu_encoder_helper_split_config - split display configuration helper function
326 * This helper function may be used by physical encoders to configure
327 * the split display related registers.
328 * @phys_enc: Pointer to physical encoder structure
329 * @interface: enum dpu_intf setting
331 void dpu_encoder_helper_split_config(
332 struct dpu_encoder_phys *phys_enc,
333 enum dpu_intf interface);
336 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
337 * timed out, including reporting frame error event to crtc and debug dump
338 * @phys_enc: Pointer to physical encoder structure
339 * @intr_idx: Failing interrupt index
341 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
342 enum dpu_intr_idx intr_idx);
345 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
346 * note: will call dpu_encoder_helper_wait_for_irq on timeout
347 * @phys_enc: Pointer to physical encoder structure
348 * @intr_idx: encoder interrupt index
349 * @wait_info: wait info struct
350 * @Return: 0 or -ERROR
352 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
353 enum dpu_intr_idx intr_idx,
354 struct dpu_encoder_wait_info *wait_info);
357 * dpu_encoder_helper_register_irq - register and enable an irq
358 * @phys_enc: Pointer to physical encoder structure
359 * @intr_idx: encoder interrupt index
360 * @Return: 0 or -ERROR
362 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
363 enum dpu_intr_idx intr_idx);
366 * dpu_encoder_helper_unregister_irq - unregister and disable an irq
367 * @phys_enc: Pointer to physical encoder structure
368 * @intr_idx: encoder interrupt index
369 * @Return: 0 or -ERROR
371 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
372 enum dpu_intr_idx intr_idx);
374 #endif /* __dpu_encoder_phys_H__ */