drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

   1 /*
   2  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
  20 #include <linux/kthread.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23
  24 #include "msm_drv.h"
  25 #include "dpu_kms.h"
  26 #include <drm/drm_crtc.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include "dpu_hwio.h"
  29 #include "dpu_hw_catalog.h"
  30 #include "dpu_hw_intf.h"
  31 #include "dpu_hw_ctl.h"
  32 #include "dpu_formats.h"
  33 #include "dpu_encoder_phys.h"
  34 #include "dpu_crtc.h"
  35 #include "dpu_trace.h"
  36 #include "dpu_core_irq.h"
  37
  38 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\
  39                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  40
  41 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
  42                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  43
  44 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\
  45                 (p) ? (p)->parent->base.id : -1, \
  46                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  47                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  48                 ##__VA_ARGS__)
  49
  50 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
  51                 (p) ? (p)->parent->base.id : -1, \
  52                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  53                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  54                 ##__VA_ARGS__)
  55
  56 /*
  57  * Two to anticipate panels that can do cmd/vid dynamic switching
  58  * plan is to create all possible physical encoder types, and switch between
  59  * them at runtime
  60  */
  61 #define NUM_PHYS_ENCODER_TYPES 2
  62
  63 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
  64         (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
  65
  66 #define MAX_CHANNELS_PER_ENC 2
  67
  68 #define IDLE_SHORT_TIMEOUT      1
  69
  70 #define MAX_VDISPLAY_SPLIT 1080
  71
  72 /**
  73  * enum dpu_enc_rc_events - events for resource control state machine
  74  * @DPU_ENC_RC_EVENT_KICKOFF:
  75  *      This event happens at NORMAL priority.
  76  *      Event that signals the start of the transfer. When this event is
  77  *      received, enable MDP/DSI core clocks. Regardless of the previous
  78  *      state, the resource should be in ON state at the end of this event.
  79  * @DPU_ENC_RC_EVENT_FRAME_DONE:
  80  *      This event happens at INTERRUPT level.
  81  *      Event signals the end of the data transfer after the PP FRAME_DONE
  82  *      event. At the end of this event, a delayed work is scheduled to go to
  83  *      IDLE_PC state after IDLE_TIMEOUT time.
  84  * @DPU_ENC_RC_EVENT_PRE_STOP:
  85  *      This event happens at NORMAL priority.
  86  *      This event, when received during the ON state, leave the RC STATE
  87  *      in the PRE_OFF state. It should be followed by the STOP event as
  88  *      part of encoder disable.
  89  *      If received during IDLE or OFF states, it will do nothing.
  90  * @DPU_ENC_RC_EVENT_STOP:
  91  *      This event happens at NORMAL priority.
  92  *      When this event is received, disable all the MDP/DSI core clocks, and
  93  *      disable IRQs. It should be called from the PRE_OFF or IDLE states.
  94  *      IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  95  *      PRE_OFF is expected when PRE_STOP was executed during the ON state.
  96  *      Resource state should be in OFF at the end of the event.
  97  * @DPU_ENC_RC_EVENT_ENTER_IDLE:
  98  *      This event happens at NORMAL priority from a work item.
  99  *      Event signals that there were no frame updates for IDLE_TIMEOUT time.
 100  *      This would disable MDP/DSI core clocks and change the resource state
 101  *      to IDLE.
 102  */
 103 enum dpu_enc_rc_events {
 104         DPU_ENC_RC_EVENT_KICKOFF = 1,
 105         DPU_ENC_RC_EVENT_FRAME_DONE,
 106         DPU_ENC_RC_EVENT_PRE_STOP,
 107         DPU_ENC_RC_EVENT_STOP,
 108         DPU_ENC_RC_EVENT_ENTER_IDLE
 109 };
 110
 111 /*
 112  * enum dpu_enc_rc_states - states that the resource control maintains
 113  * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
 114  * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
 115  * @DPU_ENC_RC_STATE_ON: Resource is in ON state
 116  * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
 117  * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
 118  */
 119 enum dpu_enc_rc_states {
 120         DPU_ENC_RC_STATE_OFF,
 121         DPU_ENC_RC_STATE_PRE_OFF,
 122         DPU_ENC_RC_STATE_ON,
 123         DPU_ENC_RC_STATE_IDLE
 124 };
 125
 126 /**
 127  * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
 128  *      encoders. Virtual encoder manages one "logical" display. Physical
 129  *      encoders manage one intf block, tied to a specific panel/sub-panel.
 130  *      Virtual encoder defers as much as possible to the physical encoders.
 131  *      Virtual encoder registers itself with the DRM Framework as the encoder.
 132  * @base:               drm_encoder base class for registration with DRM
 133  * @enc_spinlock:       Virtual-Encoder-Wide Spin Lock for IRQ purposes
 134  * @bus_scaling_client: Client handle to the bus scaling interface
 135  * @enabled:            True if the encoder is active, protected by enc_lock
 136  * @num_phys_encs:      Actual number of physical encoders contained.
 137  * @phys_encs:          Container of physical encoders managed.
 138  * @cur_master:         Pointer to the current master in this mode. Optimization
 139  *                      Only valid after enable. Cleared as disable.
 140  * @hw_pp               Handle to the pingpong blocks used for the display. No.
 141  *                      pingpong blocks can be different than num_phys_encs.
 142  * @intfs_swapped       Whether or not the phys_enc interfaces have been swapped
 143  *                      for partial update right-only cases, such as pingpong
 144  *                      split where virtual pingpong does not generate IRQs
 145  * @crtc_vblank_cb:     Callback into the upper layer / CRTC for
 146  *                      notification of the VBLANK
 147  * @crtc_vblank_cb_data:        Data from upper layer for VBLANK notification
 148  * @crtc_kickoff_cb:            Callback into CRTC that will flush & start
 149  *                              all CTL paths
 150  * @crtc_kickoff_cb_data:       Opaque user data given to crtc_kickoff_cb
 151  * @debugfs_root:               Debug file system root file node
 152  * @enc_lock:                   Lock around physical encoder
 153  *                              create/destroy/enable/disable
 154  * @frame_busy_mask:            Bitmask tracking which phys_enc we are still
 155  *                              busy processing current command.
 156  *                              Bit0 = phys_encs[0] etc.
 157  * @crtc_frame_event_cb:        callback handler for frame event
 158  * @crtc_frame_event_cb_data:   callback handler private data
 159  * @frame_done_timeout:         frame done timeout in Hz
 160  * @frame_done_timer:           watchdog timer for frame done event
 161  * @vsync_event_timer:          vsync timer
 162  * @disp_info:                  local copy of msm_display_info struct
 163  * @idle_pc_supported:          indicate if idle power collaps is supported
 164  * @rc_lock:                    resource control mutex lock to protect
 165  *                              virt encoder over various state changes
 166  * @rc_state:                   resource controller state
 167  * @delayed_off_work:           delayed worker to schedule disabling of
 168  *                              clks and resources after IDLE_TIMEOUT time.
 169  * @vsync_event_work:           worker to handle vsync event for autorefresh
 170  * @topology:                   topology of the display
 171  * @mode_set_complete:          flag to indicate modeset completion
 172  * @idle_timeout:               idle timeout duration in milliseconds
 173  */
 174 struct dpu_encoder_virt {
 175         struct drm_encoder base;
 176         spinlock_t enc_spinlock;
 177         uint32_t bus_scaling_client;
 178
 179         bool enabled;
 180
 181         unsigned int num_phys_encs;
 182         struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
 183         struct dpu_encoder_phys *cur_master;
 184         struct dpu_encoder_phys *cur_slave;
 185         struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
 186
 187         bool intfs_swapped;
 188
 189         void (*crtc_vblank_cb)(void *);
 190         void *crtc_vblank_cb_data;
 191
 192         struct dentry *debugfs_root;
 193         struct mutex enc_lock;
 194         DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
 195         void (*crtc_frame_event_cb)(void *, u32 event);
 196         void *crtc_frame_event_cb_data;
 197
 198         atomic_t frame_done_timeout;
 199         struct timer_list frame_done_timer;
 200         struct timer_list vsync_event_timer;
 201
 202         struct msm_display_info disp_info;
 203
 204         bool idle_pc_supported;
 205         struct mutex rc_lock;
 206         enum dpu_enc_rc_states rc_state;
 207         struct kthread_delayed_work delayed_off_work;
 208         struct kthread_work vsync_event_work;
 209         struct msm_display_topology topology;
 210         bool mode_set_complete;
 211
 212         u32 idle_timeout;
 213 };
 214
 215 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 216
 217 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
 218                 enum dpu_intr_idx intr_idx)
 219 {
 220         DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
 221                   DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
 222                   phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
 223
 224         if (phys_enc->parent_ops->handle_frame_done)
 225                 phys_enc->parent_ops->handle_frame_done(
 226                                 phys_enc->parent, phys_enc,
 227                                 DPU_ENCODER_FRAME_EVENT_ERROR);
 228 }
 229
 230 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
 231                 int32_t hw_id, struct dpu_encoder_wait_info *info);
 232
 233 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 234                 enum dpu_intr_idx intr_idx,
 235                 struct dpu_encoder_wait_info *wait_info)
 236 {
 237         struct dpu_encoder_irq *irq;
 238         u32 irq_status;
 239         int ret;
 240
 241         if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
 242                 DPU_ERROR("invalid params\n");
 243                 return -EINVAL;
 244         }
 245         irq = &phys_enc->irq[intr_idx];
 246
 247         /* note: do master / slave checking outside */
 248
 249         /* return EWOULDBLOCK since we know the wait isn't necessary */
 250         if (phys_enc->enable_state == DPU_ENC_DISABLED) {
 251                 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
 252                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 253                           irq->irq_idx);
 254                 return -EWOULDBLOCK;
 255         }
 256
 257         if (irq->irq_idx < 0) {
 258                 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
 259                               DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 260                               irq->name);
 261                 return 0;
 262         }
 263
 264         DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
 265                       DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 266                       irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
 267                       atomic_read(wait_info->atomic_cnt));
 268
 269         ret = dpu_encoder_helper_wait_event_timeout(
 270                         DRMID(phys_enc->parent),
 271                         irq->hw_idx,
 272                         wait_info);
 273
 274         if (ret <= 0) {
 275                 irq_status = dpu_core_irq_read(phys_enc->dpu_kms,
 276                                 irq->irq_idx, true);
 277                 if (irq_status) {
 278                         unsigned long flags;
 279
 280                         DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
 281                                       "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
 282                                       DRMID(phys_enc->parent), intr_idx,
 283                                       irq->hw_idx, irq->irq_idx,
 284                                       phys_enc->hw_pp->idx - PINGPONG_0,
 285                                       atomic_read(wait_info->atomic_cnt));
 286                         local_irq_save(flags);
 287                         irq->cb.func(phys_enc, irq->irq_idx);
 288                         local_irq_restore(flags);
 289                         ret = 0;
 290                 } else {
 291                         ret = -ETIMEDOUT;
 292                         DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
 293                                       "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
 294                                       DRMID(phys_enc->parent), intr_idx,
 295                                       irq->hw_idx, irq->irq_idx,
 296                                       phys_enc->hw_pp->idx - PINGPONG_0,
 297                                       atomic_read(wait_info->atomic_cnt));
 298                 }
 299         } else {
 300                 ret = 0;
 301                 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
 302                         intr_idx, irq->hw_idx, irq->irq_idx,
 303                         phys_enc->hw_pp->idx - PINGPONG_0,
 304                         atomic_read(wait_info->atomic_cnt));
 305         }
 306
 307         return ret;
 308 }
 309
 310 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 311                 enum dpu_intr_idx intr_idx)
 312 {
 313         struct dpu_encoder_irq *irq;
 314         int ret = 0;
 315
 316         if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
 317                 DPU_ERROR("invalid params\n");
 318                 return -EINVAL;
 319         }
 320         irq = &phys_enc->irq[intr_idx];
 321
 322         if (irq->irq_idx >= 0) {
 323                 DPU_DEBUG_PHYS(phys_enc,
 324                                 "skipping already registered irq %s type %d\n",
 325                                 irq->name, irq->intr_type);
 326                 return 0;
 327         }
 328
 329         irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
 330                         irq->intr_type, irq->hw_idx);
 331         if (irq->irq_idx < 0) {
 332                 DPU_ERROR_PHYS(phys_enc,
 333                         "failed to lookup IRQ index for %s type:%d\n",
 334                         irq->name, irq->intr_type);
 335                 return -EINVAL;
 336         }
 337
 338         ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx,
 339                         &irq->cb);
 340         if (ret) {
 341                 DPU_ERROR_PHYS(phys_enc,
 342                         "failed to register IRQ callback for %s\n",
 343                         irq->name);
 344                 irq->irq_idx = -EINVAL;
 345                 return ret;
 346         }
 347
 348         ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 349         if (ret) {
 350                 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
 351                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 352                           irq->irq_idx);
 353                 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
 354                                 irq->irq_idx, &irq->cb);
 355                 irq->irq_idx = -EINVAL;
 356                 return ret;
 357         }
 358
 359         trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
 360                                 irq->hw_idx, irq->irq_idx);
 361
 362         return ret;
 363 }
 364
 365 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
 366                 enum dpu_intr_idx intr_idx)
 367 {
 368         struct dpu_encoder_irq *irq;
 369         int ret;
 370
 371         if (!phys_enc) {
 372                 DPU_ERROR("invalid encoder\n");
 373                 return -EINVAL;
 374         }
 375         irq = &phys_enc->irq[intr_idx];
 376
 377         /* silently skip irqs that weren't registered */
 378         if (irq->irq_idx < 0) {
 379                 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
 380                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 381                           irq->irq_idx);
 382                 return 0;
 383         }
 384
 385         ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 386         if (ret) {
 387                 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
 388                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 389                           irq->irq_idx, ret);
 390         }
 391
 392         ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
 393                         &irq->cb);
 394         if (ret) {
 395                 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
 396                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 397                           irq->irq_idx, ret);
 398         }
 399
 400         trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
 401                                              irq->hw_idx, irq->irq_idx);
 402
 403         irq->irq_idx = -EINVAL;
 404
 405         return 0;
 406 }
 407
 408 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 409                                   struct dpu_encoder_hw_resources *hw_res)
 410 {
 411         struct dpu_encoder_virt *dpu_enc = NULL;
 412         int i = 0;
 413
 414         dpu_enc = to_dpu_encoder_virt(drm_enc);
 415         DPU_DEBUG_ENC(dpu_enc, "\n");
 416
 417         /* Query resources used by phys encs, expected to be without overlap */
 418         memset(hw_res, 0, sizeof(*hw_res));
 419
 420         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 421                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 422
 423                 if (phys && phys->ops.get_hw_resources)
 424                         phys->ops.get_hw_resources(phys, hw_res);
 425         }
 426 }
 427
 428 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
 429 {
 430         struct dpu_encoder_virt *dpu_enc = NULL;
 431         int i = 0;
 432
 433         if (!drm_enc) {
 434                 DPU_ERROR("invalid encoder\n");
 435                 return;
 436         }
 437
 438         dpu_enc = to_dpu_encoder_virt(drm_enc);
 439         DPU_DEBUG_ENC(dpu_enc, "\n");
 440
 441         mutex_lock(&dpu_enc->enc_lock);
 442
 443         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 444                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 445
 446                 if (phys && phys->ops.destroy) {
 447                         phys->ops.destroy(phys);
 448                         --dpu_enc->num_phys_encs;
 449                         dpu_enc->phys_encs[i] = NULL;
 450                 }
 451         }
 452
 453         if (dpu_enc->num_phys_encs)
 454                 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
 455                                 dpu_enc->num_phys_encs);
 456         dpu_enc->num_phys_encs = 0;
 457         mutex_unlock(&dpu_enc->enc_lock);
 458
 459         drm_encoder_cleanup(drm_enc);
 460         mutex_destroy(&dpu_enc->enc_lock);
 461
 462         kfree(dpu_enc);
 463 }
 464
 465 void dpu_encoder_helper_split_config(
 466                 struct dpu_encoder_phys *phys_enc,
 467                 enum dpu_intf interface)
 468 {
 469         struct dpu_encoder_virt *dpu_enc;
 470         struct split_pipe_cfg cfg = { 0 };
 471         struct dpu_hw_mdp *hw_mdptop;
 472         struct msm_display_info *disp_info;
 473
 474         if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
 475                 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
 476                 return;
 477         }
 478
 479         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
 480         hw_mdptop = phys_enc->hw_mdptop;
 481         disp_info = &dpu_enc->disp_info;
 482
 483         if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
 484                 return;
 485
 486         /**
 487          * disable split modes since encoder will be operating in as the only
 488          * encoder, either for the entire use case in the case of, for example,
 489          * single DSI, or for this frame in the case of left/right only partial
 490          * update.
 491          */
 492         if (phys_enc->split_role == ENC_ROLE_SOLO) {
 493                 if (hw_mdptop->ops.setup_split_pipe)
 494                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 495                 return;
 496         }
 497
 498         cfg.en = true;
 499         cfg.mode = phys_enc->intf_mode;
 500         cfg.intf = interface;
 501
 502         if (cfg.en && phys_enc->ops.needs_single_flush &&
 503                         phys_enc->ops.needs_single_flush(phys_enc))
 504                 cfg.split_flush_en = true;
 505
 506         if (phys_enc->split_role == ENC_ROLE_MASTER) {
 507                 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
 508
 509                 if (hw_mdptop->ops.setup_split_pipe)
 510                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 511         }
 512 }
 513
 514 static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
 515                 struct drm_display_mode *adj_mode)
 516 {
 517         struct drm_display_mode *cur_mode;
 518
 519         if (!connector || !adj_mode)
 520                 return;
 521
 522         list_for_each_entry(cur_mode, &connector->modes, head) {
 523                 if (cur_mode->vdisplay == adj_mode->vdisplay &&
 524                         cur_mode->hdisplay == adj_mode->hdisplay &&
 525                         cur_mode->vrefresh == adj_mode->vrefresh) {
 526                         adj_mode->private = cur_mode->private;
 527                         adj_mode->private_flags |= cur_mode->private_flags;
 528                 }
 529         }
 530 }
 531
 532 static struct msm_display_topology dpu_encoder_get_topology(
 533                         struct dpu_encoder_virt *dpu_enc,
 534                         struct dpu_kms *dpu_kms,
 535                         struct drm_display_mode *mode)
 536 {
 537         struct msm_display_topology topology;
 538         int i, intf_count = 0;
 539
 540         for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
 541                 if (dpu_enc->phys_encs[i])
 542                         intf_count++;
 543
 544         /* User split topology for width > 1080 */
 545         topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
 546         topology.num_enc = 0;
 547         topology.num_intf = intf_count;
 548
 549         return topology;
 550 }
 551 static int dpu_encoder_virt_atomic_check(
 552                 struct drm_encoder *drm_enc,
 553                 struct drm_crtc_state *crtc_state,
 554                 struct drm_connector_state *conn_state)
 555 {
 556         struct dpu_encoder_virt *dpu_enc;
 557         struct msm_drm_private *priv;
 558         struct dpu_kms *dpu_kms;
 559         const struct drm_display_mode *mode;
 560         struct drm_display_mode *adj_mode;
 561         struct msm_display_topology topology;
 562         int i = 0;
 563         int ret = 0;
 564
 565         if (!drm_enc || !crtc_state || !conn_state) {
 566                 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
 567                                 drm_enc != 0, crtc_state != 0, conn_state != 0);
 568                 return -EINVAL;
 569         }
 570
 571         dpu_enc = to_dpu_encoder_virt(drm_enc);
 572         DPU_DEBUG_ENC(dpu_enc, "\n");
 573
 574         priv = drm_enc->dev->dev_private;
 575         dpu_kms = to_dpu_kms(priv->kms);
 576         mode = &crtc_state->mode;
 577         adj_mode = &crtc_state->adjusted_mode;
 578         trace_dpu_enc_atomic_check(DRMID(drm_enc));
 579
 580         /*
 581          * display drivers may populate private fields of the drm display mode
 582          * structure while registering possible modes of a connector with DRM.
 583          * These private fields are not populated back while DRM invokes
 584          * the mode_set callbacks. This module retrieves and populates the
 585          * private fields of the given mode.
 586          */
 587         _dpu_encoder_adjust_mode(conn_state->connector, adj_mode);
 588
 589         /* perform atomic check on the first physical encoder (master) */
 590         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 591                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 592
 593                 if (phys && phys->ops.atomic_check)
 594                         ret = phys->ops.atomic_check(phys, crtc_state,
 595                                         conn_state);
 596                 else if (phys && phys->ops.mode_fixup)
 597                         if (!phys->ops.mode_fixup(phys, mode, adj_mode))
 598                                 ret = -EINVAL;
 599
 600                 if (ret) {
 601                         DPU_ERROR_ENC(dpu_enc,
 602                                         "mode unsupported, phys idx %d\n", i);
 603                         break;
 604                 }
 605         }
 606
 607         topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 608
 609         /* Reserve dynamic resources now. Indicating AtomicTest phase */
 610         if (!ret) {
 611                 /*
 612                  * Avoid reserving resources when mode set is pending. Topology
 613                  * info may not be available to complete reservation.
 614                  */
 615                 if (drm_atomic_crtc_needs_modeset(crtc_state)
 616                                 && dpu_enc->mode_set_complete) {
 617                         ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
 618                                              topology, true);
 619                         dpu_enc->mode_set_complete = false;
 620                 }
 621         }
 622
 623         if (!ret)
 624                 drm_mode_set_crtcinfo(adj_mode, 0);
 625
 626         trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags,
 627                         adj_mode->private_flags);
 628
 629         return ret;
 630 }
 631
 632 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
 633                         struct msm_display_info *disp_info)
 634 {
 635         struct dpu_vsync_source_cfg vsync_cfg = { 0 };
 636         struct msm_drm_private *priv;
 637         struct dpu_kms *dpu_kms;
 638         struct dpu_hw_mdp *hw_mdptop;
 639         struct drm_encoder *drm_enc;
 640         int i;
 641
 642         if (!dpu_enc || !disp_info) {
 643                 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
 644                                         dpu_enc != NULL, disp_info != NULL);
 645                 return;
 646         } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
 647                 DPU_ERROR("invalid num phys enc %d/%d\n",
 648                                 dpu_enc->num_phys_encs,
 649                                 (int) ARRAY_SIZE(dpu_enc->hw_pp));
 650                 return;
 651         }
 652
 653         drm_enc = &dpu_enc->base;
 654         /* this pointers are checked in virt_enable_helper */
 655         priv = drm_enc->dev->dev_private;
 656
 657         dpu_kms = to_dpu_kms(priv->kms);
 658         if (!dpu_kms) {
 659                 DPU_ERROR("invalid dpu_kms\n");
 660                 return;
 661         }
 662
 663         hw_mdptop = dpu_kms->hw_mdp;
 664         if (!hw_mdptop) {
 665                 DPU_ERROR("invalid mdptop\n");
 666                 return;
 667         }
 668
 669         if (hw_mdptop->ops.setup_vsync_source &&
 670                         disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
 671                 for (i = 0; i < dpu_enc->num_phys_encs; i++)
 672                         vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
 673
 674                 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
 675                 if (disp_info->is_te_using_watchdog_timer)
 676                         vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
 677                 else
 678                         vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
 679
 680                 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
 681         }
 682 }
 683
 684 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
 685 {
 686         struct dpu_encoder_virt *dpu_enc;
 687         int i;
 688
 689         if (!drm_enc) {
 690                 DPU_ERROR("invalid encoder\n");
 691                 return;
 692         }
 693
 694         dpu_enc = to_dpu_encoder_virt(drm_enc);
 695
 696         DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
 697         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 698                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 699
 700                 if (phys && phys->ops.irq_control)
 701                         phys->ops.irq_control(phys, enable);
 702         }
 703
 704 }
 705
 706 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 707                 bool enable)
 708 {
 709         struct msm_drm_private *priv;
 710         struct dpu_kms *dpu_kms;
 711         struct dpu_encoder_virt *dpu_enc;
 712
 713         dpu_enc = to_dpu_encoder_virt(drm_enc);
 714         priv = drm_enc->dev->dev_private;
 715         dpu_kms = to_dpu_kms(priv->kms);
 716
 717         trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
 718
 719         if (!dpu_enc->cur_master) {
 720                 DPU_ERROR("encoder master not set\n");
 721                 return;
 722         }
 723
 724         if (enable) {
 725                 /* enable DPU core clks */
 726                 pm_runtime_get_sync(&dpu_kms->pdev->dev);
 727
 728                 /* enable all the irq */
 729                 _dpu_encoder_irq_control(drm_enc, true);
 730
 731         } else {
 732                 /* disable all the irq */
 733                 _dpu_encoder_irq_control(drm_enc, false);
 734
 735                 /* disable DPU core clks */
 736                 pm_runtime_put_sync(&dpu_kms->pdev->dev);
 737         }
 738
 739 }
 740
 741 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 742                 u32 sw_event)
 743 {
 744         struct dpu_encoder_virt *dpu_enc;
 745         struct msm_drm_private *priv;
 746         struct msm_drm_thread *disp_thread;
 747         bool is_vid_mode = false;
 748
 749         if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private ||
 750                         !drm_enc->crtc) {
 751                 DPU_ERROR("invalid parameters\n");
 752                 return -EINVAL;
 753         }
 754         dpu_enc = to_dpu_encoder_virt(drm_enc);
 755         priv = drm_enc->dev->dev_private;
 756         is_vid_mode = dpu_enc->disp_info.capabilities &
 757                                                 MSM_DISPLAY_CAP_VID_MODE;
 758
 759         if (drm_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
 760                 DPU_ERROR("invalid crtc index\n");
 761                 return -EINVAL;
 762         }
 763         disp_thread = &priv->disp_thread[drm_enc->crtc->index];
 764
 765         /*
 766          * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
 767          * events and return early for other events (ie wb display).
 768          */
 769         if (!dpu_enc->idle_pc_supported &&
 770                         (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
 771                         sw_event != DPU_ENC_RC_EVENT_STOP &&
 772                         sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
 773                 return 0;
 774
 775         trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
 776                          dpu_enc->rc_state, "begin");
 777
 778         switch (sw_event) {
 779         case DPU_ENC_RC_EVENT_KICKOFF:
 780                 /* cancel delayed off work, if any */
 781                 if (kthread_cancel_delayed_work_sync(
 782                                 &dpu_enc->delayed_off_work))
 783                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 784                                         sw_event);
 785
 786                 mutex_lock(&dpu_enc->rc_lock);
 787
 788                 /* return if the resource control is already in ON state */
 789                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 790                         DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
 791                                       DRMID(drm_enc), sw_event);
 792                         mutex_unlock(&dpu_enc->rc_lock);
 793                         return 0;
 794                 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
 795                                 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
 796                         DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
 797                                       DRMID(drm_enc), sw_event,
 798                                       dpu_enc->rc_state);
 799                         mutex_unlock(&dpu_enc->rc_lock);
 800                         return -EINVAL;
 801                 }
 802
 803                 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
 804                         _dpu_encoder_irq_control(drm_enc, true);
 805                 else
 806                         _dpu_encoder_resource_control_helper(drm_enc, true);
 807
 808                 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
 809
 810                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 811                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 812                                  "kickoff");
 813
 814                 mutex_unlock(&dpu_enc->rc_lock);
 815                 break;
 816
 817         case DPU_ENC_RC_EVENT_FRAME_DONE:
 818                 /*
 819                  * mutex lock is not used as this event happens at interrupt
 820                  * context. And locking is not required as, the other events
 821                  * like KICKOFF and STOP does a wait-for-idle before executing
 822                  * the resource_control
 823                  */
 824                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 825                         DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
 826                                       DRMID(drm_enc), sw_event,
 827                                       dpu_enc->rc_state);
 828                         return -EINVAL;
 829                 }
 830
 831                 /*
 832                  * schedule off work item only when there are no
 833                  * frames pending
 834                  */
 835                 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
 836                         DRM_DEBUG_KMS("id:%d skip schedule work\n",
 837                                       DRMID(drm_enc));
 838                         return 0;
 839                 }
 840
 841                 kthread_queue_delayed_work(
 842                         &disp_thread->worker,
 843                         &dpu_enc->delayed_off_work,
 844                         msecs_to_jiffies(dpu_enc->idle_timeout));
 845
 846                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 847                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 848                                  "frame done");
 849                 break;
 850
 851         case DPU_ENC_RC_EVENT_PRE_STOP:
 852                 /* cancel delayed off work, if any */
 853                 if (kthread_cancel_delayed_work_sync(
 854                                 &dpu_enc->delayed_off_work))
 855                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 856                                         sw_event);
 857
 858                 mutex_lock(&dpu_enc->rc_lock);
 859
 860                 if (is_vid_mode &&
 861                           dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 862                         _dpu_encoder_irq_control(drm_enc, true);
 863                 }
 864                 /* skip if is already OFF or IDLE, resources are off already */
 865                 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
 866                                 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 867                         DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
 868                                       DRMID(drm_enc), sw_event,
 869                                       dpu_enc->rc_state);
 870                         mutex_unlock(&dpu_enc->rc_lock);
 871                         return 0;
 872                 }
 873
 874                 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
 875
 876                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 877                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 878                                  "pre stop");
 879
 880                 mutex_unlock(&dpu_enc->rc_lock);
 881                 break;
 882
 883         case DPU_ENC_RC_EVENT_STOP:
 884                 mutex_lock(&dpu_enc->rc_lock);
 885
 886                 /* return if the resource control is already in OFF state */
 887                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
 888                         DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
 889                                       DRMID(drm_enc), sw_event);
 890                         mutex_unlock(&dpu_enc->rc_lock);
 891                         return 0;
 892                 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 893                         DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
 894                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 895                         mutex_unlock(&dpu_enc->rc_lock);
 896                         return -EINVAL;
 897                 }
 898
 899                 /**
 900                  * expect to arrive here only if in either idle state or pre-off
 901                  * and in IDLE state the resources are already disabled
 902                  */
 903                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
 904                         _dpu_encoder_resource_control_helper(drm_enc, false);
 905
 906                 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
 907
 908                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 909                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 910                                  "stop");
 911
 912                 mutex_unlock(&dpu_enc->rc_lock);
 913                 break;
 914
 915         case DPU_ENC_RC_EVENT_ENTER_IDLE:
 916                 mutex_lock(&dpu_enc->rc_lock);
 917
 918                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 919                         DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
 920                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 921                         mutex_unlock(&dpu_enc->rc_lock);
 922                         return 0;
 923                 }
 924
 925                 /*
 926                  * if we are in ON but a frame was just kicked off,
 927                  * ignore the IDLE event, it's probably a stale timer event
 928                  */
 929                 if (dpu_enc->frame_busy_mask[0]) {
 930                         DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
 931                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 932                         mutex_unlock(&dpu_enc->rc_lock);
 933                         return 0;
 934                 }
 935
 936                 if (is_vid_mode)
 937                         _dpu_encoder_irq_control(drm_enc, false);
 938                 else
 939                         _dpu_encoder_resource_control_helper(drm_enc, false);
 940
 941                 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
 942
 943                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 944                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 945                                  "idle");
 946
 947                 mutex_unlock(&dpu_enc->rc_lock);
 948                 break;
 949
 950         default:
 951                 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
 952                           sw_event);
 953                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 954                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 955                                  "error");
 956                 break;
 957         }
 958
 959         trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 960                          dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 961                          "end");
 962         return 0;
 963 }
 964
 965 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 966                                       struct drm_display_mode *mode,
 967                                       struct drm_display_mode *adj_mode)
 968 {
 969         struct dpu_encoder_virt *dpu_enc;
 970         struct msm_drm_private *priv;
 971         struct dpu_kms *dpu_kms;
 972         struct list_head *connector_list;
 973         struct drm_connector *conn = NULL, *conn_iter;
 974         struct dpu_rm_hw_iter pp_iter, ctl_iter;
 975         struct msm_display_topology topology;
 976         struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
 977         int i = 0, ret;
 978
 979         if (!drm_enc) {
 980                 DPU_ERROR("invalid encoder\n");
 981                 return;
 982         }
 983
 984         dpu_enc = to_dpu_encoder_virt(drm_enc);
 985         DPU_DEBUG_ENC(dpu_enc, "\n");
 986
 987         priv = drm_enc->dev->dev_private;
 988         dpu_kms = to_dpu_kms(priv->kms);
 989         connector_list = &dpu_kms->dev->mode_config.connector_list;
 990
 991         trace_dpu_enc_mode_set(DRMID(drm_enc));
 992
 993         list_for_each_entry(conn_iter, connector_list, head)
 994                 if (conn_iter->encoder == drm_enc)
 995                         conn = conn_iter;
 996
 997         if (!conn) {
 998                 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n");
 999                 return;
1000         } else if (!conn->state) {
1001                 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n");
1002                 return;
1003         }
1004
1005         topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
1006
1007         /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
1008         ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_enc->crtc->state,
1009                              topology, false);
1010         if (ret) {
1011                 DPU_ERROR_ENC(dpu_enc,
1012                                 "failed to reserve hw resources, %d\n", ret);
1013                 return;
1014         }
1015
1016         dpu_rm_init_hw_iter(&pp_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG);
1017         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1018                 dpu_enc->hw_pp[i] = NULL;
1019                 if (!dpu_rm_get_hw(&dpu_kms->rm, &pp_iter))
1020                         break;
1021                 dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
1022         }
1023
1024         dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
1025         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1026                 if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter))
1027                         break;
1028                 hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
1029         }
1030
1031         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1032                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1033
1034                 if (phys) {
1035                         if (!dpu_enc->hw_pp[i]) {
1036                                 DPU_ERROR_ENC(dpu_enc, "no pp block assigned"
1037                                              "at idx: %d\n", i);
1038                                 return;
1039                         }
1040
1041                         if (!hw_ctl[i]) {
1042                                 DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
1043                                              "at idx: %d\n", i);
1044                                 return;
1045                         }
1046
1047                         phys->hw_pp = dpu_enc->hw_pp[i];
1048                         phys->hw_ctl = hw_ctl[i];
1049
1050                         phys->connector = conn->state->connector;
1051                         if (phys->ops.mode_set)
1052                                 phys->ops.mode_set(phys, mode, adj_mode);
1053                 }
1054         }
1055
1056         dpu_enc->mode_set_complete = true;
1057 }
1058
1059 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1060 {
1061         struct dpu_encoder_virt *dpu_enc = NULL;
1062         struct msm_drm_private *priv;
1063         struct dpu_kms *dpu_kms;
1064
1065         if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
1066                 DPU_ERROR("invalid parameters\n");
1067                 return;
1068         }
1069
1070         priv = drm_enc->dev->dev_private;
1071         dpu_kms = to_dpu_kms(priv->kms);
1072         if (!dpu_kms) {
1073                 DPU_ERROR("invalid dpu_kms\n");
1074                 return;
1075         }
1076
1077         dpu_enc = to_dpu_encoder_virt(drm_enc);
1078         if (!dpu_enc || !dpu_enc->cur_master) {
1079                 DPU_ERROR("invalid dpu encoder/master\n");
1080                 return;
1081         }
1082
1083         if (dpu_enc->cur_master->hw_mdptop &&
1084                         dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
1085                 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
1086                                 dpu_enc->cur_master->hw_mdptop,
1087                                 dpu_kms->catalog);
1088
1089         _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1090 }
1091
1092 void dpu_encoder_virt_restore(struct drm_encoder *drm_enc)
1093 {
1094         struct dpu_encoder_virt *dpu_enc = NULL;
1095         int i;
1096
1097         if (!drm_enc) {
1098                 DPU_ERROR("invalid encoder\n");
1099                 return;
1100         }
1101         dpu_enc = to_dpu_encoder_virt(drm_enc);
1102
1103         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1104                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1105
1106                 if (phys && (phys != dpu_enc->cur_master) && phys->ops.restore)
1107                         phys->ops.restore(phys);
1108         }
1109
1110         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1111                 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1112
1113         _dpu_encoder_virt_enable_helper(drm_enc);
1114 }
1115
1116 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1117 {
1118         struct dpu_encoder_virt *dpu_enc = NULL;
1119         int ret = 0;
1120         struct drm_display_mode *cur_mode = NULL;
1121
1122         if (!drm_enc) {
1123                 DPU_ERROR("invalid encoder\n");
1124                 return;
1125         }
1126         dpu_enc = to_dpu_encoder_virt(drm_enc);
1127
1128         mutex_lock(&dpu_enc->enc_lock);
1129         cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1130
1131         trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1132                              cur_mode->vdisplay);
1133
1134         /* always enable slave encoder before master */
1135         if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1136                 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1137
1138         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1139                 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1140
1141         ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1142         if (ret) {
1143                 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1144                                 ret);
1145                 goto out;
1146         }
1147
1148         _dpu_encoder_virt_enable_helper(drm_enc);
1149
1150         dpu_enc->enabled = true;
1151
1152 out:
1153         mutex_unlock(&dpu_enc->enc_lock);
1154 }
1155
1156 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1157 {
1158         struct dpu_encoder_virt *dpu_enc = NULL;
1159         struct msm_drm_private *priv;
1160         struct dpu_kms *dpu_kms;
1161         struct drm_display_mode *mode;
1162         int i = 0;
1163
1164         if (!drm_enc) {
1165                 DPU_ERROR("invalid encoder\n");
1166                 return;
1167         } else if (!drm_enc->dev) {
1168                 DPU_ERROR("invalid dev\n");
1169                 return;
1170         } else if (!drm_enc->dev->dev_private) {
1171                 DPU_ERROR("invalid dev_private\n");
1172                 return;
1173         }
1174
1175         dpu_enc = to_dpu_encoder_virt(drm_enc);
1176         DPU_DEBUG_ENC(dpu_enc, "\n");
1177
1178         mutex_lock(&dpu_enc->enc_lock);
1179         dpu_enc->enabled = false;
1180
1181         mode = &drm_enc->crtc->state->adjusted_mode;
1182
1183         priv = drm_enc->dev->dev_private;
1184         dpu_kms = to_dpu_kms(priv->kms);
1185
1186         trace_dpu_enc_disable(DRMID(drm_enc));
1187
1188         /* wait for idle */
1189         dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1190
1191         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1192
1193         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1194                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1195
1196                 if (phys && phys->ops.disable)
1197                         phys->ops.disable(phys);
1198         }
1199
1200         /* after phys waits for frame-done, should be no more frames pending */
1201         if (atomic_xchg(&dpu_enc->frame_done_timeout, 0)) {
1202                 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1203                 del_timer_sync(&dpu_enc->frame_done_timer);
1204         }
1205
1206         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1207
1208         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1209                 if (dpu_enc->phys_encs[i])
1210                         dpu_enc->phys_encs[i]->connector = NULL;
1211         }
1212
1213         DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1214
1215         dpu_rm_release(&dpu_kms->rm, drm_enc);
1216
1217         mutex_unlock(&dpu_enc->enc_lock);
1218 }
1219
1220 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
1221                 enum dpu_intf_type type, u32 controller_id)
1222 {
1223         int i = 0;
1224
1225         for (i = 0; i < catalog->intf_count; i++) {
1226                 if (catalog->intf[i].type == type
1227                     && catalog->intf[i].controller_id == controller_id) {
1228                         return catalog->intf[i].id;
1229                 }
1230         }
1231
1232         return INTF_MAX;
1233 }
1234
1235 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1236                 struct dpu_encoder_phys *phy_enc)
1237 {
1238         struct dpu_encoder_virt *dpu_enc = NULL;
1239         unsigned long lock_flags;
1240
1241         if (!drm_enc || !phy_enc)
1242                 return;
1243
1244         DPU_ATRACE_BEGIN("encoder_vblank_callback");
1245         dpu_enc = to_dpu_encoder_virt(drm_enc);
1246
1247         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1248         if (dpu_enc->crtc_vblank_cb)
1249                 dpu_enc->crtc_vblank_cb(dpu_enc->crtc_vblank_cb_data);
1250         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1251
1252         atomic_inc(&phy_enc->vsync_cnt);
1253         DPU_ATRACE_END("encoder_vblank_callback");
1254 }
1255
1256 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1257                 struct dpu_encoder_phys *phy_enc)
1258 {
1259         if (!phy_enc)
1260                 return;
1261
1262         DPU_ATRACE_BEGIN("encoder_underrun_callback");
1263         atomic_inc(&phy_enc->underrun_cnt);
1264         trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1265                                   atomic_read(&phy_enc->underrun_cnt));
1266         DPU_ATRACE_END("encoder_underrun_callback");
1267 }
1268
1269 void dpu_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
1270                 void (*vbl_cb)(void *), void *vbl_data)
1271 {
1272         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1273         unsigned long lock_flags;
1274         bool enable;
1275         int i;
1276
1277         enable = vbl_cb ? true : false;
1278
1279         if (!drm_enc) {
1280                 DPU_ERROR("invalid encoder\n");
1281                 return;
1282         }
1283         trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1284
1285         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1286         dpu_enc->crtc_vblank_cb = vbl_cb;
1287         dpu_enc->crtc_vblank_cb_data = vbl_data;
1288         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1289
1290         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1291                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1292
1293                 if (phys && phys->ops.control_vblank_irq)
1294                         phys->ops.control_vblank_irq(phys, enable);
1295         }
1296 }
1297
1298 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1299                 void (*frame_event_cb)(void *, u32 event),
1300                 void *frame_event_cb_data)
1301 {
1302         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1303         unsigned long lock_flags;
1304         bool enable;
1305
1306         enable = frame_event_cb ? true : false;
1307
1308         if (!drm_enc) {
1309                 DPU_ERROR("invalid encoder\n");
1310                 return;
1311         }
1312         trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1313
1314         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1315         dpu_enc->crtc_frame_event_cb = frame_event_cb;
1316         dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1317         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1318 }
1319
1320 static void dpu_encoder_frame_done_callback(
1321                 struct drm_encoder *drm_enc,
1322                 struct dpu_encoder_phys *ready_phys, u32 event)
1323 {
1324         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1325         unsigned int i;
1326
1327         if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1328                         | DPU_ENCODER_FRAME_EVENT_ERROR
1329                         | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1330
1331                 if (!dpu_enc->frame_busy_mask[0]) {
1332                         /**
1333                          * suppress frame_done without waiter,
1334                          * likely autorefresh
1335                          */
1336                         trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
1337                                         event, ready_phys->intf_idx);
1338                         return;
1339                 }
1340
1341                 /* One of the physical encoders has become idle */
1342                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1343                         if (dpu_enc->phys_encs[i] == ready_phys) {
1344                                 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1345                                                 dpu_enc->frame_busy_mask[0]);
1346                                 clear_bit(i, dpu_enc->frame_busy_mask);
1347                         }
1348                 }
1349
1350                 if (!dpu_enc->frame_busy_mask[0]) {
1351                         atomic_set(&dpu_enc->frame_done_timeout, 0);
1352                         del_timer(&dpu_enc->frame_done_timer);
1353
1354                         dpu_encoder_resource_control(drm_enc,
1355                                         DPU_ENC_RC_EVENT_FRAME_DONE);
1356
1357                         if (dpu_enc->crtc_frame_event_cb)
1358                                 dpu_enc->crtc_frame_event_cb(
1359                                         dpu_enc->crtc_frame_event_cb_data,
1360                                         event);
1361                 }
1362         } else {
1363                 if (dpu_enc->crtc_frame_event_cb)
1364                         dpu_enc->crtc_frame_event_cb(
1365                                 dpu_enc->crtc_frame_event_cb_data, event);
1366         }
1367 }
1368
1369 static void dpu_encoder_off_work(struct kthread_work *work)
1370 {
1371         struct dpu_encoder_virt *dpu_enc = container_of(work,
1372                         struct dpu_encoder_virt, delayed_off_work.work);
1373
1374         if (!dpu_enc) {
1375                 DPU_ERROR("invalid dpu encoder\n");
1376                 return;
1377         }
1378
1379         dpu_encoder_resource_control(&dpu_enc->base,
1380                                                 DPU_ENC_RC_EVENT_ENTER_IDLE);
1381
1382         dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1383                                 DPU_ENCODER_FRAME_EVENT_IDLE);
1384 }
1385
1386 /**
1387  * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1388  * drm_enc: Pointer to drm encoder structure
1389  * phys: Pointer to physical encoder structure
1390  * extra_flush_bits: Additional bit mask to include in flush trigger
1391  */
1392 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1393                 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits,
1394                 bool async)
1395 {
1396         struct dpu_hw_ctl *ctl;
1397         int pending_kickoff_cnt;
1398         u32 ret = UINT_MAX;
1399
1400         if (!drm_enc || !phys) {
1401                 DPU_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
1402                                 drm_enc != 0, phys != 0);
1403                 return;
1404         }
1405
1406         if (!phys->hw_pp) {
1407                 DPU_ERROR("invalid pingpong hw\n");
1408                 return;
1409         }
1410
1411         ctl = phys->hw_ctl;
1412         if (!ctl || !ctl->ops.trigger_flush) {
1413                 DPU_ERROR("missing trigger cb\n");
1414                 return;
1415         }
1416
1417         if (!async)
1418                 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1419         else
1420                 pending_kickoff_cnt = atomic_read(&phys->pending_kickoff_cnt);
1421
1422         if (extra_flush_bits && ctl->ops.update_pending_flush)
1423                 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1424
1425         ctl->ops.trigger_flush(ctl);
1426
1427         if (ctl->ops.get_pending_flush)
1428                 ret = ctl->ops.get_pending_flush(ctl);
1429
1430         trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1431                                     pending_kickoff_cnt, ctl->idx,
1432                                     extra_flush_bits, ret);
1433 }
1434
1435 /**
1436  * _dpu_encoder_trigger_start - trigger start for a physical encoder
1437  * phys: Pointer to physical encoder structure
1438  */
1439 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1440 {
1441         if (!phys) {
1442                 DPU_ERROR("invalid argument(s)\n");
1443                 return;
1444         }
1445
1446         if (!phys->hw_pp) {
1447                 DPU_ERROR("invalid pingpong hw\n");
1448                 return;
1449         }
1450
1451         if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1452                 phys->ops.trigger_start(phys);
1453 }
1454
1455 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1456 {
1457         struct dpu_hw_ctl *ctl;
1458
1459         if (!phys_enc) {
1460                 DPU_ERROR("invalid encoder\n");
1461                 return;
1462         }
1463
1464         ctl = phys_enc->hw_ctl;
1465         if (ctl && ctl->ops.trigger_start) {
1466                 ctl->ops.trigger_start(ctl);
1467                 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1468         }
1469 }
1470
1471 static int dpu_encoder_helper_wait_event_timeout(
1472                 int32_t drm_id,
1473                 int32_t hw_id,
1474                 struct dpu_encoder_wait_info *info)
1475 {
1476         int rc = 0;
1477         s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1478         s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1479         s64 time;
1480
1481         do {
1482                 rc = wait_event_timeout(*(info->wq),
1483                                 atomic_read(info->atomic_cnt) == 0, jiffies);
1484                 time = ktime_to_ms(ktime_get());
1485
1486                 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
1487                                                  expected_time,
1488                                                  atomic_read(info->atomic_cnt));
1489         /* If we timed out, counter is valid and time is less, wait again */
1490         } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1491                         (time < expected_time));
1492
1493         return rc;
1494 }
1495
1496 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1497 {
1498         struct dpu_encoder_virt *dpu_enc;
1499         struct dpu_hw_ctl *ctl;
1500         int rc;
1501
1502         if (!phys_enc) {
1503                 DPU_ERROR("invalid encoder\n");
1504                 return;
1505         }
1506         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1507         ctl = phys_enc->hw_ctl;
1508
1509         if (!ctl || !ctl->ops.reset)
1510                 return;
1511
1512         DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
1513                       ctl->idx);
1514
1515         rc = ctl->ops.reset(ctl);
1516         if (rc) {
1517                 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
1518                 dpu_dbg_dump(false, __func__, true, true);
1519         }
1520
1521         phys_enc->enable_state = DPU_ENC_ENABLED;
1522 }
1523
1524 /**
1525  * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1526  *      Iterate through the physical encoders and perform consolidated flush
1527  *      and/or control start triggering as needed. This is done in the virtual
1528  *      encoder rather than the individual physical ones in order to handle
1529  *      use cases that require visibility into multiple physical encoders at
1530  *      a time.
1531  * dpu_enc: Pointer to virtual encoder structure
1532  */
1533 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc,
1534                                       bool async)
1535 {
1536         struct dpu_hw_ctl *ctl;
1537         uint32_t i, pending_flush;
1538         unsigned long lock_flags;
1539
1540         if (!dpu_enc) {
1541                 DPU_ERROR("invalid encoder\n");
1542                 return;
1543         }
1544
1545         pending_flush = 0x0;
1546
1547         /* update pending counts and trigger kickoff ctl flush atomically */
1548         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1549
1550         /* don't perform flush/start operations for slave encoders */
1551         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1552                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1553
1554                 if (!phys || phys->enable_state == DPU_ENC_DISABLED)
1555                         continue;
1556
1557                 ctl = phys->hw_ctl;
1558                 if (!ctl)
1559                         continue;
1560
1561                 if (phys->split_role != ENC_ROLE_SLAVE)
1562                         set_bit(i, dpu_enc->frame_busy_mask);
1563                 if (!phys->ops.needs_single_flush ||
1564                                 !phys->ops.needs_single_flush(phys))
1565                         _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0,
1566                                                    async);
1567                 else if (ctl->ops.get_pending_flush)
1568                         pending_flush |= ctl->ops.get_pending_flush(ctl);
1569         }
1570
1571         /* for split flush, combine pending flush masks and send to master */
1572         if (pending_flush && dpu_enc->cur_master) {
1573                 _dpu_encoder_trigger_flush(
1574                                 &dpu_enc->base,
1575                                 dpu_enc->cur_master,
1576                                 pending_flush, async);
1577         }
1578
1579         _dpu_encoder_trigger_start(dpu_enc->cur_master);
1580
1581         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1582 }
1583
1584 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1585 {
1586         struct dpu_encoder_virt *dpu_enc;
1587         struct dpu_encoder_phys *phys;
1588         unsigned int i;
1589         struct dpu_hw_ctl *ctl;
1590         struct msm_display_info *disp_info;
1591
1592         if (!drm_enc) {
1593                 DPU_ERROR("invalid encoder\n");
1594                 return;
1595         }
1596         dpu_enc = to_dpu_encoder_virt(drm_enc);
1597         disp_info = &dpu_enc->disp_info;
1598
1599         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1600                 phys = dpu_enc->phys_encs[i];
1601
1602                 if (phys && phys->hw_ctl) {
1603                         ctl = phys->hw_ctl;
1604                         if (ctl->ops.clear_pending_flush)
1605                                 ctl->ops.clear_pending_flush(ctl);
1606
1607                         /* update only for command mode primary ctl */
1608                         if ((phys == dpu_enc->cur_master) &&
1609                            (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1610                             && ctl->ops.trigger_pending)
1611                                 ctl->ops.trigger_pending(ctl);
1612                 }
1613         }
1614 }
1615
1616 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1617                 struct drm_display_mode *mode)
1618 {
1619         u64 pclk_rate;
1620         u32 pclk_period;
1621         u32 line_time;
1622
1623         /*
1624          * For linetime calculation, only operate on master encoder.
1625          */
1626         if (!dpu_enc->cur_master)
1627                 return 0;
1628
1629         if (!dpu_enc->cur_master->ops.get_line_count) {
1630                 DPU_ERROR("get_line_count function not defined\n");
1631                 return 0;
1632         }
1633
1634         pclk_rate = mode->clock; /* pixel clock in kHz */
1635         if (pclk_rate == 0) {
1636                 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1637                 return 0;
1638         }
1639
1640         pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1641         if (pclk_period == 0) {
1642                 DPU_ERROR("pclk period is 0\n");
1643                 return 0;
1644         }
1645
1646         /*
1647          * Line time calculation based on Pixel clock and HTOTAL.
1648          * Final unit is in ns.
1649          */
1650         line_time = (pclk_period * mode->htotal) / 1000;
1651         if (line_time == 0) {
1652                 DPU_ERROR("line time calculation is 0\n");
1653                 return 0;
1654         }
1655
1656         DPU_DEBUG_ENC(dpu_enc,
1657                         "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1658                         pclk_rate, pclk_period, line_time);
1659
1660         return line_time;
1661 }
1662
1663 static int _dpu_encoder_wakeup_time(struct drm_encoder *drm_enc,
1664                 ktime_t *wakeup_time)
1665 {
1666         struct drm_display_mode *mode;
1667         struct dpu_encoder_virt *dpu_enc;
1668         u32 cur_line;
1669         u32 line_time;
1670         u32 vtotal, time_to_vsync;
1671         ktime_t cur_time;
1672
1673         dpu_enc = to_dpu_encoder_virt(drm_enc);
1674
1675         if (!drm_enc->crtc || !drm_enc->crtc->state) {
1676                 DPU_ERROR("crtc/crtc state object is NULL\n");
1677                 return -EINVAL;
1678         }
1679         mode = &drm_enc->crtc->state->adjusted_mode;
1680
1681         line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1682         if (!line_time)
1683                 return -EINVAL;
1684
1685         cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1686
1687         vtotal = mode->vtotal;
1688         if (cur_line >= vtotal)
1689                 time_to_vsync = line_time * vtotal;
1690         else
1691                 time_to_vsync = line_time * (vtotal - cur_line);
1692
1693         if (time_to_vsync == 0) {
1694                 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1695                                 vtotal);
1696                 return -EINVAL;
1697         }
1698
1699         cur_time = ktime_get();
1700         *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1701
1702         DPU_DEBUG_ENC(dpu_enc,
1703                         "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1704                         cur_line, vtotal, time_to_vsync,
1705                         ktime_to_ms(cur_time),
1706                         ktime_to_ms(*wakeup_time));
1707         return 0;
1708 }
1709
1710 static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1711 {
1712         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1713                         vsync_event_timer);
1714         struct drm_encoder *drm_enc = &dpu_enc->base;
1715         struct msm_drm_private *priv;
1716         struct msm_drm_thread *event_thread;
1717
1718         if (!drm_enc->dev || !drm_enc->dev->dev_private ||
1719                         !drm_enc->crtc) {
1720                 DPU_ERROR("invalid parameters\n");
1721                 return;
1722         }
1723
1724         priv = drm_enc->dev->dev_private;
1725
1726         if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1727                 DPU_ERROR("invalid crtc index\n");
1728                 return;
1729         }
1730         event_thread = &priv->event_thread[drm_enc->crtc->index];
1731         if (!event_thread) {
1732                 DPU_ERROR("event_thread not found for crtc:%d\n",
1733                                 drm_enc->crtc->index);
1734                 return;
1735         }
1736
1737         del_timer(&dpu_enc->vsync_event_timer);
1738 }
1739
1740 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1741 {
1742         struct dpu_encoder_virt *dpu_enc = container_of(work,
1743                         struct dpu_encoder_virt, vsync_event_work);
1744         ktime_t wakeup_time;
1745
1746         if (!dpu_enc) {
1747                 DPU_ERROR("invalid dpu encoder\n");
1748                 return;
1749         }
1750
1751         if (_dpu_encoder_wakeup_time(&dpu_enc->base, &wakeup_time))
1752                 return;
1753
1754         trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1755         mod_timer(&dpu_enc->vsync_event_timer,
1756                         nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1757 }
1758
1759 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
1760                 struct dpu_encoder_kickoff_params *params, bool async)
1761 {
1762         struct dpu_encoder_virt *dpu_enc;
1763         struct dpu_encoder_phys *phys;
1764         bool needs_hw_reset = false;
1765         unsigned int i;
1766
1767         if (!drm_enc || !params) {
1768                 DPU_ERROR("invalid args\n");
1769                 return;
1770         }
1771         dpu_enc = to_dpu_encoder_virt(drm_enc);
1772
1773         trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1774
1775         /* prepare for next kickoff, may include waiting on previous kickoff */
1776         DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1777         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1778                 phys = dpu_enc->phys_encs[i];
1779                 if (phys) {
1780                         if (phys->ops.prepare_for_kickoff)
1781                                 phys->ops.prepare_for_kickoff(phys, params);
1782                         if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1783                                 needs_hw_reset = true;
1784                 }
1785         }
1786         DPU_ATRACE_END("enc_prepare_for_kickoff");
1787
1788         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1789
1790         /* if any phys needs reset, reset all phys, in-order */
1791         if (needs_hw_reset) {
1792                 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1793                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1794                         dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1795                 }
1796         }
1797 }
1798
1799 void dpu_encoder_kickoff(struct drm_encoder *drm_enc, bool async)
1800 {
1801         struct dpu_encoder_virt *dpu_enc;
1802         struct dpu_encoder_phys *phys;
1803         ktime_t wakeup_time;
1804         unsigned int i;
1805
1806         if (!drm_enc) {
1807                 DPU_ERROR("invalid encoder\n");
1808                 return;
1809         }
1810         DPU_ATRACE_BEGIN("encoder_kickoff");
1811         dpu_enc = to_dpu_encoder_virt(drm_enc);
1812
1813         trace_dpu_enc_kickoff(DRMID(drm_enc));
1814
1815         atomic_set(&dpu_enc->frame_done_timeout,
1816                         DPU_FRAME_DONE_TIMEOUT * 1000 /
1817                         drm_enc->crtc->state->adjusted_mode.vrefresh);
1818         mod_timer(&dpu_enc->frame_done_timer, jiffies +
1819                 ((atomic_read(&dpu_enc->frame_done_timeout) * HZ) / 1000));
1820
1821         /* All phys encs are ready to go, trigger the kickoff */
1822         _dpu_encoder_kickoff_phys(dpu_enc, async);
1823
1824         /* allow phys encs to handle any post-kickoff business */
1825         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1826                 phys = dpu_enc->phys_encs[i];
1827                 if (phys && phys->ops.handle_post_kickoff)
1828                         phys->ops.handle_post_kickoff(phys);
1829         }
1830
1831         if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1832                         !_dpu_encoder_wakeup_time(drm_enc, &wakeup_time)) {
1833                 trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1834                                             ktime_to_ms(wakeup_time));
1835                 mod_timer(&dpu_enc->vsync_event_timer,
1836                                 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1837         }
1838
1839         DPU_ATRACE_END("encoder_kickoff");
1840 }
1841
1842 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
1843 {
1844         struct dpu_encoder_virt *dpu_enc;
1845         struct dpu_encoder_phys *phys;
1846         int i;
1847
1848         if (!drm_enc) {
1849                 DPU_ERROR("invalid encoder\n");
1850                 return;
1851         }
1852         dpu_enc = to_dpu_encoder_virt(drm_enc);
1853
1854         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1855                 phys = dpu_enc->phys_encs[i];
1856                 if (phys && phys->ops.prepare_commit)
1857                         phys->ops.prepare_commit(phys);
1858         }
1859 }
1860
1861 #ifdef CONFIG_DEBUG_FS
1862 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
1863 {
1864         struct dpu_encoder_virt *dpu_enc;
1865         int i;
1866
1867         if (!s || !s->private)
1868                 return -EINVAL;
1869
1870         dpu_enc = s->private;
1871
1872         mutex_lock(&dpu_enc->enc_lock);
1873         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1874                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1875
1876                 if (!phys)
1877                         continue;
1878
1879                 seq_printf(s, "intf:%d    vsync:%8d     underrun:%8d    ",
1880                                 phys->intf_idx - INTF_0,
1881                                 atomic_read(&phys->vsync_cnt),
1882                                 atomic_read(&phys->underrun_cnt));
1883
1884                 switch (phys->intf_mode) {
1885                 case INTF_MODE_VIDEO:
1886                         seq_puts(s, "mode: video\n");
1887                         break;
1888                 case INTF_MODE_CMD:
1889                         seq_puts(s, "mode: command\n");
1890                         break;
1891                 default:
1892                         seq_puts(s, "mode: ???\n");
1893                         break;
1894                 }
1895         }
1896         mutex_unlock(&dpu_enc->enc_lock);
1897
1898         return 0;
1899 }
1900
1901 static int _dpu_encoder_debugfs_status_open(struct inode *inode,
1902                 struct file *file)
1903 {
1904         return single_open(file, _dpu_encoder_status_show, inode->i_private);
1905 }
1906
1907 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1908 {
1909         struct dpu_encoder_virt *dpu_enc;
1910         struct msm_drm_private *priv;
1911         struct dpu_kms *dpu_kms;
1912         int i;
1913
1914         static const struct file_operations debugfs_status_fops = {
1915                 .open =         _dpu_encoder_debugfs_status_open,
1916                 .read =         seq_read,
1917                 .llseek =       seq_lseek,
1918                 .release =      single_release,
1919         };
1920
1921         char name[DPU_NAME_SIZE];
1922
1923         if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
1924                 DPU_ERROR("invalid encoder or kms\n");
1925                 return -EINVAL;
1926         }
1927
1928         dpu_enc = to_dpu_encoder_virt(drm_enc);
1929         priv = drm_enc->dev->dev_private;
1930         dpu_kms = to_dpu_kms(priv->kms);
1931
1932         snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
1933
1934         /* create overall sub-directory for the encoder */
1935         dpu_enc->debugfs_root = debugfs_create_dir(name,
1936                         drm_enc->dev->primary->debugfs_root);
1937         if (!dpu_enc->debugfs_root)
1938                 return -ENOMEM;
1939
1940         /* don't error check these */
1941         debugfs_create_file("status", 0600,
1942                 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
1943
1944         for (i = 0; i < dpu_enc->num_phys_encs; i++)
1945                 if (dpu_enc->phys_encs[i] &&
1946                                 dpu_enc->phys_encs[i]->ops.late_register)
1947                         dpu_enc->phys_encs[i]->ops.late_register(
1948                                         dpu_enc->phys_encs[i],
1949                                         dpu_enc->debugfs_root);
1950
1951         return 0;
1952 }
1953
1954 static void _dpu_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
1955 {
1956         struct dpu_encoder_virt *dpu_enc;
1957
1958         if (!drm_enc)
1959                 return;
1960
1961         dpu_enc = to_dpu_encoder_virt(drm_enc);
1962         debugfs_remove_recursive(dpu_enc->debugfs_root);
1963 }
1964 #else
1965 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1966 {
1967         return 0;
1968 }
1969
1970 static void _dpu_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
1971 {
1972 }
1973 #endif
1974
1975 static int dpu_encoder_late_register(struct drm_encoder *encoder)
1976 {
1977         return _dpu_encoder_init_debugfs(encoder);
1978 }
1979
1980 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
1981 {
1982         _dpu_encoder_destroy_debugfs(encoder);
1983 }
1984
1985 static int dpu_encoder_virt_add_phys_encs(
1986                 u32 display_caps,
1987                 struct dpu_encoder_virt *dpu_enc,
1988                 struct dpu_enc_phys_init_params *params)
1989 {
1990         struct dpu_encoder_phys *enc = NULL;
1991
1992         DPU_DEBUG_ENC(dpu_enc, "\n");
1993
1994         /*
1995          * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
1996          * in this function, check up-front.
1997          */
1998         if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
1999                         ARRAY_SIZE(dpu_enc->phys_encs)) {
2000                 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2001                           dpu_enc->num_phys_encs);
2002                 return -EINVAL;
2003         }
2004
2005         if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
2006                 enc = dpu_encoder_phys_vid_init(params);
2007
2008                 if (IS_ERR_OR_NULL(enc)) {
2009                         DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2010                                 PTR_ERR(enc));
2011                         return enc == 0 ? -EINVAL : PTR_ERR(enc);
2012                 }
2013
2014                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2015                 ++dpu_enc->num_phys_encs;
2016         }
2017
2018         if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
2019                 enc = dpu_encoder_phys_cmd_init(params);
2020
2021                 if (IS_ERR_OR_NULL(enc)) {
2022                         DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2023                                 PTR_ERR(enc));
2024                         return enc == 0 ? -EINVAL : PTR_ERR(enc);
2025                 }
2026
2027                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2028                 ++dpu_enc->num_phys_encs;
2029         }
2030
2031         if (params->split_role == ENC_ROLE_SLAVE)
2032                 dpu_enc->cur_slave = enc;
2033         else
2034                 dpu_enc->cur_master = enc;
2035
2036         return 0;
2037 }
2038
2039 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
2040         .handle_vblank_virt = dpu_encoder_vblank_callback,
2041         .handle_underrun_virt = dpu_encoder_underrun_callback,
2042         .handle_frame_done = dpu_encoder_frame_done_callback,
2043 };
2044
2045 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2046                                  struct dpu_kms *dpu_kms,
2047                                  struct msm_display_info *disp_info)
2048 {
2049         int ret = 0;
2050         int i = 0;
2051         enum dpu_intf_type intf_type;
2052         struct dpu_enc_phys_init_params phys_params;
2053
2054         if (!dpu_enc || !dpu_kms) {
2055                 DPU_ERROR("invalid arg(s), enc %d kms %d\n",
2056                                 dpu_enc != 0, dpu_kms != 0);
2057                 return -EINVAL;
2058         }
2059
2060         dpu_enc->cur_master = NULL;
2061
2062         memset(&phys_params, 0, sizeof(phys_params));
2063         phys_params.dpu_kms = dpu_kms;
2064         phys_params.parent = &dpu_enc->base;
2065         phys_params.parent_ops = &dpu_encoder_parent_ops;
2066         phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2067
2068         DPU_DEBUG("\n");
2069
2070         switch (disp_info->intf_type) {
2071         case DRM_MODE_ENCODER_DSI:
2072                 intf_type = INTF_DSI;
2073                 break;
2074         default:
2075                 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
2076                 return -EINVAL;
2077         }
2078
2079         WARN_ON(disp_info->num_of_h_tiles < 1);
2080
2081         DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2082
2083         if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
2084             (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
2085                 dpu_enc->idle_pc_supported =
2086                                 dpu_kms->catalog->caps->has_idle_pc;
2087
2088         mutex_lock(&dpu_enc->enc_lock);
2089         for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2090                 /*
2091                  * Left-most tile is at index 0, content is controller id
2092                  * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2093                  * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2094                  */
2095                 u32 controller_id = disp_info->h_tile_instance[i];
2096
2097                 if (disp_info->num_of_h_tiles > 1) {
2098                         if (i == 0)
2099                                 phys_params.split_role = ENC_ROLE_MASTER;
2100                         else
2101                                 phys_params.split_role = ENC_ROLE_SLAVE;
2102                 } else {
2103                         phys_params.split_role = ENC_ROLE_SOLO;
2104                 }
2105
2106                 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2107                                 i, controller_id, phys_params.split_role);
2108
2109                 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2110                                                                                                         intf_type,
2111                                                                                                         controller_id);
2112                 if (phys_params.intf_idx == INTF_MAX) {
2113                         DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n",
2114                                                   intf_type, controller_id);
2115                         ret = -EINVAL;
2116                 }
2117
2118                 if (!ret) {
2119                         ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
2120                                                                                                  dpu_enc,
2121                                                                                                  &phys_params);
2122                         if (ret)
2123                                 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2124                 }
2125         }
2126
2127         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2128                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2129
2130                 if (phys) {
2131                         atomic_set(&phys->vsync_cnt, 0);
2132                         atomic_set(&phys->underrun_cnt, 0);
2133                 }
2134         }
2135         mutex_unlock(&dpu_enc->enc_lock);
2136
2137         return ret;
2138 }
2139
2140 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2141 {
2142         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2143                         frame_done_timer);
2144         struct drm_encoder *drm_enc = &dpu_enc->base;
2145         struct msm_drm_private *priv;
2146         u32 event;
2147
2148         if (!drm_enc->dev || !drm_enc->dev->dev_private) {
2149                 DPU_ERROR("invalid parameters\n");
2150                 return;
2151         }
2152         priv = drm_enc->dev->dev_private;
2153
2154         if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2155                 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2156                               DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2157                 return;
2158         } else if (!atomic_xchg(&dpu_enc->frame_done_timeout, 0)) {
2159                 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2160                 return;
2161         }
2162
2163         DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
2164
2165         event = DPU_ENCODER_FRAME_EVENT_ERROR;
2166         trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2167         dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2168 }
2169
2170 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2171         .mode_set = dpu_encoder_virt_mode_set,
2172         .disable = dpu_encoder_virt_disable,
2173         .enable = dpu_kms_encoder_enable,
2174         .atomic_check = dpu_encoder_virt_atomic_check,
2175
2176         /* This is called by dpu_kms_encoder_enable */
2177         .commit = dpu_encoder_virt_enable,
2178 };
2179
2180 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2181                 .destroy = dpu_encoder_destroy,
2182                 .late_register = dpu_encoder_late_register,
2183                 .early_unregister = dpu_encoder_early_unregister,
2184 };
2185
2186 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2187                 struct msm_display_info *disp_info)
2188 {
2189         struct msm_drm_private *priv = dev->dev_private;
2190         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2191         struct drm_encoder *drm_enc = NULL;
2192         struct dpu_encoder_virt *dpu_enc = NULL;
2193         int ret = 0;
2194
2195         dpu_enc = to_dpu_encoder_virt(enc);
2196
2197         mutex_init(&dpu_enc->enc_lock);
2198         ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2199         if (ret)
2200                 goto fail;
2201
2202         spin_lock_init(&dpu_enc->enc_spinlock);
2203
2204         atomic_set(&dpu_enc->frame_done_timeout, 0);
2205         timer_setup(&dpu_enc->frame_done_timer,
2206                         dpu_encoder_frame_done_timeout, 0);
2207
2208         if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2209                 timer_setup(&dpu_enc->vsync_event_timer,
2210                                 dpu_encoder_vsync_event_handler,
2211                                 0);
2212
2213
2214         mutex_init(&dpu_enc->rc_lock);
2215         kthread_init_delayed_work(&dpu_enc->delayed_off_work,
2216                         dpu_encoder_off_work);
2217         dpu_enc->idle_timeout = IDLE_TIMEOUT;
2218
2219         kthread_init_work(&dpu_enc->vsync_event_work,
2220                         dpu_encoder_vsync_event_work_handler);
2221
2222         memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2223
2224         DPU_DEBUG_ENC(dpu_enc, "created\n");
2225
2226         return ret;
2227
2228 fail:
2229         DPU_ERROR("failed to create encoder\n");
2230         if (drm_enc)
2231                 dpu_encoder_destroy(drm_enc);
2232
2233         return ret;
2234
2235
2236 }
2237
2238 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2239                 int drm_enc_mode)
2240 {
2241         struct dpu_encoder_virt *dpu_enc = NULL;
2242         int rc = 0;
2243
2244         dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2245         if (!dpu_enc)
2246                 return ERR_PTR(ENOMEM);
2247
2248         rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2249                         drm_enc_mode, NULL);
2250         if (rc) {
2251                 devm_kfree(dev->dev, dpu_enc);
2252                 return ERR_PTR(rc);
2253         }
2254
2255         drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2256
2257         dpu_enc->enabled = false;
2258
2259         return &dpu_enc->base;
2260 }
2261
2262 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2263         enum msm_event_wait event)
2264 {
2265         int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2266         struct dpu_encoder_virt *dpu_enc = NULL;
2267         int i, ret = 0;
2268
2269         if (!drm_enc) {
2270                 DPU_ERROR("invalid encoder\n");
2271                 return -EINVAL;
2272         }
2273         dpu_enc = to_dpu_encoder_virt(drm_enc);
2274         DPU_DEBUG_ENC(dpu_enc, "\n");
2275
2276         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2277                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2278                 if (!phys)
2279                         continue;
2280
2281                 switch (event) {
2282                 case MSM_ENC_COMMIT_DONE:
2283                         fn_wait = phys->ops.wait_for_commit_done;
2284                         break;
2285                 case MSM_ENC_TX_COMPLETE:
2286                         fn_wait = phys->ops.wait_for_tx_complete;
2287                         break;
2288                 case MSM_ENC_VBLANK:
2289                         fn_wait = phys->ops.wait_for_vblank;
2290                         break;
2291                 default:
2292                         DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2293                                         event);
2294                         return -EINVAL;
2295                 };
2296
2297                 if (fn_wait) {
2298                         DPU_ATRACE_BEGIN("wait_for_completion_event");
2299                         ret = fn_wait(phys);
2300                         DPU_ATRACE_END("wait_for_completion_event");
2301                         if (ret)
2302                                 return ret;
2303                 }
2304         }
2305
2306         return ret;
2307 }
2308
2309 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2310 {
2311         struct dpu_encoder_virt *dpu_enc = NULL;
2312         int i;
2313
2314         if (!encoder) {
2315                 DPU_ERROR("invalid encoder\n");
2316                 return INTF_MODE_NONE;
2317         }
2318         dpu_enc = to_dpu_encoder_virt(encoder);
2319
2320         if (dpu_enc->cur_master)
2321                 return dpu_enc->cur_master->intf_mode;
2322
2323         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2324                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2325
2326                 if (phys)
2327                         return phys->intf_mode;
2328         }
2329
2330         return INTF_MODE_NONE;
2331 }