drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   9 #include <linux/debugfs.h>
  10 #include <linux/kthread.h>
  11 #include <linux/seq_file.h>
  12
  13 #include <drm/drm_crtc.h>
  14 #include <drm/drm_file.h>
  15 #include <drm/drm_probe_helper.h>
  16
  17 #include "msm_drv.h"
  18 #include "dpu_kms.h"
  19 #include "dpu_hwio.h"
  20 #include "dpu_hw_catalog.h"
  21 #include "dpu_hw_intf.h"
  22 #include "dpu_hw_ctl.h"
  23 #include "dpu_hw_dspp.h"
  24 #include "dpu_formats.h"
  25 #include "dpu_encoder_phys.h"
  26 #include "dpu_crtc.h"
  27 #include "dpu_trace.h"
  28 #include "dpu_core_irq.h"
  29
  30 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\
  31                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  32
  33 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
  34                 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  35
  36 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\
  37                 (p) ? (p)->parent->base.id : -1, \
  38                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  39                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  40                 ##__VA_ARGS__)
  41
  42 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
  43                 (p) ? (p)->parent->base.id : -1, \
  44                 (p) ? (p)->intf_idx - INTF_0 : -1, \
  45                 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  46                 ##__VA_ARGS__)
  47
  48 /*
  49  * Two to anticipate panels that can do cmd/vid dynamic switching
  50  * plan is to create all possible physical encoder types, and switch between
  51  * them at runtime
  52  */
  53 #define NUM_PHYS_ENCODER_TYPES 2
  54
  55 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
  56         (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
  57
  58 #define MAX_CHANNELS_PER_ENC 2
  59
  60 #define IDLE_SHORT_TIMEOUT      1
  61
  62 #define MAX_HDISPLAY_SPLIT 1080
  63
  64 /* timeout in frames waiting for frame done */
  65 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
  66
  67 /**
  68  * enum dpu_enc_rc_events - events for resource control state machine
  69  * @DPU_ENC_RC_EVENT_KICKOFF:
  70  *      This event happens at NORMAL priority.
  71  *      Event that signals the start of the transfer. When this event is
  72  *      received, enable MDP/DSI core clocks. Regardless of the previous
  73  *      state, the resource should be in ON state at the end of this event.
  74  * @DPU_ENC_RC_EVENT_FRAME_DONE:
  75  *      This event happens at INTERRUPT level.
  76  *      Event signals the end of the data transfer after the PP FRAME_DONE
  77  *      event. At the end of this event, a delayed work is scheduled to go to
  78  *      IDLE_PC state after IDLE_TIMEOUT time.
  79  * @DPU_ENC_RC_EVENT_PRE_STOP:
  80  *      This event happens at NORMAL priority.
  81  *      This event, when received during the ON state, leave the RC STATE
  82  *      in the PRE_OFF state. It should be followed by the STOP event as
  83  *      part of encoder disable.
  84  *      If received during IDLE or OFF states, it will do nothing.
  85  * @DPU_ENC_RC_EVENT_STOP:
  86  *      This event happens at NORMAL priority.
  87  *      When this event is received, disable all the MDP/DSI core clocks, and
  88  *      disable IRQs. It should be called from the PRE_OFF or IDLE states.
  89  *      IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  90  *      PRE_OFF is expected when PRE_STOP was executed during the ON state.
  91  *      Resource state should be in OFF at the end of the event.
  92  * @DPU_ENC_RC_EVENT_ENTER_IDLE:
  93  *      This event happens at NORMAL priority from a work item.
  94  *      Event signals that there were no frame updates for IDLE_TIMEOUT time.
  95  *      This would disable MDP/DSI core clocks and change the resource state
  96  *      to IDLE.
  97  */
  98 enum dpu_enc_rc_events {
  99         DPU_ENC_RC_EVENT_KICKOFF = 1,
 100         DPU_ENC_RC_EVENT_FRAME_DONE,
 101         DPU_ENC_RC_EVENT_PRE_STOP,
 102         DPU_ENC_RC_EVENT_STOP,
 103         DPU_ENC_RC_EVENT_ENTER_IDLE
 104 };
 105
 106 /*
 107  * enum dpu_enc_rc_states - states that the resource control maintains
 108  * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
 109  * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
 110  * @DPU_ENC_RC_STATE_ON: Resource is in ON state
 111  * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
 112  * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
 113  */
 114 enum dpu_enc_rc_states {
 115         DPU_ENC_RC_STATE_OFF,
 116         DPU_ENC_RC_STATE_PRE_OFF,
 117         DPU_ENC_RC_STATE_ON,
 118         DPU_ENC_RC_STATE_IDLE
 119 };
 120
 121 /**
 122  * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
 123  *      encoders. Virtual encoder manages one "logical" display. Physical
 124  *      encoders manage one intf block, tied to a specific panel/sub-panel.
 125  *      Virtual encoder defers as much as possible to the physical encoders.
 126  *      Virtual encoder registers itself with the DRM Framework as the encoder.
 127  * @base:               drm_encoder base class for registration with DRM
 128  * @enc_spinlock:       Virtual-Encoder-Wide Spin Lock for IRQ purposes
 129  * @bus_scaling_client: Client handle to the bus scaling interface
 130  * @enabled:            True if the encoder is active, protected by enc_lock
 131  * @num_phys_encs:      Actual number of physical encoders contained.
 132  * @phys_encs:          Container of physical encoders managed.
 133  * @cur_master:         Pointer to the current master in this mode. Optimization
 134  *                      Only valid after enable. Cleared as disable.
 135  * @hw_pp               Handle to the pingpong blocks used for the display. No.
 136  *                      pingpong blocks can be different than num_phys_encs.
 137  * @intfs_swapped       Whether or not the phys_enc interfaces have been swapped
 138  *                      for partial update right-only cases, such as pingpong
 139  *                      split where virtual pingpong does not generate IRQs
 140  * @crtc:               Pointer to the currently assigned crtc. Normally you
 141  *                      would use crtc->state->encoder_mask to determine the
 142  *                      link between encoder/crtc. However in this case we need
 143  *                      to track crtc in the disable() hook which is called
 144  *                      _after_ encoder_mask is cleared.
 145  * @crtc_kickoff_cb:            Callback into CRTC that will flush & start
 146  *                              all CTL paths
 147  * @crtc_kickoff_cb_data:       Opaque user data given to crtc_kickoff_cb
 148  * @debugfs_root:               Debug file system root file node
 149  * @enc_lock:                   Lock around physical encoder
 150  *                              create/destroy/enable/disable
 151  * @frame_busy_mask:            Bitmask tracking which phys_enc we are still
 152  *                              busy processing current command.
 153  *                              Bit0 = phys_encs[0] etc.
 154  * @crtc_frame_event_cb:        callback handler for frame event
 155  * @crtc_frame_event_cb_data:   callback handler private data
 156  * @frame_done_timeout_ms:      frame done timeout in ms
 157  * @frame_done_timer:           watchdog timer for frame done event
 158  * @vsync_event_timer:          vsync timer
 159  * @disp_info:                  local copy of msm_display_info struct
 160  * @idle_pc_supported:          indicate if idle power collaps is supported
 161  * @rc_lock:                    resource control mutex lock to protect
 162  *                              virt encoder over various state changes
 163  * @rc_state:                   resource controller state
 164  * @delayed_off_work:           delayed worker to schedule disabling of
 165  *                              clks and resources after IDLE_TIMEOUT time.
 166  * @vsync_event_work:           worker to handle vsync event for autorefresh
 167  * @topology:                   topology of the display
 168  * @idle_timeout:               idle timeout duration in milliseconds
 169  */
 170 struct dpu_encoder_virt {
 171         struct drm_encoder base;
 172         spinlock_t enc_spinlock;
 173         uint32_t bus_scaling_client;
 174
 175         bool enabled;
 176
 177         unsigned int num_phys_encs;
 178         struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
 179         struct dpu_encoder_phys *cur_master;
 180         struct dpu_encoder_phys *cur_slave;
 181         struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
 182
 183         bool intfs_swapped;
 184
 185         struct drm_crtc *crtc;
 186
 187         struct dentry *debugfs_root;
 188         struct mutex enc_lock;
 189         DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
 190         void (*crtc_frame_event_cb)(void *, u32 event);
 191         void *crtc_frame_event_cb_data;
 192
 193         atomic_t frame_done_timeout_ms;
 194         struct timer_list frame_done_timer;
 195         struct timer_list vsync_event_timer;
 196
 197         struct msm_display_info disp_info;
 198
 199         bool idle_pc_supported;
 200         struct mutex rc_lock;
 201         enum dpu_enc_rc_states rc_state;
 202         struct delayed_work delayed_off_work;
 203         struct kthread_work vsync_event_work;
 204         struct msm_display_topology topology;
 205
 206         u32 idle_timeout;
 207 };
 208
 209 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 210
 211 static u32 dither_matrix[DITHER_MATRIX_SZ] = {
 212         15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 213 };
 214
 215 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
 216 {
 217         struct dpu_hw_dither_cfg dither_cfg = { 0 };
 218
 219         if (!hw_pp->ops.setup_dither)
 220                 return;
 221
 222         switch (bpc) {
 223         case 6:
 224                 dither_cfg.c0_bitdepth = 6;
 225                 dither_cfg.c1_bitdepth = 6;
 226                 dither_cfg.c2_bitdepth = 6;
 227                 dither_cfg.c3_bitdepth = 6;
 228                 dither_cfg.temporal_en = 0;
 229                 break;
 230         default:
 231                 hw_pp->ops.setup_dither(hw_pp, NULL);
 232                 return;
 233         }
 234
 235         memcpy(&dither_cfg.matrix, dither_matrix,
 236                         sizeof(u32) * DITHER_MATRIX_SZ);
 237
 238         hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
 239 }
 240
 241 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
 242                 enum dpu_intr_idx intr_idx)
 243 {
 244         DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
 245                   DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
 246                   phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
 247
 248         if (phys_enc->parent_ops->handle_frame_done)
 249                 phys_enc->parent_ops->handle_frame_done(
 250                                 phys_enc->parent, phys_enc,
 251                                 DPU_ENCODER_FRAME_EVENT_ERROR);
 252 }
 253
 254 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
 255                 int32_t hw_id, struct dpu_encoder_wait_info *info);
 256
 257 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 258                 enum dpu_intr_idx intr_idx,
 259                 struct dpu_encoder_wait_info *wait_info)
 260 {
 261         struct dpu_encoder_irq *irq;
 262         u32 irq_status;
 263         int ret;
 264
 265         if (!wait_info || intr_idx >= INTR_IDX_MAX) {
 266                 DPU_ERROR("invalid params\n");
 267                 return -EINVAL;
 268         }
 269         irq = &phys_enc->irq[intr_idx];
 270
 271         /* note: do master / slave checking outside */
 272
 273         /* return EWOULDBLOCK since we know the wait isn't necessary */
 274         if (phys_enc->enable_state == DPU_ENC_DISABLED) {
 275                 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
 276                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 277                           irq->irq_idx);
 278                 return -EWOULDBLOCK;
 279         }
 280
 281         if (irq->irq_idx < 0) {
 282                 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
 283                               DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 284                               irq->name);
 285                 return 0;
 286         }
 287
 288         DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
 289                       DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 290                       irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
 291                       atomic_read(wait_info->atomic_cnt));
 292
 293         ret = dpu_encoder_helper_wait_event_timeout(
 294                         DRMID(phys_enc->parent),
 295                         irq->hw_idx,
 296                         wait_info);
 297
 298         if (ret <= 0) {
 299                 irq_status = dpu_core_irq_read(phys_enc->dpu_kms,
 300                                 irq->irq_idx, true);
 301                 if (irq_status) {
 302                         unsigned long flags;
 303
 304                         DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
 305                                       "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
 306                                       DRMID(phys_enc->parent), intr_idx,
 307                                       irq->hw_idx, irq->irq_idx,
 308                                       phys_enc->hw_pp->idx - PINGPONG_0,
 309                                       atomic_read(wait_info->atomic_cnt));
 310                         local_irq_save(flags);
 311                         irq->cb.func(phys_enc, irq->irq_idx);
 312                         local_irq_restore(flags);
 313                         ret = 0;
 314                 } else {
 315                         ret = -ETIMEDOUT;
 316                         DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
 317                                       "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
 318                                       DRMID(phys_enc->parent), intr_idx,
 319                                       irq->hw_idx, irq->irq_idx,
 320                                       phys_enc->hw_pp->idx - PINGPONG_0,
 321                                       atomic_read(wait_info->atomic_cnt));
 322                 }
 323         } else {
 324                 ret = 0;
 325                 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
 326                         intr_idx, irq->hw_idx, irq->irq_idx,
 327                         phys_enc->hw_pp->idx - PINGPONG_0,
 328                         atomic_read(wait_info->atomic_cnt));
 329         }
 330
 331         return ret;
 332 }
 333
 334 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 335                 enum dpu_intr_idx intr_idx)
 336 {
 337         struct dpu_encoder_irq *irq;
 338         int ret = 0;
 339
 340         if (intr_idx >= INTR_IDX_MAX) {
 341                 DPU_ERROR("invalid params\n");
 342                 return -EINVAL;
 343         }
 344         irq = &phys_enc->irq[intr_idx];
 345
 346         if (irq->irq_idx >= 0) {
 347                 DPU_DEBUG_PHYS(phys_enc,
 348                                 "skipping already registered irq %s type %d\n",
 349                                 irq->name, irq->intr_type);
 350                 return 0;
 351         }
 352
 353         irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
 354                         irq->intr_type, irq->hw_idx);
 355         if (irq->irq_idx < 0) {
 356                 DPU_ERROR_PHYS(phys_enc,
 357                         "failed to lookup IRQ index for %s type:%d\n",
 358                         irq->name, irq->intr_type);
 359                 return -EINVAL;
 360         }
 361
 362         ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx,
 363                         &irq->cb);
 364         if (ret) {
 365                 DPU_ERROR_PHYS(phys_enc,
 366                         "failed to register IRQ callback for %s\n",
 367                         irq->name);
 368                 irq->irq_idx = -EINVAL;
 369                 return ret;
 370         }
 371
 372         ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 373         if (ret) {
 374                 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
 375                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 376                           irq->irq_idx);
 377                 dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
 378                                 irq->irq_idx, &irq->cb);
 379                 irq->irq_idx = -EINVAL;
 380                 return ret;
 381         }
 382
 383         trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
 384                                 irq->hw_idx, irq->irq_idx);
 385
 386         return ret;
 387 }
 388
 389 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
 390                 enum dpu_intr_idx intr_idx)
 391 {
 392         struct dpu_encoder_irq *irq;
 393         int ret;
 394
 395         irq = &phys_enc->irq[intr_idx];
 396
 397         /* silently skip irqs that weren't registered */
 398         if (irq->irq_idx < 0) {
 399                 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
 400                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 401                           irq->irq_idx);
 402                 return 0;
 403         }
 404
 405         ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 406         if (ret) {
 407                 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
 408                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 409                           irq->irq_idx, ret);
 410         }
 411
 412         ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
 413                         &irq->cb);
 414         if (ret) {
 415                 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
 416                           DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
 417                           irq->irq_idx, ret);
 418         }
 419
 420         trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
 421                                              irq->hw_idx, irq->irq_idx);
 422
 423         irq->irq_idx = -EINVAL;
 424
 425         return 0;
 426 }
 427
 428 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 429                                   struct dpu_encoder_hw_resources *hw_res)
 430 {
 431         struct dpu_encoder_virt *dpu_enc = NULL;
 432         int i = 0;
 433
 434         dpu_enc = to_dpu_encoder_virt(drm_enc);
 435         DPU_DEBUG_ENC(dpu_enc, "\n");
 436
 437         /* Query resources used by phys encs, expected to be without overlap */
 438         memset(hw_res, 0, sizeof(*hw_res));
 439
 440         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 441                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 442
 443                 if (phys->ops.get_hw_resources)
 444                         phys->ops.get_hw_resources(phys, hw_res);
 445         }
 446 }
 447
 448 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
 449 {
 450         struct dpu_encoder_virt *dpu_enc = NULL;
 451         int i = 0;
 452
 453         if (!drm_enc) {
 454                 DPU_ERROR("invalid encoder\n");
 455                 return;
 456         }
 457
 458         dpu_enc = to_dpu_encoder_virt(drm_enc);
 459         DPU_DEBUG_ENC(dpu_enc, "\n");
 460
 461         mutex_lock(&dpu_enc->enc_lock);
 462
 463         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 464                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 465
 466                 if (phys->ops.destroy) {
 467                         phys->ops.destroy(phys);
 468                         --dpu_enc->num_phys_encs;
 469                         dpu_enc->phys_encs[i] = NULL;
 470                 }
 471         }
 472
 473         if (dpu_enc->num_phys_encs)
 474                 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
 475                                 dpu_enc->num_phys_encs);
 476         dpu_enc->num_phys_encs = 0;
 477         mutex_unlock(&dpu_enc->enc_lock);
 478
 479         drm_encoder_cleanup(drm_enc);
 480         mutex_destroy(&dpu_enc->enc_lock);
 481 }
 482
 483 void dpu_encoder_helper_split_config(
 484                 struct dpu_encoder_phys *phys_enc,
 485                 enum dpu_intf interface)
 486 {
 487         struct dpu_encoder_virt *dpu_enc;
 488         struct split_pipe_cfg cfg = { 0 };
 489         struct dpu_hw_mdp *hw_mdptop;
 490         struct msm_display_info *disp_info;
 491
 492         if (!phys_enc->hw_mdptop || !phys_enc->parent) {
 493                 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
 494                 return;
 495         }
 496
 497         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
 498         hw_mdptop = phys_enc->hw_mdptop;
 499         disp_info = &dpu_enc->disp_info;
 500
 501         if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
 502                 return;
 503
 504         /**
 505          * disable split modes since encoder will be operating in as the only
 506          * encoder, either for the entire use case in the case of, for example,
 507          * single DSI, or for this frame in the case of left/right only partial
 508          * update.
 509          */
 510         if (phys_enc->split_role == ENC_ROLE_SOLO) {
 511                 if (hw_mdptop->ops.setup_split_pipe)
 512                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 513                 return;
 514         }
 515
 516         cfg.en = true;
 517         cfg.mode = phys_enc->intf_mode;
 518         cfg.intf = interface;
 519
 520         if (cfg.en && phys_enc->ops.needs_single_flush &&
 521                         phys_enc->ops.needs_single_flush(phys_enc))
 522                 cfg.split_flush_en = true;
 523
 524         if (phys_enc->split_role == ENC_ROLE_MASTER) {
 525                 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
 526
 527                 if (hw_mdptop->ops.setup_split_pipe)
 528                         hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 529         }
 530 }
 531
 532 static struct msm_display_topology dpu_encoder_get_topology(
 533                         struct dpu_encoder_virt *dpu_enc,
 534                         struct dpu_kms *dpu_kms,
 535                         struct drm_display_mode *mode)
 536 {
 537         struct msm_display_topology topology = {0};
 538         int i, intf_count = 0;
 539
 540         for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
 541                 if (dpu_enc->phys_encs[i])
 542                         intf_count++;
 543
 544         /* Datapath topology selection
 545          *
 546          * Dual display
 547          * 2 LM, 2 INTF ( Split display using 2 interfaces)
 548          *
 549          * Single display
 550          * 1 LM, 1 INTF
 551          * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
 552          *
 553          * Adding color blocks only to primary interface if available in
 554          * sufficient number
 555          */
 556         if (intf_count == 2)
 557                 topology.num_lm = 2;
 558         else if (!dpu_kms->catalog->caps->has_3d_merge)
 559                 topology.num_lm = 1;
 560         else
 561                 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 562
 563         if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
 564                 if (dpu_kms->catalog->dspp &&
 565                         (dpu_kms->catalog->dspp_count >= topology.num_lm))
 566                         topology.num_dspp = topology.num_lm;
 567         }
 568
 569         topology.num_enc = 0;
 570         topology.num_intf = intf_count;
 571
 572         return topology;
 573 }
 574 static int dpu_encoder_virt_atomic_check(
 575                 struct drm_encoder *drm_enc,
 576                 struct drm_crtc_state *crtc_state,
 577                 struct drm_connector_state *conn_state)
 578 {
 579         struct dpu_encoder_virt *dpu_enc;
 580         struct msm_drm_private *priv;
 581         struct dpu_kms *dpu_kms;
 582         const struct drm_display_mode *mode;
 583         struct drm_display_mode *adj_mode;
 584         struct msm_display_topology topology;
 585         struct dpu_global_state *global_state;
 586         int i = 0;
 587         int ret = 0;
 588
 589         if (!drm_enc || !crtc_state || !conn_state) {
 590                 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
 591                                 drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
 592                 return -EINVAL;
 593         }
 594
 595         dpu_enc = to_dpu_encoder_virt(drm_enc);
 596         DPU_DEBUG_ENC(dpu_enc, "\n");
 597
 598         priv = drm_enc->dev->dev_private;
 599         dpu_kms = to_dpu_kms(priv->kms);
 600         mode = &crtc_state->mode;
 601         adj_mode = &crtc_state->adjusted_mode;
 602         global_state = dpu_kms_get_existing_global_state(dpu_kms);
 603         trace_dpu_enc_atomic_check(DRMID(drm_enc));
 604
 605         /* perform atomic check on the first physical encoder (master) */
 606         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 607                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 608
 609                 if (phys->ops.atomic_check)
 610                         ret = phys->ops.atomic_check(phys, crtc_state,
 611                                         conn_state);
 612                 else if (phys->ops.mode_fixup)
 613                         if (!phys->ops.mode_fixup(phys, mode, adj_mode))
 614                                 ret = -EINVAL;
 615
 616                 if (ret) {
 617                         DPU_ERROR_ENC(dpu_enc,
 618                                         "mode unsupported, phys idx %d\n", i);
 619                         break;
 620                 }
 621         }
 622
 623         topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 624
 625         /* Reserve dynamic resources now. */
 626         if (!ret) {
 627                 /*
 628                  * Avoid reserving resources when mode set is pending. Topology
 629                  * info may not be available to complete reservation.
 630                  */
 631                 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
 632                         ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
 633                                         drm_enc, crtc_state, topology);
 634                 }
 635         }
 636
 637         trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
 638
 639         return ret;
 640 }
 641
 642 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
 643                         struct msm_display_info *disp_info)
 644 {
 645         struct dpu_vsync_source_cfg vsync_cfg = { 0 };
 646         struct msm_drm_private *priv;
 647         struct dpu_kms *dpu_kms;
 648         struct dpu_hw_mdp *hw_mdptop;
 649         struct drm_encoder *drm_enc;
 650         int i;
 651
 652         if (!dpu_enc || !disp_info) {
 653                 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
 654                                         dpu_enc != NULL, disp_info != NULL);
 655                 return;
 656         } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
 657                 DPU_ERROR("invalid num phys enc %d/%d\n",
 658                                 dpu_enc->num_phys_encs,
 659                                 (int) ARRAY_SIZE(dpu_enc->hw_pp));
 660                 return;
 661         }
 662
 663         drm_enc = &dpu_enc->base;
 664         /* this pointers are checked in virt_enable_helper */
 665         priv = drm_enc->dev->dev_private;
 666
 667         dpu_kms = to_dpu_kms(priv->kms);
 668         hw_mdptop = dpu_kms->hw_mdp;
 669         if (!hw_mdptop) {
 670                 DPU_ERROR("invalid mdptop\n");
 671                 return;
 672         }
 673
 674         if (hw_mdptop->ops.setup_vsync_source &&
 675                         disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
 676                 for (i = 0; i < dpu_enc->num_phys_encs; i++)
 677                         vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
 678
 679                 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
 680                 if (disp_info->is_te_using_watchdog_timer)
 681                         vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
 682                 else
 683                         vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
 684
 685                 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
 686         }
 687 }
 688
 689 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
 690 {
 691         struct dpu_encoder_virt *dpu_enc;
 692         int i;
 693
 694         if (!drm_enc) {
 695                 DPU_ERROR("invalid encoder\n");
 696                 return;
 697         }
 698
 699         dpu_enc = to_dpu_encoder_virt(drm_enc);
 700
 701         DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
 702         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 703                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 704
 705                 if (phys->ops.irq_control)
 706                         phys->ops.irq_control(phys, enable);
 707         }
 708
 709 }
 710
 711 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 712                 bool enable)
 713 {
 714         struct msm_drm_private *priv;
 715         struct dpu_kms *dpu_kms;
 716         struct dpu_encoder_virt *dpu_enc;
 717
 718         dpu_enc = to_dpu_encoder_virt(drm_enc);
 719         priv = drm_enc->dev->dev_private;
 720         dpu_kms = to_dpu_kms(priv->kms);
 721
 722         trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
 723
 724         if (!dpu_enc->cur_master) {
 725                 DPU_ERROR("encoder master not set\n");
 726                 return;
 727         }
 728
 729         if (enable) {
 730                 /* enable DPU core clks */
 731                 pm_runtime_get_sync(&dpu_kms->pdev->dev);
 732
 733                 /* enable all the irq */
 734                 _dpu_encoder_irq_control(drm_enc, true);
 735
 736         } else {
 737                 /* disable all the irq */
 738                 _dpu_encoder_irq_control(drm_enc, false);
 739
 740                 /* disable DPU core clks */
 741                 pm_runtime_put_sync(&dpu_kms->pdev->dev);
 742         }
 743
 744 }
 745
 746 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 747                 u32 sw_event)
 748 {
 749         struct dpu_encoder_virt *dpu_enc;
 750         struct msm_drm_private *priv;
 751         bool is_vid_mode = false;
 752
 753         if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
 754                 DPU_ERROR("invalid parameters\n");
 755                 return -EINVAL;
 756         }
 757         dpu_enc = to_dpu_encoder_virt(drm_enc);
 758         priv = drm_enc->dev->dev_private;
 759         is_vid_mode = dpu_enc->disp_info.capabilities &
 760                                                 MSM_DISPLAY_CAP_VID_MODE;
 761
 762         /*
 763          * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
 764          * events and return early for other events (ie wb display).
 765          */
 766         if (!dpu_enc->idle_pc_supported &&
 767                         (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
 768                         sw_event != DPU_ENC_RC_EVENT_STOP &&
 769                         sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
 770                 return 0;
 771
 772         trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
 773                          dpu_enc->rc_state, "begin");
 774
 775         switch (sw_event) {
 776         case DPU_ENC_RC_EVENT_KICKOFF:
 777                 /* cancel delayed off work, if any */
 778                 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 779                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 780                                         sw_event);
 781
 782                 mutex_lock(&dpu_enc->rc_lock);
 783
 784                 /* return if the resource control is already in ON state */
 785                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 786                         DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n",
 787                                       DRMID(drm_enc), sw_event);
 788                         mutex_unlock(&dpu_enc->rc_lock);
 789                         return 0;
 790                 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
 791                                 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
 792                         DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n",
 793                                       DRMID(drm_enc), sw_event,
 794                                       dpu_enc->rc_state);
 795                         mutex_unlock(&dpu_enc->rc_lock);
 796                         return -EINVAL;
 797                 }
 798
 799                 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
 800                         _dpu_encoder_irq_control(drm_enc, true);
 801                 else
 802                         _dpu_encoder_resource_control_helper(drm_enc, true);
 803
 804                 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
 805
 806                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 807                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 808                                  "kickoff");
 809
 810                 mutex_unlock(&dpu_enc->rc_lock);
 811                 break;
 812
 813         case DPU_ENC_RC_EVENT_FRAME_DONE:
 814                 /*
 815                  * mutex lock is not used as this event happens at interrupt
 816                  * context. And locking is not required as, the other events
 817                  * like KICKOFF and STOP does a wait-for-idle before executing
 818                  * the resource_control
 819                  */
 820                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 821                         DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
 822                                       DRMID(drm_enc), sw_event,
 823                                       dpu_enc->rc_state);
 824                         return -EINVAL;
 825                 }
 826
 827                 /*
 828                  * schedule off work item only when there are no
 829                  * frames pending
 830                  */
 831                 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
 832                         DRM_DEBUG_KMS("id:%d skip schedule work\n",
 833                                       DRMID(drm_enc));
 834                         return 0;
 835                 }
 836
 837                 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
 838                                    msecs_to_jiffies(dpu_enc->idle_timeout));
 839
 840                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 841                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 842                                  "frame done");
 843                 break;
 844
 845         case DPU_ENC_RC_EVENT_PRE_STOP:
 846                 /* cancel delayed off work, if any */
 847                 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 848                         DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 849                                         sw_event);
 850
 851                 mutex_lock(&dpu_enc->rc_lock);
 852
 853                 if (is_vid_mode &&
 854                           dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 855                         _dpu_encoder_irq_control(drm_enc, true);
 856                 }
 857                 /* skip if is already OFF or IDLE, resources are off already */
 858                 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
 859                                 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 860                         DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
 861                                       DRMID(drm_enc), sw_event,
 862                                       dpu_enc->rc_state);
 863                         mutex_unlock(&dpu_enc->rc_lock);
 864                         return 0;
 865                 }
 866
 867                 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
 868
 869                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 870                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 871                                  "pre stop");
 872
 873                 mutex_unlock(&dpu_enc->rc_lock);
 874                 break;
 875
 876         case DPU_ENC_RC_EVENT_STOP:
 877                 mutex_lock(&dpu_enc->rc_lock);
 878
 879                 /* return if the resource control is already in OFF state */
 880                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
 881                         DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
 882                                       DRMID(drm_enc), sw_event);
 883                         mutex_unlock(&dpu_enc->rc_lock);
 884                         return 0;
 885                 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 886                         DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
 887                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 888                         mutex_unlock(&dpu_enc->rc_lock);
 889                         return -EINVAL;
 890                 }
 891
 892                 /**
 893                  * expect to arrive here only if in either idle state or pre-off
 894                  * and in IDLE state the resources are already disabled
 895                  */
 896                 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
 897                         _dpu_encoder_resource_control_helper(drm_enc, false);
 898
 899                 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
 900
 901                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 902                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 903                                  "stop");
 904
 905                 mutex_unlock(&dpu_enc->rc_lock);
 906                 break;
 907
 908         case DPU_ENC_RC_EVENT_ENTER_IDLE:
 909                 mutex_lock(&dpu_enc->rc_lock);
 910
 911                 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 912                         DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
 913                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 914                         mutex_unlock(&dpu_enc->rc_lock);
 915                         return 0;
 916                 }
 917
 918                 /*
 919                  * if we are in ON but a frame was just kicked off,
 920                  * ignore the IDLE event, it's probably a stale timer event
 921                  */
 922                 if (dpu_enc->frame_busy_mask[0]) {
 923                         DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
 924                                   DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 925                         mutex_unlock(&dpu_enc->rc_lock);
 926                         return 0;
 927                 }
 928
 929                 if (is_vid_mode)
 930                         _dpu_encoder_irq_control(drm_enc, false);
 931                 else
 932                         _dpu_encoder_resource_control_helper(drm_enc, false);
 933
 934                 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
 935
 936                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 937                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 938                                  "idle");
 939
 940                 mutex_unlock(&dpu_enc->rc_lock);
 941                 break;
 942
 943         default:
 944                 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
 945                           sw_event);
 946                 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 947                                  dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 948                                  "error");
 949                 break;
 950         }
 951
 952         trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 953                          dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 954                          "end");
 955         return 0;
 956 }
 957
 958 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 959                                       struct drm_display_mode *mode,
 960                                       struct drm_display_mode *adj_mode)
 961 {
 962         struct dpu_encoder_virt *dpu_enc;
 963         struct msm_drm_private *priv;
 964         struct dpu_kms *dpu_kms;
 965         struct list_head *connector_list;
 966         struct drm_connector *conn = NULL, *conn_iter;
 967         struct drm_crtc *drm_crtc;
 968         struct dpu_crtc_state *cstate;
 969         struct dpu_global_state *global_state;
 970         struct msm_display_topology topology;
 971         struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
 972         struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
 973         struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
 974         struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
 975         int num_lm, num_ctl, num_pp, num_dspp;
 976         int i, j;
 977
 978         if (!drm_enc) {
 979                 DPU_ERROR("invalid encoder\n");
 980                 return;
 981         }
 982
 983         dpu_enc = to_dpu_encoder_virt(drm_enc);
 984         DPU_DEBUG_ENC(dpu_enc, "\n");
 985
 986         priv = drm_enc->dev->dev_private;
 987         dpu_kms = to_dpu_kms(priv->kms);
 988         connector_list = &dpu_kms->dev->mode_config.connector_list;
 989
 990         global_state = dpu_kms_get_existing_global_state(dpu_kms);
 991         if (IS_ERR_OR_NULL(global_state)) {
 992                 DPU_ERROR("Failed to get global state");
 993                 return;
 994         }
 995
 996         trace_dpu_enc_mode_set(DRMID(drm_enc));
 997
 998         list_for_each_entry(conn_iter, connector_list, head)
 999                 if (conn_iter->encoder == drm_enc)
1000                         conn = conn_iter;
1001
1002         if (!conn) {
1003                 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n");
1004                 return;
1005         } else if (!conn->state) {
1006                 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n");
1007                 return;
1008         }
1009
1010         drm_for_each_crtc(drm_crtc, drm_enc->dev)
1011                 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
1012                         break;
1013
1014         topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
1015
1016         /* Query resource that have been reserved in atomic check step. */
1017         num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1018                 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
1019                 ARRAY_SIZE(hw_pp));
1020         num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1021                 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1022         num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1023                 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
1024         num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1025                 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
1026                 ARRAY_SIZE(hw_dspp));
1027
1028         for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1029                 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1030                                                 : NULL;
1031
1032         cstate = to_dpu_crtc_state(drm_crtc->state);
1033
1034         for (i = 0; i < num_lm; i++) {
1035                 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1036
1037                 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
1038                 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
1039                 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
1040         }
1041
1042         cstate->num_mixers = num_lm;
1043
1044         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1045                 int num_blk;
1046                 struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC];
1047                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1048
1049                 if (!dpu_enc->hw_pp[i]) {
1050                         DPU_ERROR_ENC(dpu_enc,
1051                                 "no pp block assigned at idx: %d\n", i);
1052                         return;
1053                 }
1054
1055                 if (!hw_ctl[i]) {
1056                         DPU_ERROR_ENC(dpu_enc,
1057                                 "no ctl block assigned at idx: %d\n", i);
1058                         return;
1059                 }
1060
1061                 phys->hw_pp = dpu_enc->hw_pp[i];
1062                 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
1063
1064                 num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm,
1065                         global_state, drm_enc->base.id, DPU_HW_BLK_INTF,
1066                         hw_blk, ARRAY_SIZE(hw_blk));
1067                 for (j = 0; j < num_blk; j++) {
1068                         struct dpu_hw_intf *hw_intf;
1069
1070                         hw_intf = to_dpu_hw_intf(hw_blk[i]);
1071                         if (hw_intf->idx == phys->intf_idx)
1072                                 phys->hw_intf = hw_intf;
1073                 }
1074
1075                 if (!phys->hw_intf) {
1076                         DPU_ERROR_ENC(dpu_enc,
1077                                       "no intf block assigned at idx: %d\n", i);
1078                         return;
1079                 }
1080
1081                 phys->connector = conn->state->connector;
1082                 if (phys->ops.mode_set)
1083                         phys->ops.mode_set(phys, mode, adj_mode);
1084         }
1085 }
1086
1087 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1088 {
1089         struct dpu_encoder_virt *dpu_enc = NULL;
1090         struct msm_drm_private *priv;
1091         int i;
1092
1093         if (!drm_enc || !drm_enc->dev) {
1094                 DPU_ERROR("invalid parameters\n");
1095                 return;
1096         }
1097
1098         priv = drm_enc->dev->dev_private;
1099
1100         dpu_enc = to_dpu_encoder_virt(drm_enc);
1101         if (!dpu_enc || !dpu_enc->cur_master) {
1102                 DPU_ERROR("invalid dpu encoder/master\n");
1103                 return;
1104         }
1105
1106         _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1107
1108         if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1109                         !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1110                 unsigned bpc = dpu_enc->phys_encs[0]->connector->display_info.bpc;
1111                 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1112                         if (!dpu_enc->hw_pp[i])
1113                                 continue;
1114                         _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1115                 }
1116         }
1117 }
1118
1119 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1120 {
1121         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1122
1123         mutex_lock(&dpu_enc->enc_lock);
1124
1125         if (!dpu_enc->enabled)
1126                 goto out;
1127
1128         if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1129                 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1130         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1131                 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1132
1133         _dpu_encoder_virt_enable_helper(drm_enc);
1134
1135 out:
1136         mutex_unlock(&dpu_enc->enc_lock);
1137 }
1138
1139 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1140 {
1141         struct dpu_encoder_virt *dpu_enc = NULL;
1142         int ret = 0;
1143         struct drm_display_mode *cur_mode = NULL;
1144
1145         if (!drm_enc) {
1146                 DPU_ERROR("invalid encoder\n");
1147                 return;
1148         }
1149         dpu_enc = to_dpu_encoder_virt(drm_enc);
1150
1151         mutex_lock(&dpu_enc->enc_lock);
1152         cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1153
1154         trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1155                              cur_mode->vdisplay);
1156
1157         /* always enable slave encoder before master */
1158         if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1159                 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1160
1161         if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1162                 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1163
1164         ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1165         if (ret) {
1166                 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1167                                 ret);
1168                 goto out;
1169         }
1170
1171         _dpu_encoder_virt_enable_helper(drm_enc);
1172
1173         dpu_enc->enabled = true;
1174
1175 out:
1176         mutex_unlock(&dpu_enc->enc_lock);
1177 }
1178
1179 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1180 {
1181         struct dpu_encoder_virt *dpu_enc = NULL;
1182         struct msm_drm_private *priv;
1183         struct dpu_kms *dpu_kms;
1184         struct dpu_global_state *global_state;
1185         int i = 0;
1186
1187         if (!drm_enc) {
1188                 DPU_ERROR("invalid encoder\n");
1189                 return;
1190         } else if (!drm_enc->dev) {
1191                 DPU_ERROR("invalid dev\n");
1192                 return;
1193         }
1194
1195         dpu_enc = to_dpu_encoder_virt(drm_enc);
1196         DPU_DEBUG_ENC(dpu_enc, "\n");
1197
1198         mutex_lock(&dpu_enc->enc_lock);
1199         dpu_enc->enabled = false;
1200
1201         priv = drm_enc->dev->dev_private;
1202         dpu_kms = to_dpu_kms(priv->kms);
1203         global_state = dpu_kms_get_existing_global_state(dpu_kms);
1204
1205         trace_dpu_enc_disable(DRMID(drm_enc));
1206
1207         /* wait for idle */
1208         dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1209
1210         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1211
1212         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1213                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1214
1215                 if (phys->ops.disable)
1216                         phys->ops.disable(phys);
1217         }
1218
1219         /* after phys waits for frame-done, should be no more frames pending */
1220         if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1221                 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1222                 del_timer_sync(&dpu_enc->frame_done_timer);
1223         }
1224
1225         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1226
1227         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1228                 dpu_enc->phys_encs[i]->connector = NULL;
1229         }
1230
1231         DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1232
1233         dpu_rm_release(global_state, drm_enc);
1234
1235         mutex_unlock(&dpu_enc->enc_lock);
1236 }
1237
1238 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
1239                 enum dpu_intf_type type, u32 controller_id)
1240 {
1241         int i = 0;
1242
1243         for (i = 0; i < catalog->intf_count; i++) {
1244                 if (catalog->intf[i].type == type
1245                     && catalog->intf[i].controller_id == controller_id) {
1246                         return catalog->intf[i].id;
1247                 }
1248         }
1249
1250         return INTF_MAX;
1251 }
1252
1253 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1254                 struct dpu_encoder_phys *phy_enc)
1255 {
1256         struct dpu_encoder_virt *dpu_enc = NULL;
1257         unsigned long lock_flags;
1258
1259         if (!drm_enc || !phy_enc)
1260                 return;
1261
1262         DPU_ATRACE_BEGIN("encoder_vblank_callback");
1263         dpu_enc = to_dpu_encoder_virt(drm_enc);
1264
1265         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1266         if (dpu_enc->crtc)
1267                 dpu_crtc_vblank_callback(dpu_enc->crtc);
1268         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1269
1270         atomic_inc(&phy_enc->vsync_cnt);
1271         DPU_ATRACE_END("encoder_vblank_callback");
1272 }
1273
1274 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1275                 struct dpu_encoder_phys *phy_enc)
1276 {
1277         if (!phy_enc)
1278                 return;
1279
1280         DPU_ATRACE_BEGIN("encoder_underrun_callback");
1281         atomic_inc(&phy_enc->underrun_cnt);
1282         trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1283                                   atomic_read(&phy_enc->underrun_cnt));
1284         DPU_ATRACE_END("encoder_underrun_callback");
1285 }
1286
1287 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1288 {
1289         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1290         unsigned long lock_flags;
1291
1292         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1293         /* crtc should always be cleared before re-assigning */
1294         WARN_ON(crtc && dpu_enc->crtc);
1295         dpu_enc->crtc = crtc;
1296         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1297 }
1298
1299 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1300                                         struct drm_crtc *crtc, bool enable)
1301 {
1302         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1303         unsigned long lock_flags;
1304         int i;
1305
1306         trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1307
1308         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1309         if (dpu_enc->crtc != crtc) {
1310                 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1311                 return;
1312         }
1313         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1314
1315         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1316                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1317
1318                 if (phys->ops.control_vblank_irq)
1319                         phys->ops.control_vblank_irq(phys, enable);
1320         }
1321 }
1322
1323 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1324                 void (*frame_event_cb)(void *, u32 event),
1325                 void *frame_event_cb_data)
1326 {
1327         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1328         unsigned long lock_flags;
1329         bool enable;
1330
1331         enable = frame_event_cb ? true : false;
1332
1333         if (!drm_enc) {
1334                 DPU_ERROR("invalid encoder\n");
1335                 return;
1336         }
1337         trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1338
1339         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1340         dpu_enc->crtc_frame_event_cb = frame_event_cb;
1341         dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1342         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1343 }
1344
1345 static void dpu_encoder_frame_done_callback(
1346                 struct drm_encoder *drm_enc,
1347                 struct dpu_encoder_phys *ready_phys, u32 event)
1348 {
1349         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1350         unsigned int i;
1351
1352         if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1353                         | DPU_ENCODER_FRAME_EVENT_ERROR
1354                         | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1355
1356                 if (!dpu_enc->frame_busy_mask[0]) {
1357                         /**
1358                          * suppress frame_done without waiter,
1359                          * likely autorefresh
1360                          */
1361                         trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
1362                                         event, ready_phys->intf_idx);
1363                         return;
1364                 }
1365
1366                 /* One of the physical encoders has become idle */
1367                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1368                         if (dpu_enc->phys_encs[i] == ready_phys) {
1369                                 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1370                                                 dpu_enc->frame_busy_mask[0]);
1371                                 clear_bit(i, dpu_enc->frame_busy_mask);
1372                         }
1373                 }
1374
1375                 if (!dpu_enc->frame_busy_mask[0]) {
1376                         atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1377                         del_timer(&dpu_enc->frame_done_timer);
1378
1379                         dpu_encoder_resource_control(drm_enc,
1380                                         DPU_ENC_RC_EVENT_FRAME_DONE);
1381
1382                         if (dpu_enc->crtc_frame_event_cb)
1383                                 dpu_enc->crtc_frame_event_cb(
1384                                         dpu_enc->crtc_frame_event_cb_data,
1385                                         event);
1386                 }
1387         } else {
1388                 if (dpu_enc->crtc_frame_event_cb)
1389                         dpu_enc->crtc_frame_event_cb(
1390                                 dpu_enc->crtc_frame_event_cb_data, event);
1391         }
1392 }
1393
1394 static void dpu_encoder_off_work(struct work_struct *work)
1395 {
1396         struct dpu_encoder_virt *dpu_enc = container_of(work,
1397                         struct dpu_encoder_virt, delayed_off_work.work);
1398
1399         if (!dpu_enc) {
1400                 DPU_ERROR("invalid dpu encoder\n");
1401                 return;
1402         }
1403
1404         dpu_encoder_resource_control(&dpu_enc->base,
1405                                                 DPU_ENC_RC_EVENT_ENTER_IDLE);
1406
1407         dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1408                                 DPU_ENCODER_FRAME_EVENT_IDLE);
1409 }
1410
1411 /**
1412  * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1413  * drm_enc: Pointer to drm encoder structure
1414  * phys: Pointer to physical encoder structure
1415  * extra_flush_bits: Additional bit mask to include in flush trigger
1416  */
1417 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1418                 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1419 {
1420         struct dpu_hw_ctl *ctl;
1421         int pending_kickoff_cnt;
1422         u32 ret = UINT_MAX;
1423
1424         if (!phys->hw_pp) {
1425                 DPU_ERROR("invalid pingpong hw\n");
1426                 return;
1427         }
1428
1429         ctl = phys->hw_ctl;
1430         if (!ctl->ops.trigger_flush) {
1431                 DPU_ERROR("missing trigger cb\n");
1432                 return;
1433         }
1434
1435         pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1436
1437         if (extra_flush_bits && ctl->ops.update_pending_flush)
1438                 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1439
1440         ctl->ops.trigger_flush(ctl);
1441
1442         if (ctl->ops.get_pending_flush)
1443                 ret = ctl->ops.get_pending_flush(ctl);
1444
1445         trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1446                                     pending_kickoff_cnt, ctl->idx,
1447                                     extra_flush_bits, ret);
1448 }
1449
1450 /**
1451  * _dpu_encoder_trigger_start - trigger start for a physical encoder
1452  * phys: Pointer to physical encoder structure
1453  */
1454 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1455 {
1456         if (!phys) {
1457                 DPU_ERROR("invalid argument(s)\n");
1458                 return;
1459         }
1460
1461         if (!phys->hw_pp) {
1462                 DPU_ERROR("invalid pingpong hw\n");
1463                 return;
1464         }
1465
1466         if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1467                 phys->ops.trigger_start(phys);
1468 }
1469
1470 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1471 {
1472         struct dpu_hw_ctl *ctl;
1473
1474         ctl = phys_enc->hw_ctl;
1475         if (ctl->ops.trigger_start) {
1476                 ctl->ops.trigger_start(ctl);
1477                 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1478         }
1479 }
1480
1481 static int dpu_encoder_helper_wait_event_timeout(
1482                 int32_t drm_id,
1483                 int32_t hw_id,
1484                 struct dpu_encoder_wait_info *info)
1485 {
1486         int rc = 0;
1487         s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1488         s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1489         s64 time;
1490
1491         do {
1492                 rc = wait_event_timeout(*(info->wq),
1493                                 atomic_read(info->atomic_cnt) == 0, jiffies);
1494                 time = ktime_to_ms(ktime_get());
1495
1496                 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
1497                                                  expected_time,
1498                                                  atomic_read(info->atomic_cnt));
1499         /* If we timed out, counter is valid and time is less, wait again */
1500         } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1501                         (time < expected_time));
1502
1503         return rc;
1504 }
1505
1506 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1507 {
1508         struct dpu_encoder_virt *dpu_enc;
1509         struct dpu_hw_ctl *ctl;
1510         int rc;
1511
1512         dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1513         ctl = phys_enc->hw_ctl;
1514
1515         if (!ctl->ops.reset)
1516                 return;
1517
1518         DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent),
1519                       ctl->idx);
1520
1521         rc = ctl->ops.reset(ctl);
1522         if (rc)
1523                 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
1524
1525         phys_enc->enable_state = DPU_ENC_ENABLED;
1526 }
1527
1528 /**
1529  * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1530  *      Iterate through the physical encoders and perform consolidated flush
1531  *      and/or control start triggering as needed. This is done in the virtual
1532  *      encoder rather than the individual physical ones in order to handle
1533  *      use cases that require visibility into multiple physical encoders at
1534  *      a time.
1535  * dpu_enc: Pointer to virtual encoder structure
1536  */
1537 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1538 {
1539         struct dpu_hw_ctl *ctl;
1540         uint32_t i, pending_flush;
1541         unsigned long lock_flags;
1542
1543         pending_flush = 0x0;
1544
1545         /* update pending counts and trigger kickoff ctl flush atomically */
1546         spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1547
1548         /* don't perform flush/start operations for slave encoders */
1549         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1550                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1551
1552                 if (phys->enable_state == DPU_ENC_DISABLED)
1553                         continue;
1554
1555                 ctl = phys->hw_ctl;
1556
1557                 /*
1558                  * This is cleared in frame_done worker, which isn't invoked
1559                  * for async commits. So don't set this for async, since it'll
1560                  * roll over to the next commit.
1561                  */
1562                 if (phys->split_role != ENC_ROLE_SLAVE)
1563                         set_bit(i, dpu_enc->frame_busy_mask);
1564
1565                 if (!phys->ops.needs_single_flush ||
1566                                 !phys->ops.needs_single_flush(phys))
1567                         _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1568                 else if (ctl->ops.get_pending_flush)
1569                         pending_flush |= ctl->ops.get_pending_flush(ctl);
1570         }
1571
1572         /* for split flush, combine pending flush masks and send to master */
1573         if (pending_flush && dpu_enc->cur_master) {
1574                 _dpu_encoder_trigger_flush(
1575                                 &dpu_enc->base,
1576                                 dpu_enc->cur_master,
1577                                 pending_flush);
1578         }
1579
1580         _dpu_encoder_trigger_start(dpu_enc->cur_master);
1581
1582         spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1583 }
1584
1585 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1586 {
1587         struct dpu_encoder_virt *dpu_enc;
1588         struct dpu_encoder_phys *phys;
1589         unsigned int i;
1590         struct dpu_hw_ctl *ctl;
1591         struct msm_display_info *disp_info;
1592
1593         if (!drm_enc) {
1594                 DPU_ERROR("invalid encoder\n");
1595                 return;
1596         }
1597         dpu_enc = to_dpu_encoder_virt(drm_enc);
1598         disp_info = &dpu_enc->disp_info;
1599
1600         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1601                 phys = dpu_enc->phys_encs[i];
1602
1603                 ctl = phys->hw_ctl;
1604                 if (ctl->ops.clear_pending_flush)
1605                         ctl->ops.clear_pending_flush(ctl);
1606
1607                 /* update only for command mode primary ctl */
1608                 if ((phys == dpu_enc->cur_master) &&
1609                    (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1610                     && ctl->ops.trigger_pending)
1611                         ctl->ops.trigger_pending(ctl);
1612         }
1613 }
1614
1615 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1616                 struct drm_display_mode *mode)
1617 {
1618         u64 pclk_rate;
1619         u32 pclk_period;
1620         u32 line_time;
1621
1622         /*
1623          * For linetime calculation, only operate on master encoder.
1624          */
1625         if (!dpu_enc->cur_master)
1626                 return 0;
1627
1628         if (!dpu_enc->cur_master->ops.get_line_count) {
1629                 DPU_ERROR("get_line_count function not defined\n");
1630                 return 0;
1631         }
1632
1633         pclk_rate = mode->clock; /* pixel clock in kHz */
1634         if (pclk_rate == 0) {
1635                 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1636                 return 0;
1637         }
1638
1639         pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1640         if (pclk_period == 0) {
1641                 DPU_ERROR("pclk period is 0\n");
1642                 return 0;
1643         }
1644
1645         /*
1646          * Line time calculation based on Pixel clock and HTOTAL.
1647          * Final unit is in ns.
1648          */
1649         line_time = (pclk_period * mode->htotal) / 1000;
1650         if (line_time == 0) {
1651                 DPU_ERROR("line time calculation is 0\n");
1652                 return 0;
1653         }
1654
1655         DPU_DEBUG_ENC(dpu_enc,
1656                         "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1657                         pclk_rate, pclk_period, line_time);
1658
1659         return line_time;
1660 }
1661
1662 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1663 {
1664         struct drm_display_mode *mode;
1665         struct dpu_encoder_virt *dpu_enc;
1666         u32 cur_line;
1667         u32 line_time;
1668         u32 vtotal, time_to_vsync;
1669         ktime_t cur_time;
1670
1671         dpu_enc = to_dpu_encoder_virt(drm_enc);
1672
1673         if (!drm_enc->crtc || !drm_enc->crtc->state) {
1674                 DPU_ERROR("crtc/crtc state object is NULL\n");
1675                 return -EINVAL;
1676         }
1677         mode = &drm_enc->crtc->state->adjusted_mode;
1678
1679         line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1680         if (!line_time)
1681                 return -EINVAL;
1682
1683         cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1684
1685         vtotal = mode->vtotal;
1686         if (cur_line >= vtotal)
1687                 time_to_vsync = line_time * vtotal;
1688         else
1689                 time_to_vsync = line_time * (vtotal - cur_line);
1690
1691         if (time_to_vsync == 0) {
1692                 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1693                                 vtotal);
1694                 return -EINVAL;
1695         }
1696
1697         cur_time = ktime_get();
1698         *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1699
1700         DPU_DEBUG_ENC(dpu_enc,
1701                         "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1702                         cur_line, vtotal, time_to_vsync,
1703                         ktime_to_ms(cur_time),
1704                         ktime_to_ms(*wakeup_time));
1705         return 0;
1706 }
1707
1708 static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1709 {
1710         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1711                         vsync_event_timer);
1712         struct drm_encoder *drm_enc = &dpu_enc->base;
1713         struct msm_drm_private *priv;
1714         struct msm_drm_thread *event_thread;
1715
1716         if (!drm_enc->dev || !drm_enc->crtc) {
1717                 DPU_ERROR("invalid parameters\n");
1718                 return;
1719         }
1720
1721         priv = drm_enc->dev->dev_private;
1722
1723         if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1724                 DPU_ERROR("invalid crtc index\n");
1725                 return;
1726         }
1727         event_thread = &priv->event_thread[drm_enc->crtc->index];
1728         if (!event_thread) {
1729                 DPU_ERROR("event_thread not found for crtc:%d\n",
1730                                 drm_enc->crtc->index);
1731                 return;
1732         }
1733
1734         del_timer(&dpu_enc->vsync_event_timer);
1735 }
1736
1737 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1738 {
1739         struct dpu_encoder_virt *dpu_enc = container_of(work,
1740                         struct dpu_encoder_virt, vsync_event_work);
1741         ktime_t wakeup_time;
1742
1743         if (!dpu_enc) {
1744                 DPU_ERROR("invalid dpu encoder\n");
1745                 return;
1746         }
1747
1748         if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1749                 return;
1750
1751         trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1752         mod_timer(&dpu_enc->vsync_event_timer,
1753                         nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1754 }
1755
1756 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1757 {
1758         struct dpu_encoder_virt *dpu_enc;
1759         struct dpu_encoder_phys *phys;
1760         bool needs_hw_reset = false;
1761         unsigned int i;
1762
1763         dpu_enc = to_dpu_encoder_virt(drm_enc);
1764
1765         trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1766
1767         /* prepare for next kickoff, may include waiting on previous kickoff */
1768         DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1769         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1770                 phys = dpu_enc->phys_encs[i];
1771                 if (phys->ops.prepare_for_kickoff)
1772                         phys->ops.prepare_for_kickoff(phys);
1773                 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1774                         needs_hw_reset = true;
1775         }
1776         DPU_ATRACE_END("enc_prepare_for_kickoff");
1777
1778         dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1779
1780         /* if any phys needs reset, reset all phys, in-order */
1781         if (needs_hw_reset) {
1782                 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1783                 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1784                         dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1785                 }
1786         }
1787 }
1788
1789 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1790 {
1791         struct dpu_encoder_virt *dpu_enc;
1792         struct dpu_encoder_phys *phys;
1793         ktime_t wakeup_time;
1794         unsigned long timeout_ms;
1795         unsigned int i;
1796
1797         DPU_ATRACE_BEGIN("encoder_kickoff");
1798         dpu_enc = to_dpu_encoder_virt(drm_enc);
1799
1800         trace_dpu_enc_kickoff(DRMID(drm_enc));
1801
1802         timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1803                         drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1804
1805         atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1806         mod_timer(&dpu_enc->frame_done_timer,
1807                         jiffies + msecs_to_jiffies(timeout_ms));
1808
1809         /* All phys encs are ready to go, trigger the kickoff */
1810         _dpu_encoder_kickoff_phys(dpu_enc);
1811
1812         /* allow phys encs to handle any post-kickoff business */
1813         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1814                 phys = dpu_enc->phys_encs[i];
1815                 if (phys->ops.handle_post_kickoff)
1816                         phys->ops.handle_post_kickoff(phys);
1817         }
1818
1819         if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1820                         !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
1821                 trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1822                                             ktime_to_ms(wakeup_time));
1823                 mod_timer(&dpu_enc->vsync_event_timer,
1824                                 nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1825         }
1826
1827         DPU_ATRACE_END("encoder_kickoff");
1828 }
1829
1830 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
1831 {
1832         struct dpu_encoder_virt *dpu_enc;
1833         struct dpu_encoder_phys *phys;
1834         int i;
1835
1836         if (!drm_enc) {
1837                 DPU_ERROR("invalid encoder\n");
1838                 return;
1839         }
1840         dpu_enc = to_dpu_encoder_virt(drm_enc);
1841
1842         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1843                 phys = dpu_enc->phys_encs[i];
1844                 if (phys->ops.prepare_commit)
1845                         phys->ops.prepare_commit(phys);
1846         }
1847 }
1848
1849 #ifdef CONFIG_DEBUG_FS
1850 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
1851 {
1852         struct dpu_encoder_virt *dpu_enc = s->private;
1853         int i;
1854
1855         mutex_lock(&dpu_enc->enc_lock);
1856         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1857                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1858
1859                 seq_printf(s, "intf:%d    vsync:%8d     underrun:%8d    ",
1860                                 phys->intf_idx - INTF_0,
1861                                 atomic_read(&phys->vsync_cnt),
1862                                 atomic_read(&phys->underrun_cnt));
1863
1864                 switch (phys->intf_mode) {
1865                 case INTF_MODE_VIDEO:
1866                         seq_puts(s, "mode: video\n");
1867                         break;
1868                 case INTF_MODE_CMD:
1869                         seq_puts(s, "mode: command\n");
1870                         break;
1871                 default:
1872                         seq_puts(s, "mode: ???\n");
1873                         break;
1874                 }
1875         }
1876         mutex_unlock(&dpu_enc->enc_lock);
1877
1878         return 0;
1879 }
1880
1881 static int _dpu_encoder_debugfs_status_open(struct inode *inode,
1882                 struct file *file)
1883 {
1884         return single_open(file, _dpu_encoder_status_show, inode->i_private);
1885 }
1886
1887 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1888 {
1889         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1890         int i;
1891
1892         static const struct file_operations debugfs_status_fops = {
1893                 .open =         _dpu_encoder_debugfs_status_open,
1894                 .read =         seq_read,
1895                 .llseek =       seq_lseek,
1896                 .release =      single_release,
1897         };
1898
1899         char name[DPU_NAME_SIZE];
1900
1901         if (!drm_enc->dev) {
1902                 DPU_ERROR("invalid encoder or kms\n");
1903                 return -EINVAL;
1904         }
1905
1906         snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
1907
1908         /* create overall sub-directory for the encoder */
1909         dpu_enc->debugfs_root = debugfs_create_dir(name,
1910                         drm_enc->dev->primary->debugfs_root);
1911
1912         /* don't error check these */
1913         debugfs_create_file("status", 0600,
1914                 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
1915
1916         for (i = 0; i < dpu_enc->num_phys_encs; i++)
1917                 if (dpu_enc->phys_encs[i]->ops.late_register)
1918                         dpu_enc->phys_encs[i]->ops.late_register(
1919                                         dpu_enc->phys_encs[i],
1920                                         dpu_enc->debugfs_root);
1921
1922         return 0;
1923 }
1924 #else
1925 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1926 {
1927         return 0;
1928 }
1929 #endif
1930
1931 static int dpu_encoder_late_register(struct drm_encoder *encoder)
1932 {
1933         return _dpu_encoder_init_debugfs(encoder);
1934 }
1935
1936 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
1937 {
1938         struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
1939
1940         debugfs_remove_recursive(dpu_enc->debugfs_root);
1941 }
1942
1943 static int dpu_encoder_virt_add_phys_encs(
1944                 u32 display_caps,
1945                 struct dpu_encoder_virt *dpu_enc,
1946                 struct dpu_enc_phys_init_params *params)
1947 {
1948         struct dpu_encoder_phys *enc = NULL;
1949
1950         DPU_DEBUG_ENC(dpu_enc, "\n");
1951
1952         /*
1953          * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
1954          * in this function, check up-front.
1955          */
1956         if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
1957                         ARRAY_SIZE(dpu_enc->phys_encs)) {
1958                 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
1959                           dpu_enc->num_phys_encs);
1960                 return -EINVAL;
1961         }
1962
1963         if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
1964                 enc = dpu_encoder_phys_vid_init(params);
1965
1966                 if (IS_ERR_OR_NULL(enc)) {
1967                         DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
1968                                 PTR_ERR(enc));
1969                         return enc == NULL ? -EINVAL : PTR_ERR(enc);
1970                 }
1971
1972                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1973                 ++dpu_enc->num_phys_encs;
1974         }
1975
1976         if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
1977                 enc = dpu_encoder_phys_cmd_init(params);
1978
1979                 if (IS_ERR_OR_NULL(enc)) {
1980                         DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
1981                                 PTR_ERR(enc));
1982                         return enc == NULL ? -EINVAL : PTR_ERR(enc);
1983                 }
1984
1985                 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1986                 ++dpu_enc->num_phys_encs;
1987         }
1988
1989         if (params->split_role == ENC_ROLE_SLAVE)
1990                 dpu_enc->cur_slave = enc;
1991         else
1992                 dpu_enc->cur_master = enc;
1993
1994         return 0;
1995 }
1996
1997 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
1998         .handle_vblank_virt = dpu_encoder_vblank_callback,
1999         .handle_underrun_virt = dpu_encoder_underrun_callback,
2000         .handle_frame_done = dpu_encoder_frame_done_callback,
2001 };
2002
2003 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2004                                  struct dpu_kms *dpu_kms,
2005                                  struct msm_display_info *disp_info)
2006 {
2007         int ret = 0;
2008         int i = 0;
2009         enum dpu_intf_type intf_type;
2010         struct dpu_enc_phys_init_params phys_params;
2011
2012         if (!dpu_enc) {
2013                 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2014                 return -EINVAL;
2015         }
2016
2017         dpu_enc->cur_master = NULL;
2018
2019         memset(&phys_params, 0, sizeof(phys_params));
2020         phys_params.dpu_kms = dpu_kms;
2021         phys_params.parent = &dpu_enc->base;
2022         phys_params.parent_ops = &dpu_encoder_parent_ops;
2023         phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2024
2025         DPU_DEBUG("\n");
2026
2027         switch (disp_info->intf_type) {
2028         case DRM_MODE_ENCODER_DSI:
2029                 intf_type = INTF_DSI;
2030                 break;
2031         default:
2032                 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n");
2033                 return -EINVAL;
2034         }
2035
2036         WARN_ON(disp_info->num_of_h_tiles < 1);
2037
2038         DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2039
2040         if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
2041             (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
2042                 dpu_enc->idle_pc_supported =
2043                                 dpu_kms->catalog->caps->has_idle_pc;
2044
2045         mutex_lock(&dpu_enc->enc_lock);
2046         for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2047                 /*
2048                  * Left-most tile is at index 0, content is controller id
2049                  * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2050                  * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2051                  */
2052                 u32 controller_id = disp_info->h_tile_instance[i];
2053
2054                 if (disp_info->num_of_h_tiles > 1) {
2055                         if (i == 0)
2056                                 phys_params.split_role = ENC_ROLE_MASTER;
2057                         else
2058                                 phys_params.split_role = ENC_ROLE_SLAVE;
2059                 } else {
2060                         phys_params.split_role = ENC_ROLE_SOLO;
2061                 }
2062
2063                 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2064                                 i, controller_id, phys_params.split_role);
2065
2066                 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2067                                                                                                         intf_type,
2068                                                                                                         controller_id);
2069                 if (phys_params.intf_idx == INTF_MAX) {
2070                         DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n",
2071                                                   intf_type, controller_id);
2072                         ret = -EINVAL;
2073                 }
2074
2075                 if (!ret) {
2076                         ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
2077                                                                                                  dpu_enc,
2078                                                                                                  &phys_params);
2079                         if (ret)
2080                                 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2081                 }
2082         }
2083
2084         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2085                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2086                 atomic_set(&phys->vsync_cnt, 0);
2087                 atomic_set(&phys->underrun_cnt, 0);
2088         }
2089         mutex_unlock(&dpu_enc->enc_lock);
2090
2091         return ret;
2092 }
2093
2094 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2095 {
2096         struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2097                         frame_done_timer);
2098         struct drm_encoder *drm_enc = &dpu_enc->base;
2099         u32 event;
2100
2101         if (!drm_enc->dev) {
2102                 DPU_ERROR("invalid parameters\n");
2103                 return;
2104         }
2105
2106         if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2107                 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2108                               DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2109                 return;
2110         } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2111                 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2112                 return;
2113         }
2114
2115         DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
2116
2117         event = DPU_ENCODER_FRAME_EVENT_ERROR;
2118         trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2119         dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2120 }
2121
2122 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2123         .mode_set = dpu_encoder_virt_mode_set,
2124         .disable = dpu_encoder_virt_disable,
2125         .enable = dpu_kms_encoder_enable,
2126         .atomic_check = dpu_encoder_virt_atomic_check,
2127
2128         /* This is called by dpu_kms_encoder_enable */
2129         .commit = dpu_encoder_virt_enable,
2130 };
2131
2132 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2133                 .destroy = dpu_encoder_destroy,
2134                 .late_register = dpu_encoder_late_register,
2135                 .early_unregister = dpu_encoder_early_unregister,
2136 };
2137
2138 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2139                 struct msm_display_info *disp_info)
2140 {
2141         struct msm_drm_private *priv = dev->dev_private;
2142         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2143         struct drm_encoder *drm_enc = NULL;
2144         struct dpu_encoder_virt *dpu_enc = NULL;
2145         int ret = 0;
2146
2147         dpu_enc = to_dpu_encoder_virt(enc);
2148
2149         ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2150         if (ret)
2151                 goto fail;
2152
2153         atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2154         timer_setup(&dpu_enc->frame_done_timer,
2155                         dpu_encoder_frame_done_timeout, 0);
2156
2157         if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2158                 timer_setup(&dpu_enc->vsync_event_timer,
2159                                 dpu_encoder_vsync_event_handler,
2160                                 0);
2161
2162
2163         INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2164                         dpu_encoder_off_work);
2165         dpu_enc->idle_timeout = IDLE_TIMEOUT;
2166
2167         kthread_init_work(&dpu_enc->vsync_event_work,
2168                         dpu_encoder_vsync_event_work_handler);
2169
2170         memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2171
2172         DPU_DEBUG_ENC(dpu_enc, "created\n");
2173
2174         return ret;
2175
2176 fail:
2177         DPU_ERROR("failed to create encoder\n");
2178         if (drm_enc)
2179                 dpu_encoder_destroy(drm_enc);
2180
2181         return ret;
2182
2183
2184 }
2185
2186 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2187                 int drm_enc_mode)
2188 {
2189         struct dpu_encoder_virt *dpu_enc = NULL;
2190         int rc = 0;
2191
2192         dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2193         if (!dpu_enc)
2194                 return ERR_PTR(-ENOMEM);
2195
2196         rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2197                         drm_enc_mode, NULL);
2198         if (rc) {
2199                 devm_kfree(dev->dev, dpu_enc);
2200                 return ERR_PTR(rc);
2201         }
2202
2203         drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2204
2205         spin_lock_init(&dpu_enc->enc_spinlock);
2206         dpu_enc->enabled = false;
2207         mutex_init(&dpu_enc->enc_lock);
2208         mutex_init(&dpu_enc->rc_lock);
2209
2210         return &dpu_enc->base;
2211 }
2212
2213 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2214         enum msm_event_wait event)
2215 {
2216         int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2217         struct dpu_encoder_virt *dpu_enc = NULL;
2218         int i, ret = 0;
2219
2220         if (!drm_enc) {
2221                 DPU_ERROR("invalid encoder\n");
2222                 return -EINVAL;
2223         }
2224         dpu_enc = to_dpu_encoder_virt(drm_enc);
2225         DPU_DEBUG_ENC(dpu_enc, "\n");
2226
2227         for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2228                 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2229
2230                 switch (event) {
2231                 case MSM_ENC_COMMIT_DONE:
2232                         fn_wait = phys->ops.wait_for_commit_done;
2233                         break;
2234                 case MSM_ENC_TX_COMPLETE:
2235                         fn_wait = phys->ops.wait_for_tx_complete;
2236                         break;
2237                 case MSM_ENC_VBLANK:
2238                         fn_wait = phys->ops.wait_for_vblank;
2239                         break;
2240                 default:
2241                         DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2242                                         event);
2243                         return -EINVAL;
2244                 }
2245
2246                 if (fn_wait) {
2247                         DPU_ATRACE_BEGIN("wait_for_completion_event");
2248                         ret = fn_wait(phys);
2249                         DPU_ATRACE_END("wait_for_completion_event");
2250                         if (ret)
2251                                 return ret;
2252                 }
2253         }
2254
2255         return ret;
2256 }
2257
2258 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2259 {
2260         struct dpu_encoder_virt *dpu_enc = NULL;
2261
2262         if (!encoder) {
2263                 DPU_ERROR("invalid encoder\n");
2264                 return INTF_MODE_NONE;
2265         }
2266         dpu_enc = to_dpu_encoder_virt(encoder);
2267
2268         if (dpu_enc->cur_master)
2269                 return dpu_enc->cur_master->intf_mode;
2270
2271         if (dpu_enc->num_phys_encs)
2272                 return dpu_enc->phys_encs[0]->intf_mode;
2273
2274         return INTF_MODE_NONE;
2275 }