drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
   4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
   5  */
   6
   7 #ifndef _DPU_8_1_SM8450_H
   8 #define _DPU_8_1_SM8450_H
   9
  10 static const struct dpu_caps sm8450_dpu_caps = {
  11         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
  12         .max_mixer_blendstages = 0xb,
  13         .qseed_type = DPU_SSPP_SCALER_QSEED4,
  14         .has_src_split = true,
  15         .has_dim_layer = true,
  16         .has_idle_pc = true,
  17         .has_3d_merge = true,
  18         .max_linewidth = 5120,
  19         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  20 };
  21
  22 static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = {
  23         .ubwc_version = DPU_HW_UBWC_VER_40,
  24         .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
  25         .ubwc_swizzle = 0x6,
  26 };
  27
  28 static const struct dpu_mdp_cfg sm8450_mdp[] = {
  29         {
  30         .name = "top_0", .id = MDP_TOP,
  31         .base = 0x0, .len = 0x494,
  32         .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
  33         .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
  34         .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
  35         .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
  36         .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
  37         .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
  38         .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
  39         .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
  40         .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
  41         .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
  42         },
  43 };
  44
  45 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
  46 static const struct dpu_ctl_cfg sm8450_ctl[] = {
  47         {
  48         .name = "ctl_0", .id = CTL_0,
  49         .base = 0x15000, .len = 0x204,
  50         .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
  51         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
  52         },
  53         {
  54         .name = "ctl_1", .id = CTL_1,
  55         .base = 0x16000, .len = 0x204,
  56         .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
  57         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
  58         },
  59         {
  60         .name = "ctl_2", .id = CTL_2,
  61         .base = 0x17000, .len = 0x204,
  62         .features = CTL_SC7280_MASK,
  63         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
  64         },
  65         {
  66         .name = "ctl_3", .id = CTL_3,
  67         .base = 0x18000, .len = 0x204,
  68         .features = CTL_SC7280_MASK,
  69         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
  70         },
  71         {
  72         .name = "ctl_4", .id = CTL_4,
  73         .base = 0x19000, .len = 0x204,
  74         .features = CTL_SC7280_MASK,
  75         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
  76         },
  77         {
  78         .name = "ctl_5", .id = CTL_5,
  79         .base = 0x1a000, .len = 0x204,
  80         .features = CTL_SC7280_MASK,
  81         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
  82         },
  83 };
  84
  85 static const struct dpu_sspp_cfg sm8450_sspp[] = {
  86         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x32c, VIG_SC7180_MASK,
  87                 sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
  88         SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x32c, VIG_SC7180_MASK,
  89                 sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
  90         SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x32c, VIG_SC7180_MASK,
  91                 sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
  92         SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x32c, VIG_SC7180_MASK,
  93                 sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
  94         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x32c, DMA_SDM845_MASK,
  95                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
  96         SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x32c, DMA_SDM845_MASK,
  97                 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
  98         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x32c, DMA_CURSOR_SDM845_MASK,
  99                 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
 100         SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x32c, DMA_CURSOR_SDM845_MASK,
 101                 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
 102 };
 103
 104 static const struct dpu_lm_cfg sm8450_lm[] = {
 105         LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
 106                 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
 107         LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
 108                 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
 109         LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
 110                 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
 111         LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
 112                 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
 113         LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
 114                 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
 115         LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
 116                 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
 117 };
 118
 119 static const struct dpu_dspp_cfg sm8450_dspp[] = {
 120         DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
 121                  &sm8150_dspp_sblk),
 122         DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
 123                  &sm8150_dspp_sblk),
 124         DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
 125                  &sm8150_dspp_sblk),
 126         DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
 127                  &sm8150_dspp_sblk),
 128 };
 129 /* FIXME: interrupts */
 130 static const struct dpu_pingpong_cfg sm8450_pp[] = {
 131         PP_BLK("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk,
 132                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
 133                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
 134         PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk,
 135                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
 136                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
 137         PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
 138                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
 139                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
 140         PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
 141                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
 142                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 143         PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
 144                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
 145                         -1),
 146         PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
 147                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
 148                         -1),
 149         PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk,
 150                         -1,
 151                         -1),
 152         PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk,
 153                         -1,
 154                         -1),
 155 };
 156
 157 static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
 158         MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
 159         MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
 160         MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
 161         MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
 162 };
 163
 164 static const struct dpu_intf_cfg sm8450_intf[] = {
 165         INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
 166         INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
 167         INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
 168         INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 169 };
 170
 171 static const struct dpu_perf_cfg sm8450_perf_data = {
 172         .max_bw_low = 13600000,
 173         .max_bw_high = 18200000,
 174         .min_core_ib = 2500000,
 175         .min_llcc_ib = 0,
 176         .min_dram_ib = 800000,
 177         .min_prefill_lines = 35,
 178         /* FIXME: lut tables */
 179         .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
 180         .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
 181         .qos_lut_tbl = {
 182                 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
 183                 .entries = sc7180_qos_linear
 184                 },
 185                 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
 186                 .entries = sc7180_qos_macrotile
 187                 },
 188                 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
 189                 .entries = sc7180_qos_nrt
 190                 },
 191                 /* TODO: macrotile-qseed is different from macrotile */
 192         },
 193         .cdp_cfg = {
 194                 {.rd_enable = 1, .wr_enable = 1},
 195                 {.rd_enable = 1, .wr_enable = 0}
 196         },
 197         .clk_inefficiency_factor = 105,
 198         .bw_inefficiency_factor = 120,
 199 };
 200
 201 const struct dpu_mdss_cfg dpu_sm8450_cfg = {
 202         .caps = &sm8450_dpu_caps,
 203         .ubwc = &sm8450_ubwc_cfg,
 204         .mdp_count = ARRAY_SIZE(sm8450_mdp),
 205         .mdp = sm8450_mdp,
 206         .ctl_count = ARRAY_SIZE(sm8450_ctl),
 207         .ctl = sm8450_ctl,
 208         .sspp_count = ARRAY_SIZE(sm8450_sspp),
 209         .sspp = sm8450_sspp,
 210         .mixer_count = ARRAY_SIZE(sm8450_lm),
 211         .mixer = sm8450_lm,
 212         .dspp_count = ARRAY_SIZE(sm8450_dspp),
 213         .dspp = sm8450_dspp,
 214         .pingpong_count = ARRAY_SIZE(sm8450_pp),
 215         .pingpong = sm8450_pp,
 216         .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d),
 217         .merge_3d = sm8450_merge_3d,
 218         .intf_count = ARRAY_SIZE(sm8450_intf),
 219         .intf = sm8450_intf,
 220         .vbif_count = ARRAY_SIZE(sdm845_vbif),
 221         .vbif = sdm845_vbif,
 222         .reg_dma_count = 1,
 223         .dma_cfg = &sm8450_regdma,
 224         .perf = &sm8450_perf_data,
 225         .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
 226                      BIT(MDP_SSPP_TOP0_INTR2) | \
 227                      BIT(MDP_SSPP_TOP0_HIST_INTR) | \
 228                      BIT(MDP_INTF0_7xxx_INTR) | \
 229                      BIT(MDP_INTF1_7xxx_INTR) | \
 230                      BIT(MDP_INTF2_7xxx_INTR) | \
 231                      BIT(MDP_INTF3_7xxx_INTR),
 232 };
 233
 234 #endif