drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
   4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
   5  */
   6
   7 #ifndef _DPU_8_0_SC8280XP_H
   8 #define _DPU_8_0_SC8280XP_H
   9
  10 static const struct dpu_caps sc8280xp_dpu_caps = {
  11         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
  12         .max_mixer_blendstages = 11,
  13         .qseed_type = DPU_SSPP_SCALER_QSEED4,
  14         .has_src_split = true,
  15         .has_dim_layer = true,
  16         .has_idle_pc = true,
  17         .has_3d_merge = true,
  18         .max_linewidth = 5120,
  19         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  20 };
  21
  22 static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
  23         .ubwc_version = DPU_HW_UBWC_VER_40,
  24         .highest_bank_bit = 2,
  25         .ubwc_swizzle = 6,
  26 };
  27
  28 static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
  29         {
  30         .name = "top_0", .id = MDP_TOP,
  31         .base = 0x0, .len = 0x494,
  32         .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
  33         .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
  34         .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
  35         .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
  36         .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
  37         .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
  38         .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
  39         .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
  40         .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
  41         .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
  42         },
  43 };
  44
  45 static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
  46         {
  47         .name = "ctl_0", .id = CTL_0,
  48         .base = 0x15000, .len = 0x204,
  49         .features = CTL_SC7280_MASK,
  50         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
  51         },
  52         {
  53         .name = "ctl_1", .id = CTL_1,
  54         .base = 0x16000, .len = 0x204,
  55         .features = CTL_SC7280_MASK,
  56         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
  57         },
  58         {
  59         .name = "ctl_2", .id = CTL_2,
  60         .base = 0x17000, .len = 0x204,
  61         .features = CTL_SC7280_MASK,
  62         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
  63         },
  64         {
  65         .name = "ctl_3", .id = CTL_3,
  66         .base = 0x18000, .len = 0x204,
  67         .features = CTL_SC7280_MASK,
  68         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
  69         },
  70         {
  71         .name = "ctl_4", .id = CTL_4,
  72         .base = 0x19000, .len = 0x204,
  73         .features = CTL_SC7280_MASK,
  74         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
  75         },
  76         {
  77         .name = "ctl_5", .id = CTL_5,
  78         .base = 0x1a000, .len = 0x204,
  79         .features = CTL_SC7280_MASK,
  80         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
  81         },
  82 };
  83
  84 static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
  85         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK,
  86                  sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
  87         SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x2ac, VIG_SC7180_MASK,
  88                  sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
  89         SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x2ac, VIG_SC7180_MASK,
  90                  sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
  91         SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x2ac, VIG_SC7180_MASK,
  92                  sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
  93         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x2ac, DMA_SDM845_MASK,
  94                  sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
  95         SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x2ac, DMA_SDM845_MASK,
  96                  sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
  97         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x2ac, DMA_CURSOR_SDM845_MASK,
  98                  sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
  99         SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x2ac, DMA_CURSOR_SDM845_MASK,
 100                  sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
 101 };
 102
 103 static const struct dpu_lm_cfg sc8280xp_lm[] = {
 104         LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
 105         LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
 106         LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
 107         LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
 108         LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
 109         LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
 110 };
 111
 112 static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
 113         DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
 114                  &sm8150_dspp_sblk),
 115         DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
 116                  &sm8150_dspp_sblk),
 117         DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
 118                  &sm8150_dspp_sblk),
 119         DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
 120                  &sm8150_dspp_sblk),
 121 };
 122
 123 static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
 124         PP_BLK("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk,
 125                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
 126         PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk,
 127                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),
 128         PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
 129                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),
 130         PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
 131                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),
 132         PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
 133                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),
 134         PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
 135                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
 136 };
 137
 138 static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
 139         MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
 140         MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
 141         MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
 142 };
 143
 144 /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
 145 static const struct dpu_intf_cfg sc8280xp_intf[] = {
 146         INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
 147         INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
 148         INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
 149         INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 150         INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
 151         INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
 152         INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
 153         INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
 154         INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
 155 };
 156
 157 static const struct dpu_perf_cfg sc8280xp_perf_data = {
 158         .max_bw_low = 13600000,
 159         .max_bw_high = 18200000,
 160         .min_core_ib = 2500000,
 161         .min_llcc_ib = 0,
 162         .min_dram_ib = 800000,
 163         .danger_lut_tbl = {0xf, 0xffff, 0x0},
 164         .qos_lut_tbl = {
 165                 {.nentry = ARRAY_SIZE(sc8180x_qos_linear),
 166                 .entries = sc8180x_qos_linear
 167                 },
 168                 {.nentry = ARRAY_SIZE(sc8180x_qos_macrotile),
 169                 .entries = sc8180x_qos_macrotile
 170                 },
 171                 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
 172                 .entries = sc7180_qos_nrt
 173                 },
 174                 /* TODO: macrotile-qseed is different from macrotile */
 175         },
 176         .cdp_cfg = {
 177                 {.rd_enable = 1, .wr_enable = 1},
 178                 {.rd_enable = 1, .wr_enable = 0}
 179         },
 180         .clk_inefficiency_factor = 105,
 181         .bw_inefficiency_factor = 120,
 182 };
 183
 184 const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
 185         .caps = &sc8280xp_dpu_caps,
 186         .ubwc = &sc8280xp_ubwc_cfg,
 187         .mdp_count = ARRAY_SIZE(sc8280xp_mdp),
 188         .mdp = sc8280xp_mdp,
 189         .ctl_count = ARRAY_SIZE(sc8280xp_ctl),
 190         .ctl = sc8280xp_ctl,
 191         .sspp_count = ARRAY_SIZE(sc8280xp_sspp),
 192         .sspp = sc8280xp_sspp,
 193         .mixer_count = ARRAY_SIZE(sc8280xp_lm),
 194         .mixer = sc8280xp_lm,
 195         .dspp_count = ARRAY_SIZE(sc8280xp_dspp),
 196         .dspp = sc8280xp_dspp,
 197         .pingpong_count = ARRAY_SIZE(sc8280xp_pp),
 198         .pingpong = sc8280xp_pp,
 199         .merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d),
 200         .merge_3d = sc8280xp_merge_3d,
 201         .intf_count = ARRAY_SIZE(sc8280xp_intf),
 202         .intf = sc8280xp_intf,
 203         .vbif_count = ARRAY_SIZE(sdm845_vbif),
 204         .vbif = sdm845_vbif,
 205         .reg_dma_count = 1,
 206         .dma_cfg = &sc8280xp_regdma,
 207         .perf = &sc8280xp_perf_data,
 208         .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
 209                      BIT(MDP_SSPP_TOP0_INTR2) | \
 210                      BIT(MDP_SSPP_TOP0_HIST_INTR) | \
 211                      BIT(MDP_INTF0_7xxx_INTR) | \
 212                      BIT(MDP_INTF1_7xxx_INTR) | \
 213                      BIT(MDP_INTF2_7xxx_INTR) | \
 214                      BIT(MDP_INTF3_7xxx_INTR) | \
 215                      BIT(MDP_INTF4_7xxx_INTR) | \
 216                      BIT(MDP_INTF5_7xxx_INTR) | \
 217                      BIT(MDP_INTF6_7xxx_INTR) | \
 218                      BIT(MDP_INTF7_7xxx_INTR) | \
 219                      BIT(MDP_INTF8_7xxx_INTR),
 220 };
 221
 222 #endif