drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
   4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
   5  */
   6
   7 #ifndef _DPU_5_1_SC8180X_H
   8 #define _DPU_5_1_SC8180X_H
   9
  10 static const struct dpu_caps sc8180x_dpu_caps = {
  11         .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
  12         .max_mixer_blendstages = 0xb,
  13         .qseed_type = DPU_SSPP_SCALER_QSEED3,
  14         .has_src_split = true,
  15         .has_dim_layer = true,
  16         .has_idle_pc = true,
  17         .has_3d_merge = true,
  18         .max_linewidth = 4096,
  19         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
  20         .max_hdeci_exp = MAX_HORZ_DECIMATION,
  21         .max_vdeci_exp = MAX_VERT_DECIMATION,
  22 };
  23
  24 static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
  25         .ubwc_version = DPU_HW_UBWC_VER_30,
  26         .highest_bank_bit = 0x3,
  27 };
  28
  29 static const struct dpu_mdp_cfg sc8180x_mdp[] = {
  30         {
  31         .name = "top_0", .id = MDP_TOP,
  32         .base = 0x0, .len = 0x45c,
  33         .features = BIT(DPU_MDP_AUDIO_SELECT),
  34         .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
  35         .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
  36         .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
  37         .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
  38         .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
  39         .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
  40         .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
  41         .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
  42         },
  43 };
  44
  45 static const struct dpu_ctl_cfg sc8180x_ctl[] = {
  46         {
  47         .name = "ctl_0", .id = CTL_0,
  48         .base = 0x1000, .len = 0x1e0,
  49         .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
  50         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
  51         },
  52         {
  53         .name = "ctl_1", .id = CTL_1,
  54         .base = 0x1200, .len = 0x1e0,
  55         .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
  56         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
  57         },
  58         {
  59         .name = "ctl_2", .id = CTL_2,
  60         .base = 0x1400, .len = 0x1e0,
  61         .features = BIT(DPU_CTL_ACTIVE_CFG),
  62         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
  63         },
  64         {
  65         .name = "ctl_3", .id = CTL_3,
  66         .base = 0x1600, .len = 0x1e0,
  67         .features = BIT(DPU_CTL_ACTIVE_CFG),
  68         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
  69         },
  70         {
  71         .name = "ctl_4", .id = CTL_4,
  72         .base = 0x1800, .len = 0x1e0,
  73         .features = BIT(DPU_CTL_ACTIVE_CFG),
  74         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
  75         },
  76         {
  77         .name = "ctl_5", .id = CTL_5,
  78         .base = 0x1a00, .len = 0x1e0,
  79         .features = BIT(DPU_CTL_ACTIVE_CFG),
  80         .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
  81         },
  82 };
  83
  84 static const struct dpu_sspp_cfg sc8180x_sspp[] = {
  85         SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
  86                 sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
  87         SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
  88                 sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
  89         SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
  90                 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
  91         SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
  92                 sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
  93         SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
  94                 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
  95         SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
  96                 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
  97         SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
  98                 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
  99         SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
 100                 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
 101 };
 102
 103 static const struct dpu_lm_cfg sc8180x_lm[] = {
 104         LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
 105                 &sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
 106         LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
 107                 &sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
 108         LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
 109                 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
 110         LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
 111                 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
 112         LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
 113                 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
 114         LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
 115                 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
 116 };
 117
 118 static const struct dpu_pingpong_cfg sc8180x_pp[] = {
 119         PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk,
 120                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
 121                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
 122         PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk,
 123                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
 124                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
 125         PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
 126                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
 127                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
 128         PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
 129                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
 130                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 131         PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
 132                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
 133                         -1),
 134         PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
 135                         DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
 136                         -1),
 137 };
 138
 139 static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
 140         MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
 141         MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
 142         MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
 143 };
 144
 145 static const struct dpu_intf_cfg sc8180x_intf[] = {
 146         INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
 147         INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
 148         INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
 149         /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
 150         INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 151         INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
 152         INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
 153 };
 154
 155 static const struct dpu_perf_cfg sc8180x_perf_data = {
 156         .max_bw_low = 9600000,
 157         .max_bw_high = 9600000,
 158         .min_core_ib = 2400000,
 159         .min_llcc_ib = 800000,
 160         .min_dram_ib = 800000,
 161         .danger_lut_tbl = {0xf, 0xffff, 0x0},
 162         .qos_lut_tbl = {
 163                 {.nentry = ARRAY_SIZE(sc7180_qos_linear),
 164                 .entries = sc7180_qos_linear
 165                 },
 166                 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
 167                 .entries = sc7180_qos_macrotile
 168                 },
 169                 {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
 170                 .entries = sc7180_qos_nrt
 171                 },
 172                 /* TODO: macrotile-qseed is different from macrotile */
 173         },
 174         .cdp_cfg = {
 175                 {.rd_enable = 1, .wr_enable = 1},
 176                 {.rd_enable = 1, .wr_enable = 0}
 177         },
 178         .clk_inefficiency_factor = 105,
 179         .bw_inefficiency_factor = 120,
 180 };
 181
 182 const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
 183         .caps = &sc8180x_dpu_caps,
 184         .ubwc = &sc8180x_ubwc_cfg,
 185         .mdp_count = ARRAY_SIZE(sc8180x_mdp),
 186         .mdp = sc8180x_mdp,
 187         .ctl_count = ARRAY_SIZE(sc8180x_ctl),
 188         .ctl = sc8180x_ctl,
 189         .sspp_count = ARRAY_SIZE(sc8180x_sspp),
 190         .sspp = sc8180x_sspp,
 191         .mixer_count = ARRAY_SIZE(sc8180x_lm),
 192         .mixer = sc8180x_lm,
 193         .pingpong_count = ARRAY_SIZE(sc8180x_pp),
 194         .pingpong = sc8180x_pp,
 195         .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d),
 196         .merge_3d = sc8180x_merge_3d,
 197         .intf_count = ARRAY_SIZE(sc8180x_intf),
 198         .intf = sc8180x_intf,
 199         .vbif_count = ARRAY_SIZE(sdm845_vbif),
 200         .vbif = sdm845_vbif,
 201         .reg_dma_count = 1,
 202         .dma_cfg = &sm8150_regdma,
 203         .perf = &sc8180x_perf_data,
 204         .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
 205                      BIT(MDP_SSPP_TOP0_INTR2) | \
 206                      BIT(MDP_SSPP_TOP0_HIST_INTR) | \
 207                      BIT(MDP_INTF0_INTR) | \
 208                      BIT(MDP_INTF1_INTR) | \
 209                      BIT(MDP_INTF2_INTR) | \
 210                      BIT(MDP_INTF3_INTR) | \
 211                      BIT(MDP_INTF4_INTR) | \
 212                      BIT(MDP_INTF5_INTR) | \
 213                      BIT(MDP_AD4_0_INTR) | \
 214                      BIT(MDP_AD4_1_INTR),
 215 };
 216
 217 #endif