1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
20 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
22 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
25 * adreno_regs: List of registers that are used in across all
26 * 3D devices. Each device type has different offset value for the same
27 * register, so an array of register offsets are declared for every device
28 * and are indexed by the enumeration values defined in this enum
31 REG_ADRENO_CP_RB_BASE,
32 REG_ADRENO_CP_RB_BASE_HI,
33 REG_ADRENO_CP_RB_RPTR_ADDR,
34 REG_ADRENO_CP_RB_RPTR_ADDR_HI,
35 REG_ADRENO_CP_RB_RPTR,
36 REG_ADRENO_CP_RB_WPTR,
37 REG_ADRENO_CP_RB_CNTL,
38 REG_ADRENO_REGISTER_MAX,
43 ADRENO_FW_SQE = 0, /* a6xx */
45 ADRENO_FW_GMU = 1, /* a6xx */
51 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
52 ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
62 #define ADRENO_REV(core, major, minor, patchid) \
63 ((struct adreno_rev){ core, major, minor, patchid })
65 struct adreno_gpu_funcs {
66 struct msm_gpu_funcs base;
67 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
71 struct adreno_rev rev;
74 const char *fw[ADRENO_FW_MAX];
76 enum adreno_quirks quirks;
77 struct msm_gpu *(*init)(struct drm_device *dev);
82 const struct adreno_info *adreno_info(struct adreno_rev rev);
86 struct adreno_rev rev;
87 const struct adreno_info *info;
88 uint32_t gmem; /* actual gmem size */
89 uint32_t revn; /* numeric revision name */
90 const struct adreno_gpu_funcs *funcs;
92 /* interesting register offsets to dump: */
93 const unsigned int *registers;
96 * Are we loading fw from legacy path? Prior to addition
97 * of gpu firmware to linux-firmware, the fw files were
98 * placed in toplevel firmware directory, following qcom's
99 * android kernel. But linux-firmware preferred they be
100 * placed in a 'qcom' subdirectory.
102 * For backwards compatibility, we try first to load from
103 * the new path, using request_firmware_direct() to avoid
104 * any potential timeout waiting for usermode helper, then
105 * fall back to the old path (with direct load). And
106 * finally fall back to request_firmware() with the new
107 * path to allow the usermode helper.
110 FW_LOCATION_UNKNOWN = 0,
111 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */
112 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */
117 const struct firmware *fw[ADRENO_FW_MAX];
120 * Register offsets are different between some GPUs.
121 * GPU specific offsets will be exported by GPU specific
122 * code (a3xx_gpu.c) and stored in this common location.
124 const unsigned int *reg_offsets;
126 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
128 /* platform config data (ie. from DT, or pdata) */
129 struct adreno_platform_config {
130 struct adreno_rev rev;
133 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
135 #define spin_until(X) ({ \
136 int __ret = -ETIMEDOUT; \
137 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
143 } while (time_before(jiffies, __t)); \
147 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
149 return (gpu->revn < 300);
152 static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
154 return (gpu->revn < 210);
157 static inline bool adreno_is_a225(struct adreno_gpu *gpu)
159 return gpu->revn == 225;
162 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
164 return (gpu->revn >= 300) && (gpu->revn < 400);
167 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
169 return gpu->revn == 305;
172 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
174 /* yes, 307, because a305c is 306 */
175 return gpu->revn == 307;
178 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
180 return gpu->revn == 320;
183 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
185 return gpu->revn == 330;
188 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
190 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
193 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
195 return (gpu->revn >= 400) && (gpu->revn < 500);
198 static inline int adreno_is_a420(struct adreno_gpu *gpu)
200 return gpu->revn == 420;
203 static inline int adreno_is_a430(struct adreno_gpu *gpu)
205 return gpu->revn == 430;
208 static inline int adreno_is_a530(struct adreno_gpu *gpu)
210 return gpu->revn == 530;
213 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
214 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
216 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
217 const struct firmware *fw, u64 *iova);
218 int adreno_hw_init(struct msm_gpu *gpu);
219 void adreno_recover(struct msm_gpu *gpu);
220 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
221 struct msm_file_private *ctx);
222 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
223 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
224 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
225 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
226 struct drm_printer *p);
228 void adreno_dump_info(struct msm_gpu *gpu);
229 void adreno_dump(struct msm_gpu *gpu);
230 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
231 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
233 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
234 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
236 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
237 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
239 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
241 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
242 int adreno_gpu_state_put(struct msm_gpu_state *state);
245 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
248 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
250 /* ringbuffer helpers (the parts that are adreno specific) */
253 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
255 adreno_wait_ring(ring, cnt+1);
256 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
261 OUT_PKT2(struct msm_ringbuffer *ring)
263 adreno_wait_ring(ring, 1);
264 OUT_RING(ring, CP_TYPE2_PKT);
268 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
270 adreno_wait_ring(ring, cnt+1);
271 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
274 static inline u32 PM4_PARITY(u32 val)
276 return (0x9669 >> (0xF & (val ^
277 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
278 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
282 /* Maximum number of values that can be executed for one opcode */
283 #define TYPE4_MAX_PAYLOAD 127
285 #define PKT4(_reg, _cnt) \
286 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
287 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
290 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
292 adreno_wait_ring(ring, cnt + 1);
293 OUT_RING(ring, PKT4(regindx, cnt));
297 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
299 adreno_wait_ring(ring, cnt + 1);
300 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
301 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
305 * adreno_reg_check() - Checks the validity of a register enum
306 * @gpu: Pointer to struct adreno_gpu
307 * @offset_name: The register enum that is checked
309 static inline bool adreno_reg_check(struct adreno_gpu *gpu,
310 enum adreno_regs offset_name)
312 if (offset_name >= REG_ADRENO_REGISTER_MAX ||
313 !gpu->reg_offsets[offset_name]) {
318 * REG_SKIP is a special value that tell us that the register in
319 * question isn't implemented on target but don't trigger a BUG(). This
320 * is used to cleanly implement adreno_gpu_write64() and
321 * adreno_gpu_read64() in a generic fashion
323 if (gpu->reg_offsets[offset_name] == REG_SKIP)
329 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
330 enum adreno_regs offset_name)
332 u32 reg = gpu->reg_offsets[offset_name];
334 if(adreno_reg_check(gpu,offset_name))
335 val = gpu_read(&gpu->base, reg - 1);
339 static inline void adreno_gpu_write(struct adreno_gpu *gpu,
340 enum adreno_regs offset_name, u32 data)
342 u32 reg = gpu->reg_offsets[offset_name];
343 if(adreno_reg_check(gpu, offset_name))
344 gpu_write(&gpu->base, reg - 1, data);
347 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
348 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
349 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
350 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
351 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
353 static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
354 enum adreno_regs lo, enum adreno_regs hi, u64 data)
356 adreno_gpu_write(gpu, lo, lower_32_bits(data));
357 adreno_gpu_write(gpu, hi, upper_32_bits(data));
360 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
362 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
366 * Given a register and a count, return a value to program into
367 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
368 * registers starting at _reg.
370 * The register base needs to be a multiple of the length. If it is not, the
371 * hardware will quietly mask off the bits for you and shift the size. For
372 * example, if you intend the protection to start at 0x07 for a length of 4
373 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
374 * expose registers you intended to protect!
376 #define ADRENO_PROTECT_RW(_reg, _len) \
377 ((1 << 30) | (1 << 29) | \
378 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
381 * Same as above, but allow reads over the range. For areas of mixed use (such
382 * as performance counters) this allows us to protect a much larger range with a
385 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
387 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
390 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
391 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
394 #endif /* __ADRENO_GPU_H__ */