drivers/gpu/drm/msm/adreno/adreno_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   7  */
   8
   9 #include <linux/ascii85.h>
  10 #include <linux/interconnect.h>
  11 #include <linux/qcom_scm.h>
  12 #include <linux/kernel.h>
  13 #include <linux/of_address.h>
  14 #include <linux/pm_opp.h>
  15 #include <linux/slab.h>
  16 #include <linux/soc/qcom/mdt_loader.h>
  17 #include <soc/qcom/ocmem.h>
  18 #include "adreno_gpu.h"
  19 #include "msm_gem.h"
  20 #include "msm_mmu.h"
  21
  22 static bool zap_available = true;
  23
  24 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
  25                 u32 pasid)
  26 {
  27         struct device *dev = &gpu->pdev->dev;
  28         const struct firmware *fw;
  29         const char *signed_fwname = NULL;
  30         struct device_node *np, *mem_np;
  31         struct resource r;
  32         phys_addr_t mem_phys;
  33         ssize_t mem_size;
  34         void *mem_region = NULL;
  35         int ret;
  36
  37         if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
  38                 zap_available = false;
  39                 return -EINVAL;
  40         }
  41
  42         np = of_get_child_by_name(dev->of_node, "zap-shader");
  43         if (!np) {
  44                 zap_available = false;
  45                 return -ENODEV;
  46         }
  47
  48         mem_np = of_parse_phandle(np, "memory-region", 0);
  49         of_node_put(np);
  50         if (!mem_np) {
  51                 zap_available = false;
  52                 return -EINVAL;
  53         }
  54
  55         ret = of_address_to_resource(mem_np, 0, &r);
  56         of_node_put(mem_np);
  57         if (ret)
  58                 return ret;
  59
  60         mem_phys = r.start;
  61
  62         /*
  63          * Check for a firmware-name property.  This is the new scheme
  64          * to handle firmware that may be signed with device specific
  65          * keys, allowing us to have a different zap fw path for different
  66          * devices.
  67          *
  68          * If the firmware-name property is found, we bypass the
  69          * adreno_request_fw() mechanism, because we don't need to handle
  70          * the /lib/firmware/qcom/... vs /lib/firmware/... case.
  71          *
  72          * If the firmware-name property is not found, for backwards
  73          * compatibility we fall back to the fwname from the gpulist
  74          * table.
  75          */
  76         of_property_read_string_index(np, "firmware-name", 0, &signed_fwname);
  77         if (signed_fwname) {
  78                 fwname = signed_fwname;
  79                 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);
  80                 if (ret)
  81                         fw = ERR_PTR(ret);
  82         } else if (fwname) {
  83                 /* Request the MDT file from the default location: */
  84                 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
  85         } else {
  86                 /*
  87                  * For new targets, we require the firmware-name property,
  88                  * if a zap-shader is required, rather than falling back
  89                  * to a firmware name specified in gpulist.
  90                  *
  91                  * Because the firmware is signed with a (potentially)
  92                  * device specific key, having the name come from gpulist
  93                  * was a bad idea, and is only provided for backwards
  94                  * compatibility for older targets.
  95                  */
  96                 return -ENODEV;
  97         }
  98
  99         if (IS_ERR(fw)) {
 100                 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
 101                 return PTR_ERR(fw);
 102         }
 103
 104         /* Figure out how much memory we need */
 105         mem_size = qcom_mdt_get_size(fw);
 106         if (mem_size < 0) {
 107                 ret = mem_size;
 108                 goto out;
 109         }
 110
 111         if (mem_size > resource_size(&r)) {
 112                 DRM_DEV_ERROR(dev,
 113                         "memory region is too small to load the MDT\n");
 114                 ret = -E2BIG;
 115                 goto out;
 116         }
 117
 118         /* Allocate memory for the firmware image */
 119         mem_region = memremap(mem_phys, mem_size,  MEMREMAP_WC);
 120         if (!mem_region) {
 121                 ret = -ENOMEM;
 122                 goto out;
 123         }
 124
 125         /*
 126          * Load the rest of the MDT
 127          *
 128          * Note that we could be dealing with two different paths, since
 129          * with upstream linux-firmware it would be in a qcom/ subdir..
 130          * adreno_request_fw() handles this, but qcom_mdt_load() does
 131          * not.  But since we've already gotten through adreno_request_fw()
 132          * we know which of the two cases it is:
 133          */
 134         if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {
 135                 ret = qcom_mdt_load(dev, fw, fwname, pasid,
 136                                 mem_region, mem_phys, mem_size, NULL);
 137         } else {
 138                 char *newname;
 139
 140                 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
 141
 142                 ret = qcom_mdt_load(dev, fw, newname, pasid,
 143                                 mem_region, mem_phys, mem_size, NULL);
 144                 kfree(newname);
 145         }
 146         if (ret)
 147                 goto out;
 148
 149         /* Send the image to the secure world */
 150         ret = qcom_scm_pas_auth_and_reset(pasid);
 151
 152         /*
 153          * If the scm call returns -EOPNOTSUPP we assume that this target
 154          * doesn't need/support the zap shader so quietly fail
 155          */
 156         if (ret == -EOPNOTSUPP)
 157                 zap_available = false;
 158         else if (ret)
 159                 DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
 160
 161 out:
 162         if (mem_region)
 163                 memunmap(mem_region);
 164
 165         release_firmware(fw);
 166
 167         return ret;
 168 }
 169
 170 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
 171 {
 172         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 173         struct platform_device *pdev = gpu->pdev;
 174
 175         /* Short cut if we determine the zap shader isn't available/needed */
 176         if (!zap_available)
 177                 return -ENODEV;
 178
 179         /* We need SCM to be able to load the firmware */
 180         if (!qcom_scm_is_available()) {
 181                 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
 182                 return -EPROBE_DEFER;
 183         }
 184
 185         return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
 186 }
 187
 188 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
 189 {
 190         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 191
 192         switch (param) {
 193         case MSM_PARAM_GPU_ID:
 194                 *value = adreno_gpu->info->revn;
 195                 return 0;
 196         case MSM_PARAM_GMEM_SIZE:
 197                 *value = adreno_gpu->gmem;
 198                 return 0;
 199         case MSM_PARAM_GMEM_BASE:
 200                 *value = 0x100000;
 201                 return 0;
 202         case MSM_PARAM_CHIP_ID:
 203                 *value = adreno_gpu->rev.patchid |
 204                                 (adreno_gpu->rev.minor << 8) |
 205                                 (adreno_gpu->rev.major << 16) |
 206                                 (adreno_gpu->rev.core << 24);
 207                 return 0;
 208         case MSM_PARAM_MAX_FREQ:
 209                 *value = adreno_gpu->base.fast_rate;
 210                 return 0;
 211         case MSM_PARAM_TIMESTAMP:
 212                 if (adreno_gpu->funcs->get_timestamp) {
 213                         int ret;
 214
 215                         pm_runtime_get_sync(&gpu->pdev->dev);
 216                         ret = adreno_gpu->funcs->get_timestamp(gpu, value);
 217                         pm_runtime_put_autosuspend(&gpu->pdev->dev);
 218
 219                         return ret;
 220                 }
 221                 return -EINVAL;
 222         case MSM_PARAM_NR_RINGS:
 223                 *value = gpu->nr_rings;
 224                 return 0;
 225         case MSM_PARAM_PP_PGTABLE:
 226                 *value = 0;
 227                 return 0;
 228         case MSM_PARAM_FAULTS:
 229                 *value = gpu->global_faults;
 230                 return 0;
 231         default:
 232                 DBG("%s: invalid param: %u", gpu->name, param);
 233                 return -EINVAL;
 234         }
 235 }
 236
 237 const struct firmware *
 238 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
 239 {
 240         struct drm_device *drm = adreno_gpu->base.dev;
 241         const struct firmware *fw = NULL;
 242         char *newname;
 243         int ret;
 244
 245         newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
 246         if (!newname)
 247                 return ERR_PTR(-ENOMEM);
 248
 249         /*
 250          * Try first to load from qcom/$fwfile using a direct load (to avoid
 251          * a potential timeout waiting for usermode helper)
 252          */
 253         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 254             (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
 255
 256                 ret = request_firmware_direct(&fw, newname, drm->dev);
 257                 if (!ret) {
 258                         DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
 259                                 newname);
 260                         adreno_gpu->fwloc = FW_LOCATION_NEW;
 261                         goto out;
 262                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 263                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 264                                 newname, ret);
 265                         fw = ERR_PTR(ret);
 266                         goto out;
 267                 }
 268         }
 269
 270         /*
 271          * Then try the legacy location without qcom/ prefix
 272          */
 273         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 274             (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
 275
 276                 ret = request_firmware_direct(&fw, fwname, drm->dev);
 277                 if (!ret) {
 278                         DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
 279                                 newname);
 280                         adreno_gpu->fwloc = FW_LOCATION_LEGACY;
 281                         goto out;
 282                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 283                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 284                                 fwname, ret);
 285                         fw = ERR_PTR(ret);
 286                         goto out;
 287                 }
 288         }
 289
 290         /*
 291          * Finally fall back to request_firmware() for cases where the
 292          * usermode helper is needed (I think mainly android)
 293          */
 294         if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 295             (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
 296
 297                 ret = request_firmware(&fw, newname, drm->dev);
 298                 if (!ret) {
 299                         DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
 300                                 newname);
 301                         adreno_gpu->fwloc = FW_LOCATION_HELPER;
 302                         goto out;
 303                 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 304                         DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 305                                 newname, ret);
 306                         fw = ERR_PTR(ret);
 307                         goto out;
 308                 }
 309         }
 310
 311         DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
 312         fw = ERR_PTR(-ENOENT);
 313 out:
 314         kfree(newname);
 315         return fw;
 316 }
 317
 318 int adreno_load_fw(struct adreno_gpu *adreno_gpu)
 319 {
 320         int i;
 321
 322         for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
 323                 const struct firmware *fw;
 324
 325                 if (!adreno_gpu->info->fw[i])
 326                         continue;
 327
 328                 /* Skip if the firmware has already been loaded */
 329                 if (adreno_gpu->fw[i])
 330                         continue;
 331
 332                 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
 333                 if (IS_ERR(fw))
 334                         return PTR_ERR(fw);
 335
 336                 adreno_gpu->fw[i] = fw;
 337         }
 338
 339         return 0;
 340 }
 341
 342 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
 343                 const struct firmware *fw, u64 *iova)
 344 {
 345         struct drm_gem_object *bo;
 346         void *ptr;
 347
 348         ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,
 349                 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
 350
 351         if (IS_ERR(ptr))
 352                 return ERR_CAST(ptr);
 353
 354         memcpy(ptr, &fw->data[4], fw->size - 4);
 355
 356         msm_gem_put_vaddr(bo);
 357
 358         return bo;
 359 }
 360
 361 int adreno_hw_init(struct msm_gpu *gpu)
 362 {
 363         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 364         int ret, i;
 365
 366         DBG("%s", gpu->name);
 367
 368         ret = adreno_load_fw(adreno_gpu);
 369         if (ret)
 370                 return ret;
 371
 372         for (i = 0; i < gpu->nr_rings; i++) {
 373                 struct msm_ringbuffer *ring = gpu->rb[i];
 374
 375                 if (!ring)
 376                         continue;
 377
 378                 ring->cur = ring->start;
 379                 ring->next = ring->start;
 380
 381                 /* reset completed fence seqno: */
 382                 ring->memptrs->fence = ring->seqno;
 383                 ring->memptrs->rptr = 0;
 384         }
 385
 386         /*
 387          * Setup REG_CP_RB_CNTL.  The same value is used across targets (with
 388          * the excpetion of A430 that disables the RPTR shadow) - the cacluation
 389          * for the ringbuffer size and block size is moved to msm_gpu.h for the
 390          * pre-processor to deal with and the A430 variant is ORed in here
 391          */
 392         adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
 393                 MSM_GPU_RB_CNTL_DEFAULT |
 394                 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
 395
 396         /* Setup ringbuffer address - use ringbuffer[0] for GPU init */
 397         adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
 398                 REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);
 399
 400         if (!adreno_is_a430(adreno_gpu)) {
 401                 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
 402                         REG_ADRENO_CP_RB_RPTR_ADDR_HI,
 403                         rbmemptr(gpu->rb[0], rptr));
 404         }
 405
 406         return 0;
 407 }
 408
 409 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
 410 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
 411                 struct msm_ringbuffer *ring)
 412 {
 413         if (adreno_is_a430(adreno_gpu))
 414                 return ring->memptrs->rptr = adreno_gpu_read(
 415                         adreno_gpu, REG_ADRENO_CP_RB_RPTR);
 416         else
 417                 return ring->memptrs->rptr;
 418 }
 419
 420 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
 421 {
 422         return gpu->rb[0];
 423 }
 424
 425 void adreno_recover(struct msm_gpu *gpu)
 426 {
 427         struct drm_device *dev = gpu->dev;
 428         int ret;
 429
 430         // XXX pm-runtime??  we *need* the device to be off after this
 431         // so maybe continuing to call ->pm_suspend/resume() is better?
 432
 433         gpu->funcs->pm_suspend(gpu);
 434         gpu->funcs->pm_resume(gpu);
 435
 436         ret = msm_gpu_hw_init(gpu);
 437         if (ret) {
 438                 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
 439                 /* hmm, oh well? */
 440         }
 441 }
 442
 443 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 444                 struct msm_file_private *ctx)
 445 {
 446         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 447         struct msm_drm_private *priv = gpu->dev->dev_private;
 448         struct msm_ringbuffer *ring = submit->ring;
 449         unsigned i;
 450
 451         for (i = 0; i < submit->nr_cmds; i++) {
 452                 switch (submit->cmd[i].type) {
 453                 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
 454                         /* ignore IB-targets */
 455                         break;
 456                 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
 457                         /* ignore if there has not been a ctx switch: */
 458                         if (priv->lastctx == ctx)
 459                                 break;
 460                         /* fall-thru */
 461                 case MSM_SUBMIT_CMD_BUF:
 462                         OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
 463                                 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
 464                         OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
 465                         OUT_RING(ring, submit->cmd[i].size);
 466                         OUT_PKT2(ring);
 467                         break;
 468                 }
 469         }
 470
 471         OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
 472         OUT_RING(ring, submit->seqno);
 473
 474         if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
 475                 /* Flush HLSQ lazy updates to make sure there is nothing
 476                  * pending for indirect loads after the timestamp has
 477                  * passed:
 478                  */
 479                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 480                 OUT_RING(ring, HLSQ_FLUSH);
 481         }
 482
 483         /* wait for idle before cache flush/interrupt */
 484         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
 485         OUT_RING(ring, 0x00000000);
 486
 487         if (!adreno_is_a2xx(adreno_gpu)) {
 488                 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
 489                 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
 490                 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
 491                 OUT_RING(ring, rbmemptr(ring, fence));
 492                 OUT_RING(ring, submit->seqno);
 493         } else {
 494                 /* BIT(31) means something else on a2xx */
 495                 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
 496                 OUT_RING(ring, CACHE_FLUSH_TS);
 497                 OUT_RING(ring, rbmemptr(ring, fence));
 498                 OUT_RING(ring, submit->seqno);
 499                 OUT_PKT3(ring, CP_INTERRUPT, 1);
 500                 OUT_RING(ring, 0x80000000);
 501         }
 502
 503 #if 0
 504         if (adreno_is_a3xx(adreno_gpu)) {
 505                 /* Dummy set-constant to trigger context rollover */
 506                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 507                 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
 508                 OUT_RING(ring, 0x00000000);
 509         }
 510 #endif
 511
 512         gpu->funcs->flush(gpu, ring);
 513 }
 514
 515 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 516 {
 517         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 518         uint32_t wptr;
 519
 520         /* Copy the shadow to the actual register */
 521         ring->cur = ring->next;
 522
 523         /*
 524          * Mask wptr value that we calculate to fit in the HW range. This is
 525          * to account for the possibility that the last command fit exactly into
 526          * the ringbuffer and rb->next hasn't wrapped to zero yet
 527          */
 528         wptr = get_wptr(ring);
 529
 530         /* ensure writes to ringbuffer have hit system memory: */
 531         mb();
 532
 533         adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
 534 }
 535
 536 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 537 {
 538         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 539         uint32_t wptr = get_wptr(ring);
 540
 541         /* wait for CP to drain ringbuffer: */
 542         if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
 543                 return true;
 544
 545         /* TODO maybe we need to reset GPU here to recover from hang? */
 546         DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
 547                 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
 548
 549         return false;
 550 }
 551
 552 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
 553 {
 554         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 555         int i, count = 0;
 556
 557         kref_init(&state->ref);
 558
 559         ktime_get_real_ts64(&state->time);
 560
 561         for (i = 0; i < gpu->nr_rings; i++) {
 562                 int size = 0, j;
 563
 564                 state->ring[i].fence = gpu->rb[i]->memptrs->fence;
 565                 state->ring[i].iova = gpu->rb[i]->iova;
 566                 state->ring[i].seqno = gpu->rb[i]->seqno;
 567                 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
 568                 state->ring[i].wptr = get_wptr(gpu->rb[i]);
 569
 570                 /* Copy at least 'wptr' dwords of the data */
 571                 size = state->ring[i].wptr;
 572
 573                 /* After wptr find the last non zero dword to save space */
 574                 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
 575                         if (gpu->rb[i]->start[j])
 576                                 size = j + 1;
 577
 578                 if (size) {
 579                         state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL);
 580                         if (state->ring[i].data) {
 581                                 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
 582                                 state->ring[i].data_size = size << 2;
 583                         }
 584                 }
 585         }
 586
 587         /* Some targets prefer to collect their own registers */
 588         if (!adreno_gpu->registers)
 589                 return 0;
 590
 591         /* Count the number of registers */
 592         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
 593                 count += adreno_gpu->registers[i + 1] -
 594                         adreno_gpu->registers[i] + 1;
 595
 596         state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
 597         if (state->registers) {
 598                 int pos = 0;
 599
 600                 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 601                         u32 start = adreno_gpu->registers[i];
 602                         u32 end   = adreno_gpu->registers[i + 1];
 603                         u32 addr;
 604
 605                         for (addr = start; addr <= end; addr++) {
 606                                 state->registers[pos++] = addr;
 607                                 state->registers[pos++] = gpu_read(gpu, addr);
 608                         }
 609                 }
 610
 611                 state->nr_registers = count;
 612         }
 613
 614         return 0;
 615 }
 616
 617 void adreno_gpu_state_destroy(struct msm_gpu_state *state)
 618 {
 619         int i;
 620
 621         for (i = 0; i < ARRAY_SIZE(state->ring); i++)
 622                 kvfree(state->ring[i].data);
 623
 624         for (i = 0; state->bos && i < state->nr_bos; i++)
 625                 kvfree(state->bos[i].data);
 626
 627         kfree(state->bos);
 628         kfree(state->comm);
 629         kfree(state->cmd);
 630         kfree(state->registers);
 631 }
 632
 633 static void adreno_gpu_state_kref_destroy(struct kref *kref)
 634 {
 635         struct msm_gpu_state *state = container_of(kref,
 636                 struct msm_gpu_state, ref);
 637
 638         adreno_gpu_state_destroy(state);
 639         kfree(state);
 640 }
 641
 642 int adreno_gpu_state_put(struct msm_gpu_state *state)
 643 {
 644         if (IS_ERR_OR_NULL(state))
 645                 return 1;
 646
 647         return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
 648 }
 649
 650 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
 651
 652 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
 653 {
 654         void *buf;
 655         size_t buf_itr = 0, buffer_size;
 656         char out[ASCII85_BUFSZ];
 657         long l;
 658         int i;
 659
 660         if (!src || !len)
 661                 return NULL;
 662
 663         l = ascii85_encode_len(len);
 664
 665         /*
 666          * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
 667          * account for the worst case of 5 bytes per dword plus the 1 for '\0'
 668          */
 669         buffer_size = (l * 5) + 1;
 670
 671         buf = kvmalloc(buffer_size, GFP_KERNEL);
 672         if (!buf)
 673                 return NULL;
 674
 675         for (i = 0; i < l; i++)
 676                 buf_itr += snprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
 677                                 ascii85_encode(src[i], out));
 678
 679         return buf;
 680 }
 681
 682 /* len is expected to be in bytes */
 683 static void adreno_show_object(struct drm_printer *p, void **ptr, int len,
 684                 bool *encoded)
 685 {
 686         if (!*ptr || !len)
 687                 return;
 688
 689         if (!*encoded) {
 690                 long datalen, i;
 691                 u32 *buf = *ptr;
 692
 693                 /*
 694                  * Only dump the non-zero part of the buffer - rarely will
 695                  * any data completely fill the entire allocated size of
 696                  * the buffer.
 697                  */
 698                 for (datalen = 0, i = 0; i < len >> 2; i++)
 699                         if (buf[i])
 700                                 datalen = ((i + 1) << 2);
 701
 702                 /*
 703                  * If we reach here, then the originally captured binary buffer
 704                  * will be replaced with the ascii85 encoded string
 705                  */
 706                 *ptr = adreno_gpu_ascii85_encode(buf, datalen);
 707
 708                 kvfree(buf);
 709
 710                 *encoded = true;
 711         }
 712
 713         if (!*ptr)
 714                 return;
 715
 716         drm_puts(p, "    data: !!ascii85 |\n");
 717         drm_puts(p, "     ");
 718
 719         drm_puts(p, *ptr);
 720
 721         drm_puts(p, "\n");
 722 }
 723
 724 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
 725                 struct drm_printer *p)
 726 {
 727         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 728         int i;
 729
 730         if (IS_ERR_OR_NULL(state))
 731                 return;
 732
 733         drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
 734                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 735                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 736                         adreno_gpu->rev.patchid);
 737
 738         drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
 739
 740         drm_puts(p, "ringbuffer:\n");
 741
 742         for (i = 0; i < gpu->nr_rings; i++) {
 743                 drm_printf(p, "  - id: %d\n", i);
 744                 drm_printf(p, "    iova: 0x%016llx\n", state->ring[i].iova);
 745                 drm_printf(p, "    last-fence: %d\n", state->ring[i].seqno);
 746                 drm_printf(p, "    retired-fence: %d\n", state->ring[i].fence);
 747                 drm_printf(p, "    rptr: %d\n", state->ring[i].rptr);
 748                 drm_printf(p, "    wptr: %d\n", state->ring[i].wptr);
 749                 drm_printf(p, "    size: %d\n", MSM_GPU_RINGBUFFER_SZ);
 750
 751                 adreno_show_object(p, &state->ring[i].data,
 752                         state->ring[i].data_size, &state->ring[i].encoded);
 753         }
 754
 755         if (state->bos) {
 756                 drm_puts(p, "bos:\n");
 757
 758                 for (i = 0; i < state->nr_bos; i++) {
 759                         drm_printf(p, "  - iova: 0x%016llx\n",
 760                                 state->bos[i].iova);
 761                         drm_printf(p, "    size: %zd\n", state->bos[i].size);
 762
 763                         adreno_show_object(p, &state->bos[i].data,
 764                                 state->bos[i].size, &state->bos[i].encoded);
 765                 }
 766         }
 767
 768         if (state->nr_registers) {
 769                 drm_puts(p, "registers:\n");
 770
 771                 for (i = 0; i < state->nr_registers; i++) {
 772                         drm_printf(p, "  - { offset: 0x%04x, value: 0x%08x }\n",
 773                                 state->registers[i * 2] << 2,
 774                                 state->registers[(i * 2) + 1]);
 775                 }
 776         }
 777 }
 778 #endif
 779
 780 /* Dump common gpu status and scratch registers on any hang, to make
 781  * the hangcheck logs more useful.  The scratch registers seem always
 782  * safe to read when GPU has hung (unlike some other regs, depending
 783  * on how the GPU hung), and they are useful to match up to cmdstream
 784  * dumps when debugging hangs:
 785  */
 786 void adreno_dump_info(struct msm_gpu *gpu)
 787 {
 788         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 789         int i;
 790
 791         printk("revision: %d (%d.%d.%d.%d)\n",
 792                         adreno_gpu->info->revn, adreno_gpu->rev.core,
 793                         adreno_gpu->rev.major, adreno_gpu->rev.minor,
 794                         adreno_gpu->rev.patchid);
 795
 796         for (i = 0; i < gpu->nr_rings; i++) {
 797                 struct msm_ringbuffer *ring = gpu->rb[i];
 798
 799                 printk("rb %d: fence:    %d/%d\n", i,
 800                         ring->memptrs->fence,
 801                         ring->seqno);
 802
 803                 printk("rptr:     %d\n", get_rptr(adreno_gpu, ring));
 804                 printk("rb wptr:  %d\n", get_wptr(ring));
 805         }
 806 }
 807
 808 /* would be nice to not have to duplicate the _show() stuff with printk(): */
 809 void adreno_dump(struct msm_gpu *gpu)
 810 {
 811         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 812         int i;
 813
 814         if (!adreno_gpu->registers)
 815                 return;
 816
 817         /* dump these out in a form that can be parsed by demsm: */
 818         printk("IO:region %s 00000000 00020000\n", gpu->name);
 819         for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 820                 uint32_t start = adreno_gpu->registers[i];
 821                 uint32_t end   = adreno_gpu->registers[i+1];
 822                 uint32_t addr;
 823
 824                 for (addr = start; addr <= end; addr++) {
 825                         uint32_t val = gpu_read(gpu, addr);
 826                         printk("IO:R %08x %08x\n", addr<<2, val);
 827                 }
 828         }
 829 }
 830
 831 static uint32_t ring_freewords(struct msm_ringbuffer *ring)
 832 {
 833         struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
 834         uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
 835         /* Use ring->next to calculate free size */
 836         uint32_t wptr = ring->next - ring->start;
 837         uint32_t rptr = get_rptr(adreno_gpu, ring);
 838         return (rptr + (size - 1) - wptr) % size;
 839 }
 840
 841 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
 842 {
 843         if (spin_until(ring_freewords(ring) >= ndwords))
 844                 DRM_DEV_ERROR(ring->gpu->dev->dev,
 845                         "timeout waiting for space in ringbuffer %d\n",
 846                         ring->id);
 847 }
 848
 849 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
 850 static int adreno_get_legacy_pwrlevels(struct device *dev)
 851 {
 852         struct device_node *child, *node;
 853         int ret;
 854
 855         node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
 856         if (!node) {
 857                 DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
 858                 return -ENXIO;
 859         }
 860
 861         for_each_child_of_node(node, child) {
 862                 unsigned int val;
 863
 864                 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
 865                 if (ret)
 866                         continue;
 867
 868                 /*
 869                  * Skip the intentionally bogus clock value found at the bottom
 870                  * of most legacy frequency tables
 871                  */
 872                 if (val != 27000000)
 873                         dev_pm_opp_add(dev, val, 0);
 874         }
 875
 876         of_node_put(node);
 877
 878         return 0;
 879 }
 880
 881 static int adreno_get_pwrlevels(struct device *dev,
 882                 struct msm_gpu *gpu)
 883 {
 884         unsigned long freq = ULONG_MAX;
 885         struct dev_pm_opp *opp;
 886         int ret;
 887
 888         gpu->fast_rate = 0;
 889
 890         /* You down with OPP? */
 891         if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
 892                 ret = adreno_get_legacy_pwrlevels(dev);
 893         else {
 894                 ret = dev_pm_opp_of_add_table(dev);
 895                 if (ret)
 896                         DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
 897         }
 898
 899         if (!ret) {
 900                 /* Find the fastest defined rate */
 901                 opp = dev_pm_opp_find_freq_floor(dev, &freq);
 902                 if (!IS_ERR(opp)) {
 903                         gpu->fast_rate = freq;
 904                         dev_pm_opp_put(opp);
 905                 }
 906         }
 907
 908         if (!gpu->fast_rate) {
 909                 dev_warn(dev,
 910                         "Could not find a clock rate. Using a reasonable default\n");
 911                 /* Pick a suitably safe clock speed for any target */
 912                 gpu->fast_rate = 200000000;
 913         }
 914
 915         DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
 916
 917         /* Check for an interconnect path for the bus */
 918         gpu->icc_path = of_icc_get(dev, "gfx-mem");
 919         if (!gpu->icc_path) {
 920                 /*
 921                  * Keep compatbility with device trees that don't have an
 922                  * interconnect-names property.
 923                  */
 924                 gpu->icc_path = of_icc_get(dev, NULL);
 925         }
 926         if (IS_ERR(gpu->icc_path))
 927                 gpu->icc_path = NULL;
 928
 929         gpu->ocmem_icc_path = of_icc_get(dev, "ocmem");
 930         if (IS_ERR(gpu->ocmem_icc_path))
 931                 gpu->ocmem_icc_path = NULL;
 932
 933         return 0;
 934 }
 935
 936 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
 937                           struct adreno_ocmem *adreno_ocmem)
 938 {
 939         struct ocmem_buf *ocmem_hdl;
 940         struct ocmem *ocmem;
 941
 942         ocmem = of_get_ocmem(dev);
 943         if (IS_ERR(ocmem)) {
 944                 if (PTR_ERR(ocmem) == -ENODEV) {
 945                         /*
 946                          * Return success since either the ocmem property was
 947                          * not specified in device tree, or ocmem support is
 948                          * not compiled into the kernel.
 949                          */
 950                         return 0;
 951                 }
 952
 953                 return PTR_ERR(ocmem);
 954         }
 955
 956         ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
 957         if (IS_ERR(ocmem_hdl))
 958                 return PTR_ERR(ocmem_hdl);
 959
 960         adreno_ocmem->ocmem = ocmem;
 961         adreno_ocmem->base = ocmem_hdl->addr;
 962         adreno_ocmem->hdl = ocmem_hdl;
 963         adreno_gpu->gmem = ocmem_hdl->len;
 964
 965         return 0;
 966 }
 967
 968 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
 969 {
 970         if (adreno_ocmem && adreno_ocmem->base)
 971                 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
 972                            adreno_ocmem->hdl);
 973 }
 974
 975 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 976                 struct adreno_gpu *adreno_gpu,
 977                 const struct adreno_gpu_funcs *funcs, int nr_rings)
 978 {
 979         struct adreno_platform_config *config = pdev->dev.platform_data;
 980         struct msm_gpu_config adreno_gpu_config  = { 0 };
 981         struct msm_gpu *gpu = &adreno_gpu->base;
 982
 983         adreno_gpu->funcs = funcs;
 984         adreno_gpu->info = adreno_info(config->rev);
 985         adreno_gpu->gmem = adreno_gpu->info->gmem;
 986         adreno_gpu->revn = adreno_gpu->info->revn;
 987         adreno_gpu->rev = config->rev;
 988
 989         adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
 990
 991         adreno_gpu_config.va_start = SZ_16M;
 992         adreno_gpu_config.va_end = 0xffffffff;
 993         /* maximum range of a2xx mmu */
 994         if (adreno_is_a2xx(adreno_gpu))
 995                 adreno_gpu_config.va_end = SZ_16M + 0xfff * SZ_64K;
 996
 997         adreno_gpu_config.nr_rings = nr_rings;
 998
 999         adreno_get_pwrlevels(&pdev->dev, gpu);
1000
1001         pm_runtime_set_autosuspend_delay(&pdev->dev,
1002                 adreno_gpu->info->inactive_period);
1003         pm_runtime_use_autosuspend(&pdev->dev);
1004         pm_runtime_enable(&pdev->dev);
1005
1006         return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
1007                         adreno_gpu->info->name, &adreno_gpu_config);
1008 }
1009
1010 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1011 {
1012         struct msm_gpu *gpu = &adreno_gpu->base;
1013         unsigned int i;
1014
1015         for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1016                 release_firmware(adreno_gpu->fw[i]);
1017
1018         icc_put(gpu->icc_path);
1019         icc_put(gpu->ocmem_icc_path);
1020
1021         msm_gpu_cleanup(&adreno_gpu->base);
1022 }