1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
9 #include <linux/ascii85.h>
10 #include <linux/interconnect.h>
11 #include <linux/qcom_scm.h>
12 #include <linux/kernel.h>
13 #include <linux/of_address.h>
14 #include <linux/pm_opp.h>
15 #include <linux/slab.h>
16 #include <linux/soc/qcom/mdt_loader.h>
17 #include <soc/qcom/ocmem.h>
18 #include "adreno_gpu.h"
22 static bool zap_available = true;
24 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
27 struct device *dev = &gpu->pdev->dev;
28 const struct firmware *fw;
29 const char *signed_fwname = NULL;
30 struct device_node *np, *mem_np;
34 void *mem_region = NULL;
37 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
38 zap_available = false;
42 np = of_get_child_by_name(dev->of_node, "zap-shader");
44 zap_available = false;
48 mem_np = of_parse_phandle(np, "memory-region", 0);
51 zap_available = false;
55 ret = of_address_to_resource(mem_np, 0, &r);
63 * Check for a firmware-name property. This is the new scheme
64 * to handle firmware that may be signed with device specific
65 * keys, allowing us to have a different zap fw path for different
68 * If the firmware-name property is found, we bypass the
69 * adreno_request_fw() mechanism, because we don't need to handle
70 * the /lib/firmware/qcom/... vs /lib/firmware/... case.
72 * If the firmware-name property is not found, for backwards
73 * compatibility we fall back to the fwname from the gpulist
76 of_property_read_string_index(np, "firmware-name", 0, &signed_fwname);
78 fwname = signed_fwname;
79 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);
83 /* Request the MDT file from the default location: */
84 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
87 * For new targets, we require the firmware-name property,
88 * if a zap-shader is required, rather than falling back
89 * to a firmware name specified in gpulist.
91 * Because the firmware is signed with a (potentially)
92 * device specific key, having the name come from gpulist
93 * was a bad idea, and is only provided for backwards
94 * compatibility for older targets.
100 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
104 /* Figure out how much memory we need */
105 mem_size = qcom_mdt_get_size(fw);
111 if (mem_size > resource_size(&r)) {
113 "memory region is too small to load the MDT\n");
118 /* Allocate memory for the firmware image */
119 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC);
126 * Load the rest of the MDT
128 * Note that we could be dealing with two different paths, since
129 * with upstream linux-firmware it would be in a qcom/ subdir..
130 * adreno_request_fw() handles this, but qcom_mdt_load() does
131 * not. But since we've already gotten through adreno_request_fw()
132 * we know which of the two cases it is:
134 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {
135 ret = qcom_mdt_load(dev, fw, fwname, pasid,
136 mem_region, mem_phys, mem_size, NULL);
140 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
142 ret = qcom_mdt_load(dev, fw, newname, pasid,
143 mem_region, mem_phys, mem_size, NULL);
149 /* Send the image to the secure world */
150 ret = qcom_scm_pas_auth_and_reset(pasid);
153 * If the scm call returns -EOPNOTSUPP we assume that this target
154 * doesn't need/support the zap shader so quietly fail
156 if (ret == -EOPNOTSUPP)
157 zap_available = false;
159 DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
163 memunmap(mem_region);
165 release_firmware(fw);
170 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
172 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
173 struct platform_device *pdev = gpu->pdev;
175 /* Short cut if we determine the zap shader isn't available/needed */
179 /* We need SCM to be able to load the firmware */
180 if (!qcom_scm_is_available()) {
181 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
182 return -EPROBE_DEFER;
185 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
188 struct msm_gem_address_space *
189 adreno_iommu_create_address_space(struct msm_gpu *gpu,
190 struct platform_device *pdev)
192 struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type);
193 struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, iommu);
194 struct msm_gem_address_space *aspace;
196 aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,
197 0xffffffff - SZ_16M);
199 if (IS_ERR(aspace) && !IS_ERR(mmu))
200 mmu->funcs->destroy(mmu);
205 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
207 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
210 case MSM_PARAM_GPU_ID:
211 *value = adreno_gpu->info->revn;
213 case MSM_PARAM_GMEM_SIZE:
214 *value = adreno_gpu->gmem;
216 case MSM_PARAM_GMEM_BASE:
217 *value = !adreno_is_a650(adreno_gpu) ? 0x100000 : 0;
219 case MSM_PARAM_CHIP_ID:
220 *value = adreno_gpu->rev.patchid |
221 (adreno_gpu->rev.minor << 8) |
222 (adreno_gpu->rev.major << 16) |
223 (adreno_gpu->rev.core << 24);
225 case MSM_PARAM_MAX_FREQ:
226 *value = adreno_gpu->base.fast_rate;
228 case MSM_PARAM_TIMESTAMP:
229 if (adreno_gpu->funcs->get_timestamp) {
232 pm_runtime_get_sync(&gpu->pdev->dev);
233 ret = adreno_gpu->funcs->get_timestamp(gpu, value);
234 pm_runtime_put_autosuspend(&gpu->pdev->dev);
239 case MSM_PARAM_NR_RINGS:
240 *value = gpu->nr_rings;
242 case MSM_PARAM_PP_PGTABLE:
245 case MSM_PARAM_FAULTS:
246 *value = gpu->global_faults;
249 DBG("%s: invalid param: %u", gpu->name, param);
254 const struct firmware *
255 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
257 struct drm_device *drm = adreno_gpu->base.dev;
258 const struct firmware *fw = NULL;
262 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
264 return ERR_PTR(-ENOMEM);
267 * Try first to load from qcom/$fwfile using a direct load (to avoid
268 * a potential timeout waiting for usermode helper)
270 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
271 (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
273 ret = request_firmware_direct(&fw, newname, drm->dev);
275 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
277 adreno_gpu->fwloc = FW_LOCATION_NEW;
279 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
280 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
288 * Then try the legacy location without qcom/ prefix
290 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
291 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
293 ret = request_firmware_direct(&fw, fwname, drm->dev);
295 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
297 adreno_gpu->fwloc = FW_LOCATION_LEGACY;
299 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
300 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
308 * Finally fall back to request_firmware() for cases where the
309 * usermode helper is needed (I think mainly android)
311 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
312 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
314 ret = request_firmware(&fw, newname, drm->dev);
316 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
318 adreno_gpu->fwloc = FW_LOCATION_HELPER;
320 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
321 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
328 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
329 fw = ERR_PTR(-ENOENT);
335 int adreno_load_fw(struct adreno_gpu *adreno_gpu)
339 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
340 const struct firmware *fw;
342 if (!adreno_gpu->info->fw[i])
345 /* Skip if the firmware has already been loaded */
346 if (adreno_gpu->fw[i])
349 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
353 adreno_gpu->fw[i] = fw;
359 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
360 const struct firmware *fw, u64 *iova)
362 struct drm_gem_object *bo;
365 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,
366 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
369 return ERR_CAST(ptr);
371 memcpy(ptr, &fw->data[4], fw->size - 4);
373 msm_gem_put_vaddr(bo);
378 int adreno_hw_init(struct msm_gpu *gpu)
380 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
383 DBG("%s", gpu->name);
385 ret = adreno_load_fw(adreno_gpu);
389 for (i = 0; i < gpu->nr_rings; i++) {
390 struct msm_ringbuffer *ring = gpu->rb[i];
395 ring->cur = ring->start;
396 ring->next = ring->start;
398 /* reset completed fence seqno: */
399 ring->memptrs->fence = ring->seqno;
400 ring->memptrs->rptr = 0;
404 * Setup REG_CP_RB_CNTL. The same value is used across targets (with
405 * the excpetion of A430 that disables the RPTR shadow) - the cacluation
406 * for the ringbuffer size and block size is moved to msm_gpu.h for the
407 * pre-processor to deal with and the A430 variant is ORed in here
409 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
410 MSM_GPU_RB_CNTL_DEFAULT |
411 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
413 /* Setup ringbuffer address - use ringbuffer[0] for GPU init */
414 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
415 REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);
417 if (!adreno_is_a430(adreno_gpu)) {
418 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
419 REG_ADRENO_CP_RB_RPTR_ADDR_HI,
420 rbmemptr(gpu->rb[0], rptr));
426 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
427 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
428 struct msm_ringbuffer *ring)
430 if (adreno_is_a430(adreno_gpu))
431 return ring->memptrs->rptr = adreno_gpu_read(
432 adreno_gpu, REG_ADRENO_CP_RB_RPTR);
434 return ring->memptrs->rptr;
437 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
442 void adreno_recover(struct msm_gpu *gpu)
444 struct drm_device *dev = gpu->dev;
447 // XXX pm-runtime?? we *need* the device to be off after this
448 // so maybe continuing to call ->pm_suspend/resume() is better?
450 gpu->funcs->pm_suspend(gpu);
451 gpu->funcs->pm_resume(gpu);
453 ret = msm_gpu_hw_init(gpu);
455 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
460 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
461 struct msm_file_private *ctx)
463 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
464 struct msm_drm_private *priv = gpu->dev->dev_private;
465 struct msm_ringbuffer *ring = submit->ring;
468 for (i = 0; i < submit->nr_cmds; i++) {
469 switch (submit->cmd[i].type) {
470 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
471 /* ignore IB-targets */
473 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
474 /* ignore if there has not been a ctx switch: */
475 if (priv->lastctx == ctx)
478 case MSM_SUBMIT_CMD_BUF:
479 OUT_PKT3(ring, adreno_is_a4xx(adreno_gpu) ?
480 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
481 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
482 OUT_RING(ring, submit->cmd[i].size);
488 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
489 OUT_RING(ring, submit->seqno);
491 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
492 /* Flush HLSQ lazy updates to make sure there is nothing
493 * pending for indirect loads after the timestamp has
496 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
497 OUT_RING(ring, HLSQ_FLUSH);
500 /* wait for idle before cache flush/interrupt */
501 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
502 OUT_RING(ring, 0x00000000);
504 if (!adreno_is_a2xx(adreno_gpu)) {
505 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
506 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
507 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
508 OUT_RING(ring, rbmemptr(ring, fence));
509 OUT_RING(ring, submit->seqno);
511 /* BIT(31) means something else on a2xx */
512 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
513 OUT_RING(ring, CACHE_FLUSH_TS);
514 OUT_RING(ring, rbmemptr(ring, fence));
515 OUT_RING(ring, submit->seqno);
516 OUT_PKT3(ring, CP_INTERRUPT, 1);
517 OUT_RING(ring, 0x80000000);
521 if (adreno_is_a3xx(adreno_gpu)) {
522 /* Dummy set-constant to trigger context rollover */
523 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
524 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
525 OUT_RING(ring, 0x00000000);
529 gpu->funcs->flush(gpu, ring);
532 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
534 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
537 /* Copy the shadow to the actual register */
538 ring->cur = ring->next;
541 * Mask wptr value that we calculate to fit in the HW range. This is
542 * to account for the possibility that the last command fit exactly into
543 * the ringbuffer and rb->next hasn't wrapped to zero yet
545 wptr = get_wptr(ring);
547 /* ensure writes to ringbuffer have hit system memory: */
550 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
553 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
555 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
556 uint32_t wptr = get_wptr(ring);
558 /* wait for CP to drain ringbuffer: */
559 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
562 /* TODO maybe we need to reset GPU here to recover from hang? */
563 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
564 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
569 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
571 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
574 kref_init(&state->ref);
576 ktime_get_real_ts64(&state->time);
578 for (i = 0; i < gpu->nr_rings; i++) {
581 state->ring[i].fence = gpu->rb[i]->memptrs->fence;
582 state->ring[i].iova = gpu->rb[i]->iova;
583 state->ring[i].seqno = gpu->rb[i]->seqno;
584 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
585 state->ring[i].wptr = get_wptr(gpu->rb[i]);
587 /* Copy at least 'wptr' dwords of the data */
588 size = state->ring[i].wptr;
590 /* After wptr find the last non zero dword to save space */
591 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
592 if (gpu->rb[i]->start[j])
596 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL);
597 if (state->ring[i].data) {
598 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
599 state->ring[i].data_size = size << 2;
604 /* Some targets prefer to collect their own registers */
605 if (!adreno_gpu->registers)
608 /* Count the number of registers */
609 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
610 count += adreno_gpu->registers[i + 1] -
611 adreno_gpu->registers[i] + 1;
613 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
614 if (state->registers) {
617 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
618 u32 start = adreno_gpu->registers[i];
619 u32 end = adreno_gpu->registers[i + 1];
622 for (addr = start; addr <= end; addr++) {
623 state->registers[pos++] = addr;
624 state->registers[pos++] = gpu_read(gpu, addr);
628 state->nr_registers = count;
634 void adreno_gpu_state_destroy(struct msm_gpu_state *state)
638 for (i = 0; i < ARRAY_SIZE(state->ring); i++)
639 kvfree(state->ring[i].data);
641 for (i = 0; state->bos && i < state->nr_bos; i++)
642 kvfree(state->bos[i].data);
647 kfree(state->registers);
650 static void adreno_gpu_state_kref_destroy(struct kref *kref)
652 struct msm_gpu_state *state = container_of(kref,
653 struct msm_gpu_state, ref);
655 adreno_gpu_state_destroy(state);
659 int adreno_gpu_state_put(struct msm_gpu_state *state)
661 if (IS_ERR_OR_NULL(state))
664 return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
667 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
669 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
672 size_t buf_itr = 0, buffer_size;
673 char out[ASCII85_BUFSZ];
680 l = ascii85_encode_len(len);
683 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
684 * account for the worst case of 5 bytes per dword plus the 1 for '\0'
686 buffer_size = (l * 5) + 1;
688 buf = kvmalloc(buffer_size, GFP_KERNEL);
692 for (i = 0; i < l; i++)
693 buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
694 ascii85_encode(src[i], out));
699 /* len is expected to be in bytes */
700 static void adreno_show_object(struct drm_printer *p, void **ptr, int len,
711 * Only dump the non-zero part of the buffer - rarely will
712 * any data completely fill the entire allocated size of
715 for (datalen = 0, i = 0; i < len >> 2; i++)
717 datalen = ((i + 1) << 2);
720 * If we reach here, then the originally captured binary buffer
721 * will be replaced with the ascii85 encoded string
723 *ptr = adreno_gpu_ascii85_encode(buf, datalen);
733 drm_puts(p, " data: !!ascii85 |\n");
741 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
742 struct drm_printer *p)
744 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
747 if (IS_ERR_OR_NULL(state))
750 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
751 adreno_gpu->info->revn, adreno_gpu->rev.core,
752 adreno_gpu->rev.major, adreno_gpu->rev.minor,
753 adreno_gpu->rev.patchid);
755 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
757 drm_puts(p, "ringbuffer:\n");
759 for (i = 0; i < gpu->nr_rings; i++) {
760 drm_printf(p, " - id: %d\n", i);
761 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova);
762 drm_printf(p, " last-fence: %d\n", state->ring[i].seqno);
763 drm_printf(p, " retired-fence: %d\n", state->ring[i].fence);
764 drm_printf(p, " rptr: %d\n", state->ring[i].rptr);
765 drm_printf(p, " wptr: %d\n", state->ring[i].wptr);
766 drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ);
768 adreno_show_object(p, &state->ring[i].data,
769 state->ring[i].data_size, &state->ring[i].encoded);
773 drm_puts(p, "bos:\n");
775 for (i = 0; i < state->nr_bos; i++) {
776 drm_printf(p, " - iova: 0x%016llx\n",
778 drm_printf(p, " size: %zd\n", state->bos[i].size);
780 adreno_show_object(p, &state->bos[i].data,
781 state->bos[i].size, &state->bos[i].encoded);
785 if (state->nr_registers) {
786 drm_puts(p, "registers:\n");
788 for (i = 0; i < state->nr_registers; i++) {
789 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n",
790 state->registers[i * 2] << 2,
791 state->registers[(i * 2) + 1]);
797 /* Dump common gpu status and scratch registers on any hang, to make
798 * the hangcheck logs more useful. The scratch registers seem always
799 * safe to read when GPU has hung (unlike some other regs, depending
800 * on how the GPU hung), and they are useful to match up to cmdstream
801 * dumps when debugging hangs:
803 void adreno_dump_info(struct msm_gpu *gpu)
805 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
808 printk("revision: %d (%d.%d.%d.%d)\n",
809 adreno_gpu->info->revn, adreno_gpu->rev.core,
810 adreno_gpu->rev.major, adreno_gpu->rev.minor,
811 adreno_gpu->rev.patchid);
813 for (i = 0; i < gpu->nr_rings; i++) {
814 struct msm_ringbuffer *ring = gpu->rb[i];
816 printk("rb %d: fence: %d/%d\n", i,
817 ring->memptrs->fence,
820 printk("rptr: %d\n", get_rptr(adreno_gpu, ring));
821 printk("rb wptr: %d\n", get_wptr(ring));
825 /* would be nice to not have to duplicate the _show() stuff with printk(): */
826 void adreno_dump(struct msm_gpu *gpu)
828 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
831 if (!adreno_gpu->registers)
834 /* dump these out in a form that can be parsed by demsm: */
835 printk("IO:region %s 00000000 00020000\n", gpu->name);
836 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
837 uint32_t start = adreno_gpu->registers[i];
838 uint32_t end = adreno_gpu->registers[i+1];
841 for (addr = start; addr <= end; addr++) {
842 uint32_t val = gpu_read(gpu, addr);
843 printk("IO:R %08x %08x\n", addr<<2, val);
848 static uint32_t ring_freewords(struct msm_ringbuffer *ring)
850 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
851 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
852 /* Use ring->next to calculate free size */
853 uint32_t wptr = ring->next - ring->start;
854 uint32_t rptr = get_rptr(adreno_gpu, ring);
855 return (rptr + (size - 1) - wptr) % size;
858 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
860 if (spin_until(ring_freewords(ring) >= ndwords))
861 DRM_DEV_ERROR(ring->gpu->dev->dev,
862 "timeout waiting for space in ringbuffer %d\n",
866 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
867 static int adreno_get_legacy_pwrlevels(struct device *dev)
869 struct device_node *child, *node;
872 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
874 DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
878 for_each_child_of_node(node, child) {
881 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
886 * Skip the intentionally bogus clock value found at the bottom
887 * of most legacy frequency tables
890 dev_pm_opp_add(dev, val, 0);
898 static int adreno_get_pwrlevels(struct device *dev,
901 unsigned long freq = ULONG_MAX;
902 struct dev_pm_opp *opp;
907 /* You down with OPP? */
908 if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
909 ret = adreno_get_legacy_pwrlevels(dev);
911 ret = dev_pm_opp_of_add_table(dev);
913 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
917 /* Find the fastest defined rate */
918 opp = dev_pm_opp_find_freq_floor(dev, &freq);
920 gpu->fast_rate = freq;
925 if (!gpu->fast_rate) {
927 "Could not find a clock rate. Using a reasonable default\n");
928 /* Pick a suitably safe clock speed for any target */
929 gpu->fast_rate = 200000000;
932 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
934 /* Check for an interconnect path for the bus */
935 gpu->icc_path = of_icc_get(dev, "gfx-mem");
936 if (!gpu->icc_path) {
938 * Keep compatbility with device trees that don't have an
939 * interconnect-names property.
941 gpu->icc_path = of_icc_get(dev, NULL);
943 if (IS_ERR(gpu->icc_path))
944 gpu->icc_path = NULL;
946 gpu->ocmem_icc_path = of_icc_get(dev, "ocmem");
947 if (IS_ERR(gpu->ocmem_icc_path))
948 gpu->ocmem_icc_path = NULL;
953 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
954 struct adreno_ocmem *adreno_ocmem)
956 struct ocmem_buf *ocmem_hdl;
959 ocmem = of_get_ocmem(dev);
961 if (PTR_ERR(ocmem) == -ENODEV) {
963 * Return success since either the ocmem property was
964 * not specified in device tree, or ocmem support is
965 * not compiled into the kernel.
970 return PTR_ERR(ocmem);
973 ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
974 if (IS_ERR(ocmem_hdl))
975 return PTR_ERR(ocmem_hdl);
977 adreno_ocmem->ocmem = ocmem;
978 adreno_ocmem->base = ocmem_hdl->addr;
979 adreno_ocmem->hdl = ocmem_hdl;
980 adreno_gpu->gmem = ocmem_hdl->len;
985 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
987 if (adreno_ocmem && adreno_ocmem->base)
988 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
992 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
993 struct adreno_gpu *adreno_gpu,
994 const struct adreno_gpu_funcs *funcs, int nr_rings)
996 struct adreno_platform_config *config = pdev->dev.platform_data;
997 struct msm_gpu_config adreno_gpu_config = { 0 };
998 struct msm_gpu *gpu = &adreno_gpu->base;
1000 adreno_gpu->funcs = funcs;
1001 adreno_gpu->info = adreno_info(config->rev);
1002 adreno_gpu->gmem = adreno_gpu->info->gmem;
1003 adreno_gpu->revn = adreno_gpu->info->revn;
1004 adreno_gpu->rev = config->rev;
1006 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
1008 adreno_gpu_config.nr_rings = nr_rings;
1010 adreno_get_pwrlevels(&pdev->dev, gpu);
1012 pm_runtime_set_autosuspend_delay(&pdev->dev,
1013 adreno_gpu->info->inactive_period);
1014 pm_runtime_use_autosuspend(&pdev->dev);
1015 pm_runtime_enable(&pdev->dev);
1017 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
1018 adreno_gpu->info->name, &adreno_gpu_config);
1021 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1023 struct msm_gpu *gpu = &adreno_gpu->base;
1026 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1027 release_firmware(adreno_gpu->fw[i]);
1029 icc_put(gpu->icc_path);
1030 icc_put(gpu->ocmem_icc_path);
1032 msm_gpu_cleanup(&adreno_gpu->base);