1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
9 #include "adreno_gpu.h"
11 bool hang_debug = false;
12 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
13 module_param_named(hang_debug, hang_debug, bool, 0600);
15 bool snapshot_debugbus = false;
16 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
17 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
19 bool allow_vram_carveout = false;
20 MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
21 module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
23 static const struct adreno_info gpulist[] = {
25 .rev = ADRENO_REV(2, 0, 0, 0),
29 [ADRENO_FW_PM4] = "yamato_pm4.fw",
30 [ADRENO_FW_PFP] = "yamato_pfp.fw",
33 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
34 .init = a2xx_gpu_init,
35 }, { /* a200 on i.mx51 has only 128kib gmem */
36 .rev = ADRENO_REV(2, 0, 0, 1),
40 [ADRENO_FW_PM4] = "yamato_pm4.fw",
41 [ADRENO_FW_PFP] = "yamato_pfp.fw",
44 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
45 .init = a2xx_gpu_init,
47 .rev = ADRENO_REV(2, 2, 0, ANY_ID),
51 [ADRENO_FW_PM4] = "leia_pm4_470.fw",
52 [ADRENO_FW_PFP] = "leia_pfp_470.fw",
55 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
56 .init = a2xx_gpu_init,
58 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
62 [ADRENO_FW_PM4] = "a300_pm4.fw",
63 [ADRENO_FW_PFP] = "a300_pfp.fw",
66 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
67 .init = a3xx_gpu_init,
69 .rev = ADRENO_REV(3, 0, 6, 0),
70 .revn = 307, /* because a305c is revn==306 */
73 [ADRENO_FW_PM4] = "a300_pm4.fw",
74 [ADRENO_FW_PFP] = "a300_pfp.fw",
77 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
78 .init = a3xx_gpu_init,
80 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
84 [ADRENO_FW_PM4] = "a300_pm4.fw",
85 [ADRENO_FW_PFP] = "a300_pfp.fw",
88 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
89 .init = a3xx_gpu_init,
91 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
95 [ADRENO_FW_PM4] = "a330_pm4.fw",
96 [ADRENO_FW_PFP] = "a330_pfp.fw",
99 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
100 .init = a3xx_gpu_init,
102 .rev = ADRENO_REV(4, 0, 5, ANY_ID),
106 [ADRENO_FW_PM4] = "a420_pm4.fw",
107 [ADRENO_FW_PFP] = "a420_pfp.fw",
110 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
111 .init = a4xx_gpu_init,
113 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
117 [ADRENO_FW_PM4] = "a420_pm4.fw",
118 [ADRENO_FW_PFP] = "a420_pfp.fw",
120 .gmem = (SZ_1M + SZ_512K),
121 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
122 .init = a4xx_gpu_init,
124 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
128 [ADRENO_FW_PM4] = "a420_pm4.fw",
129 [ADRENO_FW_PFP] = "a420_pfp.fw",
131 .gmem = (SZ_1M + SZ_512K),
132 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
133 .init = a4xx_gpu_init,
135 .rev = ADRENO_REV(5, 0, 6, ANY_ID),
139 [ADRENO_FW_PM4] = "a530_pm4.fw",
140 [ADRENO_FW_PFP] = "a530_pfp.fw",
142 .gmem = (SZ_128K + SZ_8K),
144 * Increase inactive period to 250 to avoid bouncing
145 * the GDSC which appears to make it grumpy
147 .inactive_period = 250,
148 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
149 ADRENO_QUIRK_LMLOADKILL_DISABLE,
150 .init = a5xx_gpu_init,
151 .zapfw = "a506_zap.mdt",
153 .rev = ADRENO_REV(5, 0, 8, ANY_ID),
157 [ADRENO_FW_PM4] = "a530_pm4.fw",
158 [ADRENO_FW_PFP] = "a530_pfp.fw",
160 .gmem = (SZ_128K + SZ_8K),
162 * Increase inactive period to 250 to avoid bouncing
163 * the GDSC which appears to make it grumpy
165 .inactive_period = 250,
166 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
167 .init = a5xx_gpu_init,
168 .zapfw = "a508_zap.mdt",
170 .rev = ADRENO_REV(5, 0, 9, ANY_ID),
174 [ADRENO_FW_PM4] = "a530_pm4.fw",
175 [ADRENO_FW_PFP] = "a530_pfp.fw",
177 .gmem = (SZ_256K + SZ_16K),
179 * Increase inactive period to 250 to avoid bouncing
180 * the GDSC which appears to make it grumpy
182 .inactive_period = 250,
183 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
184 .init = a5xx_gpu_init,
185 /* Adreno 509 uses the same ZAP as 512 */
186 .zapfw = "a512_zap.mdt",
188 .rev = ADRENO_REV(5, 1, 0, ANY_ID),
192 [ADRENO_FW_PM4] = "a530_pm4.fw",
193 [ADRENO_FW_PFP] = "a530_pfp.fw",
197 * Increase inactive period to 250 to avoid bouncing
198 * the GDSC which appears to make it grumpy
200 .inactive_period = 250,
201 .init = a5xx_gpu_init,
203 .rev = ADRENO_REV(5, 1, 2, ANY_ID),
207 [ADRENO_FW_PM4] = "a530_pm4.fw",
208 [ADRENO_FW_PFP] = "a530_pfp.fw",
210 .gmem = (SZ_256K + SZ_16K),
212 * Increase inactive period to 250 to avoid bouncing
213 * the GDSC which appears to make it grumpy
215 .inactive_period = 250,
216 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
217 .init = a5xx_gpu_init,
218 .zapfw = "a512_zap.mdt",
220 .rev = ADRENO_REV(5, 3, 0, 2),
224 [ADRENO_FW_PM4] = "a530_pm4.fw",
225 [ADRENO_FW_PFP] = "a530_pfp.fw",
226 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
230 * Increase inactive period to 250 to avoid bouncing
231 * the GDSC which appears to make it grumpy
233 .inactive_period = 250,
234 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
235 ADRENO_QUIRK_FAULT_DETECT_MASK,
236 .init = a5xx_gpu_init,
237 .zapfw = "a530_zap.mdt",
239 .rev = ADRENO_REV(5, 4, 0, ANY_ID),
243 [ADRENO_FW_PM4] = "a530_pm4.fw",
244 [ADRENO_FW_PFP] = "a530_pfp.fw",
245 [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
249 * Increase inactive period to 250 to avoid bouncing
250 * the GDSC which appears to make it grumpy
252 .inactive_period = 250,
253 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
254 .init = a5xx_gpu_init,
255 .zapfw = "a540_zap.mdt",
257 .rev = ADRENO_REV(6, 1, 8, ANY_ID),
261 [ADRENO_FW_SQE] = "a630_sqe.fw",
262 [ADRENO_FW_GMU] = "a630_gmu.bin",
265 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
266 .init = a6xx_gpu_init,
268 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
272 [ADRENO_FW_SQE] = "a630_sqe.fw",
273 [ADRENO_FW_GMU] = "a630_gmu.bin",
276 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
277 .init = a6xx_gpu_init,
278 .zapfw = "a630_zap.mdt",
281 .rev = ADRENO_REV(6, 4, 0, ANY_ID),
285 [ADRENO_FW_SQE] = "a630_sqe.fw",
286 [ADRENO_FW_GMU] = "a640_gmu.bin",
289 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
290 .init = a6xx_gpu_init,
291 .zapfw = "a640_zap.mdt",
294 .rev = ADRENO_REV(6, 5, 0, ANY_ID),
298 [ADRENO_FW_SQE] = "a650_sqe.fw",
299 [ADRENO_FW_GMU] = "a650_gmu.bin",
301 .gmem = SZ_1M + SZ_128K,
302 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
303 .init = a6xx_gpu_init,
304 .zapfw = "a650_zap.mdt",
307 .rev = ADRENO_REV(6, 6, 0, ANY_ID),
311 [ADRENO_FW_SQE] = "a660_sqe.fw",
312 [ADRENO_FW_GMU] = "a660_gmu.bin",
314 .gmem = SZ_1M + SZ_512K,
315 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
316 .init = a6xx_gpu_init,
317 .zapfw = "a660_zap.mdt",
320 .rev = ADRENO_REV(6, 3, 5, ANY_ID),
321 .name = "Adreno 7c Gen 3",
323 [ADRENO_FW_SQE] = "a660_sqe.fw",
324 [ADRENO_FW_GMU] = "a660_gmu.bin",
327 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
328 .init = a6xx_gpu_init,
331 .rev = ADRENO_REV(6, 8, 0, ANY_ID),
335 [ADRENO_FW_SQE] = "a630_sqe.fw",
336 [ADRENO_FW_GMU] = "a640_gmu.bin",
339 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
340 .init = a6xx_gpu_init,
341 .zapfw = "a640_zap.mdt",
346 MODULE_FIRMWARE("qcom/a300_pm4.fw");
347 MODULE_FIRMWARE("qcom/a300_pfp.fw");
348 MODULE_FIRMWARE("qcom/a330_pm4.fw");
349 MODULE_FIRMWARE("qcom/a330_pfp.fw");
350 MODULE_FIRMWARE("qcom/a420_pm4.fw");
351 MODULE_FIRMWARE("qcom/a420_pfp.fw");
352 MODULE_FIRMWARE("qcom/a530_pm4.fw");
353 MODULE_FIRMWARE("qcom/a530_pfp.fw");
354 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
355 MODULE_FIRMWARE("qcom/a530_zap.mdt");
356 MODULE_FIRMWARE("qcom/a530_zap.b00");
357 MODULE_FIRMWARE("qcom/a530_zap.b01");
358 MODULE_FIRMWARE("qcom/a530_zap.b02");
359 MODULE_FIRMWARE("qcom/a630_sqe.fw");
360 MODULE_FIRMWARE("qcom/a630_gmu.bin");
361 MODULE_FIRMWARE("qcom/a630_zap.mbn");
363 static inline bool _rev_match(uint8_t entry, uint8_t id)
365 return (entry == ANY_ID) || (entry == id);
368 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
371 return _rev_match(rev1.core, rev2.core) &&
372 _rev_match(rev1.major, rev2.major) &&
373 _rev_match(rev1.minor, rev2.minor) &&
374 _rev_match(rev1.patchid, rev2.patchid);
377 const struct adreno_info *adreno_info(struct adreno_rev rev)
382 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
383 const struct adreno_info *info = &gpulist[i];
384 if (adreno_cmp_rev(info->rev, rev))
391 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
393 struct msm_drm_private *priv = dev->dev_private;
394 struct platform_device *pdev = priv->gpu_pdev;
395 struct msm_gpu *gpu = NULL;
396 struct adreno_gpu *adreno_gpu;
400 gpu = dev_to_gpu(&pdev->dev);
403 dev_err_once(dev->dev, "no GPU device was found\n");
407 adreno_gpu = to_adreno_gpu(gpu);
410 * The number one reason for HW init to fail is if the firmware isn't
411 * loaded yet. Try that first and don't bother continuing on
415 ret = adreno_load_fw(adreno_gpu);
419 /* Make sure pm runtime is active and reset any previous errors */
420 pm_runtime_set_active(&pdev->dev);
422 ret = pm_runtime_get_sync(&pdev->dev);
424 pm_runtime_put_sync(&pdev->dev);
425 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
429 mutex_lock(&gpu->lock);
430 ret = msm_gpu_hw_init(gpu);
431 mutex_unlock(&gpu->lock);
432 pm_runtime_put_autosuspend(&pdev->dev);
434 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
438 #ifdef CONFIG_DEBUG_FS
439 if (gpu->funcs->debugfs_init) {
440 gpu->funcs->debugfs_init(gpu, dev->primary);
441 gpu->funcs->debugfs_init(gpu, dev->render);
448 static int find_chipid(struct device *dev, struct adreno_rev *rev)
450 struct device_node *node = dev->of_node;
455 /* first search the compat strings for qcom,adreno-XYZ.W: */
456 ret = of_property_read_string_index(node, "compatible", 0, &compat);
458 unsigned int r, patch;
460 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
461 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
467 rev->patchid = patch;
473 /* and if that fails, fall back to legacy "qcom,chipid" property: */
474 ret = of_property_read_u32(node, "qcom,chipid", &chipid);
476 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
480 rev->core = (chipid >> 24) & 0xff;
481 rev->major = (chipid >> 16) & 0xff;
482 rev->minor = (chipid >> 8) & 0xff;
483 rev->patchid = (chipid & 0xff);
485 dev_warn(dev, "Using legacy qcom,chipid binding!\n");
486 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
487 rev->core, rev->major, rev->minor, rev->patchid);
492 static int adreno_bind(struct device *dev, struct device *master, void *data)
494 static struct adreno_platform_config config = {};
495 const struct adreno_info *info;
496 struct msm_drm_private *priv = dev_get_drvdata(master);
497 struct drm_device *drm = priv->dev;
501 ret = find_chipid(dev, &config.rev);
505 dev->platform_data = &config;
506 priv->gpu_pdev = to_platform_device(dev);
508 info = adreno_info(config.rev);
511 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
512 config.rev.core, config.rev.major,
513 config.rev.minor, config.rev.patchid);
517 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
518 config.rev.minor, config.rev.patchid);
520 priv->is_a2xx = config.rev.core == 2;
521 priv->has_cached_coherent = config.rev.core >= 6;
523 gpu = info->init(drm);
525 dev_warn(drm->dev, "failed to load adreno gpu\n");
532 static void adreno_unbind(struct device *dev, struct device *master,
535 struct msm_drm_private *priv = dev_get_drvdata(master);
536 struct msm_gpu *gpu = dev_to_gpu(dev);
538 pm_runtime_force_suspend(dev);
539 gpu->funcs->destroy(gpu);
541 priv->gpu_pdev = NULL;
544 static const struct component_ops a3xx_ops = {
546 .unbind = adreno_unbind,
549 static void adreno_device_register_headless(void)
551 /* on imx5, we don't have a top-level mdp/dpu node
552 * this creates a dummy node for the driver for that case
554 struct platform_device_info dummy_info = {
564 platform_device_register_full(&dummy_info);
567 static int adreno_probe(struct platform_device *pdev)
572 ret = component_add(&pdev->dev, &a3xx_ops);
576 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
577 adreno_device_register_headless();
582 static int adreno_remove(struct platform_device *pdev)
584 component_del(&pdev->dev, &a3xx_ops);
588 static void adreno_shutdown(struct platform_device *pdev)
590 pm_runtime_force_suspend(&pdev->dev);
593 static const struct of_device_id dt_match[] = {
594 { .compatible = "qcom,adreno" },
595 { .compatible = "qcom,adreno-3xx" },
596 /* for compatibility with imx5 gpu: */
597 { .compatible = "amd,imageon" },
598 /* for backwards compat w/ downstream kgsl DT files: */
599 { .compatible = "qcom,kgsl-3d0" },
604 static int adreno_resume(struct device *dev)
606 struct msm_gpu *gpu = dev_to_gpu(dev);
608 return gpu->funcs->pm_resume(gpu);
611 static int adreno_suspend(struct device *dev)
613 struct msm_gpu *gpu = dev_to_gpu(dev);
615 return gpu->funcs->pm_suspend(gpu);
619 static const struct dev_pm_ops adreno_pm_ops = {
620 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
621 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
624 static struct platform_driver adreno_driver = {
625 .probe = adreno_probe,
626 .remove = adreno_remove,
627 .shutdown = adreno_shutdown,
630 .of_match_table = dt_match,
631 .pm = &adreno_pm_ops,
635 void __init adreno_register(void)
637 platform_driver_register(&adreno_driver);
640 void __exit adreno_unregister(void)
642 platform_driver_unregister(&adreno_driver);