drivers/gpu/drm/msm/adreno/a6xx_gmu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
   3
   4 #include <linux/clk.h>
   5 #include <linux/interconnect.h>
   6 #include <linux/pm_domain.h>
   7 #include <linux/pm_opp.h>
   8 #include <soc/qcom/cmd-db.h>
   9 #include <drm/drm_gem.h>
  10
  11 #include "a6xx_gpu.h"
  12 #include "a6xx_gmu.xml.h"
  13 #include "msm_gem.h"
  14 #include "msm_gpu_trace.h"
  15 #include "msm_mmu.h"
  16
  17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
  18 {
  19         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
  20         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
  21         struct msm_gpu *gpu = &adreno_gpu->base;
  22
  23         /* FIXME: add a banner here */
  24         gmu->hung = true;
  25
  26         /* Turn off the hangcheck timer while we are resetting */
  27         del_timer(&gpu->hangcheck_timer);
  28
  29         /* Queue the GPU handler because we need to treat this as a recovery */
  30         kthread_queue_work(gpu->worker, &gpu->recover_work);
  31 }
  32
  33 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
  34 {
  35         struct a6xx_gmu *gmu = data;
  36         u32 status;
  37
  38         status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
  39         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
  40
  41         if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
  42                 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
  43
  44                 a6xx_gmu_fault(gmu);
  45         }
  46
  47         if (status &  A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
  48                 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
  49
  50         if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
  51                 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
  52                         gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
  53
  54         return IRQ_HANDLED;
  55 }
  56
  57 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
  58 {
  59         struct a6xx_gmu *gmu = data;
  60         u32 status;
  61
  62         status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
  63         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
  64
  65         if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
  66                 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
  67
  68                 a6xx_gmu_fault(gmu);
  69         }
  70
  71         return IRQ_HANDLED;
  72 }
  73
  74 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
  75 {
  76         u32 val;
  77
  78         /* This can be called from gpu state code so make sure GMU is valid */
  79         if (!gmu->initialized)
  80                 return false;
  81
  82         val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
  83
  84         return !(val &
  85                 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
  86                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
  87 }
  88
  89 /* Check to see if the GX rail is still powered */
  90 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
  91 {
  92         u32 val;
  93
  94         /* This can be called from gpu state code so make sure GMU is valid */
  95         if (!gmu->initialized)
  96                 return false;
  97
  98         val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
  99
 100         return !(val &
 101                 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
 102                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
 103 }
 104
 105 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
 106 {
 107         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 108         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 109         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 110         u32 perf_index;
 111         unsigned long gpu_freq;
 112         int ret = 0;
 113
 114         gpu_freq = dev_pm_opp_get_freq(opp);
 115
 116         if (gpu_freq == gmu->freq)
 117                 return;
 118
 119         for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
 120                 if (gpu_freq == gmu->gpu_freqs[perf_index])
 121                         break;
 122
 123         gmu->current_perf_index = perf_index;
 124         gmu->freq = gmu->gpu_freqs[perf_index];
 125
 126         trace_msm_gmu_freq_change(gmu->freq, perf_index);
 127
 128         /*
 129          * This can get called from devfreq while the hardware is idle. Don't
 130          * bring up the power if it isn't already active
 131          */
 132         if (pm_runtime_get_if_in_use(gmu->dev) == 0)
 133                 return;
 134
 135         if (!gmu->legacy) {
 136                 a6xx_hfi_set_freq(gmu, perf_index);
 137                 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
 138                 pm_runtime_put(gmu->dev);
 139                 return;
 140         }
 141
 142         gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
 143
 144         gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
 145                         ((3 & 0xf) << 28) | perf_index);
 146
 147         /*
 148          * Send an invalid index as a vote for the bus bandwidth and let the
 149          * firmware decide on the right vote
 150          */
 151         gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
 152
 153         /* Set and clear the OOB for DCVS to trigger the GMU */
 154         a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
 155         a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
 156
 157         ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
 158         if (ret)
 159                 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 160
 161         dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
 162         pm_runtime_put(gmu->dev);
 163 }
 164
 165 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
 166 {
 167         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 168         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 169         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 170
 171         return  gmu->freq;
 172 }
 173
 174 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
 175 {
 176         u32 val;
 177         int local = gmu->idle_level;
 178
 179         /* SPTP and IFPC both report as IFPC */
 180         if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
 181                 local = GMU_IDLE_STATE_IFPC;
 182
 183         val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
 184
 185         if (val == local) {
 186                 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
 187                         !a6xx_gmu_gx_is_on(gmu))
 188                         return true;
 189         }
 190
 191         return false;
 192 }
 193
 194 /* Wait for the GMU to get to its most idle state */
 195 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
 196 {
 197         return spin_until(a6xx_gmu_check_idle_level(gmu));
 198 }
 199
 200 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
 201 {
 202         int ret;
 203         u32 val;
 204         u32 mask, reset_val;
 205
 206         val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
 207         if (val <= 0x20010004) {
 208                 mask = 0xffffffff;
 209                 reset_val = 0xbabeface;
 210         } else {
 211                 mask = 0x1ff;
 212                 reset_val = 0x100;
 213         }
 214
 215         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
 216
 217         /* Set the log wptr index
 218          * note: downstream saves the value in poweroff and restores it here
 219          */
 220         gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
 221
 222         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
 223
 224         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
 225                 (val & mask) == reset_val, 100, 10000);
 226
 227         if (ret)
 228                 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
 229
 230         return ret;
 231 }
 232
 233 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
 234 {
 235         u32 val;
 236         int ret;
 237
 238         gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
 239
 240         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
 241                 val & 1, 100, 10000);
 242         if (ret)
 243                 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
 244
 245         return ret;
 246 }
 247
 248 struct a6xx_gmu_oob_bits {
 249         int set, ack, set_new, ack_new;
 250         const char *name;
 251 };
 252
 253 /* These are the interrupt / ack bits for each OOB request that are set
 254  * in a6xx_gmu_set_oob and a6xx_clear_oob
 255  */
 256 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
 257         [GMU_OOB_GPU_SET] = {
 258                 .name = "GPU_SET",
 259                 .set = 16,
 260                 .ack = 24,
 261                 .set_new = 30,
 262                 .ack_new = 31,
 263         },
 264
 265         [GMU_OOB_PERFCOUNTER_SET] = {
 266                 .name = "PERFCOUNTER",
 267                 .set = 17,
 268                 .ack = 25,
 269                 .set_new = 28,
 270                 .ack_new = 30,
 271         },
 272
 273         [GMU_OOB_BOOT_SLUMBER] = {
 274                 .name = "BOOT_SLUMBER",
 275                 .set = 22,
 276                 .ack = 30,
 277         },
 278
 279         [GMU_OOB_DCVS_SET] = {
 280                 .name = "GPU_DCVS",
 281                 .set = 23,
 282                 .ack = 31,
 283         },
 284 };
 285
 286 /* Trigger a OOB (out of band) request to the GMU */
 287 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
 288 {
 289         int ret;
 290         u32 val;
 291         int request, ack;
 292
 293         if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
 294                 return -EINVAL;
 295
 296         if (gmu->legacy) {
 297                 request = a6xx_gmu_oob_bits[state].set;
 298                 ack = a6xx_gmu_oob_bits[state].ack;
 299         } else {
 300                 request = a6xx_gmu_oob_bits[state].set_new;
 301                 ack = a6xx_gmu_oob_bits[state].ack_new;
 302                 if (!request || !ack) {
 303                         DRM_DEV_ERROR(gmu->dev,
 304                                       "Invalid non-legacy GMU request %s\n",
 305                                       a6xx_gmu_oob_bits[state].name);
 306                         return -EINVAL;
 307                 }
 308         }
 309
 310         /* Trigger the equested OOB operation */
 311         gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
 312
 313         /* Wait for the acknowledge interrupt */
 314         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
 315                 val & (1 << ack), 100, 10000);
 316
 317         if (ret)
 318                 DRM_DEV_ERROR(gmu->dev,
 319                         "Timeout waiting for GMU OOB set %s: 0x%x\n",
 320                                 a6xx_gmu_oob_bits[state].name,
 321                                 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
 322
 323         /* Clear the acknowledge interrupt */
 324         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
 325
 326         return ret;
 327 }
 328
 329 /* Clear a pending OOB state in the GMU */
 330 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
 331 {
 332         int bit;
 333
 334         if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
 335                 return;
 336
 337         if (gmu->legacy)
 338                 bit = a6xx_gmu_oob_bits[state].ack;
 339         else
 340                 bit = a6xx_gmu_oob_bits[state].ack_new;
 341
 342         gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit);
 343 }
 344
 345 /* Enable CPU control of SPTP power power collapse */
 346 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
 347 {
 348         int ret;
 349         u32 val;
 350
 351         if (!gmu->legacy)
 352                 return 0;
 353
 354         gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
 355
 356         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
 357                 (val & 0x38) == 0x28, 1, 100);
 358
 359         if (ret) {
 360                 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
 361                         gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
 362         }
 363
 364         return 0;
 365 }
 366
 367 /* Disable CPU control of SPTP power power collapse */
 368 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
 369 {
 370         u32 val;
 371         int ret;
 372
 373         if (!gmu->legacy)
 374                 return;
 375
 376         /* Make sure retention is on */
 377         gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
 378
 379         gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
 380
 381         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
 382                 (val & 0x04), 100, 10000);
 383
 384         if (ret)
 385                 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
 386                         gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
 387 }
 388
 389 /* Let the GMU know we are starting a boot sequence */
 390 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
 391 {
 392         u32 vote;
 393
 394         /* Let the GMU know we are getting ready for boot */
 395         gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
 396
 397         /* Choose the "default" power level as the highest available */
 398         vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
 399
 400         gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
 401         gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
 402
 403         /* Let the GMU know the boot sequence has started */
 404         return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 405 }
 406
 407 /* Let the GMU know that we are about to go into slumber */
 408 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
 409 {
 410         int ret;
 411
 412         /* Disable the power counter so the GMU isn't busy */
 413         gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
 414
 415         /* Disable SPTP_PC if the CPU is responsible for it */
 416         if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
 417                 a6xx_sptprac_disable(gmu);
 418
 419         if (!gmu->legacy) {
 420                 ret = a6xx_hfi_send_prep_slumber(gmu);
 421                 goto out;
 422         }
 423
 424         /* Tell the GMU to get ready to slumber */
 425         gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
 426
 427         ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 428         a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 429
 430         if (!ret) {
 431                 /* Check to see if the GMU really did slumber */
 432                 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
 433                         != 0x0f) {
 434                         DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
 435                         ret = -ETIMEDOUT;
 436                 }
 437         }
 438
 439 out:
 440         /* Put fence into allow mode */
 441         gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
 442         return ret;
 443 }
 444
 445 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
 446 {
 447         int ret;
 448         u32 val;
 449
 450         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
 451         /* Wait for the register to finish posting */
 452         wmb();
 453
 454         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
 455                 val & (1 << 1), 100, 10000);
 456         if (ret) {
 457                 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
 458                 return ret;
 459         }
 460
 461         ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
 462                 !val, 100, 10000);
 463
 464         if (ret) {
 465                 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
 466                 return ret;
 467         }
 468
 469         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
 470
 471         /* Set up CX GMU counter 0 to count busy ticks */
 472         gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
 473         gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);
 474
 475         /* Enable the power counter */
 476         gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
 477         return 0;
 478 }
 479
 480 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
 481 {
 482         int ret;
 483         u32 val;
 484
 485         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
 486
 487         ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
 488                 val, val & (1 << 16), 100, 10000);
 489         if (ret)
 490                 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
 491
 492         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
 493 }
 494
 495 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
 496 {
 497         return msm_writel(value, ptr + (offset << 2));
 498 }
 499
 500 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
 501                 const char *name);
 502
 503 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
 504 {
 505         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 506         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 507         struct platform_device *pdev = to_platform_device(gmu->dev);
 508         void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
 509         void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
 510         uint32_t pdc_address_offset;
 511
 512         if (!pdcptr || !seqptr)
 513                 goto err;
 514
 515         if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
 516                 pdc_address_offset = 0x30090;
 517         else if (adreno_is_a650(adreno_gpu))
 518                 pdc_address_offset = 0x300a0;
 519         else
 520                 pdc_address_offset = 0x30080;
 521
 522         /* Disable SDE clock gating */
 523         gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
 524
 525         /* Setup RSC PDC handshake for sleep and wakeup */
 526         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
 527         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
 528         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
 529         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
 530         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
 531         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
 532         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
 533         gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
 534         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
 535         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
 536         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
 537
 538         /* Load RSC sequencer uCode for sleep and wakeup */
 539         if (adreno_is_a650(adreno_gpu)) {
 540                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
 541                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
 542                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
 543                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
 544                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
 545         } else {
 546                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
 547                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
 548                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
 549                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
 550                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
 551         }
 552
 553         /* Load PDC sequencer uCode for power up and power down sequence */
 554         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
 555         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
 556         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
 557         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
 558         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
 559
 560         /* Set TCS commands used by PDC sequence for low power modes */
 561         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
 562         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
 563         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
 564         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
 565         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
 566         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
 567         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
 568         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
 569         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
 570
 571         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
 572         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
 573         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
 574
 575         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
 576         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
 577         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
 578         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
 579         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
 580         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
 581
 582         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
 583         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
 584         if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
 585                 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
 586         else
 587                 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
 588         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
 589         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
 590         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
 591
 592         /* Setup GPU PDC */
 593         pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
 594         pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
 595
 596         /* ensure no writes happen before the uCode is fully written */
 597         wmb();
 598
 599 err:
 600         if (!IS_ERR_OR_NULL(pdcptr))
 601                 iounmap(pdcptr);
 602         if (!IS_ERR_OR_NULL(seqptr))
 603                 iounmap(seqptr);
 604 }
 605
 606 /*
 607  * The lowest 16 bits of this value are the number of XO clock cycles for main
 608  * hysteresis which is set at 0x1680 cycles (300 us).  The higher 16 bits are
 609  * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
 610  */
 611
 612 #define GMU_PWR_COL_HYST 0x000a1680
 613
 614 /* Set up the idle state for the GMU */
 615 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
 616 {
 617         /* Disable GMU WB/RB buffer */
 618         gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
 619         gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
 620         gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
 621
 622         gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
 623
 624         switch (gmu->idle_level) {
 625         case GMU_IDLE_STATE_IFPC:
 626                 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
 627                         GMU_PWR_COL_HYST);
 628                 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
 629                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
 630                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
 631                 fallthrough;
 632         case GMU_IDLE_STATE_SPTP:
 633                 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
 634                         GMU_PWR_COL_HYST);
 635                 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
 636                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
 637                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
 638         }
 639
 640         /* Enable RPMh GPU client */
 641         gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
 642                 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
 643                 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
 644                 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
 645                 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
 646                 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
 647                 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
 648 }
 649
 650 struct block_header {
 651         u32 addr;
 652         u32 size;
 653         u32 type;
 654         u32 value;
 655         u32 data[];
 656 };
 657
 658 /* this should be a general kernel helper */
 659 static int in_range(u32 addr, u32 start, u32 size)
 660 {
 661         return addr >= start && addr < start + size;
 662 }
 663
 664 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
 665 {
 666         if (!in_range(blk->addr, bo->iova, bo->size))
 667                 return false;
 668
 669         memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
 670         return true;
 671 }
 672
 673 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
 674 {
 675         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 676         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 677         const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
 678         const struct block_header *blk;
 679         u32 reg_offset;
 680
 681         u32 itcm_base = 0x00000000;
 682         u32 dtcm_base = 0x00040000;
 683
 684         if (adreno_is_a650(adreno_gpu))
 685                 dtcm_base = 0x10004000;
 686
 687         if (gmu->legacy) {
 688                 /* Sanity check the size of the firmware that was loaded */
 689                 if (fw_image->size > 0x8000) {
 690                         DRM_DEV_ERROR(gmu->dev,
 691                                 "GMU firmware is bigger than the available region\n");
 692                         return -EINVAL;
 693                 }
 694
 695                 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
 696                                (u32*) fw_image->data, fw_image->size);
 697                 return 0;
 698         }
 699
 700
 701         for (blk = (const struct block_header *) fw_image->data;
 702              (const u8*) blk < fw_image->data + fw_image->size;
 703              blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
 704                 if (blk->size == 0)
 705                         continue;
 706
 707                 if (in_range(blk->addr, itcm_base, SZ_16K)) {
 708                         reg_offset = (blk->addr - itcm_base) >> 2;
 709                         gmu_write_bulk(gmu,
 710                                 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
 711                                 blk->data, blk->size);
 712                 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
 713                         reg_offset = (blk->addr - dtcm_base) >> 2;
 714                         gmu_write_bulk(gmu,
 715                                 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
 716                                 blk->data, blk->size);
 717                 } else if (!fw_block_mem(&gmu->icache, blk) &&
 718                            !fw_block_mem(&gmu->dcache, blk) &&
 719                            !fw_block_mem(&gmu->dummy, blk)) {
 720                         DRM_DEV_ERROR(gmu->dev,
 721                                 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
 722                                 blk->addr, blk->size, blk->data[0]);
 723                 }
 724         }
 725
 726         return 0;
 727 }
 728
 729 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
 730 {
 731         static bool rpmh_init;
 732         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 733         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 734         int ret;
 735         u32 chipid;
 736
 737         if (adreno_is_a650(adreno_gpu))
 738                 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
 739
 740         if (state == GMU_WARM_BOOT) {
 741                 ret = a6xx_rpmh_start(gmu);
 742                 if (ret)
 743                         return ret;
 744         } else {
 745                 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
 746                         "GMU firmware is not loaded\n"))
 747                         return -ENOENT;
 748
 749                 /* Turn on register retention */
 750                 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
 751
 752                 /* We only need to load the RPMh microcode once */
 753                 if (!rpmh_init) {
 754                         a6xx_gmu_rpmh_init(gmu);
 755                         rpmh_init = true;
 756                 } else {
 757                         ret = a6xx_rpmh_start(gmu);
 758                         if (ret)
 759                                 return ret;
 760                 }
 761
 762                 ret = a6xx_gmu_fw_load(gmu);
 763                 if (ret)
 764                         return ret;
 765         }
 766
 767         gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
 768         gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
 769
 770         /* Write the iova of the HFI table */
 771         gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
 772         gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
 773
 774         gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
 775                 (1 << 31) | (0xa << 18) | (0xa0));
 776
 777         chipid = adreno_gpu->rev.core << 24;
 778         chipid |= adreno_gpu->rev.major << 16;
 779         chipid |= adreno_gpu->rev.minor << 12;
 780         chipid |= adreno_gpu->rev.patchid << 8;
 781
 782         gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
 783
 784         gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
 785                   gmu->log.iova | (gmu->log.size / SZ_4K - 1));
 786
 787         /* Set up the lowest idle level on the GMU */
 788         a6xx_gmu_power_config(gmu);
 789
 790         ret = a6xx_gmu_start(gmu);
 791         if (ret)
 792                 return ret;
 793
 794         if (gmu->legacy) {
 795                 ret = a6xx_gmu_gfx_rail_on(gmu);
 796                 if (ret)
 797                         return ret;
 798         }
 799
 800         /* Enable SPTP_PC if the CPU is responsible for it */
 801         if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
 802                 ret = a6xx_sptprac_enable(gmu);
 803                 if (ret)
 804                         return ret;
 805         }
 806
 807         ret = a6xx_gmu_hfi_start(gmu);
 808         if (ret)
 809                 return ret;
 810
 811         /* FIXME: Do we need this wmb() here? */
 812         wmb();
 813
 814         return 0;
 815 }
 816
 817 #define A6XX_HFI_IRQ_MASK \
 818         (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
 819
 820 #define A6XX_GMU_IRQ_MASK \
 821         (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
 822          A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
 823          A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
 824
 825 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
 826 {
 827         disable_irq(gmu->gmu_irq);
 828         disable_irq(gmu->hfi_irq);
 829
 830         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
 831         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
 832 }
 833
 834 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
 835 {
 836         u32 val;
 837
 838         /* Make sure there are no outstanding RPMh votes */
 839         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
 840                 (val & 1), 100, 10000);
 841         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
 842                 (val & 1), 100, 10000);
 843         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
 844                 (val & 1), 100, 10000);
 845         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
 846                 (val & 1), 100, 1000);
 847 }
 848
 849 /* Force the GMU off in case it isn't responsive */
 850 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
 851 {
 852         /* Flush all the queues */
 853         a6xx_hfi_stop(gmu);
 854
 855         /* Stop the interrupts */
 856         a6xx_gmu_irq_disable(gmu);
 857
 858         /* Force off SPTP in case the GMU is managing it */
 859         a6xx_sptprac_disable(gmu);
 860
 861         /* Make sure there are no outstanding RPMh votes */
 862         a6xx_gmu_rpmh_off(gmu);
 863 }
 864
 865 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
 866 {
 867         struct dev_pm_opp *gpu_opp;
 868         unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
 869
 870         gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
 871         if (IS_ERR_OR_NULL(gpu_opp))
 872                 return;
 873
 874         gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
 875         a6xx_gmu_set_freq(gpu, gpu_opp);
 876         dev_pm_opp_put(gpu_opp);
 877 }
 878
 879 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
 880 {
 881         struct dev_pm_opp *gpu_opp;
 882         unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
 883
 884         gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
 885         if (IS_ERR_OR_NULL(gpu_opp))
 886                 return;
 887
 888         dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp);
 889         dev_pm_opp_put(gpu_opp);
 890 }
 891
 892 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
 893 {
 894         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 895         struct msm_gpu *gpu = &adreno_gpu->base;
 896         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 897         int status, ret;
 898
 899         if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
 900                 return 0;
 901
 902         gmu->hung = false;
 903
 904         /* Turn on the resources */
 905         pm_runtime_get_sync(gmu->dev);
 906
 907         /*
 908          * "enable" the GX power domain which won't actually do anything but it
 909          * will make sure that the refcounting is correct in case we need to
 910          * bring down the GX after a GMU failure
 911          */
 912         if (!IS_ERR_OR_NULL(gmu->gxpd))
 913                 pm_runtime_get_sync(gmu->gxpd);
 914
 915         /* Use a known rate to bring up the GMU */
 916         clk_set_rate(gmu->core_clk, 200000000);
 917         ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
 918         if (ret) {
 919                 pm_runtime_put(gmu->gxpd);
 920                 pm_runtime_put(gmu->dev);
 921                 return ret;
 922         }
 923
 924         /* Set the bus quota to a reasonable value for boot */
 925         a6xx_gmu_set_initial_bw(gpu, gmu);
 926
 927         /* Enable the GMU interrupt */
 928         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
 929         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
 930         enable_irq(gmu->gmu_irq);
 931
 932         /* Check to see if we are doing a cold or warm boot */
 933         status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
 934                 GMU_WARM_BOOT : GMU_COLD_BOOT;
 935
 936         /*
 937          * Warm boot path does not work on newer GPUs
 938          * Presumably this is because icache/dcache regions must be restored
 939          */
 940         if (!gmu->legacy)
 941                 status = GMU_COLD_BOOT;
 942
 943         ret = a6xx_gmu_fw_start(gmu, status);
 944         if (ret)
 945                 goto out;
 946
 947         ret = a6xx_hfi_start(gmu, status);
 948         if (ret)
 949                 goto out;
 950
 951         /*
 952          * Turn on the GMU firmware fault interrupt after we know the boot
 953          * sequence is successful
 954          */
 955         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
 956         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
 957         enable_irq(gmu->hfi_irq);
 958
 959         /* Set the GPU to the current freq */
 960         a6xx_gmu_set_initial_freq(gpu, gmu);
 961
 962 out:
 963         /* On failure, shut down the GMU to leave it in a good state */
 964         if (ret) {
 965                 disable_irq(gmu->gmu_irq);
 966                 a6xx_rpmh_stop(gmu);
 967                 pm_runtime_put(gmu->gxpd);
 968                 pm_runtime_put(gmu->dev);
 969         }
 970
 971         return ret;
 972 }
 973
 974 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
 975 {
 976         u32 reg;
 977
 978         if (!gmu->initialized)
 979                 return true;
 980
 981         reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
 982
 983         if (reg &  A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
 984                 return false;
 985
 986         return true;
 987 }
 988
 989 #define GBIF_CLIENT_HALT_MASK             BIT(0)
 990 #define GBIF_ARB_HALT_MASK                BIT(1)
 991
 992 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
 993 {
 994         struct msm_gpu *gpu = &adreno_gpu->base;
 995
 996         if (!a6xx_has_gbif(adreno_gpu)) {
 997                 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
 998                 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
 999                                                                 0xf) == 0xf);
1000                 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
1001
1002                 return;
1003         }
1004
1005         /* Halt new client requests on GBIF */
1006         gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
1007         spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1008                         (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
1009
1010         /* Halt all AXI requests on GBIF */
1011         gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
1012         spin_until((gpu_read(gpu,  REG_A6XX_GBIF_HALT_ACK) &
1013                         (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
1014
1015         /* The GBIF halt needs to be explicitly cleared */
1016         gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
1017 }
1018
1019 /* Gracefully try to shut down the GMU and by extension the GPU */
1020 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1021 {
1022         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1023         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1024         u32 val;
1025
1026         /*
1027          * The GMU may still be in slumber unless the GPU started so check and
1028          * skip putting it back into slumber if so
1029          */
1030         val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1031
1032         if (val != 0xf) {
1033                 int ret = a6xx_gmu_wait_for_idle(gmu);
1034
1035                 /* If the GMU isn't responding assume it is hung */
1036                 if (ret) {
1037                         a6xx_gmu_force_off(gmu);
1038                         return;
1039                 }
1040
1041                 a6xx_bus_clear_pending_transactions(adreno_gpu);
1042
1043                 /* tell the GMU we want to slumber */
1044                 a6xx_gmu_notify_slumber(gmu);
1045
1046                 ret = gmu_poll_timeout(gmu,
1047                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1048                         !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1049                         100, 10000);
1050
1051                 /*
1052                  * Let the user know we failed to slumber but don't worry too
1053                  * much because we are powering down anyway
1054                  */
1055
1056                 if (ret)
1057                         DRM_DEV_ERROR(gmu->dev,
1058                                 "Unable to slumber GMU: status = 0%x/0%x\n",
1059                                 gmu_read(gmu,
1060                                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1061                                 gmu_read(gmu,
1062                                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1063         }
1064
1065         /* Turn off HFI */
1066         a6xx_hfi_stop(gmu);
1067
1068         /* Stop the interrupts and mask the hardware */
1069         a6xx_gmu_irq_disable(gmu);
1070
1071         /* Tell RPMh to power off the GPU */
1072         a6xx_rpmh_stop(gmu);
1073 }
1074
1075
1076 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1077 {
1078         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1079         struct msm_gpu *gpu = &a6xx_gpu->base.base;
1080
1081         if (!pm_runtime_active(gmu->dev))
1082                 return 0;
1083
1084         /*
1085          * Force the GMU off if we detected a hang, otherwise try to shut it
1086          * down gracefully
1087          */
1088         if (gmu->hung)
1089                 a6xx_gmu_force_off(gmu);
1090         else
1091                 a6xx_gmu_shutdown(gmu);
1092
1093         /* Remove the bus vote */
1094         dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
1095
1096         /*
1097          * Make sure the GX domain is off before turning off the GMU (CX)
1098          * domain. Usually the GMU does this but only if the shutdown sequence
1099          * was successful
1100          */
1101         if (!IS_ERR_OR_NULL(gmu->gxpd))
1102                 pm_runtime_put_sync(gmu->gxpd);
1103
1104         clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1105
1106         pm_runtime_put_sync(gmu->dev);
1107
1108         return 0;
1109 }
1110
1111 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1112 {
1113         msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false);
1114         msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false);
1115         msm_gem_kernel_put(gmu->icache.obj, gmu->aspace, false);
1116         msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace, false);
1117         msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace, false);
1118         msm_gem_kernel_put(gmu->log.obj, gmu->aspace, false);
1119
1120         gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1121         msm_gem_address_space_put(gmu->aspace);
1122 }
1123
1124 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1125                 size_t size, u64 iova)
1126 {
1127         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1128         struct drm_device *dev = a6xx_gpu->base.base.dev;
1129         uint32_t flags = MSM_BO_WC;
1130         u64 range_start, range_end;
1131         int ret;
1132
1133         size = PAGE_ALIGN(size);
1134         if (!iova) {
1135                 /* no fixed address - use GMU's uncached range */
1136                 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1137                 range_end = 0x80000000;
1138         } else {
1139                 /* range for fixed address */
1140                 range_start = iova;
1141                 range_end = iova + size;
1142                 /* use IOMMU_PRIV for icache/dcache */
1143                 flags |= MSM_BO_MAP_PRIV;
1144         }
1145
1146         bo->obj = msm_gem_new(dev, size, flags);
1147         if (IS_ERR(bo->obj))
1148                 return PTR_ERR(bo->obj);
1149
1150         ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1151                 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT);
1152         if (ret) {
1153                 drm_gem_object_put(bo->obj);
1154                 return ret;
1155         }
1156
1157         bo->virt = msm_gem_get_vaddr(bo->obj);
1158         bo->size = size;
1159
1160         return 0;
1161 }
1162
1163 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1164 {
1165         struct iommu_domain *domain;
1166         struct msm_mmu *mmu;
1167
1168         domain = iommu_domain_alloc(&platform_bus_type);
1169         if (!domain)
1170                 return -ENODEV;
1171
1172         mmu = msm_iommu_new(gmu->dev, domain);
1173         gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1174         if (IS_ERR(gmu->aspace)) {
1175                 iommu_domain_free(domain);
1176                 return PTR_ERR(gmu->aspace);
1177         }
1178
1179         return 0;
1180 }
1181
1182 /* Return the 'arc-level' for the given frequency */
1183 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1184                                            unsigned long freq)
1185 {
1186         struct dev_pm_opp *opp;
1187         unsigned int val;
1188
1189         if (!freq)
1190                 return 0;
1191
1192         opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1193         if (IS_ERR(opp))
1194                 return 0;
1195
1196         val = dev_pm_opp_get_level(opp);
1197
1198         dev_pm_opp_put(opp);
1199
1200         return val;
1201 }
1202
1203 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1204                 unsigned long *freqs, int freqs_count, const char *id)
1205 {
1206         int i, j;
1207         const u16 *pri, *sec;
1208         size_t pri_count, sec_count;
1209
1210         pri = cmd_db_read_aux_data(id, &pri_count);
1211         if (IS_ERR(pri))
1212                 return PTR_ERR(pri);
1213         /*
1214          * The data comes back as an array of unsigned shorts so adjust the
1215          * count accordingly
1216          */
1217         pri_count >>= 1;
1218         if (!pri_count)
1219                 return -EINVAL;
1220
1221         sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1222         if (IS_ERR(sec))
1223                 return PTR_ERR(sec);
1224
1225         sec_count >>= 1;
1226         if (!sec_count)
1227                 return -EINVAL;
1228
1229         /* Construct a vote for each frequency */
1230         for (i = 0; i < freqs_count; i++) {
1231                 u8 pindex = 0, sindex = 0;
1232                 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1233
1234                 /* Get the primary index that matches the arc level */
1235                 for (j = 0; j < pri_count; j++) {
1236                         if (pri[j] >= level) {
1237                                 pindex = j;
1238                                 break;
1239                         }
1240                 }
1241
1242                 if (j == pri_count) {
1243                         DRM_DEV_ERROR(dev,
1244                                       "Level %u not found in the RPMh list\n",
1245                                       level);
1246                         DRM_DEV_ERROR(dev, "Available levels:\n");
1247                         for (j = 0; j < pri_count; j++)
1248                                 DRM_DEV_ERROR(dev, "  %u\n", pri[j]);
1249
1250                         return -EINVAL;
1251                 }
1252
1253                 /*
1254                  * Look for a level in in the secondary list that matches. If
1255                  * nothing fits, use the maximum non zero vote
1256                  */
1257
1258                 for (j = 0; j < sec_count; j++) {
1259                         if (sec[j] >= level) {
1260                                 sindex = j;
1261                                 break;
1262                         } else if (sec[j]) {
1263                                 sindex = j;
1264                         }
1265                 }
1266
1267                 /* Construct the vote */
1268                 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1269                         (sindex << 8) | pindex;
1270         }
1271
1272         return 0;
1273 }
1274
1275 /*
1276  * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1277  * to construct the list of votes on the CPU and send it over. Query the RPMh
1278  * voltage levels and build the votes
1279  */
1280
1281 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1282 {
1283         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1284         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1285         struct msm_gpu *gpu = &adreno_gpu->base;
1286         int ret;
1287
1288         /* Build the GX votes */
1289         ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1290                 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1291
1292         /* Build the CX votes */
1293         ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1294                 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1295
1296         return ret;
1297 }
1298
1299 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1300                 u32 size)
1301 {
1302         int count = dev_pm_opp_get_opp_count(dev);
1303         struct dev_pm_opp *opp;
1304         int i, index = 0;
1305         unsigned long freq = 1;
1306
1307         /*
1308          * The OPP table doesn't contain the "off" frequency level so we need to
1309          * add 1 to the table size to account for it
1310          */
1311
1312         if (WARN(count + 1 > size,
1313                 "The GMU frequency table is being truncated\n"))
1314                 count = size - 1;
1315
1316         /* Set the "off" frequency */
1317         freqs[index++] = 0;
1318
1319         for (i = 0; i < count; i++) {
1320                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1321                 if (IS_ERR(opp))
1322                         break;
1323
1324                 dev_pm_opp_put(opp);
1325                 freqs[index++] = freq++;
1326         }
1327
1328         return index;
1329 }
1330
1331 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1332 {
1333         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1334         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1335         struct msm_gpu *gpu = &adreno_gpu->base;
1336
1337         int ret = 0;
1338
1339         /*
1340          * The GMU handles its own frequency switching so build a list of
1341          * available frequencies to send during initialization
1342          */
1343         ret = dev_pm_opp_of_add_table(gmu->dev);
1344         if (ret) {
1345                 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1346                 return ret;
1347         }
1348
1349         gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1350                 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1351
1352         /*
1353          * The GMU also handles GPU frequency switching so build a list
1354          * from the GPU OPP table
1355          */
1356         gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1357                 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1358
1359         gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1360
1361         /* Build the list of RPMh votes that we'll send to the GMU */
1362         return a6xx_gmu_rpmh_votes_init(gmu);
1363 }
1364
1365 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1366 {
1367         int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1368
1369         if (ret < 1)
1370                 return ret;
1371
1372         gmu->nr_clocks = ret;
1373
1374         gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1375                 gmu->nr_clocks, "gmu");
1376
1377         return 0;
1378 }
1379
1380 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1381                 const char *name)
1382 {
1383         void __iomem *ret;
1384         struct resource *res = platform_get_resource_byname(pdev,
1385                         IORESOURCE_MEM, name);
1386
1387         if (!res) {
1388                 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1389                 return ERR_PTR(-EINVAL);
1390         }
1391
1392         ret = ioremap(res->start, resource_size(res));
1393         if (!ret) {
1394                 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1395                 return ERR_PTR(-EINVAL);
1396         }
1397
1398         return ret;
1399 }
1400
1401 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1402                 const char *name, irq_handler_t handler)
1403 {
1404         int irq, ret;
1405
1406         irq = platform_get_irq_byname(pdev, name);
1407
1408         ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
1409         if (ret) {
1410                 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1411                               name, ret);
1412                 return ret;
1413         }
1414
1415         disable_irq(irq);
1416
1417         return irq;
1418 }
1419
1420 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1421 {
1422         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1423         struct platform_device *pdev = to_platform_device(gmu->dev);
1424
1425         if (!gmu->initialized)
1426                 return;
1427
1428         pm_runtime_force_suspend(gmu->dev);
1429
1430         if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1431                 pm_runtime_disable(gmu->gxpd);
1432                 dev_pm_domain_detach(gmu->gxpd, false);
1433         }
1434
1435         iounmap(gmu->mmio);
1436         if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1437                 iounmap(gmu->rscc);
1438         gmu->mmio = NULL;
1439         gmu->rscc = NULL;
1440
1441         a6xx_gmu_memory_free(gmu);
1442
1443         free_irq(gmu->gmu_irq, gmu);
1444         free_irq(gmu->hfi_irq, gmu);
1445
1446         /* Drop reference taken in of_find_device_by_node */
1447         put_device(gmu->dev);
1448
1449         gmu->initialized = false;
1450 }
1451
1452 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1453 {
1454         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1455         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1456         struct platform_device *pdev = of_find_device_by_node(node);
1457         int ret;
1458
1459         if (!pdev)
1460                 return -ENODEV;
1461
1462         gmu->dev = &pdev->dev;
1463
1464         of_dma_configure(gmu->dev, node, true);
1465
1466         /* Fow now, don't do anything fancy until we get our feet under us */
1467         gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1468
1469         pm_runtime_enable(gmu->dev);
1470
1471         /* Get the list of clocks */
1472         ret = a6xx_gmu_clocks_probe(gmu);
1473         if (ret)
1474                 goto err_put_device;
1475
1476         ret = a6xx_gmu_memory_probe(gmu);
1477         if (ret)
1478                 goto err_put_device;
1479
1480         /* Allocate memory for the GMU dummy page */
1481         ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000);
1482         if (ret)
1483                 goto err_memory;
1484
1485         if (adreno_is_a650(adreno_gpu)) {
1486                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1487                         SZ_16M - SZ_16K, 0x04000);
1488                 if (ret)
1489                         goto err_memory;
1490         } else if (adreno_is_a640(adreno_gpu)) {
1491                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1492                         SZ_256K - SZ_16K, 0x04000);
1493                 if (ret)
1494                         goto err_memory;
1495
1496                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1497                         SZ_256K - SZ_16K, 0x44000);
1498                 if (ret)
1499                         goto err_memory;
1500         } else {
1501                 /* HFI v1, has sptprac */
1502                 gmu->legacy = true;
1503
1504                 /* Allocate memory for the GMU debug region */
1505                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0);
1506                 if (ret)
1507                         goto err_memory;
1508         }
1509
1510         /* Allocate memory for for the HFI queues */
1511         ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0);
1512         if (ret)
1513                 goto err_memory;
1514
1515         /* Allocate memory for the GMU log region */
1516         ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0);
1517         if (ret)
1518                 goto err_memory;
1519
1520         /* Map the GMU registers */
1521         gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1522         if (IS_ERR(gmu->mmio)) {
1523                 ret = PTR_ERR(gmu->mmio);
1524                 goto err_memory;
1525         }
1526
1527         if (adreno_is_a650(adreno_gpu)) {
1528                 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1529                 if (IS_ERR(gmu->rscc))
1530                         goto err_mmio;
1531         } else {
1532                 gmu->rscc = gmu->mmio + 0x23000;
1533         }
1534
1535         /* Get the HFI and GMU interrupts */
1536         gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1537         gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1538
1539         if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)
1540                 goto err_mmio;
1541
1542         /*
1543          * Get a link to the GX power domain to reset the GPU in case of GMU
1544          * crash
1545          */
1546         gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1547
1548         /* Get the power levels for the GMU and GPU */
1549         a6xx_gmu_pwrlevels_probe(gmu);
1550
1551         /* Set up the HFI queues */
1552         a6xx_hfi_init(gmu);
1553
1554         gmu->initialized = true;
1555
1556         return 0;
1557
1558 err_mmio:
1559         iounmap(gmu->mmio);
1560         if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1561                 iounmap(gmu->rscc);
1562         free_irq(gmu->gmu_irq, gmu);
1563         free_irq(gmu->hfi_irq, gmu);
1564
1565         ret = -ENODEV;
1566
1567 err_memory:
1568         a6xx_gmu_memory_free(gmu);
1569 err_put_device:
1570         /* Drop reference taken in of_find_device_by_node */
1571         put_device(gmu->dev);
1572
1573         return ret;
1574 }