1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2010 Matt Turner.
4 * Copyright 2012 Red Hat
6 * Authors: Matthew Garrett
11 #include <linux/delay.h>
12 #include <linux/dma-buf-map.h>
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_atomic_state_helper.h>
16 #include <drm/drm_crtc_helper.h>
17 #include <drm/drm_damage_helper.h>
18 #include <drm/drm_format_helper.h>
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_gem_atomic_helper.h>
21 #include <drm/drm_gem_framebuffer_helper.h>
22 #include <drm/drm_plane_helper.h>
23 #include <drm/drm_print.h>
24 #include <drm/drm_probe_helper.h>
25 #include <drm/drm_simple_kms_helper.h>
27 #include "mgag200_drv.h"
29 #define MGAG200_LUT_SIZE 256
32 * This file contains setup code for the CRTC.
35 static void mga_crtc_load_lut(struct drm_crtc *crtc)
37 struct drm_device *dev = crtc->dev;
38 struct mga_device *mdev = to_mga_device(dev);
39 struct drm_framebuffer *fb;
40 u16 *r_ptr, *g_ptr, *b_ptr;
46 if (!mdev->display_pipe.plane.state)
49 fb = mdev->display_pipe.plane.state->fb;
51 r_ptr = crtc->gamma_store;
52 g_ptr = r_ptr + crtc->gamma_size;
53 b_ptr = g_ptr + crtc->gamma_size;
55 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
57 if (fb && fb->format->cpp[0] * 8 == 16) {
58 int inc = (fb->format->depth == 15) ? 8 : 4;
60 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
61 if (fb->format->depth == 16) {
62 if (i > (MGAG200_LUT_SIZE >> 1)) {
75 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
76 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
77 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
81 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
83 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8);
84 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
85 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8);
89 static inline void mga_wait_vsync(struct mga_device *mdev)
91 unsigned long timeout = jiffies + HZ/10;
92 unsigned int status = 0;
95 status = RREG32(MGAREG_Status);
96 } while ((status & 0x08) && time_before(jiffies, timeout));
97 timeout = jiffies + HZ/10;
100 status = RREG32(MGAREG_Status);
101 } while (!(status & 0x08) && time_before(jiffies, timeout));
104 static inline void mga_wait_busy(struct mga_device *mdev)
106 unsigned long timeout = jiffies + HZ;
107 unsigned int status = 0;
109 status = RREG8(MGAREG_Status + 2);
110 } while ((status & 0x01) && time_before(jiffies, timeout));
117 static int mgag200_g200_set_plls(struct mga_device *mdev, long clock)
119 struct drm_device *dev = &mdev->base;
120 const int post_div_max = 7;
121 const int in_div_min = 1;
122 const int in_div_max = 6;
123 const int feed_div_min = 7;
124 const int feed_div_max = 127;
126 u8 n = 0, m = 0, p, s;
129 long delta, tmp_delta;
130 long ref_clk = mdev->model.g200.ref_clk;
131 long p_clk_min = mdev->model.g200.pclk_min;
132 long p_clk_max = mdev->model.g200.pclk_max;
134 if (clock > p_clk_max) {
135 drm_err(dev, "Pixel Clock %ld too high\n", clock);
139 if (clock < p_clk_min >> 3)
140 clock = p_clk_min >> 3;
144 p <= post_div_max && f_vco < p_clk_min;
145 p = (p << 1) + 1, f_vco <<= 1)
150 for (testm = in_div_min; testm <= in_div_max; testm++) {
151 for (testn = feed_div_min; testn <= feed_div_max; testn++) {
152 computed = ref_clk * (testn + 1) / (testm + 1);
153 if (computed < f_vco)
154 tmp_delta = f_vco - computed;
156 tmp_delta = computed - f_vco;
157 if (tmp_delta < delta) {
164 f_vco = ref_clk * (n + 1) / (m + 1);
167 else if (f_vco < 140000)
169 else if (f_vco < 180000)
174 drm_dbg_kms(dev, "clock: %ld vco: %ld m: %d n: %d p: %d s: %d\n",
175 clock, f_vco, m, n, p, s);
177 WREG_DAC(MGA1064_PIX_PLLC_M, m);
178 WREG_DAC(MGA1064_PIX_PLLC_N, n);
179 WREG_DAC(MGA1064_PIX_PLLC_P, (p | (s << 3)));
184 #define P_ARRAY_SIZE 9
186 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
188 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
189 unsigned int vcomax, vcomin, pllreffreq;
190 unsigned int delta, tmpdelta, permitteddelta;
191 unsigned int testp, testm, testn;
192 unsigned int p, m, n;
193 unsigned int computed;
194 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
198 if (unique_rev_id <= 0x03) {
206 permitteddelta = clock * 5 / 1000;
208 for (testp = 8; testp > 0; testp /= 2) {
209 if (clock * testp > vcomax)
211 if (clock * testp < vcomin)
214 for (testn = 17; testn < 256; testn++) {
215 for (testm = 1; testm < 32; testm++) {
216 computed = (pllreffreq * testn) /
218 if (computed > clock)
219 tmpdelta = computed - clock;
221 tmpdelta = clock - computed;
222 if (tmpdelta < delta) {
245 /* Permited delta is 0.5% as VESA Specification */
246 permitteddelta = clock * 5 / 1000;
248 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
249 testp = pvalues_e4[i];
251 if ((clock * testp) > vcomax)
253 if ((clock * testp) < vcomin)
256 for (testn = 50; testn <= 256; testn++) {
257 for (testm = 1; testm <= 32; testm++) {
258 computed = (pllreffreq * testn) /
260 if (computed > clock)
261 tmpdelta = computed - clock;
263 tmpdelta = clock - computed;
265 if (tmpdelta < delta) {
275 fvv = pllreffreq * (n + 1) / (m + 1);
276 fvv = (fvv - 800000) / 50000;
287 if (delta > permitteddelta) {
288 pr_warn("PLL delta too large\n");
292 WREG_DAC(MGA1064_PIX_PLLC_M, m);
293 WREG_DAC(MGA1064_PIX_PLLC_N, n);
294 WREG_DAC(MGA1064_PIX_PLLC_P, p);
296 if (unique_rev_id >= 0x04) {
297 WREG_DAC(0x1a, 0x09);
299 WREG_DAC(0x1a, 0x01);
306 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
308 unsigned int vcomax, vcomin, pllreffreq;
309 unsigned int delta, tmpdelta;
310 unsigned int testp, testm, testn, testp2;
311 unsigned int p, m, n;
312 unsigned int computed;
313 int i, j, tmpcount, vcount;
314 bool pll_locked = false;
321 if (mdev->type == G200_EW3) {
327 for (testp = 1; testp < 8; testp++) {
328 for (testp2 = 1; testp2 < 8; testp2++) {
331 if ((clock * testp * testp2) > vcomax)
333 if ((clock * testp * testp2) < vcomin)
335 for (testm = 1; testm < 26; testm++) {
336 for (testn = 32; testn < 2048 ; testn++) {
337 computed = (pllreffreq * testn) /
338 (testm * testp * testp2);
339 if (computed > clock)
340 tmpdelta = computed - clock;
342 tmpdelta = clock - computed;
343 if (tmpdelta < delta) {
345 m = ((testn & 0x100) >> 1) |
348 p = ((testn & 0x600) >> 3) |
362 for (testp = 1; testp < 9; testp++) {
363 if (clock * testp > vcomax)
365 if (clock * testp < vcomin)
368 for (testm = 1; testm < 17; testm++) {
369 for (testn = 1; testn < 151; testn++) {
370 computed = (pllreffreq * testn) /
372 if (computed > clock)
373 tmpdelta = computed - clock;
375 tmpdelta = clock - computed;
376 if (tmpdelta < delta) {
388 for (i = 0; i <= 32 && pll_locked == false; i++) {
390 WREG8(MGAREG_CRTC_INDEX, 0x1e);
391 tmp = RREG8(MGAREG_CRTC_DATA);
393 WREG8(MGAREG_CRTC_DATA, tmp+1);
396 /* set pixclkdis to 1 */
397 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
398 tmp = RREG8(DAC_DATA);
399 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
400 WREG8(DAC_DATA, tmp);
402 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
403 tmp = RREG8(DAC_DATA);
404 tmp |= MGA1064_REMHEADCTL_CLKDIS;
405 WREG8(DAC_DATA, tmp);
407 /* select PLL Set C */
408 tmp = RREG8(MGAREG_MEM_MISC_READ);
410 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
412 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
413 tmp = RREG8(DAC_DATA);
414 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
415 WREG8(DAC_DATA, tmp);
420 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
421 tmp = RREG8(DAC_DATA);
423 WREG8(DAC_DATA, tmp);
427 /* program pixel pll register */
428 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
429 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
430 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
435 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
436 tmp = RREG8(DAC_DATA);
438 WREG_DAC(MGA1064_VREF_CTL, tmp);
442 /* select the pixel pll */
443 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
444 tmp = RREG8(DAC_DATA);
445 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
446 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
447 WREG8(DAC_DATA, tmp);
449 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
450 tmp = RREG8(DAC_DATA);
451 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
452 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
453 WREG8(DAC_DATA, tmp);
455 /* reset dotclock rate bit */
456 WREG8(MGAREG_SEQ_INDEX, 1);
457 tmp = RREG8(MGAREG_SEQ_DATA);
459 WREG8(MGAREG_SEQ_DATA, tmp);
461 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
462 tmp = RREG8(DAC_DATA);
463 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
464 WREG8(DAC_DATA, tmp);
466 vcount = RREG8(MGAREG_VCOUNT);
468 for (j = 0; j < 30 && pll_locked == false; j++) {
469 tmpcount = RREG8(MGAREG_VCOUNT);
470 if (tmpcount < vcount)
472 if ((tmpcount - vcount) > 2)
478 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
479 tmp = RREG8(DAC_DATA);
480 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
481 WREG_DAC(MGA1064_REMHEADCTL, tmp);
485 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
487 unsigned int vcomax, vcomin, pllreffreq;
488 unsigned int delta, tmpdelta;
489 unsigned int testp, testm, testn;
490 unsigned int p, m, n;
491 unsigned int computed;
501 for (testp = 16; testp > 0; testp--) {
502 if (clock * testp > vcomax)
504 if (clock * testp < vcomin)
507 for (testn = 1; testn < 257; testn++) {
508 for (testm = 1; testm < 17; testm++) {
509 computed = (pllreffreq * testn) /
511 if (computed > clock)
512 tmpdelta = computed - clock;
514 tmpdelta = clock - computed;
515 if (tmpdelta < delta) {
525 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
526 tmp = RREG8(DAC_DATA);
527 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
528 WREG8(DAC_DATA, tmp);
530 tmp = RREG8(MGAREG_MEM_MISC_READ);
532 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
534 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
535 tmp = RREG8(DAC_DATA);
536 WREG8(DAC_DATA, tmp & ~0x40);
538 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
539 tmp = RREG8(DAC_DATA);
540 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
541 WREG8(DAC_DATA, tmp);
543 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
544 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
545 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
549 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
550 tmp = RREG8(DAC_DATA);
551 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
552 WREG8(DAC_DATA, tmp);
556 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
557 tmp = RREG8(DAC_DATA);
558 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
559 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
560 WREG8(DAC_DATA, tmp);
562 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
563 tmp = RREG8(DAC_DATA);
564 WREG8(DAC_DATA, tmp | 0x40);
566 tmp = RREG8(MGAREG_MEM_MISC_READ);
568 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
570 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
571 tmp = RREG8(DAC_DATA);
572 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
573 WREG8(DAC_DATA, tmp);
578 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
580 unsigned int vcomax, vcomin, pllreffreq;
581 unsigned int delta, tmpdelta;
582 unsigned int testp, testm, testn;
583 unsigned int p, m, n;
584 unsigned int computed;
585 int i, j, tmpcount, vcount;
587 bool pll_locked = false;
591 if (mdev->type == G200_EH3) {
600 for (testm = 150; testm >= 6; testm--) {
601 if (clock * testm > vcomax)
603 if (clock * testm < vcomin)
605 for (testn = 120; testn >= 60; testn--) {
606 computed = (pllreffreq * testn) / testm;
607 if (computed > clock)
608 tmpdelta = computed - clock;
610 tmpdelta = clock - computed;
611 if (tmpdelta < delta) {
631 for (testp = 16; testp > 0; testp >>= 1) {
632 if (clock * testp > vcomax)
634 if (clock * testp < vcomin)
637 for (testm = 1; testm < 33; testm++) {
638 for (testn = 17; testn < 257; testn++) {
639 computed = (pllreffreq * testn) /
641 if (computed > clock)
642 tmpdelta = computed - clock;
644 tmpdelta = clock - computed;
645 if (tmpdelta < delta) {
651 if ((clock * testp) >= 600000)
657 for (i = 0; i <= 32 && pll_locked == false; i++) {
658 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
659 tmp = RREG8(DAC_DATA);
660 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
661 WREG8(DAC_DATA, tmp);
663 tmp = RREG8(MGAREG_MEM_MISC_READ);
665 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
667 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
668 tmp = RREG8(DAC_DATA);
669 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
670 WREG8(DAC_DATA, tmp);
674 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
675 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
676 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
680 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
681 tmp = RREG8(DAC_DATA);
682 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
683 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
684 WREG8(DAC_DATA, tmp);
686 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
687 tmp = RREG8(DAC_DATA);
688 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
689 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
690 WREG8(DAC_DATA, tmp);
692 vcount = RREG8(MGAREG_VCOUNT);
694 for (j = 0; j < 30 && pll_locked == false; j++) {
695 tmpcount = RREG8(MGAREG_VCOUNT);
696 if (tmpcount < vcount)
698 if ((tmpcount - vcount) > 2)
708 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
710 static const unsigned int m_div_val[] = { 1, 2, 4, 8 };
711 unsigned int vcomax, vcomin, pllreffreq;
712 unsigned int delta, tmpdelta;
713 int testr, testn, testm, testo;
714 unsigned int p, m, n;
715 unsigned int computed, vco;
725 for (testr = 0; testr < 4; testr++) {
728 for (testn = 5; testn < 129; testn++) {
731 for (testm = 3; testm >= 0; testm--) {
734 for (testo = 5; testo < 33; testo++) {
735 vco = pllreffreq * (testn + 1) /
741 computed = vco / (m_div_val[testm] * (testo + 1));
742 if (computed > clock)
743 tmpdelta = computed - clock;
745 tmpdelta = clock - computed;
746 if (tmpdelta < delta) {
748 m = testm | (testo << 3);
750 p = testr | (testr << 3);
757 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
758 tmp = RREG8(DAC_DATA);
759 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
760 WREG8(DAC_DATA, tmp);
762 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
763 tmp = RREG8(DAC_DATA);
764 tmp |= MGA1064_REMHEADCTL_CLKDIS;
765 WREG8(DAC_DATA, tmp);
767 tmp = RREG8(MGAREG_MEM_MISC_READ);
768 tmp |= (0x3<<2) | 0xc0;
769 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
771 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
772 tmp = RREG8(DAC_DATA);
773 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
774 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
775 WREG8(DAC_DATA, tmp);
779 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
780 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
781 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
788 static int mgag200_crtc_set_plls(struct mga_device *mdev, long clock)
795 return mgag200_g200_set_plls(mdev, clock);
798 return mga_g200se_set_plls(mdev, clock);
801 return mga_g200wb_set_plls(mdev, clock);
803 return mga_g200ev_set_plls(mdev, clock);
806 return mga_g200eh_set_plls(mdev, clock);
808 return mga_g200er_set_plls(mdev, clock);
811 misc = RREG8(MGA_MISC_IN);
812 misc &= ~MGAREG_MISC_CLK_SEL_MASK;
813 misc |= MGAREG_MISC_CLK_SEL_MGA_MSK;
814 WREG8(MGA_MISC_OUT, misc);
819 static void mgag200_g200wb_hold_bmc(struct mga_device *mdev)
824 /* 1- The first step is to warn the BMC of an upcoming mode change.
825 * We are putting the misc<0> to output.*/
827 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
828 tmp = RREG8(DAC_DATA);
830 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
832 /* we are putting a 1 on the misc<0> line */
833 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
834 tmp = RREG8(DAC_DATA);
836 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
838 /* 2- Second step to mask and further scan request
839 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
841 WREG8(DAC_INDEX, MGA1064_SPAREREG);
842 tmp = RREG8(DAC_DATA);
844 WREG_DAC(MGA1064_SPAREREG, tmp);
846 /* 3a- the third step is to verifu if there is an active scan
847 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
850 while (!(tmp & 0x1) && iter_max) {
851 WREG8(DAC_INDEX, MGA1064_SPAREREG);
852 tmp = RREG8(DAC_DATA);
857 /* 3b- this step occurs only if the remove is actually scanning
858 * we are waiting for the end of the frame which is a 1 on
859 * remvsyncsts (XSPAREREG<1>)
863 while ((tmp & 0x2) && iter_max) {
864 WREG8(DAC_INDEX, MGA1064_SPAREREG);
865 tmp = RREG8(DAC_DATA);
872 static void mgag200_g200wb_release_bmc(struct mga_device *mdev)
876 /* 1- The first step is to ensure that the vrsten and hrsten are set */
877 WREG8(MGAREG_CRTCEXT_INDEX, 1);
878 tmp = RREG8(MGAREG_CRTCEXT_DATA);
879 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
881 /* 2- second step is to assert the rstlvl2 */
882 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
883 tmp = RREG8(DAC_DATA);
885 WREG8(DAC_DATA, tmp);
890 /* 3- deassert rstlvl2 */
892 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
893 WREG8(DAC_DATA, tmp);
895 /* 4- remove mask of scan request */
896 WREG8(DAC_INDEX, MGA1064_SPAREREG);
897 tmp = RREG8(DAC_DATA);
899 WREG8(DAC_DATA, tmp);
901 /* 5- put back a 0 on the misc<0> line */
902 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
903 tmp = RREG8(DAC_DATA);
905 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
909 * This is how the framebuffer base address is stored in g200 cards:
910 * * Assume @offset is the gpu_addr variable of the framebuffer object
911 * * Then addr is the number of _pixels_ (not bytes) from the start of
912 * VRAM to the first pixel we want to display. (divided by 2 for 32bit
914 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
915 * addr<20> -> CRTCEXT0<6>
916 * addr<19-16> -> CRTCEXT0<3-0>
917 * addr<15-8> -> CRTCC<7-0>
918 * addr<7-0> -> CRTCD<7-0>
920 * CRTCEXT0 has to be programmed last to trigger an update and make the
921 * new addr variable take effect.
923 static void mgag200_set_startadd(struct mga_device *mdev,
924 unsigned long offset)
926 struct drm_device *dev = &mdev->base;
928 u8 crtcc, crtcd, crtcext0;
930 startadd = offset / 8;
933 * Can't store addresses any higher than that, but we also
934 * don't have more than 16 MiB of memory, so it should be fine.
936 drm_WARN_ON(dev, startadd > 0x1fffff);
938 RREG_ECRT(0x00, crtcext0);
940 crtcc = (startadd >> 8) & 0xff;
941 crtcd = startadd & 0xff;
943 crtcext0 |= ((startadd >> 14) & BIT(6)) |
944 ((startadd >> 16) & 0x0f);
946 WREG_CRT(0x0c, crtcc);
947 WREG_CRT(0x0d, crtcd);
948 WREG_ECRT(0x00, crtcext0);
951 static void mgag200_set_dac_regs(struct mga_device *mdev)
955 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
956 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
957 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
958 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
959 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
960 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
961 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
962 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
963 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
964 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
967 switch (mdev->type) {
970 dacvalue[MGA1064_SYS_PLL_M] = 0x04;
971 dacvalue[MGA1064_SYS_PLL_N] = 0x2D;
972 dacvalue[MGA1064_SYS_PLL_P] = 0x19;
976 dacvalue[MGA1064_VREF_CTL] = 0x03;
977 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
978 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
979 MGA1064_MISC_CTL_VGA8 |
980 MGA1064_MISC_CTL_DAC_RAM_CS;
984 dacvalue[MGA1064_VREF_CTL] = 0x07;
987 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
988 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
989 MGA1064_MISC_CTL_DAC_RAM_CS;
993 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
994 MGA1064_MISC_CTL_DAC_RAM_CS;
1000 for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
1004 ((i >= 0x1f) && (i <= 0x29)) ||
1005 ((i >= 0x30) && (i <= 0x37)))
1007 if (IS_G200_SE(mdev) &&
1008 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
1010 if ((mdev->type == G200_EV ||
1011 mdev->type == G200_WB ||
1012 mdev->type == G200_EH ||
1013 mdev->type == G200_EW3 ||
1014 mdev->type == G200_EH3) &&
1015 (i >= 0x44) && (i <= 0x4e))
1018 WREG_DAC(i, dacvalue[i]);
1021 if (mdev->type == G200_ER)
1025 static void mgag200_init_regs(struct mga_device *mdev)
1029 mgag200_set_dac_regs(mdev);
1042 RREG_CRT(0x11, crtc11);
1043 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT |
1044 MGAREG_CRTC11_VINTEN |
1045 MGAREG_CRTC11_VINTCLR);
1046 WREG_CRT(0x11, crtc11);
1048 if (mdev->type == G200_ER)
1049 WREG_ECRT(0x24, 0x5);
1051 if (mdev->type == G200_EW3)
1052 WREG_ECRT(0x34, 0x5);
1054 misc = RREG8(MGA_MISC_IN);
1055 misc |= MGAREG_MISC_IOADSEL;
1056 WREG8(MGA_MISC_OUT, misc);
1059 static void mgag200_set_mode_regs(struct mga_device *mdev,
1060 const struct drm_display_mode *mode)
1062 unsigned int hdisplay, hsyncstart, hsyncend, htotal;
1063 unsigned int vdisplay, vsyncstart, vsyncend, vtotal;
1064 u8 misc, crtcext1, crtcext2, crtcext5;
1066 hdisplay = mode->hdisplay / 8 - 1;
1067 hsyncstart = mode->hsync_start / 8 - 1;
1068 hsyncend = mode->hsync_end / 8 - 1;
1069 htotal = mode->htotal / 8 - 1;
1071 /* Work around hardware quirk */
1072 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1075 vdisplay = mode->vdisplay - 1;
1076 vsyncstart = mode->vsync_start - 1;
1077 vsyncend = mode->vsync_end - 1;
1078 vtotal = mode->vtotal - 2;
1080 misc = RREG8(MGA_MISC_IN);
1082 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1083 misc |= MGAREG_MISC_HSYNCPOL;
1085 misc &= ~MGAREG_MISC_HSYNCPOL;
1087 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1088 misc |= MGAREG_MISC_VSYNCPOL;
1090 misc &= ~MGAREG_MISC_VSYNCPOL;
1092 crtcext1 = (((htotal - 4) & 0x100) >> 8) |
1093 ((hdisplay & 0x100) >> 7) |
1094 ((hsyncstart & 0x100) >> 6) |
1096 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1097 crtcext1 |= BIT(7) | /* vrsten */
1098 BIT(3); /* hrsten */
1100 crtcext2 = ((vtotal & 0xc00) >> 10) |
1101 ((vdisplay & 0x400) >> 8) |
1102 ((vdisplay & 0xc00) >> 7) |
1103 ((vsyncstart & 0xc00) >> 5) |
1104 ((vdisplay & 0x400) >> 3);
1107 WREG_CRT(0, htotal - 4);
1108 WREG_CRT(1, hdisplay);
1109 WREG_CRT(2, hdisplay);
1110 WREG_CRT(3, (htotal & 0x1F) | 0x80);
1111 WREG_CRT(4, hsyncstart);
1112 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1113 WREG_CRT(6, vtotal & 0xFF);
1114 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1115 ((vdisplay & 0x100) >> 7) |
1116 ((vsyncstart & 0x100) >> 6) |
1117 ((vdisplay & 0x100) >> 5) |
1118 ((vdisplay & 0x100) >> 4) | /* linecomp */
1119 ((vtotal & 0x200) >> 4) |
1120 ((vdisplay & 0x200) >> 3) |
1121 ((vsyncstart & 0x200) >> 2));
1122 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1123 ((vdisplay & 0x200) >> 3));
1124 WREG_CRT(16, vsyncstart & 0xFF);
1125 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1126 WREG_CRT(18, vdisplay & 0xFF);
1128 WREG_CRT(21, vdisplay & 0xFF);
1129 WREG_CRT(22, (vtotal + 1) & 0xFF);
1131 WREG_CRT(24, vdisplay & 0xFF);
1133 WREG_ECRT(0x01, crtcext1);
1134 WREG_ECRT(0x02, crtcext2);
1135 WREG_ECRT(0x05, crtcext5);
1137 WREG8(MGA_MISC_OUT, misc);
1140 static u8 mgag200_get_bpp_shift(const struct drm_format_info *format)
1142 static const u8 bpp_shift[] = {0, 1, 0, 2};
1144 return bpp_shift[format->cpp[0] - 1];
1148 * Calculates the HW offset value from the framebuffer's pitch. The
1149 * offset is a multiple of the pixel size and depends on the display
1152 static u32 mgag200_calculate_offset(struct mga_device *mdev,
1153 const struct drm_framebuffer *fb)
1155 u32 offset = fb->pitches[0] / fb->format->cpp[0];
1156 u8 bppshift = mgag200_get_bpp_shift(fb->format);
1158 if (fb->format->cpp[0] * 8 == 24)
1159 offset = (offset * 3) >> (4 - bppshift);
1161 offset = offset >> (4 - bppshift);
1166 static void mgag200_set_offset(struct mga_device *mdev,
1167 const struct drm_framebuffer *fb)
1169 u8 crtc13, crtcext0;
1170 u32 offset = mgag200_calculate_offset(mdev, fb);
1172 RREG_ECRT(0, crtcext0);
1174 crtc13 = offset & 0xff;
1176 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK;
1177 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK;
1179 WREG_CRT(0x13, crtc13);
1180 WREG_ECRT(0x00, crtcext0);
1183 static void mgag200_set_format_regs(struct mga_device *mdev,
1184 const struct drm_framebuffer *fb)
1186 struct drm_device *dev = &mdev->base;
1187 const struct drm_format_info *format = fb->format;
1188 unsigned int bpp, bppshift, scale;
1189 u8 crtcext3, xmulctrl;
1191 bpp = format->cpp[0] * 8;
1193 bppshift = mgag200_get_bpp_shift(format);
1196 scale = ((1 << bppshift) * 3) - 1;
1199 scale = (1 << bppshift) - 1;
1203 RREG_ECRT(3, crtcext3);
1207 xmulctrl = MGA1064_MUL_CTL_8bits;
1210 if (format->depth == 15)
1211 xmulctrl = MGA1064_MUL_CTL_15bits;
1213 xmulctrl = MGA1064_MUL_CTL_16bits;
1216 xmulctrl = MGA1064_MUL_CTL_24bits;
1219 xmulctrl = MGA1064_MUL_CTL_32_24bits;
1222 /* BUG: We should have caught this problem already. */
1223 drm_WARN_ON(dev, "invalid format depth\n");
1227 crtcext3 &= ~GENMASK(2, 0);
1230 WREG_DAC(MGA1064_MUL_CTL, xmulctrl);
1242 WREG_ECRT(3, crtcext3);
1245 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev)
1247 static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */
1250 memctl = RREG32(MGAREG_MEMCTL);
1252 memctl |= RESET_FLAG;
1253 WREG32(MGAREG_MEMCTL, memctl);
1257 memctl &= ~RESET_FLAG;
1258 WREG32(MGAREG_MEMCTL, memctl);
1261 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev,
1262 const struct drm_display_mode *mode,
1263 const struct drm_framebuffer *fb)
1265 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
1266 unsigned int hiprilvl;
1269 if (unique_rev_id >= 0x04) {
1271 } else if (unique_rev_id >= 0x02) {
1275 if (fb->format->cpp[0] * 8 > 16)
1277 else if (fb->format->cpp[0] * 8 > 8)
1282 mb = (mode->clock * bpp) / 1000;
1296 } else if (unique_rev_id >= 0x01) {
1302 crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */
1304 WREG_ECRT(0x06, crtcext6);
1307 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev)
1309 WREG_ECRT(0x06, 0x00);
1312 static void mgag200_enable_display(struct mga_device *mdev)
1314 u8 seq0, seq1, crtcext1;
1316 RREG_SEQ(0x00, seq0);
1317 seq0 |= MGAREG_SEQ0_SYNCRST |
1318 MGAREG_SEQ0_ASYNCRST;
1319 WREG_SEQ(0x00, seq0);
1322 * TODO: replace busy waiting with vblank IRQ; put
1323 * msleep(50) before changing SCROFF
1325 mga_wait_vsync(mdev);
1326 mga_wait_busy(mdev);
1328 RREG_SEQ(0x01, seq1);
1329 seq1 &= ~MGAREG_SEQ1_SCROFF;
1330 WREG_SEQ(0x01, seq1);
1334 RREG_ECRT(0x01, crtcext1);
1335 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF;
1336 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF;
1337 WREG_ECRT(0x01, crtcext1);
1340 static void mgag200_disable_display(struct mga_device *mdev)
1342 u8 seq0, seq1, crtcext1;
1344 RREG_SEQ(0x00, seq0);
1345 seq0 &= ~MGAREG_SEQ0_SYNCRST;
1346 WREG_SEQ(0x00, seq0);
1349 * TODO: replace busy waiting with vblank IRQ; put
1350 * msleep(50) before changing SCROFF
1352 mga_wait_vsync(mdev);
1353 mga_wait_busy(mdev);
1355 RREG_SEQ(0x01, seq1);
1356 seq1 |= MGAREG_SEQ1_SCROFF;
1357 WREG_SEQ(0x01, seq1);
1361 RREG_ECRT(0x01, crtcext1);
1362 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF |
1363 MGAREG_CRTCEXT1_HSYNCOFF;
1364 WREG_ECRT(0x01, crtcext1);
1371 static int mga_vga_get_modes(struct drm_connector *connector)
1373 struct mga_connector *mga_connector = to_mga_connector(connector);
1377 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1379 drm_connector_update_edid_property(connector, edid);
1380 ret = drm_add_edid_modes(connector, edid);
1386 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1389 uint32_t total_area, divisor;
1390 uint64_t active_area, pixels_per_second, bandwidth;
1391 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1395 if (!mode->htotal || !mode->vtotal || !mode->clock)
1398 active_area = mode->hdisplay * mode->vdisplay;
1399 total_area = mode->htotal * mode->vtotal;
1401 pixels_per_second = active_area * mode->clock * 1000;
1402 do_div(pixels_per_second, total_area);
1404 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1405 do_div(bandwidth, divisor);
1407 return (uint32_t)(bandwidth);
1410 #define MODE_BANDWIDTH MODE_BAD
1412 static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector,
1413 struct drm_display_mode *mode)
1415 struct drm_device *dev = connector->dev;
1416 struct mga_device *mdev = to_mga_device(dev);
1419 if (IS_G200_SE(mdev)) {
1420 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
1422 if (unique_rev_id == 0x01) {
1423 if (mode->hdisplay > 1600)
1424 return MODE_VIRTUAL_X;
1425 if (mode->vdisplay > 1200)
1426 return MODE_VIRTUAL_Y;
1427 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1429 return MODE_BANDWIDTH;
1430 } else if (unique_rev_id == 0x02) {
1431 if (mode->hdisplay > 1920)
1432 return MODE_VIRTUAL_X;
1433 if (mode->vdisplay > 1200)
1434 return MODE_VIRTUAL_Y;
1435 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1437 return MODE_BANDWIDTH;
1439 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1441 return MODE_BANDWIDTH;
1443 } else if (mdev->type == G200_WB) {
1444 if (mode->hdisplay > 1280)
1445 return MODE_VIRTUAL_X;
1446 if (mode->vdisplay > 1024)
1447 return MODE_VIRTUAL_Y;
1448 if (mga_vga_calculate_mode_bandwidth(mode, bpp) >
1450 return MODE_BANDWIDTH;
1451 } else if (mdev->type == G200_EV &&
1452 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1453 > (32700 * 1024))) {
1454 return MODE_BANDWIDTH;
1455 } else if (mdev->type == G200_EH &&
1456 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1457 > (37500 * 1024))) {
1458 return MODE_BANDWIDTH;
1459 } else if (mdev->type == G200_ER &&
1460 (mga_vga_calculate_mode_bandwidth(mode,
1461 bpp) > (55000 * 1024))) {
1462 return MODE_BANDWIDTH;
1465 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1466 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1467 return MODE_H_ILLEGAL;
1470 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1471 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1472 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1473 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1477 /* Validate the mode input by the user */
1478 if (connector->cmdline_mode.specified) {
1479 if (connector->cmdline_mode.bpp_specified)
1480 bpp = connector->cmdline_mode.bpp;
1483 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->vram_fb_available) {
1484 if (connector->cmdline_mode.specified)
1485 connector->cmdline_mode.specified = false;
1492 static void mga_connector_destroy(struct drm_connector *connector)
1494 struct mga_connector *mga_connector = to_mga_connector(connector);
1495 mgag200_i2c_destroy(mga_connector->i2c);
1496 drm_connector_cleanup(connector);
1499 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1500 .get_modes = mga_vga_get_modes,
1501 .mode_valid = mga_vga_mode_valid,
1504 static const struct drm_connector_funcs mga_vga_connector_funcs = {
1505 .reset = drm_atomic_helper_connector_reset,
1506 .fill_modes = drm_helper_probe_single_connector_modes,
1507 .destroy = mga_connector_destroy,
1508 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1509 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1512 static int mgag200_vga_connector_init(struct mga_device *mdev)
1514 struct drm_device *dev = &mdev->base;
1515 struct mga_connector *mconnector = &mdev->connector;
1516 struct drm_connector *connector = &mconnector->base;
1517 struct mga_i2c_chan *i2c;
1520 i2c = mgag200_i2c_create(dev);
1522 drm_warn(dev, "failed to add DDC bus\n");
1524 ret = drm_connector_init_with_ddc(dev, connector,
1525 &mga_vga_connector_funcs,
1526 DRM_MODE_CONNECTOR_VGA,
1529 goto err_mgag200_i2c_destroy;
1530 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1532 mconnector->i2c = i2c;
1536 err_mgag200_i2c_destroy:
1537 mgag200_i2c_destroy(i2c);
1542 * Simple Display Pipe
1545 static enum drm_mode_status
1546 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
1547 const struct drm_display_mode *mode)
1553 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb,
1554 struct drm_rect *clip, const struct dma_buf_map *map)
1556 void *vmap = map->vaddr; /* TODO: Use mapping abstraction properly */
1558 drm_fb_memcpy_dstclip(mdev->vram, fb->pitches[0], vmap, fb, clip);
1560 /* Always scanout image at VRAM offset 0 */
1561 mgag200_set_startadd(mdev, (u32)0);
1562 mgag200_set_offset(mdev, fb);
1566 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
1567 struct drm_crtc_state *crtc_state,
1568 struct drm_plane_state *plane_state)
1570 struct drm_crtc *crtc = &pipe->crtc;
1571 struct drm_device *dev = crtc->dev;
1572 struct mga_device *mdev = to_mga_device(dev);
1573 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1574 struct drm_framebuffer *fb = plane_state->fb;
1575 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
1576 struct drm_rect fullscreen = {
1583 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1584 mgag200_g200wb_hold_bmc(mdev);
1586 mgag200_set_format_regs(mdev, fb);
1587 mgag200_set_mode_regs(mdev, adjusted_mode);
1588 mgag200_crtc_set_plls(mdev, adjusted_mode->clock);
1590 if (mdev->type == G200_ER)
1591 mgag200_g200er_reset_tagfifo(mdev);
1593 if (IS_G200_SE(mdev))
1594 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb);
1595 else if (mdev->type == G200_EV)
1596 mgag200_g200ev_set_hiprilvl(mdev);
1598 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1599 mgag200_g200wb_release_bmc(mdev);
1601 mga_crtc_load_lut(crtc);
1602 mgag200_enable_display(mdev);
1604 mgag200_handle_damage(mdev, fb, &fullscreen, &shadow_plane_state->map[0]);
1608 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
1610 struct drm_crtc *crtc = &pipe->crtc;
1611 struct mga_device *mdev = to_mga_device(crtc->dev);
1613 mgag200_disable_display(mdev);
1617 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe,
1618 struct drm_plane_state *plane_state,
1619 struct drm_crtc_state *crtc_state)
1621 struct drm_plane *plane = plane_state->plane;
1622 struct drm_framebuffer *new_fb = plane_state->fb;
1623 struct drm_framebuffer *fb = NULL;
1629 fb = plane->state->fb;
1631 if (!fb || (fb->format != new_fb->format))
1632 crtc_state->mode_changed = true; /* update PLL settings */
1638 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
1639 struct drm_plane_state *old_state)
1641 struct drm_plane *plane = &pipe->plane;
1642 struct drm_device *dev = plane->dev;
1643 struct mga_device *mdev = to_mga_device(dev);
1644 struct drm_plane_state *state = plane->state;
1645 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);
1646 struct drm_framebuffer *fb = state->fb;
1647 struct drm_rect damage;
1652 if (drm_atomic_helper_damage_merged(old_state, state, &damage))
1653 mgag200_handle_damage(mdev, fb, &damage, &shadow_plane_state->map[0]);
1656 static const struct drm_simple_display_pipe_funcs
1657 mgag200_simple_display_pipe_funcs = {
1658 .mode_valid = mgag200_simple_display_pipe_mode_valid,
1659 .enable = mgag200_simple_display_pipe_enable,
1660 .disable = mgag200_simple_display_pipe_disable,
1661 .check = mgag200_simple_display_pipe_check,
1662 .update = mgag200_simple_display_pipe_update,
1663 DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS,
1666 static const uint32_t mgag200_simple_display_pipe_formats[] = {
1667 DRM_FORMAT_XRGB8888,
1672 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = {
1673 DRM_FORMAT_MOD_LINEAR,
1674 DRM_FORMAT_MOD_INVALID
1681 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
1682 .fb_create = drm_gem_fb_create_with_dirty,
1683 .atomic_check = drm_atomic_helper_check,
1684 .atomic_commit = drm_atomic_helper_commit,
1687 static unsigned int mgag200_preferred_depth(struct mga_device *mdev)
1689 if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024))
1695 int mgag200_modeset_init(struct mga_device *mdev)
1697 struct drm_device *dev = &mdev->base;
1698 struct drm_connector *connector = &mdev->connector.base;
1699 struct drm_simple_display_pipe *pipe = &mdev->display_pipe;
1700 size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats);
1703 mgag200_init_regs(mdev);
1705 ret = drmm_mode_config_init(dev);
1707 drm_err(dev, "drmm_mode_config_init() failed, error %d\n",
1712 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1713 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1715 dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev);
1717 dev->mode_config.fb_base = mdev->mc.vram_base;
1719 dev->mode_config.funcs = &mgag200_mode_config_funcs;
1721 ret = mgag200_vga_connector_init(mdev);
1724 "mgag200_vga_connector_init() failed, error %d\n",
1729 ret = drm_simple_display_pipe_init(dev, pipe,
1730 &mgag200_simple_display_pipe_funcs,
1731 mgag200_simple_display_pipe_formats,
1733 mgag200_simple_display_pipe_fmtmods,
1737 "drm_simple_display_pipe_init() failed, error %d\n",
1742 /* FIXME: legacy gamma tables; convert to CRTC state */
1743 drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE);
1745 drm_mode_config_reset(dev);