drivers/gpu/drm/mgag200/mgag200_mode.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2010 Matt Turner.
   4  * Copyright 2012 Red Hat
   5  *
   6  * Authors: Matthew Garrett
   7  *          Matt Turner
   8  *          Dave Airlie
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/dma-buf-map.h>
  13
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_atomic_state_helper.h>
  16 #include <drm/drm_crtc_helper.h>
  17 #include <drm/drm_damage_helper.h>
  18 #include <drm/drm_format_helper.h>
  19 #include <drm/drm_fourcc.h>
  20 #include <drm/drm_gem_atomic_helper.h>
  21 #include <drm/drm_gem_framebuffer_helper.h>
  22 #include <drm/drm_plane_helper.h>
  23 #include <drm/drm_print.h>
  24 #include <drm/drm_probe_helper.h>
  25 #include <drm/drm_simple_kms_helper.h>
  26
  27 #include "mgag200_drv.h"
  28
  29 #define MGAG200_LUT_SIZE 256
  30
  31 /*
  32  * This file contains setup code for the CRTC.
  33  */
  34
  35 static void mga_crtc_load_lut(struct drm_crtc *crtc)
  36 {
  37         struct drm_device *dev = crtc->dev;
  38         struct mga_device *mdev = to_mga_device(dev);
  39         struct drm_framebuffer *fb;
  40         u16 *r_ptr, *g_ptr, *b_ptr;
  41         int i;
  42
  43         if (!crtc->enabled)
  44                 return;
  45
  46         if (!mdev->display_pipe.plane.state)
  47                 return;
  48
  49         fb = mdev->display_pipe.plane.state->fb;
  50
  51         r_ptr = crtc->gamma_store;
  52         g_ptr = r_ptr + crtc->gamma_size;
  53         b_ptr = g_ptr + crtc->gamma_size;
  54
  55         WREG8(DAC_INDEX + MGA1064_INDEX, 0);
  56
  57         if (fb && fb->format->cpp[0] * 8 == 16) {
  58                 int inc = (fb->format->depth == 15) ? 8 : 4;
  59                 u8 r, b;
  60                 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
  61                         if (fb->format->depth == 16) {
  62                                 if (i > (MGAG200_LUT_SIZE >> 1)) {
  63                                         r = b = 0;
  64                                 } else {
  65                                         r = *r_ptr++ >> 8;
  66                                         b = *b_ptr++ >> 8;
  67                                         r_ptr++;
  68                                         b_ptr++;
  69                                 }
  70                         } else {
  71                                 r = *r_ptr++ >> 8;
  72                                 b = *b_ptr++ >> 8;
  73                         }
  74                         /* VGA registers */
  75                         WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
  76                         WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
  77                         WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
  78                 }
  79                 return;
  80         }
  81         for (i = 0; i < MGAG200_LUT_SIZE; i++) {
  82                 /* VGA registers */
  83                 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8);
  84                 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8);
  85                 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8);
  86         }
  87 }
  88
  89 static inline void mga_wait_vsync(struct mga_device *mdev)
  90 {
  91         unsigned long timeout = jiffies + HZ/10;
  92         unsigned int status = 0;
  93
  94         do {
  95                 status = RREG32(MGAREG_Status);
  96         } while ((status & 0x08) && time_before(jiffies, timeout));
  97         timeout = jiffies + HZ/10;
  98         status = 0;
  99         do {
 100                 status = RREG32(MGAREG_Status);
 101         } while (!(status & 0x08) && time_before(jiffies, timeout));
 102 }
 103
 104 static inline void mga_wait_busy(struct mga_device *mdev)
 105 {
 106         unsigned long timeout = jiffies + HZ;
 107         unsigned int status = 0;
 108         do {
 109                 status = RREG8(MGAREG_Status + 2);
 110         } while ((status & 0x01) && time_before(jiffies, timeout));
 111 }
 112
 113 /*
 114  * PLL setup
 115  */
 116
 117 static int mgag200_g200_set_plls(struct mga_device *mdev, long clock)
 118 {
 119         struct drm_device *dev = &mdev->base;
 120         const int post_div_max = 7;
 121         const int in_div_min = 1;
 122         const int in_div_max = 6;
 123         const int feed_div_min = 7;
 124         const int feed_div_max = 127;
 125         u8 testm, testn;
 126         u8 n = 0, m = 0, p, s;
 127         long f_vco;
 128         long computed;
 129         long delta, tmp_delta;
 130         long ref_clk = mdev->model.g200.ref_clk;
 131         long p_clk_min = mdev->model.g200.pclk_min;
 132         long p_clk_max =  mdev->model.g200.pclk_max;
 133
 134         if (clock > p_clk_max) {
 135                 drm_err(dev, "Pixel Clock %ld too high\n", clock);
 136                 return 1;
 137         }
 138
 139         if (clock < p_clk_min >> 3)
 140                 clock = p_clk_min >> 3;
 141
 142         f_vco = clock;
 143         for (p = 0;
 144              p <= post_div_max && f_vco < p_clk_min;
 145              p = (p << 1) + 1, f_vco <<= 1)
 146                 ;
 147
 148         delta = clock;
 149
 150         for (testm = in_div_min; testm <= in_div_max; testm++) {
 151                 for (testn = feed_div_min; testn <= feed_div_max; testn++) {
 152                         computed = ref_clk * (testn + 1) / (testm + 1);
 153                         if (computed < f_vco)
 154                                 tmp_delta = f_vco - computed;
 155                         else
 156                                 tmp_delta = computed - f_vco;
 157                         if (tmp_delta < delta) {
 158                                 delta = tmp_delta;
 159                                 m = testm;
 160                                 n = testn;
 161                         }
 162                 }
 163         }
 164         f_vco = ref_clk * (n + 1) / (m + 1);
 165         if (f_vco < 100000)
 166                 s = 0;
 167         else if (f_vco < 140000)
 168                 s = 1;
 169         else if (f_vco < 180000)
 170                 s = 2;
 171         else
 172                 s = 3;
 173
 174         drm_dbg_kms(dev, "clock: %ld vco: %ld m: %d n: %d p: %d s: %d\n",
 175                     clock, f_vco, m, n, p, s);
 176
 177         WREG_DAC(MGA1064_PIX_PLLC_M, m);
 178         WREG_DAC(MGA1064_PIX_PLLC_N, n);
 179         WREG_DAC(MGA1064_PIX_PLLC_P, (p | (s << 3)));
 180
 181         return 0;
 182 }
 183
 184 #define P_ARRAY_SIZE 9
 185
 186 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
 187 {
 188         u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
 189         unsigned int vcomax, vcomin, pllreffreq;
 190         unsigned int delta, tmpdelta, permitteddelta;
 191         unsigned int testp, testm, testn;
 192         unsigned int p, m, n;
 193         unsigned int computed;
 194         unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
 195         unsigned int fvv;
 196         unsigned int i;
 197
 198         if (unique_rev_id <= 0x03) {
 199
 200                 m = n = p = 0;
 201                 vcomax = 320000;
 202                 vcomin = 160000;
 203                 pllreffreq = 25000;
 204
 205                 delta = 0xffffffff;
 206                 permitteddelta = clock * 5 / 1000;
 207
 208                 for (testp = 8; testp > 0; testp /= 2) {
 209                         if (clock * testp > vcomax)
 210                                 continue;
 211                         if (clock * testp < vcomin)
 212                                 continue;
 213
 214                         for (testn = 17; testn < 256; testn++) {
 215                                 for (testm = 1; testm < 32; testm++) {
 216                                         computed = (pllreffreq * testn) /
 217                                                 (testm * testp);
 218                                         if (computed > clock)
 219                                                 tmpdelta = computed - clock;
 220                                         else
 221                                                 tmpdelta = clock - computed;
 222                                         if (tmpdelta < delta) {
 223                                                 delta = tmpdelta;
 224                                                 m = testm - 1;
 225                                                 n = testn - 1;
 226                                                 p = testp - 1;
 227                                         }
 228                                 }
 229                         }
 230                 }
 231         } else {
 232
 233
 234                 m = n = p = 0;
 235                 vcomax        = 1600000;
 236                 vcomin        = 800000;
 237                 pllreffreq    = 25000;
 238
 239                 if (clock < 25000)
 240                         clock = 25000;
 241
 242                 clock = clock * 2;
 243
 244                 delta = 0xFFFFFFFF;
 245                 /* Permited delta is 0.5% as VESA Specification */
 246                 permitteddelta = clock * 5 / 1000;
 247
 248                 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
 249                         testp = pvalues_e4[i];
 250
 251                         if ((clock * testp) > vcomax)
 252                                 continue;
 253                         if ((clock * testp) < vcomin)
 254                                 continue;
 255
 256                         for (testn = 50; testn <= 256; testn++) {
 257                                 for (testm = 1; testm <= 32; testm++) {
 258                                         computed = (pllreffreq * testn) /
 259                                                 (testm * testp);
 260                                         if (computed > clock)
 261                                                 tmpdelta = computed - clock;
 262                                         else
 263                                                 tmpdelta = clock - computed;
 264
 265                                         if (tmpdelta < delta) {
 266                                                 delta = tmpdelta;
 267                                                 m = testm - 1;
 268                                                 n = testn - 1;
 269                                                 p = testp - 1;
 270                                         }
 271                                 }
 272                         }
 273                 }
 274
 275                 fvv = pllreffreq * (n + 1) / (m + 1);
 276                 fvv = (fvv - 800000) / 50000;
 277
 278                 if (fvv > 15)
 279                         fvv = 15;
 280
 281                 p |= (fvv << 4);
 282                 m |= 0x80;
 283
 284                 clock = clock / 2;
 285         }
 286
 287         if (delta > permitteddelta) {
 288                 pr_warn("PLL delta too large\n");
 289                 return 1;
 290         }
 291
 292         WREG_DAC(MGA1064_PIX_PLLC_M, m);
 293         WREG_DAC(MGA1064_PIX_PLLC_N, n);
 294         WREG_DAC(MGA1064_PIX_PLLC_P, p);
 295
 296         if (unique_rev_id >= 0x04) {
 297                 WREG_DAC(0x1a, 0x09);
 298                 msleep(20);
 299                 WREG_DAC(0x1a, 0x01);
 300
 301         }
 302
 303         return 0;
 304 }
 305
 306 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
 307 {
 308         unsigned int vcomax, vcomin, pllreffreq;
 309         unsigned int delta, tmpdelta;
 310         unsigned int testp, testm, testn, testp2;
 311         unsigned int p, m, n;
 312         unsigned int computed;
 313         int i, j, tmpcount, vcount;
 314         bool pll_locked = false;
 315         u8 tmp;
 316
 317         m = n = p = 0;
 318
 319         delta = 0xffffffff;
 320
 321         if (mdev->type == G200_EW3) {
 322
 323                 vcomax = 800000;
 324                 vcomin = 400000;
 325                 pllreffreq = 25000;
 326
 327                 for (testp = 1; testp < 8; testp++) {
 328                         for (testp2 = 1; testp2 < 8; testp2++) {
 329                                 if (testp < testp2)
 330                                         continue;
 331                                 if ((clock * testp * testp2) > vcomax)
 332                                         continue;
 333                                 if ((clock * testp * testp2) < vcomin)
 334                                         continue;
 335                                 for (testm = 1; testm < 26; testm++) {
 336                                         for (testn = 32; testn < 2048 ; testn++) {
 337                                                 computed = (pllreffreq * testn) /
 338                                                         (testm * testp * testp2);
 339                                                 if (computed > clock)
 340                                                         tmpdelta = computed - clock;
 341                                                 else
 342                                                         tmpdelta = clock - computed;
 343                                                 if (tmpdelta < delta) {
 344                                                         delta = tmpdelta;
 345                                                         m = ((testn & 0x100) >> 1) |
 346                                                                 (testm);
 347                                                         n = (testn & 0xFF);
 348                                                         p = ((testn & 0x600) >> 3) |
 349                                                                 (testp2 << 3) |
 350                                                                 (testp);
 351                                                 }
 352                                         }
 353                                 }
 354                         }
 355                 }
 356         } else {
 357
 358                 vcomax = 550000;
 359                 vcomin = 150000;
 360                 pllreffreq = 48000;
 361
 362                 for (testp = 1; testp < 9; testp++) {
 363                         if (clock * testp > vcomax)
 364                                 continue;
 365                         if (clock * testp < vcomin)
 366                                 continue;
 367
 368                         for (testm = 1; testm < 17; testm++) {
 369                                 for (testn = 1; testn < 151; testn++) {
 370                                         computed = (pllreffreq * testn) /
 371                                                 (testm * testp);
 372                                         if (computed > clock)
 373                                                 tmpdelta = computed - clock;
 374                                         else
 375                                                 tmpdelta = clock - computed;
 376                                         if (tmpdelta < delta) {
 377                                                 delta = tmpdelta;
 378                                                 n = testn - 1;
 379                                                 m = (testm - 1) |
 380                                                         ((n >> 1) & 0x80);
 381                                                 p = testp - 1;
 382                                         }
 383                                 }
 384                         }
 385                 }
 386         }
 387
 388         for (i = 0; i <= 32 && pll_locked == false; i++) {
 389                 if (i > 0) {
 390                         WREG8(MGAREG_CRTC_INDEX, 0x1e);
 391                         tmp = RREG8(MGAREG_CRTC_DATA);
 392                         if (tmp < 0xff)
 393                                 WREG8(MGAREG_CRTC_DATA, tmp+1);
 394                 }
 395
 396                 /* set pixclkdis to 1 */
 397                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 398                 tmp = RREG8(DAC_DATA);
 399                 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
 400                 WREG8(DAC_DATA, tmp);
 401
 402                 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
 403                 tmp = RREG8(DAC_DATA);
 404                 tmp |= MGA1064_REMHEADCTL_CLKDIS;
 405                 WREG8(DAC_DATA, tmp);
 406
 407                 /* select PLL Set C */
 408                 tmp = RREG8(MGAREG_MEM_MISC_READ);
 409                 tmp |= 0x3 << 2;
 410                 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 411
 412                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 413                 tmp = RREG8(DAC_DATA);
 414                 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
 415                 WREG8(DAC_DATA, tmp);
 416
 417                 udelay(500);
 418
 419                 /* reset the PLL */
 420                 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
 421                 tmp = RREG8(DAC_DATA);
 422                 tmp &= ~0x04;
 423                 WREG8(DAC_DATA, tmp);
 424
 425                 udelay(50);
 426
 427                 /* program pixel pll register */
 428                 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
 429                 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
 430                 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
 431
 432                 udelay(50);
 433
 434                 /* turn pll on */
 435                 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
 436                 tmp = RREG8(DAC_DATA);
 437                 tmp |= 0x04;
 438                 WREG_DAC(MGA1064_VREF_CTL, tmp);
 439
 440                 udelay(500);
 441
 442                 /* select the pixel pll */
 443                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 444                 tmp = RREG8(DAC_DATA);
 445                 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
 446                 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
 447                 WREG8(DAC_DATA, tmp);
 448
 449                 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
 450                 tmp = RREG8(DAC_DATA);
 451                 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
 452                 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
 453                 WREG8(DAC_DATA, tmp);
 454
 455                 /* reset dotclock rate bit */
 456                 WREG8(MGAREG_SEQ_INDEX, 1);
 457                 tmp = RREG8(MGAREG_SEQ_DATA);
 458                 tmp &= ~0x8;
 459                 WREG8(MGAREG_SEQ_DATA, tmp);
 460
 461                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 462                 tmp = RREG8(DAC_DATA);
 463                 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
 464                 WREG8(DAC_DATA, tmp);
 465
 466                 vcount = RREG8(MGAREG_VCOUNT);
 467
 468                 for (j = 0; j < 30 && pll_locked == false; j++) {
 469                         tmpcount = RREG8(MGAREG_VCOUNT);
 470                         if (tmpcount < vcount)
 471                                 vcount = 0;
 472                         if ((tmpcount - vcount) > 2)
 473                                 pll_locked = true;
 474                         else
 475                                 udelay(5);
 476                 }
 477         }
 478         WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
 479         tmp = RREG8(DAC_DATA);
 480         tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
 481         WREG_DAC(MGA1064_REMHEADCTL, tmp);
 482         return 0;
 483 }
 484
 485 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
 486 {
 487         unsigned int vcomax, vcomin, pllreffreq;
 488         unsigned int delta, tmpdelta;
 489         unsigned int testp, testm, testn;
 490         unsigned int p, m, n;
 491         unsigned int computed;
 492         u8 tmp;
 493
 494         m = n = p = 0;
 495         vcomax = 550000;
 496         vcomin = 150000;
 497         pllreffreq = 50000;
 498
 499         delta = 0xffffffff;
 500
 501         for (testp = 16; testp > 0; testp--) {
 502                 if (clock * testp > vcomax)
 503                         continue;
 504                 if (clock * testp < vcomin)
 505                         continue;
 506
 507                 for (testn = 1; testn < 257; testn++) {
 508                         for (testm = 1; testm < 17; testm++) {
 509                                 computed = (pllreffreq * testn) /
 510                                         (testm * testp);
 511                                 if (computed > clock)
 512                                         tmpdelta = computed - clock;
 513                                 else
 514                                         tmpdelta = clock - computed;
 515                                 if (tmpdelta < delta) {
 516                                         delta = tmpdelta;
 517                                         n = testn - 1;
 518                                         m = testm - 1;
 519                                         p = testp - 1;
 520                                 }
 521                         }
 522                 }
 523         }
 524
 525         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 526         tmp = RREG8(DAC_DATA);
 527         tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
 528         WREG8(DAC_DATA, tmp);
 529
 530         tmp = RREG8(MGAREG_MEM_MISC_READ);
 531         tmp |= 0x3 << 2;
 532         WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 533
 534         WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
 535         tmp = RREG8(DAC_DATA);
 536         WREG8(DAC_DATA, tmp & ~0x40);
 537
 538         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 539         tmp = RREG8(DAC_DATA);
 540         tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 541         WREG8(DAC_DATA, tmp);
 542
 543         WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
 544         WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
 545         WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
 546
 547         udelay(50);
 548
 549         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 550         tmp = RREG8(DAC_DATA);
 551         tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 552         WREG8(DAC_DATA, tmp);
 553
 554         udelay(500);
 555
 556         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 557         tmp = RREG8(DAC_DATA);
 558         tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
 559         tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
 560         WREG8(DAC_DATA, tmp);
 561
 562         WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
 563         tmp = RREG8(DAC_DATA);
 564         WREG8(DAC_DATA, tmp | 0x40);
 565
 566         tmp = RREG8(MGAREG_MEM_MISC_READ);
 567         tmp |= (0x3 << 2);
 568         WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 569
 570         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 571         tmp = RREG8(DAC_DATA);
 572         tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
 573         WREG8(DAC_DATA, tmp);
 574
 575         return 0;
 576 }
 577
 578 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
 579 {
 580         unsigned int vcomax, vcomin, pllreffreq;
 581         unsigned int delta, tmpdelta;
 582         unsigned int testp, testm, testn;
 583         unsigned int p, m, n;
 584         unsigned int computed;
 585         int i, j, tmpcount, vcount;
 586         u8 tmp;
 587         bool pll_locked = false;
 588
 589         m = n = p = 0;
 590
 591         if (mdev->type == G200_EH3) {
 592                 vcomax = 3000000;
 593                 vcomin = 1500000;
 594                 pllreffreq = 25000;
 595
 596                 delta = 0xffffffff;
 597
 598                 testp = 0;
 599
 600                 for (testm = 150; testm >= 6; testm--) {
 601                         if (clock * testm > vcomax)
 602                                 continue;
 603                         if (clock * testm < vcomin)
 604                                 continue;
 605                         for (testn = 120; testn >= 60; testn--) {
 606                                 computed = (pllreffreq * testn) / testm;
 607                                 if (computed > clock)
 608                                         tmpdelta = computed - clock;
 609                                 else
 610                                         tmpdelta = clock - computed;
 611                                 if (tmpdelta < delta) {
 612                                         delta = tmpdelta;
 613                                         n = testn;
 614                                         m = testm;
 615                                         p = testp;
 616                                 }
 617                                 if (delta == 0)
 618                                         break;
 619                         }
 620                         if (delta == 0)
 621                                 break;
 622                 }
 623         } else {
 624
 625                 vcomax = 800000;
 626                 vcomin = 400000;
 627                 pllreffreq = 33333;
 628
 629                 delta = 0xffffffff;
 630
 631                 for (testp = 16; testp > 0; testp >>= 1) {
 632                         if (clock * testp > vcomax)
 633                                 continue;
 634                         if (clock * testp < vcomin)
 635                                 continue;
 636
 637                         for (testm = 1; testm < 33; testm++) {
 638                                 for (testn = 17; testn < 257; testn++) {
 639                                         computed = (pllreffreq * testn) /
 640                                                 (testm * testp);
 641                                         if (computed > clock)
 642                                                 tmpdelta = computed - clock;
 643                                         else
 644                                                 tmpdelta = clock - computed;
 645                                         if (tmpdelta < delta) {
 646                                                 delta = tmpdelta;
 647                                                 n = testn - 1;
 648                                                 m = (testm - 1);
 649                                                 p = testp - 1;
 650                                         }
 651                                         if ((clock * testp) >= 600000)
 652                                                 p |= 0x80;
 653                                 }
 654                         }
 655                 }
 656         }
 657         for (i = 0; i <= 32 && pll_locked == false; i++) {
 658                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 659                 tmp = RREG8(DAC_DATA);
 660                 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
 661                 WREG8(DAC_DATA, tmp);
 662
 663                 tmp = RREG8(MGAREG_MEM_MISC_READ);
 664                 tmp |= 0x3 << 2;
 665                 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 666
 667                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 668                 tmp = RREG8(DAC_DATA);
 669                 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 670                 WREG8(DAC_DATA, tmp);
 671
 672                 udelay(500);
 673
 674                 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
 675                 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
 676                 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
 677
 678                 udelay(500);
 679
 680                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 681                 tmp = RREG8(DAC_DATA);
 682                 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
 683                 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
 684                 WREG8(DAC_DATA, tmp);
 685
 686                 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 687                 tmp = RREG8(DAC_DATA);
 688                 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
 689                 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 690                 WREG8(DAC_DATA, tmp);
 691
 692                 vcount = RREG8(MGAREG_VCOUNT);
 693
 694                 for (j = 0; j < 30 && pll_locked == false; j++) {
 695                         tmpcount = RREG8(MGAREG_VCOUNT);
 696                         if (tmpcount < vcount)
 697                                 vcount = 0;
 698                         if ((tmpcount - vcount) > 2)
 699                                 pll_locked = true;
 700                         else
 701                                 udelay(5);
 702                 }
 703         }
 704
 705         return 0;
 706 }
 707
 708 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
 709 {
 710         static const unsigned int m_div_val[] = { 1, 2, 4, 8 };
 711         unsigned int vcomax, vcomin, pllreffreq;
 712         unsigned int delta, tmpdelta;
 713         int testr, testn, testm, testo;
 714         unsigned int p, m, n;
 715         unsigned int computed, vco;
 716         int tmp;
 717
 718         m = n = p = 0;
 719         vcomax = 1488000;
 720         vcomin = 1056000;
 721         pllreffreq = 48000;
 722
 723         delta = 0xffffffff;
 724
 725         for (testr = 0; testr < 4; testr++) {
 726                 if (delta == 0)
 727                         break;
 728                 for (testn = 5; testn < 129; testn++) {
 729                         if (delta == 0)
 730                                 break;
 731                         for (testm = 3; testm >= 0; testm--) {
 732                                 if (delta == 0)
 733                                         break;
 734                                 for (testo = 5; testo < 33; testo++) {
 735                                         vco = pllreffreq * (testn + 1) /
 736                                                 (testr + 1);
 737                                         if (vco < vcomin)
 738                                                 continue;
 739                                         if (vco > vcomax)
 740                                                 continue;
 741                                         computed = vco / (m_div_val[testm] * (testo + 1));
 742                                         if (computed > clock)
 743                                                 tmpdelta = computed - clock;
 744                                         else
 745                                                 tmpdelta = clock - computed;
 746                                         if (tmpdelta < delta) {
 747                                                 delta = tmpdelta;
 748                                                 m = testm | (testo << 3);
 749                                                 n = testn;
 750                                                 p = testr | (testr << 3);
 751                                         }
 752                                 }
 753                         }
 754                 }
 755         }
 756
 757         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 758         tmp = RREG8(DAC_DATA);
 759         tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
 760         WREG8(DAC_DATA, tmp);
 761
 762         WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
 763         tmp = RREG8(DAC_DATA);
 764         tmp |= MGA1064_REMHEADCTL_CLKDIS;
 765         WREG8(DAC_DATA, tmp);
 766
 767         tmp = RREG8(MGAREG_MEM_MISC_READ);
 768         tmp |= (0x3<<2) | 0xc0;
 769         WREG8(MGAREG_MEM_MISC_WRITE, tmp);
 770
 771         WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
 772         tmp = RREG8(DAC_DATA);
 773         tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
 774         tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
 775         WREG8(DAC_DATA, tmp);
 776
 777         udelay(500);
 778
 779         WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
 780         WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
 781         WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
 782
 783         udelay(50);
 784
 785         return 0;
 786 }
 787
 788 static int mgag200_crtc_set_plls(struct mga_device *mdev, long clock)
 789 {
 790         u8 misc;
 791
 792         switch(mdev->type) {
 793         case G200_PCI:
 794         case G200_AGP:
 795                 return mgag200_g200_set_plls(mdev, clock);
 796         case G200_SE_A:
 797         case G200_SE_B:
 798                 return mga_g200se_set_plls(mdev, clock);
 799         case G200_WB:
 800         case G200_EW3:
 801                 return mga_g200wb_set_plls(mdev, clock);
 802         case G200_EV:
 803                 return mga_g200ev_set_plls(mdev, clock);
 804         case G200_EH:
 805         case G200_EH3:
 806                 return mga_g200eh_set_plls(mdev, clock);
 807         case G200_ER:
 808                 return mga_g200er_set_plls(mdev, clock);
 809         }
 810
 811         misc = RREG8(MGA_MISC_IN);
 812         misc &= ~MGAREG_MISC_CLK_SEL_MASK;
 813         misc |= MGAREG_MISC_CLK_SEL_MGA_MSK;
 814         WREG8(MGA_MISC_OUT, misc);
 815
 816         return 0;
 817 }
 818
 819 static void mgag200_g200wb_hold_bmc(struct mga_device *mdev)
 820 {
 821         u8 tmp;
 822         int iter_max;
 823
 824         /* 1- The first step is to warn the BMC of an upcoming mode change.
 825          * We are putting the misc<0> to output.*/
 826
 827         WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
 828         tmp = RREG8(DAC_DATA);
 829         tmp |= 0x10;
 830         WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
 831
 832         /* we are putting a 1 on the misc<0> line */
 833         WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
 834         tmp = RREG8(DAC_DATA);
 835         tmp |= 0x10;
 836         WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
 837
 838         /* 2- Second step to mask and further scan request
 839          * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
 840          */
 841         WREG8(DAC_INDEX, MGA1064_SPAREREG);
 842         tmp = RREG8(DAC_DATA);
 843         tmp |= 0x80;
 844         WREG_DAC(MGA1064_SPAREREG, tmp);
 845
 846         /* 3a- the third step is to verifu if there is an active scan
 847          * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
 848          */
 849         iter_max = 300;
 850         while (!(tmp & 0x1) && iter_max) {
 851                 WREG8(DAC_INDEX, MGA1064_SPAREREG);
 852                 tmp = RREG8(DAC_DATA);
 853                 udelay(1000);
 854                 iter_max--;
 855         }
 856
 857         /* 3b- this step occurs only if the remove is actually scanning
 858          * we are waiting for the end of the frame which is a 1 on
 859          * remvsyncsts (XSPAREREG<1>)
 860          */
 861         if (iter_max) {
 862                 iter_max = 300;
 863                 while ((tmp & 0x2) && iter_max) {
 864                         WREG8(DAC_INDEX, MGA1064_SPAREREG);
 865                         tmp = RREG8(DAC_DATA);
 866                         udelay(1000);
 867                         iter_max--;
 868                 }
 869         }
 870 }
 871
 872 static void mgag200_g200wb_release_bmc(struct mga_device *mdev)
 873 {
 874         u8 tmp;
 875
 876         /* 1- The first step is to ensure that the vrsten and hrsten are set */
 877         WREG8(MGAREG_CRTCEXT_INDEX, 1);
 878         tmp = RREG8(MGAREG_CRTCEXT_DATA);
 879         WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
 880
 881         /* 2- second step is to assert the rstlvl2 */
 882         WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
 883         tmp = RREG8(DAC_DATA);
 884         tmp |= 0x8;
 885         WREG8(DAC_DATA, tmp);
 886
 887         /* wait 10 us */
 888         udelay(10);
 889
 890         /* 3- deassert rstlvl2 */
 891         tmp &= ~0x08;
 892         WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
 893         WREG8(DAC_DATA, tmp);
 894
 895         /* 4- remove mask of scan request */
 896         WREG8(DAC_INDEX, MGA1064_SPAREREG);
 897         tmp = RREG8(DAC_DATA);
 898         tmp &= ~0x80;
 899         WREG8(DAC_DATA, tmp);
 900
 901         /* 5- put back a 0 on the misc<0> line */
 902         WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
 903         tmp = RREG8(DAC_DATA);
 904         tmp &= ~0x10;
 905         WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
 906 }
 907
 908 /*
 909  * This is how the framebuffer base address is stored in g200 cards:
 910  *   * Assume @offset is the gpu_addr variable of the framebuffer object
 911  *   * Then addr is the number of _pixels_ (not bytes) from the start of
 912  *     VRAM to the first pixel we want to display. (divided by 2 for 32bit
 913  *     framebuffers)
 914  *   * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
 915  *      addr<20> -> CRTCEXT0<6>
 916  *      addr<19-16> -> CRTCEXT0<3-0>
 917  *      addr<15-8> -> CRTCC<7-0>
 918  *      addr<7-0> -> CRTCD<7-0>
 919  *
 920  *  CRTCEXT0 has to be programmed last to trigger an update and make the
 921  *  new addr variable take effect.
 922  */
 923 static void mgag200_set_startadd(struct mga_device *mdev,
 924                                  unsigned long offset)
 925 {
 926         struct drm_device *dev = &mdev->base;
 927         u32 startadd;
 928         u8 crtcc, crtcd, crtcext0;
 929
 930         startadd = offset / 8;
 931
 932         /*
 933          * Can't store addresses any higher than that, but we also
 934          * don't have more than 16 MiB of memory, so it should be fine.
 935          */
 936         drm_WARN_ON(dev, startadd > 0x1fffff);
 937
 938         RREG_ECRT(0x00, crtcext0);
 939
 940         crtcc = (startadd >> 8) & 0xff;
 941         crtcd = startadd & 0xff;
 942         crtcext0 &= 0xb0;
 943         crtcext0 |= ((startadd >> 14) & BIT(6)) |
 944                     ((startadd >> 16) & 0x0f);
 945
 946         WREG_CRT(0x0c, crtcc);
 947         WREG_CRT(0x0d, crtcd);
 948         WREG_ECRT(0x00, crtcext0);
 949 }
 950
 951 static void mgag200_set_dac_regs(struct mga_device *mdev)
 952 {
 953         size_t i;
 954         u8 dacvalue[] = {
 955                 /* 0x00: */        0,    0,    0,    0,    0,    0, 0x00,    0,
 956                 /* 0x08: */        0,    0,    0,    0,    0,    0,    0,    0,
 957                 /* 0x10: */        0,    0,    0,    0,    0,    0,    0,    0,
 958                 /* 0x18: */     0x00,    0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
 959                 /* 0x20: */     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 960                 /* 0x28: */     0x00, 0x00, 0x00, 0x00,    0,    0,    0, 0x40,
 961                 /* 0x30: */     0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
 962                 /* 0x38: */     0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
 963                 /* 0x40: */        0,    0,    0,    0,    0,    0,    0,    0,
 964                 /* 0x48: */        0,    0,    0,    0,    0,    0,    0,    0
 965         };
 966
 967         switch (mdev->type) {
 968         case G200_PCI:
 969         case G200_AGP:
 970                 dacvalue[MGA1064_SYS_PLL_M] = 0x04;
 971                 dacvalue[MGA1064_SYS_PLL_N] = 0x2D;
 972                 dacvalue[MGA1064_SYS_PLL_P] = 0x19;
 973                 break;
 974         case G200_SE_A:
 975         case G200_SE_B:
 976                 dacvalue[MGA1064_VREF_CTL] = 0x03;
 977                 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
 978                 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
 979                                              MGA1064_MISC_CTL_VGA8 |
 980                                              MGA1064_MISC_CTL_DAC_RAM_CS;
 981                 break;
 982         case G200_WB:
 983         case G200_EW3:
 984                 dacvalue[MGA1064_VREF_CTL] = 0x07;
 985                 break;
 986         case G200_EV:
 987                 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
 988                 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
 989                                              MGA1064_MISC_CTL_DAC_RAM_CS;
 990                 break;
 991         case G200_EH:
 992         case G200_EH3:
 993                 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
 994                                              MGA1064_MISC_CTL_DAC_RAM_CS;
 995                 break;
 996         case G200_ER:
 997                 break;
 998         }
 999
1000         for (i = 0; i < ARRAY_SIZE(dacvalue); i++) {
1001                 if ((i <= 0x17) ||
1002                     (i == 0x1b) ||
1003                     (i == 0x1c) ||
1004                     ((i >= 0x1f) && (i <= 0x29)) ||
1005                     ((i >= 0x30) && (i <= 0x37)))
1006                         continue;
1007                 if (IS_G200_SE(mdev) &&
1008                     ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
1009                         continue;
1010                 if ((mdev->type == G200_EV ||
1011                     mdev->type == G200_WB ||
1012                     mdev->type == G200_EH ||
1013                     mdev->type == G200_EW3 ||
1014                     mdev->type == G200_EH3) &&
1015                     (i >= 0x44) && (i <= 0x4e))
1016                         continue;
1017
1018                 WREG_DAC(i, dacvalue[i]);
1019         }
1020
1021         if (mdev->type == G200_ER)
1022                 WREG_DAC(0x90, 0);
1023 }
1024
1025 static void mgag200_init_regs(struct mga_device *mdev)
1026 {
1027         u8 crtc11, misc;
1028
1029         mgag200_set_dac_regs(mdev);
1030
1031         WREG_SEQ(2, 0x0f);
1032         WREG_SEQ(3, 0x00);
1033         WREG_SEQ(4, 0x0e);
1034
1035         WREG_CRT(10, 0);
1036         WREG_CRT(11, 0);
1037         WREG_CRT(12, 0);
1038         WREG_CRT(13, 0);
1039         WREG_CRT(14, 0);
1040         WREG_CRT(15, 0);
1041
1042         RREG_CRT(0x11, crtc11);
1043         crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT |
1044                     MGAREG_CRTC11_VINTEN |
1045                     MGAREG_CRTC11_VINTCLR);
1046         WREG_CRT(0x11, crtc11);
1047
1048         if (mdev->type == G200_ER)
1049                 WREG_ECRT(0x24, 0x5);
1050
1051         if (mdev->type == G200_EW3)
1052                 WREG_ECRT(0x34, 0x5);
1053
1054         misc = RREG8(MGA_MISC_IN);
1055         misc |= MGAREG_MISC_IOADSEL;
1056         WREG8(MGA_MISC_OUT, misc);
1057 }
1058
1059 static void mgag200_set_mode_regs(struct mga_device *mdev,
1060                                   const struct drm_display_mode *mode)
1061 {
1062         unsigned int hdisplay, hsyncstart, hsyncend, htotal;
1063         unsigned int vdisplay, vsyncstart, vsyncend, vtotal;
1064         u8 misc, crtcext1, crtcext2, crtcext5;
1065
1066         hdisplay = mode->hdisplay / 8 - 1;
1067         hsyncstart = mode->hsync_start / 8 - 1;
1068         hsyncend = mode->hsync_end / 8 - 1;
1069         htotal = mode->htotal / 8 - 1;
1070
1071         /* Work around hardware quirk */
1072         if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1073                 htotal++;
1074
1075         vdisplay = mode->vdisplay - 1;
1076         vsyncstart = mode->vsync_start - 1;
1077         vsyncend = mode->vsync_end - 1;
1078         vtotal = mode->vtotal - 2;
1079
1080         misc = RREG8(MGA_MISC_IN);
1081
1082         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1083                 misc |= MGAREG_MISC_HSYNCPOL;
1084         else
1085                 misc &= ~MGAREG_MISC_HSYNCPOL;
1086
1087         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1088                 misc |= MGAREG_MISC_VSYNCPOL;
1089         else
1090                 misc &= ~MGAREG_MISC_VSYNCPOL;
1091
1092         crtcext1 = (((htotal - 4) & 0x100) >> 8) |
1093                    ((hdisplay & 0x100) >> 7) |
1094                    ((hsyncstart & 0x100) >> 6) |
1095                     (htotal & 0x40);
1096         if (mdev->type == G200_WB || mdev->type == G200_EW3)
1097                 crtcext1 |= BIT(7) | /* vrsten */
1098                             BIT(3); /* hrsten */
1099
1100         crtcext2 = ((vtotal & 0xc00) >> 10) |
1101                    ((vdisplay & 0x400) >> 8) |
1102                    ((vdisplay & 0xc00) >> 7) |
1103                    ((vsyncstart & 0xc00) >> 5) |
1104                    ((vdisplay & 0x400) >> 3);
1105         crtcext5 = 0x00;
1106
1107         WREG_CRT(0, htotal - 4);
1108         WREG_CRT(1, hdisplay);
1109         WREG_CRT(2, hdisplay);
1110         WREG_CRT(3, (htotal & 0x1F) | 0x80);
1111         WREG_CRT(4, hsyncstart);
1112         WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1113         WREG_CRT(6, vtotal & 0xFF);
1114         WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1115                  ((vdisplay & 0x100) >> 7) |
1116                  ((vsyncstart & 0x100) >> 6) |
1117                  ((vdisplay & 0x100) >> 5) |
1118                  ((vdisplay & 0x100) >> 4) | /* linecomp */
1119                  ((vtotal & 0x200) >> 4) |
1120                  ((vdisplay & 0x200) >> 3) |
1121                  ((vsyncstart & 0x200) >> 2));
1122         WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1123                  ((vdisplay & 0x200) >> 3));
1124         WREG_CRT(16, vsyncstart & 0xFF);
1125         WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1126         WREG_CRT(18, vdisplay & 0xFF);
1127         WREG_CRT(20, 0);
1128         WREG_CRT(21, vdisplay & 0xFF);
1129         WREG_CRT(22, (vtotal + 1) & 0xFF);
1130         WREG_CRT(23, 0xc3);
1131         WREG_CRT(24, vdisplay & 0xFF);
1132
1133         WREG_ECRT(0x01, crtcext1);
1134         WREG_ECRT(0x02, crtcext2);
1135         WREG_ECRT(0x05, crtcext5);
1136
1137         WREG8(MGA_MISC_OUT, misc);
1138 }
1139
1140 static u8 mgag200_get_bpp_shift(struct mga_device *mdev,
1141                                 const struct drm_format_info *format)
1142 {
1143         return mdev->bpp_shifts[format->cpp[0] - 1];
1144 }
1145
1146 /*
1147  * Calculates the HW offset value from the framebuffer's pitch. The
1148  * offset is a multiple of the pixel size and depends on the display
1149  * format.
1150  */
1151 static u32 mgag200_calculate_offset(struct mga_device *mdev,
1152                                     const struct drm_framebuffer *fb)
1153 {
1154         u32 offset = fb->pitches[0] / fb->format->cpp[0];
1155         u8 bppshift = mgag200_get_bpp_shift(mdev, fb->format);
1156
1157         if (fb->format->cpp[0] * 8 == 24)
1158                 offset = (offset * 3) >> (4 - bppshift);
1159         else
1160                 offset = offset >> (4 - bppshift);
1161
1162         return offset;
1163 }
1164
1165 static void mgag200_set_offset(struct mga_device *mdev,
1166                                const struct drm_framebuffer *fb)
1167 {
1168         u8 crtc13, crtcext0;
1169         u32 offset = mgag200_calculate_offset(mdev, fb);
1170
1171         RREG_ECRT(0, crtcext0);
1172
1173         crtc13 = offset & 0xff;
1174
1175         crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK;
1176         crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK;
1177
1178         WREG_CRT(0x13, crtc13);
1179         WREG_ECRT(0x00, crtcext0);
1180 }
1181
1182 static void mgag200_set_format_regs(struct mga_device *mdev,
1183                                     const struct drm_framebuffer *fb)
1184 {
1185         struct drm_device *dev = &mdev->base;
1186         const struct drm_format_info *format = fb->format;
1187         unsigned int bpp, bppshift, scale;
1188         u8 crtcext3, xmulctrl;
1189
1190         bpp = format->cpp[0] * 8;
1191
1192         bppshift = mgag200_get_bpp_shift(mdev, format);
1193         switch (bpp) {
1194         case 24:
1195                 scale = ((1 << bppshift) * 3) - 1;
1196                 break;
1197         default:
1198                 scale = (1 << bppshift) - 1;
1199                 break;
1200         }
1201
1202         RREG_ECRT(3, crtcext3);
1203
1204         switch (bpp) {
1205         case 8:
1206                 xmulctrl = MGA1064_MUL_CTL_8bits;
1207                 break;
1208         case 16:
1209                 if (format->depth == 15)
1210                         xmulctrl = MGA1064_MUL_CTL_15bits;
1211                 else
1212                         xmulctrl = MGA1064_MUL_CTL_16bits;
1213                 break;
1214         case 24:
1215                 xmulctrl = MGA1064_MUL_CTL_24bits;
1216                 break;
1217         case 32:
1218                 xmulctrl = MGA1064_MUL_CTL_32_24bits;
1219                 break;
1220         default:
1221                 /* BUG: We should have caught this problem already. */
1222                 drm_WARN_ON(dev, "invalid format depth\n");
1223                 return;
1224         }
1225
1226         crtcext3 &= ~GENMASK(2, 0);
1227         crtcext3 |= scale;
1228
1229         WREG_DAC(MGA1064_MUL_CTL, xmulctrl);
1230
1231         WREG_GFX(0, 0x00);
1232         WREG_GFX(1, 0x00);
1233         WREG_GFX(2, 0x00);
1234         WREG_GFX(3, 0x00);
1235         WREG_GFX(4, 0x00);
1236         WREG_GFX(5, 0x40);
1237         WREG_GFX(6, 0x05);
1238         WREG_GFX(7, 0x0f);
1239         WREG_GFX(8, 0x0f);
1240
1241         WREG_ECRT(3, crtcext3);
1242 }
1243
1244 static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev)
1245 {
1246         static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */
1247         u32 memctl;
1248
1249         memctl = RREG32(MGAREG_MEMCTL);
1250
1251         memctl |= RESET_FLAG;
1252         WREG32(MGAREG_MEMCTL, memctl);
1253
1254         udelay(1000);
1255
1256         memctl &= ~RESET_FLAG;
1257         WREG32(MGAREG_MEMCTL, memctl);
1258 }
1259
1260 static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev,
1261                                         const struct drm_display_mode *mode,
1262                                         const struct drm_framebuffer *fb)
1263 {
1264         u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
1265         unsigned int hiprilvl;
1266         u8 crtcext6;
1267
1268         if  (unique_rev_id >= 0x04) {
1269                 hiprilvl = 0;
1270         } else if (unique_rev_id >= 0x02) {
1271                 unsigned int bpp;
1272                 unsigned long mb;
1273
1274                 if (fb->format->cpp[0] * 8 > 16)
1275                         bpp = 32;
1276                 else if (fb->format->cpp[0] * 8 > 8)
1277                         bpp = 16;
1278                 else
1279                         bpp = 8;
1280
1281                 mb = (mode->clock * bpp) / 1000;
1282                 if (mb > 3100)
1283                         hiprilvl = 0;
1284                 else if (mb > 2600)
1285                         hiprilvl = 1;
1286                 else if (mb > 1900)
1287                         hiprilvl = 2;
1288                 else if (mb > 1160)
1289                         hiprilvl = 3;
1290                 else if (mb > 440)
1291                         hiprilvl = 4;
1292                 else
1293                         hiprilvl = 5;
1294
1295         } else if (unique_rev_id >= 0x01) {
1296                 hiprilvl = 3;
1297         } else {
1298                 hiprilvl = 4;
1299         }
1300
1301         crtcext6 = hiprilvl; /* implicitly sets maxhipri to 0 */
1302
1303         WREG_ECRT(0x06, crtcext6);
1304 }
1305
1306 static void mgag200_g200ev_set_hiprilvl(struct mga_device *mdev)
1307 {
1308         WREG_ECRT(0x06, 0x00);
1309 }
1310
1311 static void mgag200_enable_display(struct mga_device *mdev)
1312 {
1313         u8 seq0, seq1, crtcext1;
1314
1315         RREG_SEQ(0x00, seq0);
1316         seq0 |= MGAREG_SEQ0_SYNCRST |
1317                 MGAREG_SEQ0_ASYNCRST;
1318         WREG_SEQ(0x00, seq0);
1319
1320         /*
1321          * TODO: replace busy waiting with vblank IRQ; put
1322          *       msleep(50) before changing SCROFF
1323          */
1324         mga_wait_vsync(mdev);
1325         mga_wait_busy(mdev);
1326
1327         RREG_SEQ(0x01, seq1);
1328         seq1 &= ~MGAREG_SEQ1_SCROFF;
1329         WREG_SEQ(0x01, seq1);
1330
1331         msleep(20);
1332
1333         RREG_ECRT(0x01, crtcext1);
1334         crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF;
1335         crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF;
1336         WREG_ECRT(0x01, crtcext1);
1337 }
1338
1339 static void mgag200_disable_display(struct mga_device *mdev)
1340 {
1341         u8 seq0, seq1, crtcext1;
1342
1343         RREG_SEQ(0x00, seq0);
1344         seq0 &= ~MGAREG_SEQ0_SYNCRST;
1345         WREG_SEQ(0x00, seq0);
1346
1347         /*
1348          * TODO: replace busy waiting with vblank IRQ; put
1349          *       msleep(50) before changing SCROFF
1350          */
1351         mga_wait_vsync(mdev);
1352         mga_wait_busy(mdev);
1353
1354         RREG_SEQ(0x01, seq1);
1355         seq1 |= MGAREG_SEQ1_SCROFF;
1356         WREG_SEQ(0x01, seq1);
1357
1358         msleep(20);
1359
1360         RREG_ECRT(0x01, crtcext1);
1361         crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF |
1362                     MGAREG_CRTCEXT1_HSYNCOFF;
1363         WREG_ECRT(0x01, crtcext1);
1364 }
1365
1366 /*
1367  * Connector
1368  */
1369
1370 static int mga_vga_get_modes(struct drm_connector *connector)
1371 {
1372         struct mga_connector *mga_connector = to_mga_connector(connector);
1373         struct edid *edid;
1374         int ret = 0;
1375
1376         edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1377         if (edid) {
1378                 drm_connector_update_edid_property(connector, edid);
1379                 ret = drm_add_edid_modes(connector, edid);
1380                 kfree(edid);
1381         }
1382         return ret;
1383 }
1384
1385 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1386                                                         int bits_per_pixel)
1387 {
1388         uint32_t total_area, divisor;
1389         uint64_t active_area, pixels_per_second, bandwidth;
1390         uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1391
1392         divisor = 1024;
1393
1394         if (!mode->htotal || !mode->vtotal || !mode->clock)
1395                 return 0;
1396
1397         active_area = mode->hdisplay * mode->vdisplay;
1398         total_area = mode->htotal * mode->vtotal;
1399
1400         pixels_per_second = active_area * mode->clock * 1000;
1401         do_div(pixels_per_second, total_area);
1402
1403         bandwidth = pixels_per_second * bytes_per_pixel * 100;
1404         do_div(bandwidth, divisor);
1405
1406         return (uint32_t)(bandwidth);
1407 }
1408
1409 #define MODE_BANDWIDTH  MODE_BAD
1410
1411 static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector,
1412                                  struct drm_display_mode *mode)
1413 {
1414         struct drm_device *dev = connector->dev;
1415         struct mga_device *mdev = to_mga_device(dev);
1416         int bpp = 32;
1417
1418         if (IS_G200_SE(mdev)) {
1419                 u32 unique_rev_id = mdev->model.g200se.unique_rev_id;
1420
1421                 if (unique_rev_id == 0x01) {
1422                         if (mode->hdisplay > 1600)
1423                                 return MODE_VIRTUAL_X;
1424                         if (mode->vdisplay > 1200)
1425                                 return MODE_VIRTUAL_Y;
1426                         if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1427                                 > (24400 * 1024))
1428                                 return MODE_BANDWIDTH;
1429                 } else if (unique_rev_id == 0x02) {
1430                         if (mode->hdisplay > 1920)
1431                                 return MODE_VIRTUAL_X;
1432                         if (mode->vdisplay > 1200)
1433                                 return MODE_VIRTUAL_Y;
1434                         if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1435                                 > (30100 * 1024))
1436                                 return MODE_BANDWIDTH;
1437                 } else {
1438                         if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1439                                 > (55000 * 1024))
1440                                 return MODE_BANDWIDTH;
1441                 }
1442         } else if (mdev->type == G200_WB) {
1443                 if (mode->hdisplay > 1280)
1444                         return MODE_VIRTUAL_X;
1445                 if (mode->vdisplay > 1024)
1446                         return MODE_VIRTUAL_Y;
1447                 if (mga_vga_calculate_mode_bandwidth(mode, bpp) >
1448                     (31877 * 1024))
1449                         return MODE_BANDWIDTH;
1450         } else if (mdev->type == G200_EV &&
1451                 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1452                         > (32700 * 1024))) {
1453                 return MODE_BANDWIDTH;
1454         } else if (mdev->type == G200_EH &&
1455                 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1456                         > (37500 * 1024))) {
1457                 return MODE_BANDWIDTH;
1458         } else if (mdev->type == G200_ER &&
1459                 (mga_vga_calculate_mode_bandwidth(mode,
1460                         bpp) > (55000 * 1024))) {
1461                 return MODE_BANDWIDTH;
1462         }
1463
1464         if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1465             (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1466                 return MODE_H_ILLEGAL;
1467         }
1468
1469         if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1470             mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1471             mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1472             mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1473                 return MODE_BAD;
1474         }
1475
1476         /* Validate the mode input by the user */
1477         if (connector->cmdline_mode.specified) {
1478                 if (connector->cmdline_mode.bpp_specified)
1479                         bpp = connector->cmdline_mode.bpp;
1480         }
1481
1482         if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->vram_fb_available) {
1483                 if (connector->cmdline_mode.specified)
1484                         connector->cmdline_mode.specified = false;
1485                 return MODE_BAD;
1486         }
1487
1488         return MODE_OK;
1489 }
1490
1491 static void mga_connector_destroy(struct drm_connector *connector)
1492 {
1493         struct mga_connector *mga_connector = to_mga_connector(connector);
1494         mgag200_i2c_destroy(mga_connector->i2c);
1495         drm_connector_cleanup(connector);
1496 }
1497
1498 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1499         .get_modes  = mga_vga_get_modes,
1500         .mode_valid = mga_vga_mode_valid,
1501 };
1502
1503 static const struct drm_connector_funcs mga_vga_connector_funcs = {
1504         .reset                  = drm_atomic_helper_connector_reset,
1505         .fill_modes             = drm_helper_probe_single_connector_modes,
1506         .destroy                = mga_connector_destroy,
1507         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1508         .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
1509 };
1510
1511 static int mgag200_vga_connector_init(struct mga_device *mdev)
1512 {
1513         struct drm_device *dev = &mdev->base;
1514         struct mga_connector *mconnector = &mdev->connector;
1515         struct drm_connector *connector = &mconnector->base;
1516         struct mga_i2c_chan *i2c;
1517         int ret;
1518
1519         i2c = mgag200_i2c_create(dev);
1520         if (!i2c)
1521                 drm_warn(dev, "failed to add DDC bus\n");
1522
1523         ret = drm_connector_init_with_ddc(dev, connector,
1524                                           &mga_vga_connector_funcs,
1525                                           DRM_MODE_CONNECTOR_VGA,
1526                                           &i2c->adapter);
1527         if (ret)
1528                 goto err_mgag200_i2c_destroy;
1529         drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1530
1531         mconnector->i2c = i2c;
1532
1533         return 0;
1534
1535 err_mgag200_i2c_destroy:
1536         mgag200_i2c_destroy(i2c);
1537         return ret;
1538 }
1539
1540 /*
1541  * Simple Display Pipe
1542  */
1543
1544 static enum drm_mode_status
1545 mgag200_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
1546                                        const struct drm_display_mode *mode)
1547 {
1548         return MODE_OK;
1549 }
1550
1551 static void
1552 mgag200_handle_damage(struct mga_device *mdev, struct drm_framebuffer *fb,
1553                       struct drm_rect *clip, const struct dma_buf_map *map)
1554 {
1555         void *vmap = map->vaddr; /* TODO: Use mapping abstraction properly */
1556
1557         drm_fb_memcpy_dstclip(mdev->vram, fb->pitches[0], vmap, fb, clip);
1558
1559         /* Always scanout image at VRAM offset 0 */
1560         mgag200_set_startadd(mdev, (u32)0);
1561         mgag200_set_offset(mdev, fb);
1562 }
1563
1564 static void
1565 mgag200_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
1566                                    struct drm_crtc_state *crtc_state,
1567                                    struct drm_plane_state *plane_state)
1568 {
1569         struct drm_crtc *crtc = &pipe->crtc;
1570         struct drm_device *dev = crtc->dev;
1571         struct mga_device *mdev = to_mga_device(dev);
1572         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1573         struct drm_framebuffer *fb = plane_state->fb;
1574         struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
1575         struct drm_rect fullscreen = {
1576                 .x1 = 0,
1577                 .x2 = fb->width,
1578                 .y1 = 0,
1579                 .y2 = fb->height,
1580         };
1581
1582         if (mdev->type == G200_WB || mdev->type == G200_EW3)
1583                 mgag200_g200wb_hold_bmc(mdev);
1584
1585         mgag200_set_format_regs(mdev, fb);
1586         mgag200_set_mode_regs(mdev, adjusted_mode);
1587         mgag200_crtc_set_plls(mdev, adjusted_mode->clock);
1588
1589         if (mdev->type == G200_ER)
1590                 mgag200_g200er_reset_tagfifo(mdev);
1591
1592         if (IS_G200_SE(mdev))
1593                 mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, fb);
1594         else if (mdev->type == G200_EV)
1595                 mgag200_g200ev_set_hiprilvl(mdev);
1596
1597         if (mdev->type == G200_WB || mdev->type == G200_EW3)
1598                 mgag200_g200wb_release_bmc(mdev);
1599
1600         mga_crtc_load_lut(crtc);
1601         mgag200_enable_display(mdev);
1602
1603         mgag200_handle_damage(mdev, fb, &fullscreen, &shadow_plane_state->map[0]);
1604 }
1605
1606 static void
1607 mgag200_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
1608 {
1609         struct drm_crtc *crtc = &pipe->crtc;
1610         struct mga_device *mdev = to_mga_device(crtc->dev);
1611
1612         mgag200_disable_display(mdev);
1613 }
1614
1615 static int
1616 mgag200_simple_display_pipe_check(struct drm_simple_display_pipe *pipe,
1617                                   struct drm_plane_state *plane_state,
1618                                   struct drm_crtc_state *crtc_state)
1619 {
1620         struct drm_plane *plane = plane_state->plane;
1621         struct drm_framebuffer *new_fb = plane_state->fb;
1622         struct drm_framebuffer *fb = NULL;
1623
1624         if (!new_fb)
1625                 return 0;
1626
1627         if (plane->state)
1628                 fb = plane->state->fb;
1629
1630         if (!fb || (fb->format != new_fb->format))
1631                 crtc_state->mode_changed = true; /* update PLL settings */
1632
1633         return 0;
1634 }
1635
1636 static void
1637 mgag200_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
1638                                    struct drm_plane_state *old_state)
1639 {
1640         struct drm_plane *plane = &pipe->plane;
1641         struct drm_device *dev = plane->dev;
1642         struct mga_device *mdev = to_mga_device(dev);
1643         struct drm_plane_state *state = plane->state;
1644         struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);
1645         struct drm_framebuffer *fb = state->fb;
1646         struct drm_rect damage;
1647
1648         if (!fb)
1649                 return;
1650
1651         if (drm_atomic_helper_damage_merged(old_state, state, &damage))
1652                 mgag200_handle_damage(mdev, fb, &damage, &shadow_plane_state->map[0]);
1653 }
1654
1655 static const struct drm_simple_display_pipe_funcs
1656 mgag200_simple_display_pipe_funcs = {
1657         .mode_valid = mgag200_simple_display_pipe_mode_valid,
1658         .enable     = mgag200_simple_display_pipe_enable,
1659         .disable    = mgag200_simple_display_pipe_disable,
1660         .check      = mgag200_simple_display_pipe_check,
1661         .update     = mgag200_simple_display_pipe_update,
1662         DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS,
1663 };
1664
1665 static const uint32_t mgag200_simple_display_pipe_formats[] = {
1666         DRM_FORMAT_XRGB8888,
1667         DRM_FORMAT_RGB565,
1668         DRM_FORMAT_RGB888,
1669 };
1670
1671 static const uint64_t mgag200_simple_display_pipe_fmtmods[] = {
1672         DRM_FORMAT_MOD_LINEAR,
1673         DRM_FORMAT_MOD_INVALID
1674 };
1675
1676 /*
1677  * Mode config
1678  */
1679
1680 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
1681         .fb_create     = drm_gem_fb_create_with_dirty,
1682         .atomic_check  = drm_atomic_helper_check,
1683         .atomic_commit = drm_atomic_helper_commit,
1684 };
1685
1686 static unsigned int mgag200_preferred_depth(struct mga_device *mdev)
1687 {
1688         if (IS_G200_SE(mdev) && mdev->vram_fb_available < (2048*1024))
1689                 return 16;
1690         else
1691                 return 32;
1692 }
1693
1694 int mgag200_modeset_init(struct mga_device *mdev)
1695 {
1696         struct drm_device *dev = &mdev->base;
1697         struct drm_connector *connector = &mdev->connector.base;
1698         struct drm_simple_display_pipe *pipe = &mdev->display_pipe;
1699         size_t format_count = ARRAY_SIZE(mgag200_simple_display_pipe_formats);
1700         int ret;
1701
1702         mdev->bpp_shifts[0] = 0;
1703         mdev->bpp_shifts[1] = 1;
1704         mdev->bpp_shifts[2] = 0;
1705         mdev->bpp_shifts[3] = 2;
1706
1707         mgag200_init_regs(mdev);
1708
1709         ret = drmm_mode_config_init(dev);
1710         if (ret) {
1711                 drm_err(dev, "drmm_mode_config_init() failed, error %d\n",
1712                         ret);
1713                 return ret;
1714         }
1715
1716         dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1717         dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1718
1719         dev->mode_config.preferred_depth = mgag200_preferred_depth(mdev);
1720
1721         dev->mode_config.fb_base = mdev->mc.vram_base;
1722
1723         dev->mode_config.funcs = &mgag200_mode_config_funcs;
1724
1725         ret = mgag200_vga_connector_init(mdev);
1726         if (ret) {
1727                 drm_err(dev,
1728                         "mgag200_vga_connector_init() failed, error %d\n",
1729                         ret);
1730                 return ret;
1731         }
1732
1733         ret = drm_simple_display_pipe_init(dev, pipe,
1734                                            &mgag200_simple_display_pipe_funcs,
1735                                            mgag200_simple_display_pipe_formats,
1736                                            format_count,
1737                                            mgag200_simple_display_pipe_fmtmods,
1738                                            connector);
1739         if (ret) {
1740                 drm_err(dev,
1741                         "drm_simple_display_pipe_init() failed, error %d\n",
1742                         ret);
1743                 return ret;
1744         }
1745
1746         /* FIXME: legacy gamma tables; convert to CRTC state */
1747         drm_mode_crtc_set_gamma_size(&pipe->crtc, MGAG200_LUT_SIZE);
1748
1749         drm_mode_config_reset(dev);
1750
1751         return 0;
1752 }