1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
9 #include <linux/component.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of_graph.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/reset.h>
17 #include <drm/bridge/dw_hdmi.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_device.h>
20 #include <drm/drm_edid.h>
21 #include <drm/drm_probe_helper.h>
22 #include <drm/drm_print.h>
24 #include <linux/media-bus-format.h>
25 #include <linux/videodev2.h>
27 #include "meson_drv.h"
28 #include "meson_dw_hdmi.h"
29 #include "meson_registers.h"
30 #include "meson_vclk.h"
31 #include "meson_venc.h"
33 #define DRIVER_NAME "meson-dw-hdmi"
34 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
39 * HDMI Output is composed of :
41 * - A Synopsys DesignWare HDMI Controller IP
42 * - A TOP control block controlling the Clocks and PHY
43 * - A custom HDMI PHY in order convert video to TMDS signal
47 * ___________________________________
49 * |___________________________________|
51 * | Synopsys HDMI | HDMI PHY |=> TMDS
52 * | Controller |________________|
53 * |___________________________________|<=> DDC
56 * The HDMI TOP block only supports HPD sensing.
57 * The Synopsys HDMI Controller interrupt is routed
58 * through the TOP Block interrupt.
59 * Communication to the TOP Block and the Synopsys
60 * HDMI Controller is done a pair of addr+read/write
62 * The HDMI PHY is configured by registers in the
65 * Pixel data arrives in 4:4:4 format from the VENC
66 * block and the VPU HDMI mux selects either the ENCI
67 * encoder for the 576i or 480i formats or the ENCP
68 * encoder for all the other formats including
69 * interlaced HD formats.
70 * The VENC uses a DVI encoder on top of the ENCI
71 * or ENCP encoders to generate DVI timings for the
74 * GXBB, GXL and GXM embeds the Synopsys DesignWare
75 * HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
76 * audio source interfaces.
78 * We handle the following features :
80 * - HPD Rise & Fall interrupt
81 * - HDMI Controller Interrupt
82 * - HDMI PHY Init for 480i to 1080p60
83 * - VENC & HDMI Clock setup for 480i to 1080p60
84 * - VENC Mode setup for 480i to 1080p60
88 * - PHY, Clock and Mode setup for 2k && 4k modes
89 * - SDDC Scrambling mode for HDMI 2.0a
94 /* TOP Block Communication Channel */
95 #define HDMITX_TOP_ADDR_REG 0x0
96 #define HDMITX_TOP_DATA_REG 0x4
97 #define HDMITX_TOP_CTRL_REG 0x8
98 #define HDMITX_TOP_G12A_OFFSET 0x8000
100 /* Controller Communication Channel */
101 #define HDMITX_DWC_ADDR_REG 0x10
102 #define HDMITX_DWC_DATA_REG 0x14
103 #define HDMITX_DWC_CTRL_REG 0x18
106 #define HHI_MEM_PD_REG0 0x100 /* 0x40 */
107 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
108 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
109 #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
110 #define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
111 #define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
112 #define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
113 #define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */
115 static DEFINE_SPINLOCK(reg_lock);
117 enum meson_venc_source {
118 MESON_VENC_SOURCE_NONE = 0,
119 MESON_VENC_SOURCE_ENCI = 1,
120 MESON_VENC_SOURCE_ENCP = 2,
123 struct meson_dw_hdmi;
125 struct meson_dw_hdmi_data {
126 unsigned int (*top_read)(struct meson_dw_hdmi *dw_hdmi,
128 void (*top_write)(struct meson_dw_hdmi *dw_hdmi,
129 unsigned int addr, unsigned int data);
130 unsigned int (*dwc_read)(struct meson_dw_hdmi *dw_hdmi,
132 void (*dwc_write)(struct meson_dw_hdmi *dw_hdmi,
133 unsigned int addr, unsigned int data);
136 struct meson_dw_hdmi {
137 struct drm_encoder encoder;
138 struct dw_hdmi_plat_data dw_plat_data;
139 struct meson_drm *priv;
141 void __iomem *hdmitx;
142 const struct meson_dw_hdmi_data *data;
143 struct reset_control *hdmitx_apb;
144 struct reset_control *hdmitx_ctrl;
145 struct reset_control *hdmitx_phy;
146 struct clk *hdmi_pclk;
147 struct clk *venci_clk;
148 struct regulator *hdmi_supply;
150 struct dw_hdmi *hdmi;
152 #define encoder_to_meson_dw_hdmi(x) \
153 container_of(x, struct meson_dw_hdmi, encoder)
155 static inline int dw_hdmi_is_compatible(struct meson_dw_hdmi *dw_hdmi,
158 return of_device_is_compatible(dw_hdmi->dev->of_node, compat);
161 /* PHY (via TOP bridge) and Controller dedicated register interface */
163 static unsigned int dw_hdmi_top_read(struct meson_dw_hdmi *dw_hdmi,
169 spin_lock_irqsave(®_lock, flags);
171 /* ADDR must be written twice */
172 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
173 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
175 /* Read needs a second DATA read */
176 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
177 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
179 spin_unlock_irqrestore(®_lock, flags);
184 static unsigned int dw_hdmi_g12a_top_read(struct meson_dw_hdmi *dw_hdmi,
187 return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
190 static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi,
191 unsigned int addr, unsigned int data)
195 spin_lock_irqsave(®_lock, flags);
197 /* ADDR must be written twice */
198 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
199 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
201 /* Write needs single DATA write */
202 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
204 spin_unlock_irqrestore(®_lock, flags);
207 static inline void dw_hdmi_g12a_top_write(struct meson_dw_hdmi *dw_hdmi,
208 unsigned int addr, unsigned int data)
210 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
213 /* Helper to change specific bits in PHY registers */
214 static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi *dw_hdmi,
219 unsigned int data = dw_hdmi->data->top_read(dw_hdmi, addr);
224 dw_hdmi->data->top_write(dw_hdmi, addr, data);
227 static unsigned int dw_hdmi_dwc_read(struct meson_dw_hdmi *dw_hdmi,
233 spin_lock_irqsave(®_lock, flags);
235 /* ADDR must be written twice */
236 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
237 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
239 /* Read needs a second DATA read */
240 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
241 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
243 spin_unlock_irqrestore(®_lock, flags);
248 static unsigned int dw_hdmi_g12a_dwc_read(struct meson_dw_hdmi *dw_hdmi,
251 return readb(dw_hdmi->hdmitx + addr);
254 static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi,
255 unsigned int addr, unsigned int data)
259 spin_lock_irqsave(®_lock, flags);
261 /* ADDR must be written twice */
262 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
263 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
265 /* Write needs single DATA write */
266 writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
268 spin_unlock_irqrestore(®_lock, flags);
271 static inline void dw_hdmi_g12a_dwc_write(struct meson_dw_hdmi *dw_hdmi,
272 unsigned int addr, unsigned int data)
274 writeb(data, dw_hdmi->hdmitx + addr);
277 /* Helper to change specific bits in controller registers */
278 static inline void dw_hdmi_dwc_write_bits(struct meson_dw_hdmi *dw_hdmi,
283 unsigned int data = dw_hdmi->data->dwc_read(dw_hdmi, addr);
288 dw_hdmi->data->dwc_write(dw_hdmi, addr, data);
293 /* Setup PHY bandwidth modes */
294 static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi,
295 struct drm_display_mode *mode)
297 struct meson_drm *priv = dw_hdmi->priv;
298 unsigned int pixel_clock = mode->clock;
300 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
301 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) {
302 if (pixel_clock >= 371250) {
303 /* 5.94Gbps, 3.7125Gbps */
304 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x333d3282);
305 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b);
306 } else if (pixel_clock >= 297000) {
308 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382);
309 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b);
310 } else if (pixel_clock >= 148500) {
312 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303362);
313 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2016315b);
315 /* 742.5Mbps, and below */
316 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33604142);
317 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x0016315b);
319 } else if (dw_hdmi_is_compatible(dw_hdmi,
320 "amlogic,meson-gxbb-dw-hdmi")) {
321 if (pixel_clock >= 371250) {
322 /* 5.94Gbps, 3.7125Gbps */
323 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33353245);
324 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2100115b);
325 } else if (pixel_clock >= 297000) {
327 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33634283);
328 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0xb000115b);
330 /* 1.485Gbps, and below */
331 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33632122);
332 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2000115b);
334 } else if (dw_hdmi_is_compatible(dw_hdmi,
335 "amlogic,meson-g12a-dw-hdmi")) {
336 if (pixel_clock >= 371250) {
337 /* 5.94Gbps, 3.7125Gbps */
338 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
339 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
340 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x0000080b);
341 } else if (pixel_clock >= 297000) {
343 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb6262);
344 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
345 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003);
347 /* 1.485Gbps, and below */
348 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb4242);
349 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
350 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003);
355 static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi)
357 struct meson_drm *priv = dw_hdmi->priv;
359 /* Enable and software reset */
360 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
364 /* Enable and unreset */
365 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
370 static void dw_hdmi_set_vclk(struct meson_dw_hdmi *dw_hdmi,
371 struct drm_display_mode *mode)
373 struct meson_drm *priv = dw_hdmi->priv;
374 int vic = drm_match_cea_mode(mode);
375 unsigned int vclk_freq;
376 unsigned int venc_freq;
377 unsigned int hdmi_freq;
379 vclk_freq = mode->clock;
382 meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, vclk_freq,
383 vclk_freq, vclk_freq, false);
387 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
390 venc_freq = vclk_freq;
391 hdmi_freq = vclk_freq;
393 if (meson_venc_hdmi_venc_repeat(vic))
396 vclk_freq = max(venc_freq, hdmi_freq);
398 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
401 DRM_DEBUG_DRIVER("vclk:%d venc=%d hdmi=%d enci=%d\n",
402 vclk_freq, venc_freq, hdmi_freq,
403 priv->venc.hdmi_use_enci);
405 meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, vclk_freq,
406 venc_freq, hdmi_freq, priv->venc.hdmi_use_enci);
409 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
410 struct drm_display_mode *mode)
412 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
413 struct meson_drm *priv = dw_hdmi->priv;
414 unsigned int wr_clk =
415 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING));
417 DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name,
418 mode->clock > 340000 ? 40 : 10);
421 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
423 /* Bring HDMITX MEM output of power down */
424 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
426 /* Bring out of reset */
427 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0);
429 /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
430 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
433 /* Enable cec_clk and hdcp22_tmdsclk_en */
434 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
437 /* Enable normal output to PHY */
438 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
440 /* TMDS pattern setup (TOFIX Handle the YUV420 case) */
441 if (mode->clock > 340000) {
442 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
444 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
447 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
449 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
453 /* Load TMDS pattern */
454 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
456 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
458 /* Setup PHY parameters */
459 meson_hdmi_phy_setup_mode(dw_hdmi, mode);
462 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
463 0xffff << 16, 0x0390 << 16);
466 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
467 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
468 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
469 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
472 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
475 /* Disable clock, fifo, fifo_wr */
476 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
478 dw_hdmi_set_high_tmds_clock_ratio(hdmi);
482 /* Reset PHY 3 times in a row */
483 meson_dw_hdmi_phy_reset(dw_hdmi);
484 meson_dw_hdmi_phy_reset(dw_hdmi);
485 meson_dw_hdmi_phy_reset(dw_hdmi);
487 /* Temporary Disable VENC video stream */
488 if (priv->venc.hdmi_use_enci)
489 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
491 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
493 /* Temporary Disable HDMI video stream to HDMI-TX */
494 writel_bits_relaxed(0x3, 0,
495 priv->io_base + _REG(VPU_HDMI_SETTING));
496 writel_bits_relaxed(0xf << 8, 0,
497 priv->io_base + _REG(VPU_HDMI_SETTING));
499 /* Re-Enable VENC video stream */
500 if (priv->venc.hdmi_use_enci)
501 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
503 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
505 /* Push back HDMI clock settings */
506 writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8),
507 priv->io_base + _REG(VPU_HDMI_SETTING));
509 /* Enable and Select HDMI video source for HDMI-TX */
510 if (priv->venc.hdmi_use_enci)
511 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI,
512 priv->io_base + _REG(VPU_HDMI_SETTING));
514 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP,
515 priv->io_base + _REG(VPU_HDMI_SETTING));
520 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi,
523 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
524 struct meson_drm *priv = dw_hdmi->priv;
526 DRM_DEBUG_DRIVER("\n");
528 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
531 static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
534 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
536 return !!dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_STAT0) ?
537 connector_status_connected : connector_status_disconnected;
540 static void dw_hdmi_setup_hpd(struct dw_hdmi *hdmi,
543 struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
545 /* Setup HPD Filter */
546 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER,
549 /* Clear interrupts */
550 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
551 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL);
553 /* Unmask interrupts */
554 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_INTR_MASKN,
555 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL,
556 HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL);
559 static const struct dw_hdmi_phy_ops meson_dw_hdmi_phy_ops = {
560 .init = dw_hdmi_phy_init,
561 .disable = dw_hdmi_phy_disable,
562 .read_hpd = dw_hdmi_read_hpd,
563 .setup_hpd = dw_hdmi_setup_hpd,
566 static irqreturn_t dw_hdmi_top_irq(int irq, void *dev_id)
568 struct meson_dw_hdmi *dw_hdmi = dev_id;
571 stat = dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_INTR_STAT);
572 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat);
574 /* HPD Events, handle in the threaded interrupt handler */
575 if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) {
576 dw_hdmi->irq_stat = stat;
577 return IRQ_WAKE_THREAD;
580 /* HDMI Controller Interrupt */
584 /* TOFIX Handle HDCP Interrupts */
589 /* Threaded interrupt handler to manage HPD events */
590 static irqreturn_t dw_hdmi_top_thread_irq(int irq, void *dev_id)
592 struct meson_dw_hdmi *dw_hdmi = dev_id;
593 u32 stat = dw_hdmi->irq_stat;
596 if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) {
597 bool hpd_connected = false;
599 if (stat & HDMITX_TOP_INTR_HPD_RISE)
600 hpd_connected = true;
602 dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected,
605 drm_helper_hpd_irq_event(dw_hdmi->encoder.dev);
611 static enum drm_mode_status
612 dw_hdmi_mode_valid(struct drm_connector *connector,
613 const struct drm_display_mode *mode)
615 struct meson_drm *priv = connector->dev->dev_private;
616 unsigned int vclk_freq;
617 unsigned int venc_freq;
618 unsigned int hdmi_freq;
619 int vic = drm_match_cea_mode(mode);
620 enum drm_mode_status status;
622 DRM_DEBUG_DRIVER("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
624 /* If sink max TMDS clock, we reject the mode */
625 if (connector->display_info.max_tmds_clock &&
626 mode->clock > connector->display_info.max_tmds_clock)
629 /* Check against non-VIC supported modes */
631 status = meson_venc_hdmi_supported_mode(mode);
632 if (status != MODE_OK)
635 return meson_vclk_dmt_supported_freq(priv, mode->clock);
636 /* Check against supported VIC modes */
637 } else if (!meson_venc_hdmi_supported_vic(vic))
640 vclk_freq = mode->clock;
642 /* 480i/576i needs global pixel doubling */
643 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
646 venc_freq = vclk_freq;
647 hdmi_freq = vclk_freq;
649 /* VENC double pixels for 1080i and 720p modes */
650 if (meson_venc_hdmi_venc_repeat(vic))
653 vclk_freq = max(venc_freq, hdmi_freq);
655 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
658 dev_dbg(connector->dev->dev, "%s: vclk:%d venc=%d hdmi=%d\n", __func__,
659 vclk_freq, venc_freq, hdmi_freq);
661 return meson_vclk_vic_supported_freq(vclk_freq);
666 static void meson_venc_hdmi_encoder_destroy(struct drm_encoder *encoder)
668 drm_encoder_cleanup(encoder);
671 static const struct drm_encoder_funcs meson_venc_hdmi_encoder_funcs = {
672 .destroy = meson_venc_hdmi_encoder_destroy,
675 static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
676 struct drm_crtc_state *crtc_state,
677 struct drm_connector_state *conn_state)
682 static void meson_venc_hdmi_encoder_disable(struct drm_encoder *encoder)
684 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder);
685 struct meson_drm *priv = dw_hdmi->priv;
687 DRM_DEBUG_DRIVER("\n");
689 writel_bits_relaxed(0x3, 0,
690 priv->io_base + _REG(VPU_HDMI_SETTING));
692 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
693 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
696 static void meson_venc_hdmi_encoder_enable(struct drm_encoder *encoder)
698 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder);
699 struct meson_drm *priv = dw_hdmi->priv;
701 DRM_DEBUG_DRIVER("%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP");
703 if (priv->venc.hdmi_use_enci)
704 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
706 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
709 static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder,
710 struct drm_display_mode *mode,
711 struct drm_display_mode *adjusted_mode)
713 struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder);
714 struct meson_drm *priv = dw_hdmi->priv;
715 int vic = drm_match_cea_mode(mode);
717 DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode->name, vic);
719 /* VENC + VENC-DVI Mode setup */
720 meson_venc_hdmi_mode_set(priv, vic, mode);
723 dw_hdmi_set_vclk(dw_hdmi, mode);
725 /* Setup YUV444 to HDMI-TX, no 10bit diphering */
726 writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
729 static const struct drm_encoder_helper_funcs
730 meson_venc_hdmi_encoder_helper_funcs = {
731 .atomic_check = meson_venc_hdmi_encoder_atomic_check,
732 .disable = meson_venc_hdmi_encoder_disable,
733 .enable = meson_venc_hdmi_encoder_enable,
734 .mode_set = meson_venc_hdmi_encoder_mode_set,
739 static int meson_dw_hdmi_reg_read(void *context, unsigned int reg,
740 unsigned int *result)
742 struct meson_dw_hdmi *dw_hdmi = context;
744 *result = dw_hdmi->data->dwc_read(dw_hdmi, reg);
750 static int meson_dw_hdmi_reg_write(void *context, unsigned int reg,
753 struct meson_dw_hdmi *dw_hdmi = context;
755 dw_hdmi->data->dwc_write(dw_hdmi, reg, val);
760 static const struct regmap_config meson_dw_hdmi_regmap_config = {
763 .reg_read = meson_dw_hdmi_reg_read,
764 .reg_write = meson_dw_hdmi_reg_write,
765 .max_register = 0x10000,
769 static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = {
770 .top_read = dw_hdmi_top_read,
771 .top_write = dw_hdmi_top_write,
772 .dwc_read = dw_hdmi_dwc_read,
773 .dwc_write = dw_hdmi_dwc_write,
776 static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
777 .top_read = dw_hdmi_g12a_top_read,
778 .top_write = dw_hdmi_g12a_top_write,
779 .dwc_read = dw_hdmi_g12a_dwc_read,
780 .dwc_write = dw_hdmi_g12a_dwc_write,
783 static bool meson_hdmi_connector_is_available(struct device *dev)
785 struct device_node *ep, *remote;
787 /* HDMI Connector is on the second port, first endpoint */
788 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, 0);
792 /* If the endpoint node exists, consider it enabled */
793 remote = of_graph_get_remote_port(ep);
805 static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
808 struct platform_device *pdev = to_platform_device(dev);
809 const struct meson_dw_hdmi_data *match;
810 struct meson_dw_hdmi *meson_dw_hdmi;
811 struct drm_device *drm = data;
812 struct meson_drm *priv = drm->dev_private;
813 struct dw_hdmi_plat_data *dw_plat_data;
814 struct drm_encoder *encoder;
815 struct resource *res;
819 DRM_DEBUG_DRIVER("\n");
821 if (!meson_hdmi_connector_is_available(dev)) {
822 dev_info(drm->dev, "HDMI Output connector not available\n");
826 match = of_device_get_match_data(&pdev->dev);
828 dev_err(&pdev->dev, "failed to get match data\n");
832 meson_dw_hdmi = devm_kzalloc(dev, sizeof(*meson_dw_hdmi),
837 meson_dw_hdmi->priv = priv;
838 meson_dw_hdmi->dev = dev;
839 meson_dw_hdmi->data = match;
840 dw_plat_data = &meson_dw_hdmi->dw_plat_data;
841 encoder = &meson_dw_hdmi->encoder;
843 meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi");
844 if (IS_ERR(meson_dw_hdmi->hdmi_supply)) {
845 if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER)
846 return -EPROBE_DEFER;
847 meson_dw_hdmi->hdmi_supply = NULL;
849 ret = regulator_enable(meson_dw_hdmi->hdmi_supply);
854 meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev,
856 if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) {
857 dev_err(dev, "Failed to get hdmitx_apb reset\n");
858 return PTR_ERR(meson_dw_hdmi->hdmitx_apb);
861 meson_dw_hdmi->hdmitx_ctrl = devm_reset_control_get_exclusive(dev,
863 if (IS_ERR(meson_dw_hdmi->hdmitx_ctrl)) {
864 dev_err(dev, "Failed to get hdmitx reset\n");
865 return PTR_ERR(meson_dw_hdmi->hdmitx_ctrl);
868 meson_dw_hdmi->hdmitx_phy = devm_reset_control_get_exclusive(dev,
870 if (IS_ERR(meson_dw_hdmi->hdmitx_phy)) {
871 dev_err(dev, "Failed to get hdmitx_phy reset\n");
872 return PTR_ERR(meson_dw_hdmi->hdmitx_phy);
875 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
876 meson_dw_hdmi->hdmitx = devm_ioremap_resource(dev, res);
877 if (IS_ERR(meson_dw_hdmi->hdmitx))
878 return PTR_ERR(meson_dw_hdmi->hdmitx);
880 meson_dw_hdmi->hdmi_pclk = devm_clk_get(dev, "isfr");
881 if (IS_ERR(meson_dw_hdmi->hdmi_pclk)) {
882 dev_err(dev, "Unable to get HDMI pclk\n");
883 return PTR_ERR(meson_dw_hdmi->hdmi_pclk);
885 clk_prepare_enable(meson_dw_hdmi->hdmi_pclk);
887 meson_dw_hdmi->venci_clk = devm_clk_get(dev, "venci");
888 if (IS_ERR(meson_dw_hdmi->venci_clk)) {
889 dev_err(dev, "Unable to get venci clk\n");
890 return PTR_ERR(meson_dw_hdmi->venci_clk);
892 clk_prepare_enable(meson_dw_hdmi->venci_clk);
894 dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi,
895 &meson_dw_hdmi_regmap_config);
896 if (IS_ERR(dw_plat_data->regm))
897 return PTR_ERR(dw_plat_data->regm);
899 irq = platform_get_irq(pdev, 0);
901 dev_err(dev, "Failed to get hdmi top irq\n");
905 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_top_irq,
906 dw_hdmi_top_thread_irq, IRQF_SHARED,
907 "dw_hdmi_top_irq", meson_dw_hdmi);
909 dev_err(dev, "Failed to request hdmi top irq\n");
915 drm_encoder_helper_add(encoder, &meson_venc_hdmi_encoder_helper_funcs);
917 ret = drm_encoder_init(drm, encoder, &meson_venc_hdmi_encoder_funcs,
918 DRM_MODE_ENCODER_TMDS, "meson_hdmi");
920 dev_err(priv->dev, "Failed to init HDMI encoder\n");
924 encoder->possible_crtcs = BIT(0);
926 DRM_DEBUG_DRIVER("encoder initialized\n");
929 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
931 /* Bring HDMITX MEM output of power down */
932 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
934 /* Reset HDMITX APB & TX & PHY */
935 reset_control_reset(meson_dw_hdmi->hdmitx_apb);
936 reset_control_reset(meson_dw_hdmi->hdmitx_ctrl);
937 reset_control_reset(meson_dw_hdmi->hdmitx_phy);
939 /* Enable APB3 fail on error */
940 if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
941 writel_bits_relaxed(BIT(15), BIT(15),
942 meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);
943 writel_bits_relaxed(BIT(15), BIT(15),
944 meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG);
947 /* Bring out of reset */
948 meson_dw_hdmi->data->top_write(meson_dw_hdmi,
949 HDMITX_TOP_SW_RESET, 0);
953 meson_dw_hdmi->data->top_write(meson_dw_hdmi,
954 HDMITX_TOP_CLK_CNTL, 0xff);
956 /* Enable HDMI-TX Interrupt */
957 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
958 HDMITX_TOP_INTR_CORE);
960 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN,
961 HDMITX_TOP_INTR_CORE);
963 /* Bridge / Connector */
965 dw_plat_data->mode_valid = dw_hdmi_mode_valid;
966 dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops;
967 dw_plat_data->phy_name = "meson_dw_hdmi_phy";
968 dw_plat_data->phy_data = meson_dw_hdmi;
969 dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
970 dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
972 platform_set_drvdata(pdev, meson_dw_hdmi);
974 meson_dw_hdmi->hdmi = dw_hdmi_bind(pdev, encoder,
975 &meson_dw_hdmi->dw_plat_data);
976 if (IS_ERR(meson_dw_hdmi->hdmi))
977 return PTR_ERR(meson_dw_hdmi->hdmi);
979 DRM_DEBUG_DRIVER("HDMI controller initialized\n");
984 static void meson_dw_hdmi_unbind(struct device *dev, struct device *master,
987 struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev);
989 dw_hdmi_unbind(meson_dw_hdmi->hdmi);
992 static const struct component_ops meson_dw_hdmi_ops = {
993 .bind = meson_dw_hdmi_bind,
994 .unbind = meson_dw_hdmi_unbind,
997 static int meson_dw_hdmi_probe(struct platform_device *pdev)
999 return component_add(&pdev->dev, &meson_dw_hdmi_ops);
1002 static int meson_dw_hdmi_remove(struct platform_device *pdev)
1004 component_del(&pdev->dev, &meson_dw_hdmi_ops);
1009 static const struct of_device_id meson_dw_hdmi_of_table[] = {
1010 { .compatible = "amlogic,meson-gxbb-dw-hdmi",
1011 .data = &meson_dw_hdmi_gx_data },
1012 { .compatible = "amlogic,meson-gxl-dw-hdmi",
1013 .data = &meson_dw_hdmi_gx_data },
1014 { .compatible = "amlogic,meson-gxm-dw-hdmi",
1015 .data = &meson_dw_hdmi_gx_data },
1016 { .compatible = "amlogic,meson-g12a-dw-hdmi",
1017 .data = &meson_dw_hdmi_g12a_data },
1020 MODULE_DEVICE_TABLE(of, meson_dw_hdmi_of_table);
1022 static struct platform_driver meson_dw_hdmi_platform_driver = {
1023 .probe = meson_dw_hdmi_probe,
1024 .remove = meson_dw_hdmi_remove,
1026 .name = DRIVER_NAME,
1027 .of_match_table = meson_dw_hdmi_of_table,
1030 module_platform_driver(meson_dw_hdmi_platform_driver);
1032 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
1033 MODULE_DESCRIPTION(DRIVER_DESC);
1034 MODULE_LICENSE("GPL");