1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Chunhui Dai <chunhui.dai@mediatek.com>
7 #ifndef _MTK_HDMI_PHY_H
8 #define _MTK_HDMI_PHY_H
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/types.h>
22 struct mtk_hdmi_phy_conf {
24 const struct clk_ops *hdmi_phy_clk_ops;
25 void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
26 void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
32 struct mtk_hdmi_phy_conf *conf;
35 unsigned long pll_rate;
36 unsigned char drv_imp_clk;
37 unsigned char drv_imp_d2;
38 unsigned char drv_imp_d1;
39 unsigned char drv_imp_d0;
41 unsigned int ibias_up;
44 void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
46 void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
48 void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
50 struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
51 long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
52 unsigned long *parent_rate);
53 unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
54 unsigned long parent_rate);
56 extern struct platform_driver mtk_hdmi_phy_driver;
57 extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
58 extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
60 #endif /* _MTK_HDMI_PHY_H */