drivers/gpu/drm/mediatek/mtk_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Jie Qiu <jie.qiu@mediatek.com>
   5  */
   6
   7 #include <linux/arm-smccc.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/hdmi.h>
  11 #include <linux/i2c.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/module.h>
  16 #include <linux/mutex.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/of.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/phy/phy.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24
  25 #include <sound/hdmi-codec.h>
  26
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_bridge.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_print.h>
  32 #include <drm/drm_probe_helper.h>
  33
  34 #include "mtk_cec.h"
  35 #include "mtk_hdmi.h"
  36 #include "mtk_hdmi_regs.h"
  37
  38 #define NCTS_BYTES      7
  39
  40 enum mtk_hdmi_clk_id {
  41         MTK_HDMI_CLK_HDMI_PIXEL,
  42         MTK_HDMI_CLK_HDMI_PLL,
  43         MTK_HDMI_CLK_AUD_BCLK,
  44         MTK_HDMI_CLK_AUD_SPDIF,
  45         MTK_HDMI_CLK_COUNT
  46 };
  47
  48 enum hdmi_aud_input_type {
  49         HDMI_AUD_INPUT_I2S = 0,
  50         HDMI_AUD_INPUT_SPDIF,
  51 };
  52
  53 enum hdmi_aud_i2s_fmt {
  54         HDMI_I2S_MODE_RJT_24BIT = 0,
  55         HDMI_I2S_MODE_RJT_16BIT,
  56         HDMI_I2S_MODE_LJT_24BIT,
  57         HDMI_I2S_MODE_LJT_16BIT,
  58         HDMI_I2S_MODE_I2S_24BIT,
  59         HDMI_I2S_MODE_I2S_16BIT
  60 };
  61
  62 enum hdmi_aud_mclk {
  63         HDMI_AUD_MCLK_128FS,
  64         HDMI_AUD_MCLK_192FS,
  65         HDMI_AUD_MCLK_256FS,
  66         HDMI_AUD_MCLK_384FS,
  67         HDMI_AUD_MCLK_512FS,
  68         HDMI_AUD_MCLK_768FS,
  69         HDMI_AUD_MCLK_1152FS,
  70 };
  71
  72 enum hdmi_aud_channel_type {
  73         HDMI_AUD_CHAN_TYPE_1_0 = 0,
  74         HDMI_AUD_CHAN_TYPE_1_1,
  75         HDMI_AUD_CHAN_TYPE_2_0,
  76         HDMI_AUD_CHAN_TYPE_2_1,
  77         HDMI_AUD_CHAN_TYPE_3_0,
  78         HDMI_AUD_CHAN_TYPE_3_1,
  79         HDMI_AUD_CHAN_TYPE_4_0,
  80         HDMI_AUD_CHAN_TYPE_4_1,
  81         HDMI_AUD_CHAN_TYPE_5_0,
  82         HDMI_AUD_CHAN_TYPE_5_1,
  83         HDMI_AUD_CHAN_TYPE_6_0,
  84         HDMI_AUD_CHAN_TYPE_6_1,
  85         HDMI_AUD_CHAN_TYPE_7_0,
  86         HDMI_AUD_CHAN_TYPE_7_1,
  87         HDMI_AUD_CHAN_TYPE_3_0_LRS,
  88         HDMI_AUD_CHAN_TYPE_3_1_LRS,
  89         HDMI_AUD_CHAN_TYPE_4_0_CLRS,
  90         HDMI_AUD_CHAN_TYPE_4_1_CLRS,
  91         HDMI_AUD_CHAN_TYPE_6_1_CS,
  92         HDMI_AUD_CHAN_TYPE_6_1_CH,
  93         HDMI_AUD_CHAN_TYPE_6_1_OH,
  94         HDMI_AUD_CHAN_TYPE_6_1_CHR,
  95         HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
  96         HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
  97         HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
  98         HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
  99         HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
 100         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
 101         HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
 102         HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
 103         HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
 104         HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
 105         HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
 106         HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
 107         HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
 108         HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
 109         HDMI_AUD_CHAN_TYPE_6_0_CS,
 110         HDMI_AUD_CHAN_TYPE_6_0_CH,
 111         HDMI_AUD_CHAN_TYPE_6_0_OH,
 112         HDMI_AUD_CHAN_TYPE_6_0_CHR,
 113         HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
 114         HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
 115         HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
 116         HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
 117         HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
 118         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
 119         HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
 120         HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
 121         HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
 122         HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
 123         HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
 124         HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
 125         HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
 126         HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
 127         HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
 128         HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
 129 };
 130
 131 enum hdmi_aud_channel_swap_type {
 132         HDMI_AUD_SWAP_LR,
 133         HDMI_AUD_SWAP_LFE_CC,
 134         HDMI_AUD_SWAP_LSRS,
 135         HDMI_AUD_SWAP_RLS_RRS,
 136         HDMI_AUD_SWAP_LR_STATUS,
 137 };
 138
 139 struct hdmi_audio_param {
 140         enum hdmi_audio_coding_type aud_codec;
 141         enum hdmi_audio_sample_size aud_sampe_size;
 142         enum hdmi_aud_input_type aud_input_type;
 143         enum hdmi_aud_i2s_fmt aud_i2s_fmt;
 144         enum hdmi_aud_mclk aud_mclk;
 145         enum hdmi_aud_channel_type aud_input_chan_type;
 146         struct hdmi_codec_params codec_params;
 147 };
 148
 149 struct mtk_hdmi_conf {
 150         bool tz_disabled;
 151         bool cea_modes_only;
 152         unsigned long max_mode_clock;
 153 };
 154
 155 struct mtk_hdmi {
 156         struct drm_bridge bridge;
 157         struct drm_bridge *next_bridge;
 158         struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
 159         struct device *dev;
 160         const struct mtk_hdmi_conf *conf;
 161         struct phy *phy;
 162         struct device *cec_dev;
 163         struct i2c_adapter *ddc_adpt;
 164         struct clk *clk[MTK_HDMI_CLK_COUNT];
 165         struct drm_display_mode mode;
 166         bool dvi_mode;
 167         u32 min_clock;
 168         u32 max_clock;
 169         u32 max_hdisplay;
 170         u32 max_vdisplay;
 171         u32 ibias;
 172         u32 ibias_up;
 173         struct regmap *sys_regmap;
 174         unsigned int sys_offset;
 175         void __iomem *regs;
 176         enum hdmi_colorspace csp;
 177         struct hdmi_audio_param aud_param;
 178         bool audio_enable;
 179         bool powered;
 180         bool enabled;
 181         hdmi_codec_plugged_cb plugged_cb;
 182         struct device *codec_dev;
 183         struct mutex update_plugged_status_lock;
 184 };
 185
 186 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 187 {
 188         return container_of(b, struct mtk_hdmi, bridge);
 189 }
 190
 191 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
 192 {
 193         return readl(hdmi->regs + offset);
 194 }
 195
 196 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
 197 {
 198         writel(val, hdmi->regs + offset);
 199 }
 200
 201 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 202 {
 203         void __iomem *reg = hdmi->regs + offset;
 204         u32 tmp;
 205
 206         tmp = readl(reg);
 207         tmp &= ~bits;
 208         writel(tmp, reg);
 209 }
 210
 211 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 212 {
 213         void __iomem *reg = hdmi->regs + offset;
 214         u32 tmp;
 215
 216         tmp = readl(reg);
 217         tmp |= bits;
 218         writel(tmp, reg);
 219 }
 220
 221 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
 222 {
 223         void __iomem *reg = hdmi->regs + offset;
 224         u32 tmp;
 225
 226         tmp = readl(reg);
 227         tmp = (tmp & ~mask) | (val & mask);
 228         writel(tmp, reg);
 229 }
 230
 231 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 232 {
 233         mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
 234                       VIDEO_SOURCE_SEL);
 235 }
 236
 237 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 238 {
 239         struct arm_smccc_res res;
 240
 241         /*
 242          * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
 243          * output. This bit can only be controlled in ARM supervisor mode.
 244          * The ARM trusted firmware provides an API for the HDMI driver to set
 245          * this control bit to enable HDMI output in supervisor mode.
 246          */
 247         if (hdmi->conf && hdmi->conf->tz_disabled)
 248                 regmap_update_bits(hdmi->sys_regmap,
 249                                    hdmi->sys_offset + HDMI_SYS_CFG20,
 250                                    0x80008005, enable ? 0x80000005 : 0x8000);
 251         else
 252                 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
 253                               0x80000000, 0, 0, 0, 0, 0, &res);
 254
 255         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 256                            HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
 257         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 258                            HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
 259 }
 260
 261 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
 262 {
 263         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 264                            HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
 265 }
 266
 267 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
 268 {
 269         mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 270 }
 271
 272 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
 273 {
 274         mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
 275 }
 276
 277 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
 278 {
 279         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 280                            HDMI_RST, HDMI_RST);
 281         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 282                            HDMI_RST, 0);
 283         mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
 284         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 285                            ANLG_ON, ANLG_ON);
 286 }
 287
 288 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
 289 {
 290         mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
 291                       CFG2_NOTICE_EN);
 292 }
 293
 294 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
 295 {
 296         mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
 297 }
 298
 299 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
 300 {
 301         mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
 302 }
 303
 304 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
 305                                         u8 len)
 306 {
 307         u32 ctrl_reg = GRL_CTRL;
 308         int i;
 309         u8 *frame_data;
 310         enum hdmi_infoframe_type frame_type;
 311         u8 frame_ver;
 312         u8 frame_len;
 313         u8 checksum;
 314         int ctrl_frame_en = 0;
 315
 316         frame_type = *buffer++;
 317         frame_ver = *buffer++;
 318         frame_len = *buffer++;
 319         checksum = *buffer++;
 320         frame_data = buffer;
 321
 322         dev_dbg(hdmi->dev,
 323                 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
 324                 frame_type, frame_ver, frame_len, checksum);
 325
 326         switch (frame_type) {
 327         case HDMI_INFOFRAME_TYPE_AVI:
 328                 ctrl_frame_en = CTRL_AVI_EN;
 329                 ctrl_reg = GRL_CTRL;
 330                 break;
 331         case HDMI_INFOFRAME_TYPE_SPD:
 332                 ctrl_frame_en = CTRL_SPD_EN;
 333                 ctrl_reg = GRL_CTRL;
 334                 break;
 335         case HDMI_INFOFRAME_TYPE_AUDIO:
 336                 ctrl_frame_en = CTRL_AUDIO_EN;
 337                 ctrl_reg = GRL_CTRL;
 338                 break;
 339         case HDMI_INFOFRAME_TYPE_VENDOR:
 340                 ctrl_frame_en = VS_EN;
 341                 ctrl_reg = GRL_ACP_ISRC_CTRL;
 342                 break;
 343         default:
 344                 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
 345                 return;
 346         }
 347         mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
 348         mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
 349         mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
 350         mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
 351
 352         mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
 353         for (i = 0; i < frame_len; i++)
 354                 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
 355
 356         mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
 357 }
 358
 359 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
 360 {
 361         mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
 362                       AUDIO_PACKET_OFF);
 363 }
 364
 365 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
 366 {
 367         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 368                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
 369         usleep_range(2000, 4000);
 370         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 371                            HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
 372 }
 373
 374 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
 375 {
 376         regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 377                            DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
 378                            COLOR_8BIT_MODE);
 379 }
 380
 381 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
 382 {
 383         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 384         usleep_range(2000, 4000);
 385         mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
 386 }
 387
 388 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
 389 {
 390         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
 391                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 392         usleep_range(2000, 4000);
 393         mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
 394                       CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
 395 }
 396
 397 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
 398 {
 399         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
 400                       CTS_CTRL_SOFT);
 401 }
 402
 403 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
 404                                                bool enable)
 405 {
 406         mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
 407                       NCTS_WRI_ANYTIME);
 408 }
 409
 410 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
 411                                      struct drm_display_mode *mode)
 412 {
 413         mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
 414
 415         if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
 416             mode->clock == 74250 &&
 417             mode->vdisplay == 1080)
 418                 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 419         else
 420                 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
 421 }
 422
 423 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
 424                                         enum hdmi_aud_channel_swap_type swap)
 425 {
 426         u8 swap_bit;
 427
 428         switch (swap) {
 429         case HDMI_AUD_SWAP_LR:
 430                 swap_bit = LR_SWAP;
 431                 break;
 432         case HDMI_AUD_SWAP_LFE_CC:
 433                 swap_bit = LFE_CC_SWAP;
 434                 break;
 435         case HDMI_AUD_SWAP_LSRS:
 436                 swap_bit = LSRS_SWAP;
 437                 break;
 438         case HDMI_AUD_SWAP_RLS_RRS:
 439                 swap_bit = RLS_RRS_SWAP;
 440                 break;
 441         case HDMI_AUD_SWAP_LR_STATUS:
 442                 swap_bit = LR_STATUS_SWAP;
 443                 break;
 444         default:
 445                 swap_bit = LFE_CC_SWAP;
 446                 break;
 447         }
 448         mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
 449 }
 450
 451 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
 452                                         enum hdmi_audio_sample_size bit_num)
 453 {
 454         u32 val;
 455
 456         switch (bit_num) {
 457         case HDMI_AUDIO_SAMPLE_SIZE_16:
 458                 val = AOUT_16BIT;
 459                 break;
 460         case HDMI_AUDIO_SAMPLE_SIZE_20:
 461                 val = AOUT_20BIT;
 462                 break;
 463         case HDMI_AUDIO_SAMPLE_SIZE_24:
 464         case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
 465                 val = AOUT_24BIT;
 466                 break;
 467         }
 468
 469         mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
 470 }
 471
 472 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 473                                         enum hdmi_aud_i2s_fmt i2s_fmt)
 474 {
 475         u32 val;
 476
 477         val = mtk_hdmi_read(hdmi, GRL_CFG0);
 478         val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 479
 480         switch (i2s_fmt) {
 481         case HDMI_I2S_MODE_RJT_24BIT:
 482                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
 483                 break;
 484         case HDMI_I2S_MODE_RJT_16BIT:
 485                 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
 486                 break;
 487         case HDMI_I2S_MODE_LJT_24BIT:
 488         default:
 489                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
 490                 break;
 491         case HDMI_I2S_MODE_LJT_16BIT:
 492                 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
 493                 break;
 494         case HDMI_I2S_MODE_I2S_24BIT:
 495                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
 496                 break;
 497         case HDMI_I2S_MODE_I2S_16BIT:
 498                 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
 499                 break;
 500         }
 501         mtk_hdmi_write(hdmi, GRL_CFG0, val);
 502 }
 503
 504 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
 505 {
 506         const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
 507         u8 val;
 508
 509         /* Disable high bitrate, set DST packet normal/double */
 510         mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
 511
 512         if (dst)
 513                 val = DST_NORMAL_DOUBLE | SACD_DST;
 514         else
 515                 val = 0;
 516
 517         mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
 518 }
 519
 520 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
 521                                         enum hdmi_aud_channel_type channel_type,
 522                                         u8 channel_count)
 523 {
 524         unsigned int ch_switch;
 525         u8 i2s_uv;
 526
 527         ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
 528                     CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
 529                     CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
 530                     CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
 531
 532         if (channel_count == 2) {
 533                 i2s_uv = I2S_UV_CH_EN(0);
 534         } else if (channel_count == 3 || channel_count == 4) {
 535                 if (channel_count == 4 &&
 536                     (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
 537                     channel_type == HDMI_AUD_CHAN_TYPE_4_0))
 538                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
 539                 else
 540                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
 541         } else if (channel_count == 6 || channel_count == 5) {
 542                 if (channel_count == 6 &&
 543                     channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
 544                     channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
 545                         i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 546                                  I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 547                 } else {
 548                         i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
 549                                  I2S_UV_CH_EN(0);
 550                 }
 551         } else if (channel_count == 8 || channel_count == 7) {
 552                 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
 553                          I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
 554         } else {
 555                 i2s_uv = I2S_UV_CH_EN(0);
 556         }
 557
 558         mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
 559         mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
 560         mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
 561         mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
 562 }
 563
 564 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 565                                            enum hdmi_aud_input_type input_type)
 566 {
 567         u32 val;
 568
 569         val = mtk_hdmi_read(hdmi, GRL_CFG1);
 570         if (input_type == HDMI_AUD_INPUT_I2S &&
 571             (val & CFG1_SPDIF) == CFG1_SPDIF) {
 572                 val &= ~CFG1_SPDIF;
 573         } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
 574                 (val & CFG1_SPDIF) == 0) {
 575                 val |= CFG1_SPDIF;
 576         }
 577         mtk_hdmi_write(hdmi, GRL_CFG1, val);
 578 }
 579
 580 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
 581                                                u8 *channel_status)
 582 {
 583         int i;
 584
 585         for (i = 0; i < 5; i++) {
 586                 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
 587                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
 588                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
 589         }
 590         for (; i < 24; i++) {
 591                 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
 592                 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
 593         }
 594 }
 595
 596 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 597 {
 598         u32 val;
 599
 600         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 601         if (val & MIX_CTRL_SRC_EN) {
 602                 val &= ~MIX_CTRL_SRC_EN;
 603                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 604                 usleep_range(255, 512);
 605                 val |= MIX_CTRL_SRC_EN;
 606                 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 607         }
 608 }
 609
 610 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 611 {
 612         u32 val;
 613
 614         val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
 615         val &= ~MIX_CTRL_SRC_EN;
 616         mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 617         mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
 618 }
 619
 620 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 621                                      enum hdmi_aud_mclk mclk)
 622 {
 623         u32 val;
 624
 625         val = mtk_hdmi_read(hdmi, GRL_CFG5);
 626         val &= CFG5_CD_RATIO_MASK;
 627
 628         switch (mclk) {
 629         case HDMI_AUD_MCLK_128FS:
 630                 val |= CFG5_FS128;
 631                 break;
 632         case HDMI_AUD_MCLK_256FS:
 633                 val |= CFG5_FS256;
 634                 break;
 635         case HDMI_AUD_MCLK_384FS:
 636                 val |= CFG5_FS384;
 637                 break;
 638         case HDMI_AUD_MCLK_512FS:
 639                 val |= CFG5_FS512;
 640                 break;
 641         case HDMI_AUD_MCLK_768FS:
 642                 val |= CFG5_FS768;
 643                 break;
 644         default:
 645                 val |= CFG5_FS256;
 646                 break;
 647         }
 648         mtk_hdmi_write(hdmi, GRL_CFG5, val);
 649 }
 650
 651 struct hdmi_acr_n {
 652         unsigned int clock;
 653         unsigned int n[3];
 654 };
 655
 656 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
 657 static const struct hdmi_acr_n hdmi_rec_n_table[] = {
 658         /* Clock, N: 32kHz 44.1kHz 48kHz */
 659         {  25175, {  4576,  7007,  6864 } },
 660         {  74176, { 11648, 17836, 11648 } },
 661         { 148352, { 11648,  8918,  5824 } },
 662         { 296703, {  5824,  4459,  5824 } },
 663         { 297000, {  3072,  4704,  5120 } },
 664         {      0, {  4096,  6272,  6144 } }, /* all other TMDS clocks */
 665 };
 666
 667 /**
 668  * hdmi_recommended_n() - Return N value recommended by HDMI specification
 669  * @freq: audio sample rate in Hz
 670  * @clock: rounded TMDS clock in kHz
 671  */
 672 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
 673 {
 674         const struct hdmi_acr_n *recommended;
 675         unsigned int i;
 676
 677         for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
 678                 if (clock == hdmi_rec_n_table[i].clock)
 679                         break;
 680         }
 681         recommended = hdmi_rec_n_table + i;
 682
 683         switch (freq) {
 684         case 32000:
 685                 return recommended->n[0];
 686         case 44100:
 687                 return recommended->n[1];
 688         case 48000:
 689                 return recommended->n[2];
 690         case 88200:
 691                 return recommended->n[1] * 2;
 692         case 96000:
 693                 return recommended->n[2] * 2;
 694         case 176400:
 695                 return recommended->n[1] * 4;
 696         case 192000:
 697                 return recommended->n[2] * 4;
 698         default:
 699                 return (128 * freq) / 1000;
 700         }
 701 }
 702
 703 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
 704 {
 705         switch (clock) {
 706         case 25175:
 707                 return 25174825;        /* 25.2/1.001 MHz */
 708         case 74176:
 709                 return 74175824;        /* 74.25/1.001 MHz */
 710         case 148352:
 711                 return 148351648;       /* 148.5/1.001 MHz */
 712         case 296703:
 713                 return 296703297;       /* 297/1.001 MHz */
 714         default:
 715                 return clock * 1000;
 716         }
 717 }
 718
 719 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
 720                                       unsigned int tmds_clock, unsigned int n)
 721 {
 722         return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
 723                                      128 * audio_sample_rate);
 724 }
 725
 726 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
 727                                     unsigned int cts)
 728 {
 729         unsigned char val[NCTS_BYTES];
 730         int i;
 731
 732         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 733         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 734         mtk_hdmi_write(hdmi, GRL_NCTS, 0);
 735         memset(val, 0, sizeof(val));
 736
 737         val[0] = (cts >> 24) & 0xff;
 738         val[1] = (cts >> 16) & 0xff;
 739         val[2] = (cts >> 8) & 0xff;
 740         val[3] = cts & 0xff;
 741
 742         val[4] = (n >> 16) & 0xff;
 743         val[5] = (n >> 8) & 0xff;
 744         val[6] = n & 0xff;
 745
 746         for (i = 0; i < NCTS_BYTES; i++)
 747                 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
 748 }
 749
 750 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
 751                                      unsigned int sample_rate,
 752                                      unsigned int clock)
 753 {
 754         unsigned int n, cts;
 755
 756         n = hdmi_recommended_n(sample_rate, clock);
 757         cts = hdmi_expected_cts(sample_rate, clock, n);
 758
 759         dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
 760                 __func__, sample_rate, clock, n, cts);
 761
 762         mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
 763                       AUDIO_I2S_NCTS_SEL);
 764         do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
 765 }
 766
 767 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
 768 {
 769         switch (channel_type) {
 770         case HDMI_AUD_CHAN_TYPE_1_0:
 771         case HDMI_AUD_CHAN_TYPE_1_1:
 772         case HDMI_AUD_CHAN_TYPE_2_0:
 773                 return 2;
 774         case HDMI_AUD_CHAN_TYPE_2_1:
 775         case HDMI_AUD_CHAN_TYPE_3_0:
 776                 return 3;
 777         case HDMI_AUD_CHAN_TYPE_3_1:
 778         case HDMI_AUD_CHAN_TYPE_4_0:
 779         case HDMI_AUD_CHAN_TYPE_3_0_LRS:
 780                 return 4;
 781         case HDMI_AUD_CHAN_TYPE_4_1:
 782         case HDMI_AUD_CHAN_TYPE_5_0:
 783         case HDMI_AUD_CHAN_TYPE_3_1_LRS:
 784         case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
 785                 return 5;
 786         case HDMI_AUD_CHAN_TYPE_5_1:
 787         case HDMI_AUD_CHAN_TYPE_6_0:
 788         case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
 789         case HDMI_AUD_CHAN_TYPE_6_0_CS:
 790         case HDMI_AUD_CHAN_TYPE_6_0_CH:
 791         case HDMI_AUD_CHAN_TYPE_6_0_OH:
 792         case HDMI_AUD_CHAN_TYPE_6_0_CHR:
 793                 return 6;
 794         case HDMI_AUD_CHAN_TYPE_6_1:
 795         case HDMI_AUD_CHAN_TYPE_6_1_CS:
 796         case HDMI_AUD_CHAN_TYPE_6_1_CH:
 797         case HDMI_AUD_CHAN_TYPE_6_1_OH:
 798         case HDMI_AUD_CHAN_TYPE_6_1_CHR:
 799         case HDMI_AUD_CHAN_TYPE_7_0:
 800         case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
 801         case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
 802         case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
 803         case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
 804         case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
 805         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
 806         case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
 807         case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
 808         case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
 809         case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
 810         case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
 811         case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
 812         case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
 813         case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
 814         case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
 815                 return 7;
 816         case HDMI_AUD_CHAN_TYPE_7_1:
 817         case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
 818         case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
 819         case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
 820         case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
 821         case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
 822         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
 823         case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
 824         case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
 825         case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
 826         case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
 827         case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
 828         case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
 829         case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
 830         case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
 831                 return 8;
 832         default:
 833                 return 2;
 834         }
 835 }
 836
 837 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
 838 {
 839         unsigned long rate;
 840         int ret;
 841
 842         /* The DPI driver already should have set TVDPLL to the correct rate */
 843         ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
 844         if (ret) {
 845                 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
 846                         ret);
 847                 return ret;
 848         }
 849
 850         rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
 851
 852         if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
 853                 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
 854                          rate);
 855         else
 856                 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
 857
 858         mtk_hdmi_hw_config_sys(hdmi);
 859         mtk_hdmi_hw_set_deep_color_mode(hdmi);
 860         return 0;
 861 }
 862
 863 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
 864                                             struct drm_display_mode *mode)
 865 {
 866         mtk_hdmi_hw_reset(hdmi);
 867         mtk_hdmi_hw_enable_notice(hdmi, true);
 868         mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
 869         mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
 870         mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
 871
 872         mtk_hdmi_hw_msic_setting(hdmi, mode);
 873 }
 874
 875
 876 static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
 877 {
 878         enum hdmi_aud_channel_type chan_type;
 879         u8 chan_count;
 880         bool dst;
 881
 882         mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
 883         mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
 884
 885         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
 886             hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
 887                 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 888         } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
 889                 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
 890         }
 891
 892         mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
 893         mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
 894
 895         dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
 896                (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
 897         mtk_hdmi_hw_audio_config(hdmi, dst);
 898
 899         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
 900                 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
 901         else
 902                 chan_type = hdmi->aud_param.aud_input_chan_type;
 903         chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
 904         mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
 905         mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
 906 }
 907
 908 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
 909                                 struct drm_display_mode *display_mode)
 910 {
 911         unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
 912
 913         mtk_hdmi_hw_ncts_enable(hdmi, false);
 914         mtk_hdmi_hw_aud_src_disable(hdmi);
 915         mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
 916
 917         if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
 918                 switch (sample_rate) {
 919                 case 32000:
 920                 case 44100:
 921                 case 48000:
 922                 case 88200:
 923                 case 96000:
 924                         break;
 925                 default:
 926                         return -EINVAL;
 927                 }
 928                 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
 929         } else {
 930                 switch (sample_rate) {
 931                 case 32000:
 932                 case 44100:
 933                 case 48000:
 934                         break;
 935                 default:
 936                         return -EINVAL;
 937                 }
 938                 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
 939         }
 940
 941         mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
 942
 943         mtk_hdmi_hw_aud_src_reenable(hdmi);
 944         return 0;
 945 }
 946
 947 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
 948                                       struct drm_display_mode *display_mode)
 949 {
 950         mtk_hdmi_hw_aud_mute(hdmi);
 951         mtk_hdmi_hw_send_aud_packet(hdmi, false);
 952
 953         mtk_hdmi_aud_set_input(hdmi);
 954         mtk_hdmi_aud_set_src(hdmi, display_mode);
 955         mtk_hdmi_hw_aud_set_channel_status(hdmi,
 956                         hdmi->aud_param.codec_params.iec.status);
 957
 958         usleep_range(50, 100);
 959
 960         mtk_hdmi_hw_ncts_enable(hdmi, true);
 961         mtk_hdmi_hw_send_aud_packet(hdmi, true);
 962         mtk_hdmi_hw_aud_unmute(hdmi);
 963         return 0;
 964 }
 965
 966 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
 967                                         struct drm_display_mode *mode)
 968 {
 969         struct hdmi_avi_infoframe frame;
 970         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 971         ssize_t err;
 972
 973         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
 974                                                        hdmi->curr_conn, mode);
 975         if (err < 0) {
 976                 dev_err(hdmi->dev,
 977                         "Failed to get AVI infoframe from mode: %zd\n", err);
 978                 return err;
 979         }
 980
 981         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 982         if (err < 0) {
 983                 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
 984                 return err;
 985         }
 986
 987         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
 988         return 0;
 989 }
 990
 991 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
 992                                         const char *vendor,
 993                                         const char *product)
 994 {
 995         struct hdmi_spd_infoframe frame;
 996         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
 997         ssize_t err;
 998
 999         err = hdmi_spd_infoframe_init(&frame, vendor, product);
1000         if (err < 0) {
1001                 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1002                         err);
1003                 return err;
1004         }
1005
1006         err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1007         if (err < 0) {
1008                 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1009                 return err;
1010         }
1011
1012         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1013         return 0;
1014 }
1015
1016 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1017 {
1018         struct hdmi_audio_infoframe frame;
1019         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
1020         ssize_t err;
1021
1022         err = hdmi_audio_infoframe_init(&frame);
1023         if (err < 0) {
1024                 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1025                         err);
1026                 return err;
1027         }
1028
1029         frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1030         frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1031         frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1032         frame.channels = mtk_hdmi_aud_get_chnl_count(
1033                                         hdmi->aud_param.aud_input_chan_type);
1034
1035         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1036         if (err < 0) {
1037                 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1038                         err);
1039                 return err;
1040         }
1041
1042         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1043         return 0;
1044 }
1045
1046 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1047                                                 struct drm_display_mode *mode)
1048 {
1049         struct hdmi_vendor_infoframe frame;
1050         u8 buffer[10];
1051         ssize_t err;
1052
1053         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1054                                                           hdmi->curr_conn, mode);
1055         if (err) {
1056                 dev_err(hdmi->dev,
1057                         "Failed to get vendor infoframe from mode: %zd\n", err);
1058                 return err;
1059         }
1060
1061         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1062         if (err < 0) {
1063                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1064                         err);
1065                 return err;
1066         }
1067
1068         mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1069         return 0;
1070 }
1071
1072 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1073 {
1074         struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1075
1076         hdmi->csp = HDMI_COLORSPACE_RGB;
1077         aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1078         aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1079         aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1080         aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1081         aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1082         aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1083
1084         return 0;
1085 }
1086
1087 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1088 {
1089         mtk_hdmi_hw_send_aud_packet(hdmi, true);
1090         hdmi->audio_enable = true;
1091 }
1092
1093 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1094 {
1095         mtk_hdmi_hw_send_aud_packet(hdmi, false);
1096         hdmi->audio_enable = false;
1097 }
1098
1099 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1100                                     struct hdmi_audio_param *param)
1101 {
1102         if (!hdmi->audio_enable) {
1103                 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1104                 return -EINVAL;
1105         }
1106         dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1107                 param->aud_codec, param->aud_input_type,
1108                 param->aud_input_chan_type, param->codec_params.sample_rate);
1109         memcpy(&hdmi->aud_param, param, sizeof(*param));
1110         return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1111 }
1112
1113 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1114                                             struct drm_display_mode *mode)
1115 {
1116         int ret;
1117
1118         mtk_hdmi_hw_vid_black(hdmi, true);
1119         mtk_hdmi_hw_aud_mute(hdmi);
1120         mtk_hdmi_hw_send_av_mute(hdmi);
1121         phy_power_off(hdmi->phy);
1122
1123         ret = mtk_hdmi_video_change_vpll(hdmi,
1124                                          mode->clock * 1000);
1125         if (ret) {
1126                 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1127                 return ret;
1128         }
1129         mtk_hdmi_video_set_display_mode(hdmi, mode);
1130
1131         phy_power_on(hdmi->phy);
1132         mtk_hdmi_aud_output_config(hdmi, mode);
1133
1134         mtk_hdmi_hw_vid_black(hdmi, false);
1135         mtk_hdmi_hw_aud_unmute(hdmi);
1136         mtk_hdmi_hw_send_av_unmute(hdmi);
1137
1138         return 0;
1139 }
1140
1141 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1142         [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1143         [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1144         [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1145         [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1146 };
1147
1148 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1149                                 struct device_node *np)
1150 {
1151         int i;
1152
1153         for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1154                 hdmi->clk[i] = of_clk_get_by_name(np,
1155                                                   mtk_hdmi_clk_names[i]);
1156                 if (IS_ERR(hdmi->clk[i]))
1157                         return PTR_ERR(hdmi->clk[i]);
1158         }
1159         return 0;
1160 }
1161
1162 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1163 {
1164         int ret;
1165
1166         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1167         if (ret)
1168                 return ret;
1169
1170         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1171         if (ret)
1172                 goto err;
1173
1174         return 0;
1175 err:
1176         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1177         return ret;
1178 }
1179
1180 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1181 {
1182         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1183         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1184 }
1185
1186 static enum drm_connector_status
1187 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
1188 {
1189         bool connected;
1190
1191         mutex_lock(&hdmi->update_plugged_status_lock);
1192         connected = mtk_cec_hpd_high(hdmi->cec_dev);
1193         if (hdmi->plugged_cb && hdmi->codec_dev)
1194                 hdmi->plugged_cb(hdmi->codec_dev, connected);
1195         mutex_unlock(&hdmi->update_plugged_status_lock);
1196
1197         return connected ?
1198                connector_status_connected : connector_status_disconnected;
1199 }
1200
1201 static enum drm_connector_status mtk_hdmi_detect(struct mtk_hdmi *hdmi)
1202 {
1203         return mtk_hdmi_update_plugged_status(hdmi);
1204 }
1205
1206 static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1207                                       const struct drm_display_info *info,
1208                                       const struct drm_display_mode *mode)
1209 {
1210         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1211         struct drm_bridge *next_bridge;
1212
1213         dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1214                 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1215                 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1216
1217         next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge);
1218         if (next_bridge) {
1219                 struct drm_display_mode adjusted_mode;
1220
1221                 drm_mode_copy(&adjusted_mode, mode);
1222                 if (!drm_bridge_chain_mode_fixup(next_bridge, mode,
1223                                                  &adjusted_mode))
1224                         return MODE_BAD;
1225         }
1226
1227         if (hdmi->conf) {
1228                 if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
1229                         return MODE_BAD;
1230
1231                 if (hdmi->conf->max_mode_clock &&
1232                     mode->clock > hdmi->conf->max_mode_clock)
1233                         return MODE_CLOCK_HIGH;
1234         }
1235
1236         if (mode->clock < 27000)
1237                 return MODE_CLOCK_LOW;
1238         if (mode->clock > 297000)
1239                 return MODE_CLOCK_HIGH;
1240
1241         return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1242 }
1243
1244 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1245 {
1246         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1247
1248         if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) {
1249                 static enum drm_connector_status status;
1250
1251                 status = mtk_hdmi_detect(hdmi);
1252                 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1253                 drm_bridge_hpd_notify(&hdmi->bridge, status);
1254         }
1255 }
1256
1257 /*
1258  * Bridge callbacks
1259  */
1260
1261 static enum drm_connector_status mtk_hdmi_bridge_detect(struct drm_bridge *bridge)
1262 {
1263         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1264
1265         return mtk_hdmi_detect(hdmi);
1266 }
1267
1268 static struct edid *mtk_hdmi_bridge_get_edid(struct drm_bridge *bridge,
1269                                              struct drm_connector *connector)
1270 {
1271         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1272         struct edid *edid;
1273
1274         if (!hdmi->ddc_adpt)
1275                 return NULL;
1276         edid = drm_get_edid(connector, hdmi->ddc_adpt);
1277         if (!edid)
1278                 return NULL;
1279         hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1280         return edid;
1281 }
1282
1283 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
1284                                   enum drm_bridge_attach_flags flags)
1285 {
1286         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1287         int ret;
1288
1289         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
1290                 DRM_ERROR("%s: The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n",
1291                           __func__);
1292                 return -EINVAL;
1293         }
1294
1295         if (hdmi->next_bridge) {
1296                 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1297                                         bridge, flags);
1298                 if (ret)
1299                         return ret;
1300         }
1301
1302         mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1303
1304         return 0;
1305 }
1306
1307 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1308                                        const struct drm_display_mode *mode,
1309                                        struct drm_display_mode *adjusted_mode)
1310 {
1311         return true;
1312 }
1313
1314 static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
1315                                            struct drm_bridge_state *old_bridge_state)
1316 {
1317         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1318
1319         if (!hdmi->enabled)
1320                 return;
1321
1322         phy_power_off(hdmi->phy);
1323         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1324         clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1325
1326         hdmi->curr_conn = NULL;
1327
1328         hdmi->enabled = false;
1329 }
1330
1331 static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
1332                                                 struct drm_bridge_state *old_state)
1333 {
1334         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1335
1336         if (!hdmi->powered)
1337                 return;
1338
1339         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1340         mtk_hdmi_hw_make_reg_writable(hdmi, false);
1341
1342         hdmi->powered = false;
1343 }
1344
1345 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1346                                 const struct drm_display_mode *mode,
1347                                 const struct drm_display_mode *adjusted_mode)
1348 {
1349         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1350
1351         dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1352                 adjusted_mode->name, adjusted_mode->hdisplay);
1353         dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1354                 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1355                 adjusted_mode->htotal);
1356         dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1357                 adjusted_mode->hskew, adjusted_mode->vdisplay);
1358         dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1359                 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1360                 adjusted_mode->vtotal);
1361         dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1362                 adjusted_mode->vscan, adjusted_mode->flags);
1363
1364         drm_mode_copy(&hdmi->mode, adjusted_mode);
1365 }
1366
1367 static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1368                                               struct drm_bridge_state *old_state)
1369 {
1370         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1371
1372         mtk_hdmi_hw_make_reg_writable(hdmi, true);
1373         mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1374
1375         hdmi->powered = true;
1376 }
1377
1378 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1379                                     struct drm_display_mode *mode)
1380 {
1381         mtk_hdmi_setup_audio_infoframe(hdmi);
1382         mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1383         mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1384         if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1385                 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1386 }
1387
1388 static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
1389                                           struct drm_bridge_state *old_state)
1390 {
1391         struct drm_atomic_state *state = old_state->base.state;
1392         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1393
1394         /* Retrieve the connector through the atomic state. */
1395         hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state,
1396                                                                    bridge->encoder);
1397
1398         mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1399         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1400         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1401         phy_power_on(hdmi->phy);
1402         mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1403
1404         hdmi->enabled = true;
1405 }
1406
1407 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1408         .mode_valid = mtk_hdmi_bridge_mode_valid,
1409         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1410         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1411         .atomic_reset = drm_atomic_helper_bridge_reset,
1412         .attach = mtk_hdmi_bridge_attach,
1413         .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1414         .atomic_disable = mtk_hdmi_bridge_atomic_disable,
1415         .atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable,
1416         .mode_set = mtk_hdmi_bridge_mode_set,
1417         .atomic_pre_enable = mtk_hdmi_bridge_atomic_pre_enable,
1418         .atomic_enable = mtk_hdmi_bridge_atomic_enable,
1419         .detect = mtk_hdmi_bridge_detect,
1420         .get_edid = mtk_hdmi_bridge_get_edid,
1421 };
1422
1423 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1424                                    struct platform_device *pdev)
1425 {
1426         struct device *dev = &pdev->dev;
1427         struct device_node *np = dev->of_node;
1428         struct device_node *cec_np, *remote, *i2c_np;
1429         struct platform_device *cec_pdev;
1430         struct regmap *regmap;
1431         struct resource *mem;
1432         int ret;
1433
1434         ret = mtk_hdmi_get_all_clk(hdmi, np);
1435         if (ret) {
1436                 if (ret != -EPROBE_DEFER)
1437                         dev_err(dev, "Failed to get clocks: %d\n", ret);
1438
1439                 return ret;
1440         }
1441
1442         /* The CEC module handles HDMI hotplug detection */
1443         cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1444         if (!cec_np) {
1445                 dev_err(dev, "Failed to find CEC node\n");
1446                 return -EINVAL;
1447         }
1448
1449         cec_pdev = of_find_device_by_node(cec_np);
1450         if (!cec_pdev) {
1451                 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1452                         cec_np);
1453                 of_node_put(cec_np);
1454                 return -EPROBE_DEFER;
1455         }
1456         of_node_put(cec_np);
1457         hdmi->cec_dev = &cec_pdev->dev;
1458
1459         /*
1460          * The mediatek,syscon-hdmi property contains a phandle link to the
1461          * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1462          * registers it contains.
1463          */
1464         regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1465         ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1466                                          &hdmi->sys_offset);
1467         if (IS_ERR(regmap))
1468                 ret = PTR_ERR(regmap);
1469         if (ret) {
1470                 dev_err(dev,
1471                         "Failed to get system configuration registers: %d\n",
1472                         ret);
1473                 goto put_device;
1474         }
1475         hdmi->sys_regmap = regmap;
1476
1477         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1478         hdmi->regs = devm_ioremap_resource(dev, mem);
1479         if (IS_ERR(hdmi->regs)) {
1480                 ret = PTR_ERR(hdmi->regs);
1481                 goto put_device;
1482         }
1483
1484         remote = of_graph_get_remote_node(np, 1, 0);
1485         if (!remote) {
1486                 ret = -EINVAL;
1487                 goto put_device;
1488         }
1489
1490         if (!of_device_is_compatible(remote, "hdmi-connector")) {
1491                 hdmi->next_bridge = of_drm_find_bridge(remote);
1492                 if (!hdmi->next_bridge) {
1493                         dev_err(dev, "Waiting for external bridge\n");
1494                         of_node_put(remote);
1495                         ret = -EPROBE_DEFER;
1496                         goto put_device;
1497                 }
1498         }
1499
1500         i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1501         if (!i2c_np) {
1502                 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1503                         remote);
1504                 of_node_put(remote);
1505                 ret = -EINVAL;
1506                 goto put_device;
1507         }
1508         of_node_put(remote);
1509
1510         hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1511         of_node_put(i2c_np);
1512         if (!hdmi->ddc_adpt) {
1513                 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1514                 ret = -EINVAL;
1515                 goto put_device;
1516         }
1517
1518         return 0;
1519 put_device:
1520         put_device(hdmi->cec_dev);
1521         return ret;
1522 }
1523
1524 /*
1525  * HDMI audio codec callbacks
1526  */
1527
1528 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1529                                     struct hdmi_codec_daifmt *daifmt,
1530                                     struct hdmi_codec_params *params)
1531 {
1532         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1533         struct hdmi_audio_param hdmi_params;
1534         unsigned int chan = params->cea.channels;
1535
1536         dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1537                 params->sample_rate, params->sample_width, chan);
1538
1539         if (!hdmi->bridge.encoder)
1540                 return -ENODEV;
1541
1542         switch (chan) {
1543         case 2:
1544                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1545                 break;
1546         case 4:
1547                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1548                 break;
1549         case 6:
1550                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1551                 break;
1552         case 8:
1553                 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1554                 break;
1555         default:
1556                 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1557                 return -EINVAL;
1558         }
1559
1560         switch (params->sample_rate) {
1561         case 32000:
1562         case 44100:
1563         case 48000:
1564         case 88200:
1565         case 96000:
1566         case 176400:
1567         case 192000:
1568                 break;
1569         default:
1570                 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1571                         params->sample_rate);
1572                 return -EINVAL;
1573         }
1574
1575         switch (daifmt->fmt) {
1576         case HDMI_I2S:
1577                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1578                 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1579                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1580                 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1581                 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1582                 break;
1583         case HDMI_SPDIF:
1584                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1585                 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1586                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1587                 break;
1588         default:
1589                 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1590                         daifmt->fmt);
1591                 return -EINVAL;
1592         }
1593
1594         memcpy(&hdmi_params.codec_params, params,
1595                sizeof(hdmi_params.codec_params));
1596
1597         mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1598
1599         return 0;
1600 }
1601
1602 static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1603 {
1604         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1605
1606         mtk_hdmi_audio_enable(hdmi);
1607
1608         return 0;
1609 }
1610
1611 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1612 {
1613         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1614
1615         mtk_hdmi_audio_disable(hdmi);
1616 }
1617
1618 static int
1619 mtk_hdmi_audio_mute(struct device *dev, void *data,
1620                     bool enable, int direction)
1621 {
1622         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1623
1624         if (enable)
1625                 mtk_hdmi_hw_aud_mute(hdmi);
1626         else
1627                 mtk_hdmi_hw_aud_unmute(hdmi);
1628
1629         return 0;
1630 }
1631
1632 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1633 {
1634         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1635
1636         if (hdmi->enabled)
1637                 memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
1638         else
1639                 memset(buf, 0, len);
1640         return 0;
1641 }
1642
1643 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
1644                                           hdmi_codec_plugged_cb fn,
1645                                           struct device *codec_dev)
1646 {
1647         struct mtk_hdmi *hdmi = data;
1648
1649         mutex_lock(&hdmi->update_plugged_status_lock);
1650         hdmi->plugged_cb = fn;
1651         hdmi->codec_dev = codec_dev;
1652         mutex_unlock(&hdmi->update_plugged_status_lock);
1653
1654         mtk_hdmi_update_plugged_status(hdmi);
1655
1656         return 0;
1657 }
1658
1659 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1660         .hw_params = mtk_hdmi_audio_hw_params,
1661         .audio_startup = mtk_hdmi_audio_startup,
1662         .audio_shutdown = mtk_hdmi_audio_shutdown,
1663         .mute_stream = mtk_hdmi_audio_mute,
1664         .get_eld = mtk_hdmi_audio_get_eld,
1665         .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
1666         .no_capture_mute = 1,
1667 };
1668
1669 static int mtk_hdmi_register_audio_driver(struct device *dev)
1670 {
1671         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1672         struct hdmi_codec_pdata codec_data = {
1673                 .ops = &mtk_hdmi_audio_codec_ops,
1674                 .max_i2s_channels = 2,
1675                 .i2s = 1,
1676                 .data = hdmi,
1677         };
1678         struct platform_device *pdev;
1679
1680         pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1681                                              PLATFORM_DEVID_AUTO, &codec_data,
1682                                              sizeof(codec_data));
1683         if (IS_ERR(pdev))
1684                 return PTR_ERR(pdev);
1685
1686         DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1687         return 0;
1688 }
1689
1690 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1691 {
1692         struct mtk_hdmi *hdmi;
1693         struct device *dev = &pdev->dev;
1694         int ret;
1695
1696         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1697         if (!hdmi)
1698                 return -ENOMEM;
1699
1700         hdmi->dev = dev;
1701         hdmi->conf = of_device_get_match_data(dev);
1702
1703         ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1704         if (ret)
1705                 return ret;
1706
1707         hdmi->phy = devm_phy_get(dev, "hdmi");
1708         if (IS_ERR(hdmi->phy)) {
1709                 ret = PTR_ERR(hdmi->phy);
1710                 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1711                 return ret;
1712         }
1713
1714         mutex_init(&hdmi->update_plugged_status_lock);
1715         platform_set_drvdata(pdev, hdmi);
1716
1717         ret = mtk_hdmi_output_init(hdmi);
1718         if (ret) {
1719                 dev_err(dev, "Failed to initialize hdmi output\n");
1720                 return ret;
1721         }
1722
1723         ret = mtk_hdmi_register_audio_driver(dev);
1724         if (ret) {
1725                 dev_err(dev, "Failed to register audio driver: %d\n", ret);
1726                 return ret;
1727         }
1728
1729         hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1730         hdmi->bridge.of_node = pdev->dev.of_node;
1731         hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
1732                          | DRM_BRIDGE_OP_HPD;
1733         hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1734         drm_bridge_add(&hdmi->bridge);
1735
1736         ret = mtk_hdmi_clk_enable_audio(hdmi);
1737         if (ret) {
1738                 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1739                 goto err_bridge_remove;
1740         }
1741
1742         return 0;
1743
1744 err_bridge_remove:
1745         drm_bridge_remove(&hdmi->bridge);
1746         return ret;
1747 }
1748
1749 static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1750 {
1751         struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1752
1753         drm_bridge_remove(&hdmi->bridge);
1754         mtk_hdmi_clk_disable_audio(hdmi);
1755         return 0;
1756 }
1757
1758 #ifdef CONFIG_PM_SLEEP
1759 static int mtk_hdmi_suspend(struct device *dev)
1760 {
1761         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1762
1763         mtk_hdmi_clk_disable_audio(hdmi);
1764
1765         return 0;
1766 }
1767
1768 static int mtk_hdmi_resume(struct device *dev)
1769 {
1770         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1771         int ret = 0;
1772
1773         ret = mtk_hdmi_clk_enable_audio(hdmi);
1774         if (ret) {
1775                 dev_err(dev, "hdmi resume failed!\n");
1776                 return ret;
1777         }
1778
1779         return 0;
1780 }
1781 #endif
1782 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1783                          mtk_hdmi_suspend, mtk_hdmi_resume);
1784
1785 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
1786         .tz_disabled = true,
1787 };
1788
1789 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
1790         .max_mode_clock = 148500,
1791         .cea_modes_only = true,
1792 };
1793
1794 static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1795         { .compatible = "mediatek,mt2701-hdmi",
1796           .data = &mtk_hdmi_conf_mt2701,
1797         },
1798         { .compatible = "mediatek,mt8167-hdmi",
1799           .data = &mtk_hdmi_conf_mt8167,
1800         },
1801         { .compatible = "mediatek,mt8173-hdmi",
1802         },
1803         {}
1804 };
1805 MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_of_ids);
1806
1807 static struct platform_driver mtk_hdmi_driver = {
1808         .probe = mtk_drm_hdmi_probe,
1809         .remove = mtk_drm_hdmi_remove,
1810         .driver = {
1811                 .name = "mediatek-drm-hdmi",
1812                 .of_match_table = mtk_drm_hdmi_of_ids,
1813                 .pm = &mtk_hdmi_pm_ops,
1814         },
1815 };
1816
1817 static struct platform_driver * const mtk_hdmi_drivers[] = {
1818         &mtk_hdmi_ddc_driver,
1819         &mtk_cec_driver,
1820         &mtk_hdmi_driver,
1821 };
1822
1823 static int __init mtk_hdmitx_init(void)
1824 {
1825         return platform_register_drivers(mtk_hdmi_drivers,
1826                                          ARRAY_SIZE(mtk_hdmi_drivers));
1827 }
1828
1829 static void __exit mtk_hdmitx_exit(void)
1830 {
1831         platform_unregister_drivers(mtk_hdmi_drivers,
1832                                     ARRAY_SIZE(mtk_hdmi_drivers));
1833 }
1834
1835 module_init(mtk_hdmitx_init);
1836 module_exit(mtk_hdmitx_exit);
1837
1838 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1839 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1840 MODULE_LICENSE("GPL v2");