drivers/gpu/drm/mediatek/mtk_drm_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/mailbox_controller.h>
   9 #include <linux/pm_runtime.h>
  10 #include <linux/soc/mediatek/mtk-cmdq.h>
  11 #include <linux/soc/mediatek/mtk-mmsys.h>
  12 #include <linux/soc/mediatek/mtk-mutex.h>
  13
  14 #include <asm/barrier.h>
  15 #include <soc/mediatek/smi.h>
  16
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20 #include <drm/drm_probe_helper.h>
  21 #include <drm/drm_vblank.h>
  22
  23 #include "mtk_drm_drv.h"
  24 #include "mtk_drm_crtc.h"
  25 #include "mtk_drm_ddp_comp.h"
  26 #include "mtk_drm_gem.h"
  27 #include "mtk_drm_plane.h"
  28
  29 /*
  30  * struct mtk_drm_crtc - MediaTek specific crtc structure.
  31  * @base: crtc object.
  32  * @enabled: records whether crtc_enable succeeded
  33  * @planes: array of 4 drm_plane structures, one for each overlay plane
  34  * @pending_planes: whether any plane has pending changes to be applied
  35  * @mmsys_dev: pointer to the mmsys device for configuration registers
  36  * @mutex: handle to one of the ten disp_mutex streams
  37  * @ddp_comp_nr: number of components in ddp_comp
  38  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
  39  *
  40  * TODO: Needs update: this header is missing a bunch of member descriptions.
  41  */
  42 struct mtk_drm_crtc {
  43         struct drm_crtc                 base;
  44         bool                            enabled;
  45
  46         bool                            pending_needs_vblank;
  47         struct drm_pending_vblank_event *event;
  48
  49         struct drm_plane                *planes;
  50         unsigned int                    layer_nr;
  51         bool                            pending_planes;
  52         bool                            pending_async_planes;
  53
  54 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  55         struct mbox_client              cmdq_cl;
  56         struct mbox_chan                *cmdq_chan;
  57         u32                             cmdq_event;
  58 #endif
  59
  60         struct device                   *mmsys_dev;
  61         struct mtk_mutex                *mutex;
  62         unsigned int                    ddp_comp_nr;
  63         struct mtk_ddp_comp             **ddp_comp;
  64
  65         /* lock for display hardware access */
  66         struct mutex                    hw_lock;
  67         bool                            config_updating;
  68 };
  69
  70 struct mtk_crtc_state {
  71         struct drm_crtc_state           base;
  72
  73         bool                            pending_config;
  74         unsigned int                    pending_width;
  75         unsigned int                    pending_height;
  76         unsigned int                    pending_vrefresh;
  77 };
  78
  79 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
  80 {
  81         return container_of(c, struct mtk_drm_crtc, base);
  82 }
  83
  84 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
  85 {
  86         return container_of(s, struct mtk_crtc_state, base);
  87 }
  88
  89 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
  90 {
  91         struct drm_crtc *crtc = &mtk_crtc->base;
  92         unsigned long flags;
  93
  94         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  95         drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
  96         drm_crtc_vblank_put(crtc);
  97         mtk_crtc->event = NULL;
  98         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  99 }
 100
 101 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
 102 {
 103         drm_crtc_handle_vblank(&mtk_crtc->base);
 104         if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
 105                 mtk_drm_crtc_finish_page_flip(mtk_crtc);
 106                 mtk_crtc->pending_needs_vblank = false;
 107         }
 108 }
 109
 110 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
 111 {
 112         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 113
 114         mtk_mutex_put(mtk_crtc->mutex);
 115
 116         drm_crtc_cleanup(crtc);
 117 }
 118
 119 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
 120 {
 121         struct mtk_crtc_state *state;
 122
 123         if (crtc->state)
 124                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 125
 126         kfree(to_mtk_crtc_state(crtc->state));
 127         crtc->state = NULL;
 128
 129         state = kzalloc(sizeof(*state), GFP_KERNEL);
 130         if (state)
 131                 __drm_atomic_helper_crtc_reset(crtc, &state->base);
 132 }
 133
 134 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
 135 {
 136         struct mtk_crtc_state *state;
 137
 138         state = kzalloc(sizeof(*state), GFP_KERNEL);
 139         if (!state)
 140                 return NULL;
 141
 142         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 143
 144         WARN_ON(state->base.crtc != crtc);
 145         state->base.crtc = crtc;
 146
 147         return &state->base;
 148 }
 149
 150 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
 151                                        struct drm_crtc_state *state)
 152 {
 153         __drm_atomic_helper_crtc_destroy_state(state);
 154         kfree(to_mtk_crtc_state(state));
 155 }
 156
 157 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 158                                     const struct drm_display_mode *mode,
 159                                     struct drm_display_mode *adjusted_mode)
 160 {
 161         /* Nothing to do here, but this callback is mandatory. */
 162         return true;
 163 }
 164
 165 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 166 {
 167         struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
 168
 169         state->pending_width = crtc->mode.hdisplay;
 170         state->pending_height = crtc->mode.vdisplay;
 171         state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
 172         wmb();  /* Make sure the above parameters are set before update */
 173         state->pending_config = true;
 174 }
 175
 176 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
 177 {
 178         int ret;
 179         int i;
 180
 181         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 182                 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
 183                 if (ret) {
 184                         DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
 185                         goto err;
 186                 }
 187         }
 188
 189         return 0;
 190 err:
 191         while (--i >= 0)
 192                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 193         return ret;
 194 }
 195
 196 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
 197 {
 198         int i;
 199
 200         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 201                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 202 }
 203
 204 static
 205 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
 206                                                 struct drm_plane *plane,
 207                                                 unsigned int *local_layer)
 208 {
 209         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 210         struct mtk_ddp_comp *comp;
 211         int i, count = 0;
 212         unsigned int local_index = plane - mtk_crtc->planes;
 213
 214         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 215                 comp = mtk_crtc->ddp_comp[i];
 216                 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
 217                         *local_layer = local_index - count;
 218                         return comp;
 219                 }
 220                 count += mtk_ddp_comp_layer_nr(comp);
 221         }
 222
 223         WARN(1, "Failed to find component for plane %d\n", plane->index);
 224         return NULL;
 225 }
 226
 227 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 228 static struct cmdq_pkt *mtk_drm_cmdq_pkt_create(struct mbox_chan *chan, size_t size)
 229 {
 230         struct cmdq_pkt *pkt;
 231         struct device *dev;
 232         dma_addr_t dma_addr;
 233
 234         pkt = kzalloc(sizeof(*pkt), GFP_KERNEL);
 235         if (!pkt)
 236                 return ERR_PTR(-ENOMEM);
 237         pkt->va_base = kzalloc(size, GFP_KERNEL);
 238         if (!pkt->va_base) {
 239                 kfree(pkt);
 240                 return ERR_PTR(-ENOMEM);
 241         }
 242         pkt->buf_size = size;
 243
 244         dev = chan->mbox->dev;
 245         dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
 246                                   DMA_TO_DEVICE);
 247         if (dma_mapping_error(dev, dma_addr)) {
 248                 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
 249                 kfree(pkt->va_base);
 250                 kfree(pkt);
 251                 return ERR_PTR(-ENOMEM);
 252         }
 253
 254         pkt->pa_base = dma_addr;
 255
 256         return pkt;
 257 }
 258
 259 static void mtk_drm_cmdq_pkt_destroy(struct mbox_chan *chan, struct cmdq_pkt *pkt)
 260 {
 261         dma_unmap_single(chan->mbox->dev, pkt->pa_base, pkt->buf_size,
 262                          DMA_TO_DEVICE);
 263         kfree(pkt->va_base);
 264         kfree(pkt);
 265 }
 266
 267 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
 268 {
 269         struct mtk_drm_crtc *mtk_crtc = container_of(cl, struct mtk_drm_crtc, cmdq_cl);
 270         struct cmdq_cb_data *data = mssg;
 271
 272         mtk_drm_cmdq_pkt_destroy(mtk_crtc->cmdq_chan, data->pkt);
 273 }
 274 #endif
 275
 276 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
 277 {
 278         struct drm_crtc *crtc = &mtk_crtc->base;
 279         struct drm_connector *connector;
 280         struct drm_encoder *encoder;
 281         struct drm_connector_list_iter conn_iter;
 282         unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
 283         int ret;
 284         int i;
 285
 286         if (WARN_ON(!crtc->state))
 287                 return -EINVAL;
 288
 289         width = crtc->state->adjusted_mode.hdisplay;
 290         height = crtc->state->adjusted_mode.vdisplay;
 291         vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
 292
 293         drm_for_each_encoder(encoder, crtc->dev) {
 294                 if (encoder->crtc != crtc)
 295                         continue;
 296
 297                 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 298                 drm_for_each_connector_iter(connector, &conn_iter) {
 299                         if (connector->encoder != encoder)
 300                                 continue;
 301                         if (connector->display_info.bpc != 0 &&
 302                             bpc > connector->display_info.bpc)
 303                                 bpc = connector->display_info.bpc;
 304                 }
 305                 drm_connector_list_iter_end(&conn_iter);
 306         }
 307
 308         ret = pm_runtime_resume_and_get(crtc->dev->dev);
 309         if (ret < 0) {
 310                 DRM_ERROR("Failed to enable power domain: %d\n", ret);
 311                 return ret;
 312         }
 313
 314         ret = mtk_mutex_prepare(mtk_crtc->mutex);
 315         if (ret < 0) {
 316                 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
 317                 goto err_pm_runtime_put;
 318         }
 319
 320         ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
 321         if (ret < 0) {
 322                 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
 323                 goto err_mutex_unprepare;
 324         }
 325
 326         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 327                 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
 328                                       mtk_crtc->ddp_comp[i]->id,
 329                                       mtk_crtc->ddp_comp[i + 1]->id);
 330                 mtk_mutex_add_comp(mtk_crtc->mutex,
 331                                         mtk_crtc->ddp_comp[i]->id);
 332         }
 333         mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 334         mtk_mutex_enable(mtk_crtc->mutex);
 335
 336         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 337                 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
 338
 339                 if (i == 1)
 340                         mtk_ddp_comp_bgclr_in_on(comp);
 341
 342                 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
 343                 mtk_ddp_comp_start(comp);
 344         }
 345
 346         /* Initially configure all planes */
 347         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 348                 struct drm_plane *plane = &mtk_crtc->planes[i];
 349                 struct mtk_plane_state *plane_state;
 350                 struct mtk_ddp_comp *comp;
 351                 unsigned int local_layer;
 352
 353                 plane_state = to_mtk_plane_state(plane->state);
 354                 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
 355                 if (comp)
 356                         mtk_ddp_comp_layer_config(comp, local_layer,
 357                                                   plane_state, NULL);
 358         }
 359
 360         return 0;
 361
 362 err_mutex_unprepare:
 363         mtk_mutex_unprepare(mtk_crtc->mutex);
 364 err_pm_runtime_put:
 365         pm_runtime_put(crtc->dev->dev);
 366         return ret;
 367 }
 368
 369 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
 370 {
 371         struct drm_device *drm = mtk_crtc->base.dev;
 372         struct drm_crtc *crtc = &mtk_crtc->base;
 373         int i;
 374
 375         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 376                 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
 377                 if (i == 1)
 378                         mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
 379         }
 380
 381         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 382                 mtk_mutex_remove_comp(mtk_crtc->mutex,
 383                                            mtk_crtc->ddp_comp[i]->id);
 384         mtk_mutex_disable(mtk_crtc->mutex);
 385         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 386                 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
 387                                          mtk_crtc->ddp_comp[i]->id,
 388                                          mtk_crtc->ddp_comp[i + 1]->id);
 389                 mtk_mutex_remove_comp(mtk_crtc->mutex,
 390                                            mtk_crtc->ddp_comp[i]->id);
 391         }
 392         mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 393         mtk_crtc_ddp_clk_disable(mtk_crtc);
 394         mtk_mutex_unprepare(mtk_crtc->mutex);
 395
 396         pm_runtime_put(drm->dev);
 397
 398         if (crtc->state->event && !crtc->state->active) {
 399                 spin_lock_irq(&crtc->dev->event_lock);
 400                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 401                 crtc->state->event = NULL;
 402                 spin_unlock_irq(&crtc->dev->event_lock);
 403         }
 404 }
 405
 406 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
 407                                 struct cmdq_pkt *cmdq_handle)
 408 {
 409         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 410         struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
 411         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 412         unsigned int i;
 413         unsigned int local_layer;
 414
 415         /*
 416          * TODO: instead of updating the registers here, we should prepare
 417          * working registers in atomic_commit and let the hardware command
 418          * queue update module registers on vblank.
 419          */
 420         if (state->pending_config) {
 421                 mtk_ddp_comp_config(comp, state->pending_width,
 422                                     state->pending_height,
 423                                     state->pending_vrefresh, 0,
 424                                     cmdq_handle);
 425
 426                 state->pending_config = false;
 427         }
 428
 429         if (mtk_crtc->pending_planes) {
 430                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 431                         struct drm_plane *plane = &mtk_crtc->planes[i];
 432                         struct mtk_plane_state *plane_state;
 433
 434                         plane_state = to_mtk_plane_state(plane->state);
 435
 436                         if (!plane_state->pending.config)
 437                                 continue;
 438
 439                         comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
 440                                                           &local_layer);
 441
 442                         if (comp)
 443                                 mtk_ddp_comp_layer_config(comp, local_layer,
 444                                                           plane_state,
 445                                                           cmdq_handle);
 446                         plane_state->pending.config = false;
 447                 }
 448                 mtk_crtc->pending_planes = false;
 449         }
 450
 451         if (mtk_crtc->pending_async_planes) {
 452                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 453                         struct drm_plane *plane = &mtk_crtc->planes[i];
 454                         struct mtk_plane_state *plane_state;
 455
 456                         plane_state = to_mtk_plane_state(plane->state);
 457
 458                         if (!plane_state->pending.async_config)
 459                                 continue;
 460
 461                         comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
 462                                                           &local_layer);
 463
 464                         if (comp)
 465                                 mtk_ddp_comp_layer_config(comp, local_layer,
 466                                                           plane_state,
 467                                                           cmdq_handle);
 468                         plane_state->pending.async_config = false;
 469                 }
 470                 mtk_crtc->pending_async_planes = false;
 471         }
 472 }
 473
 474 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
 475                                        bool needs_vblank)
 476 {
 477 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 478         struct cmdq_pkt *cmdq_handle;
 479 #endif
 480         struct drm_crtc *crtc = &mtk_crtc->base;
 481         struct mtk_drm_private *priv = crtc->dev->dev_private;
 482         unsigned int pending_planes = 0, pending_async_planes = 0;
 483         int i;
 484
 485         mutex_lock(&mtk_crtc->hw_lock);
 486         mtk_crtc->config_updating = true;
 487         if (needs_vblank)
 488                 mtk_crtc->pending_needs_vblank = true;
 489
 490         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 491                 struct drm_plane *plane = &mtk_crtc->planes[i];
 492                 struct mtk_plane_state *plane_state;
 493
 494                 plane_state = to_mtk_plane_state(plane->state);
 495                 if (plane_state->pending.dirty) {
 496                         plane_state->pending.config = true;
 497                         plane_state->pending.dirty = false;
 498                         pending_planes |= BIT(i);
 499                 } else if (plane_state->pending.async_dirty) {
 500                         plane_state->pending.async_config = true;
 501                         plane_state->pending.async_dirty = false;
 502                         pending_async_planes |= BIT(i);
 503                 }
 504         }
 505         if (pending_planes)
 506                 mtk_crtc->pending_planes = true;
 507         if (pending_async_planes)
 508                 mtk_crtc->pending_async_planes = true;
 509
 510         if (priv->data->shadow_register) {
 511                 mtk_mutex_acquire(mtk_crtc->mutex);
 512                 mtk_crtc_ddp_config(crtc, NULL);
 513                 mtk_mutex_release(mtk_crtc->mutex);
 514         }
 515 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 516         if (mtk_crtc->cmdq_chan) {
 517                 mbox_flush(mtk_crtc->cmdq_chan, 2000);
 518                 cmdq_handle = mtk_drm_cmdq_pkt_create(mtk_crtc->cmdq_chan, PAGE_SIZE);
 519                 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 520                 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
 521                 mtk_crtc_ddp_config(crtc, cmdq_handle);
 522                 cmdq_pkt_finalize(cmdq_handle);
 523                 dma_sync_single_for_device(mtk_crtc->cmdq_chan->mbox->dev,
 524                                             cmdq_handle->pa_base,
 525                                             cmdq_handle->cmd_buf_size,
 526                                             DMA_TO_DEVICE);
 527                 mbox_send_message(mtk_crtc->cmdq_chan, cmdq_handle);
 528                 mbox_client_txdone(mtk_crtc->cmdq_chan, 0);
 529         }
 530 #endif
 531         mtk_crtc->config_updating = false;
 532         mutex_unlock(&mtk_crtc->hw_lock);
 533 }
 534
 535 static void mtk_crtc_ddp_irq(void *data)
 536 {
 537         struct drm_crtc *crtc = data;
 538         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 539         struct mtk_drm_private *priv = crtc->dev->dev_private;
 540
 541 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 542         if (!priv->data->shadow_register && !mtk_crtc->cmdq_chan)
 543 #else
 544         if (!priv->data->shadow_register)
 545 #endif
 546                 mtk_crtc_ddp_config(crtc, NULL);
 547
 548         mtk_drm_finish_page_flip(mtk_crtc);
 549 }
 550
 551 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
 552 {
 553         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 554         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 555
 556         mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
 557
 558         return 0;
 559 }
 560
 561 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
 562 {
 563         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 564         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 565
 566         mtk_ddp_comp_disable_vblank(comp);
 567 }
 568
 569 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
 570                              struct mtk_plane_state *state)
 571 {
 572         unsigned int local_layer;
 573         struct mtk_ddp_comp *comp;
 574
 575         comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
 576         if (comp)
 577                 return mtk_ddp_comp_layer_check(comp, local_layer, state);
 578         return 0;
 579 }
 580
 581 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
 582                                struct drm_atomic_state *state)
 583 {
 584         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 585         const struct drm_plane_helper_funcs *plane_helper_funcs =
 586                         plane->helper_private;
 587
 588         if (!mtk_crtc->enabled)
 589                 return;
 590
 591         plane_helper_funcs->atomic_update(plane, state);
 592         mtk_drm_crtc_update_config(mtk_crtc, false);
 593 }
 594
 595 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 596                                        struct drm_atomic_state *state)
 597 {
 598         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 599         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 600         int ret;
 601
 602         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 603
 604         ret = mtk_smi_larb_get(comp->larb_dev);
 605         if (ret) {
 606                 DRM_ERROR("Failed to get larb: %d\n", ret);
 607                 return;
 608         }
 609
 610         ret = mtk_crtc_ddp_hw_init(mtk_crtc);
 611         if (ret) {
 612                 mtk_smi_larb_put(comp->larb_dev);
 613                 return;
 614         }
 615
 616         drm_crtc_vblank_on(crtc);
 617         mtk_crtc->enabled = true;
 618 }
 619
 620 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 621                                         struct drm_atomic_state *state)
 622 {
 623         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 624         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 625         int i;
 626
 627         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 628         if (!mtk_crtc->enabled)
 629                 return;
 630
 631         /* Set all pending plane state to disabled */
 632         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 633                 struct drm_plane *plane = &mtk_crtc->planes[i];
 634                 struct mtk_plane_state *plane_state;
 635
 636                 plane_state = to_mtk_plane_state(plane->state);
 637                 plane_state->pending.enable = false;
 638                 plane_state->pending.config = true;
 639         }
 640         mtk_crtc->pending_planes = true;
 641
 642         mtk_drm_crtc_update_config(mtk_crtc, false);
 643         /* Wait for planes to be disabled */
 644         drm_crtc_wait_one_vblank(crtc);
 645
 646         drm_crtc_vblank_off(crtc);
 647         mtk_crtc_ddp_hw_fini(mtk_crtc);
 648         mtk_smi_larb_put(comp->larb_dev);
 649
 650         mtk_crtc->enabled = false;
 651 }
 652
 653 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 654                                       struct drm_atomic_state *state)
 655 {
 656         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 657                                                                           crtc);
 658         struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
 659         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 660
 661         if (mtk_crtc->event && mtk_crtc_state->base.event)
 662                 DRM_ERROR("new event while there is still a pending event\n");
 663
 664         if (mtk_crtc_state->base.event) {
 665                 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
 666                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 667                 mtk_crtc->event = mtk_crtc_state->base.event;
 668                 mtk_crtc_state->base.event = NULL;
 669         }
 670 }
 671
 672 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 673                                       struct drm_atomic_state *state)
 674 {
 675         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 676         int i;
 677
 678         if (crtc->state->color_mgmt_changed)
 679                 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 680                         mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
 681                         mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
 682                 }
 683         mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
 684 }
 685
 686 static const struct drm_crtc_funcs mtk_crtc_funcs = {
 687         .set_config             = drm_atomic_helper_set_config,
 688         .page_flip              = drm_atomic_helper_page_flip,
 689         .destroy                = mtk_drm_crtc_destroy,
 690         .reset                  = mtk_drm_crtc_reset,
 691         .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
 692         .atomic_destroy_state   = mtk_drm_crtc_destroy_state,
 693         .enable_vblank          = mtk_drm_crtc_enable_vblank,
 694         .disable_vblank         = mtk_drm_crtc_disable_vblank,
 695 };
 696
 697 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
 698         .mode_fixup     = mtk_drm_crtc_mode_fixup,
 699         .mode_set_nofb  = mtk_drm_crtc_mode_set_nofb,
 700         .atomic_begin   = mtk_drm_crtc_atomic_begin,
 701         .atomic_flush   = mtk_drm_crtc_atomic_flush,
 702         .atomic_enable  = mtk_drm_crtc_atomic_enable,
 703         .atomic_disable = mtk_drm_crtc_atomic_disable,
 704 };
 705
 706 static int mtk_drm_crtc_init(struct drm_device *drm,
 707                              struct mtk_drm_crtc *mtk_crtc,
 708                              unsigned int pipe)
 709 {
 710         struct drm_plane *primary = NULL;
 711         struct drm_plane *cursor = NULL;
 712         int i, ret;
 713
 714         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 715                 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
 716                         primary = &mtk_crtc->planes[i];
 717                 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
 718                         cursor = &mtk_crtc->planes[i];
 719         }
 720
 721         ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
 722                                         &mtk_crtc_funcs, NULL);
 723         if (ret)
 724                 goto err_cleanup_crtc;
 725
 726         drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
 727
 728         return 0;
 729
 730 err_cleanup_crtc:
 731         drm_crtc_cleanup(&mtk_crtc->base);
 732         return ret;
 733 }
 734
 735 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
 736                                         int comp_idx)
 737 {
 738         struct mtk_ddp_comp *comp;
 739
 740         if (comp_idx > 1)
 741                 return 0;
 742
 743         comp = mtk_crtc->ddp_comp[comp_idx];
 744         if (!comp->funcs)
 745                 return 0;
 746
 747         if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
 748                 return 0;
 749
 750         return mtk_ddp_comp_layer_nr(comp);
 751 }
 752
 753 static inline
 754 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
 755                                             unsigned int num_planes)
 756 {
 757         if (plane_idx == 0)
 758                 return DRM_PLANE_TYPE_PRIMARY;
 759         else if (plane_idx == (num_planes - 1))
 760                 return DRM_PLANE_TYPE_CURSOR;
 761         else
 762                 return DRM_PLANE_TYPE_OVERLAY;
 763
 764 }
 765
 766 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
 767                                          struct mtk_drm_crtc *mtk_crtc,
 768                                          int comp_idx, int pipe)
 769 {
 770         int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
 771         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
 772         int i, ret;
 773
 774         for (i = 0; i < num_planes; i++) {
 775                 ret = mtk_plane_init(drm_dev,
 776                                 &mtk_crtc->planes[mtk_crtc->layer_nr],
 777                                 BIT(pipe),
 778                                 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
 779                                                         num_planes),
 780                                 mtk_ddp_comp_supported_rotations(comp));
 781                 if (ret)
 782                         return ret;
 783
 784                 mtk_crtc->layer_nr++;
 785         }
 786         return 0;
 787 }
 788
 789 int mtk_drm_crtc_create(struct drm_device *drm_dev,
 790                         const enum mtk_ddp_comp_id *path, unsigned int path_len)
 791 {
 792         struct mtk_drm_private *priv = drm_dev->dev_private;
 793         struct device *dev = drm_dev->dev;
 794         struct mtk_drm_crtc *mtk_crtc;
 795         unsigned int num_comp_planes = 0;
 796         int pipe = priv->num_pipes;
 797         int ret;
 798         int i;
 799         bool has_ctm = false;
 800         uint gamma_lut_size = 0;
 801
 802         if (!path)
 803                 return 0;
 804
 805         for (i = 0; i < path_len; i++) {
 806                 enum mtk_ddp_comp_id comp_id = path[i];
 807                 struct device_node *node;
 808                 struct mtk_ddp_comp *comp;
 809
 810                 node = priv->comp_node[comp_id];
 811                 comp = &priv->ddp_comp[comp_id];
 812
 813                 if (!node) {
 814                         dev_info(dev,
 815                                  "Not creating crtc %d because component %d is disabled or missing\n",
 816                                  pipe, comp_id);
 817                         return 0;
 818                 }
 819
 820                 if (!comp->dev) {
 821                         dev_err(dev, "Component %pOF not initialized\n", node);
 822                         return -ENODEV;
 823                 }
 824         }
 825
 826         mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
 827         if (!mtk_crtc)
 828                 return -ENOMEM;
 829
 830         mtk_crtc->mmsys_dev = priv->mmsys_dev;
 831         mtk_crtc->ddp_comp_nr = path_len;
 832         mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
 833                                                 sizeof(*mtk_crtc->ddp_comp),
 834                                                 GFP_KERNEL);
 835         if (!mtk_crtc->ddp_comp)
 836                 return -ENOMEM;
 837
 838         mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
 839         if (IS_ERR(mtk_crtc->mutex)) {
 840                 ret = PTR_ERR(mtk_crtc->mutex);
 841                 dev_err(dev, "Failed to get mutex: %d\n", ret);
 842                 return ret;
 843         }
 844
 845         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 846                 enum mtk_ddp_comp_id comp_id = path[i];
 847                 struct mtk_ddp_comp *comp;
 848
 849                 comp = &priv->ddp_comp[comp_id];
 850                 mtk_crtc->ddp_comp[i] = comp;
 851
 852                 if (comp->funcs) {
 853                         if (comp->funcs->gamma_set)
 854                                 gamma_lut_size = MTK_LUT_SIZE;
 855
 856                         if (comp->funcs->ctm_set)
 857                                 has_ctm = true;
 858                 }
 859         }
 860
 861         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 862                 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
 863
 864         mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
 865                                         sizeof(struct drm_plane), GFP_KERNEL);
 866
 867         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 868                 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
 869                                                     pipe);
 870                 if (ret)
 871                         return ret;
 872         }
 873
 874         ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
 875         if (ret < 0)
 876                 return ret;
 877
 878         if (gamma_lut_size)
 879                 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
 880         drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
 881         priv->num_pipes++;
 882         mutex_init(&mtk_crtc->hw_lock);
 883
 884 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 885         mtk_crtc->cmdq_cl.dev = mtk_crtc->mmsys_dev;
 886         mtk_crtc->cmdq_cl.tx_block = false;
 887         mtk_crtc->cmdq_cl.knows_txdone = true;
 888         mtk_crtc->cmdq_cl.rx_callback = ddp_cmdq_cb;
 889         mtk_crtc->cmdq_chan =
 890                         mbox_request_channel(&mtk_crtc->cmdq_cl,
 891                                               drm_crtc_index(&mtk_crtc->base));
 892         if (IS_ERR(mtk_crtc->cmdq_chan)) {
 893                 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
 894                         drm_crtc_index(&mtk_crtc->base));
 895                 mtk_crtc->cmdq_chan = NULL;
 896         }
 897
 898         if (mtk_crtc->cmdq_chan) {
 899                 ret = of_property_read_u32_index(priv->mutex_node,
 900                                                  "mediatek,gce-events",
 901                                                  drm_crtc_index(&mtk_crtc->base),
 902                                                  &mtk_crtc->cmdq_event);
 903                 if (ret) {
 904                         dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
 905                                 drm_crtc_index(&mtk_crtc->base));
 906                         mbox_free_channel(mtk_crtc->cmdq_chan);
 907                         mtk_crtc->cmdq_chan = NULL;
 908                 }
 909         }
 910 #endif
 911         return 0;
 912 }