drivers/gpu/drm/mediatek/mtk_drm_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/mailbox_controller.h>
   9 #include <linux/pm_runtime.h>
  10 #include <linux/soc/mediatek/mtk-cmdq.h>
  11 #include <linux/soc/mediatek/mtk-mmsys.h>
  12 #include <linux/soc/mediatek/mtk-mutex.h>
  13
  14 #include <asm/barrier.h>
  15 #include <soc/mediatek/smi.h>
  16
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20 #include <drm/drm_probe_helper.h>
  21 #include <drm/drm_vblank.h>
  22
  23 #include "mtk_drm_drv.h"
  24 #include "mtk_drm_crtc.h"
  25 #include "mtk_drm_ddp_comp.h"
  26 #include "mtk_drm_gem.h"
  27 #include "mtk_drm_plane.h"
  28
  29 /*
  30  * struct mtk_drm_crtc - MediaTek specific crtc structure.
  31  * @base: crtc object.
  32  * @enabled: records whether crtc_enable succeeded
  33  * @planes: array of 4 drm_plane structures, one for each overlay plane
  34  * @pending_planes: whether any plane has pending changes to be applied
  35  * @mmsys_dev: pointer to the mmsys device for configuration registers
  36  * @mutex: handle to one of the ten disp_mutex streams
  37  * @ddp_comp_nr: number of components in ddp_comp
  38  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
  39  *
  40  * TODO: Needs update: this header is missing a bunch of member descriptions.
  41  */
  42 struct mtk_drm_crtc {
  43         struct drm_crtc                 base;
  44         bool                            enabled;
  45
  46         bool                            pending_needs_vblank;
  47         struct drm_pending_vblank_event *event;
  48
  49         struct drm_plane                *planes;
  50         unsigned int                    layer_nr;
  51         bool                            pending_planes;
  52         bool                            pending_async_planes;
  53
  54 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  55         struct mbox_client              cmdq_cl;
  56         struct mbox_chan                *cmdq_chan;
  57         struct cmdq_pkt                 cmdq_handle;
  58         u32                             cmdq_event;
  59         u32                             cmdq_vblank_cnt;
  60 #endif
  61
  62         struct device                   *mmsys_dev;
  63         struct mtk_mutex                *mutex;
  64         unsigned int                    ddp_comp_nr;
  65         struct mtk_ddp_comp             **ddp_comp;
  66
  67         /* lock for display hardware access */
  68         struct mutex                    hw_lock;
  69         bool                            config_updating;
  70 };
  71
  72 struct mtk_crtc_state {
  73         struct drm_crtc_state           base;
  74
  75         bool                            pending_config;
  76         unsigned int                    pending_width;
  77         unsigned int                    pending_height;
  78         unsigned int                    pending_vrefresh;
  79 };
  80
  81 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
  82 {
  83         return container_of(c, struct mtk_drm_crtc, base);
  84 }
  85
  86 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
  87 {
  88         return container_of(s, struct mtk_crtc_state, base);
  89 }
  90
  91 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
  92 {
  93         struct drm_crtc *crtc = &mtk_crtc->base;
  94         unsigned long flags;
  95
  96         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  97         drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
  98         drm_crtc_vblank_put(crtc);
  99         mtk_crtc->event = NULL;
 100         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 101 }
 102
 103 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
 104 {
 105         drm_crtc_handle_vblank(&mtk_crtc->base);
 106         if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
 107                 mtk_drm_crtc_finish_page_flip(mtk_crtc);
 108                 mtk_crtc->pending_needs_vblank = false;
 109         }
 110 }
 111
 112 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
 113 {
 114         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 115
 116         mtk_mutex_put(mtk_crtc->mutex);
 117
 118         drm_crtc_cleanup(crtc);
 119 }
 120
 121 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
 122 {
 123         struct mtk_crtc_state *state;
 124
 125         if (crtc->state)
 126                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 127
 128         kfree(to_mtk_crtc_state(crtc->state));
 129         crtc->state = NULL;
 130
 131         state = kzalloc(sizeof(*state), GFP_KERNEL);
 132         if (state)
 133                 __drm_atomic_helper_crtc_reset(crtc, &state->base);
 134 }
 135
 136 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
 137 {
 138         struct mtk_crtc_state *state;
 139
 140         state = kzalloc(sizeof(*state), GFP_KERNEL);
 141         if (!state)
 142                 return NULL;
 143
 144         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 145
 146         WARN_ON(state->base.crtc != crtc);
 147         state->base.crtc = crtc;
 148
 149         return &state->base;
 150 }
 151
 152 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
 153                                        struct drm_crtc_state *state)
 154 {
 155         __drm_atomic_helper_crtc_destroy_state(state);
 156         kfree(to_mtk_crtc_state(state));
 157 }
 158
 159 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 160                                     const struct drm_display_mode *mode,
 161                                     struct drm_display_mode *adjusted_mode)
 162 {
 163         /* Nothing to do here, but this callback is mandatory. */
 164         return true;
 165 }
 166
 167 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 168 {
 169         struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
 170
 171         state->pending_width = crtc->mode.hdisplay;
 172         state->pending_height = crtc->mode.vdisplay;
 173         state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
 174         wmb();  /* Make sure the above parameters are set before update */
 175         state->pending_config = true;
 176 }
 177
 178 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
 179 {
 180         int ret;
 181         int i;
 182
 183         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 184                 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
 185                 if (ret) {
 186                         DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
 187                         goto err;
 188                 }
 189         }
 190
 191         return 0;
 192 err:
 193         while (--i >= 0)
 194                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 195         return ret;
 196 }
 197
 198 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
 199 {
 200         int i;
 201
 202         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 203                 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
 204 }
 205
 206 static
 207 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
 208                                                 struct drm_plane *plane,
 209                                                 unsigned int *local_layer)
 210 {
 211         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 212         struct mtk_ddp_comp *comp;
 213         int i, count = 0;
 214         unsigned int local_index = plane - mtk_crtc->planes;
 215
 216         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 217                 comp = mtk_crtc->ddp_comp[i];
 218                 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
 219                         *local_layer = local_index - count;
 220                         return comp;
 221                 }
 222                 count += mtk_ddp_comp_layer_nr(comp);
 223         }
 224
 225         WARN(1, "Failed to find component for plane %d\n", plane->index);
 226         return NULL;
 227 }
 228
 229 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 230 static int mtk_drm_cmdq_pkt_create(struct mbox_chan *chan, struct cmdq_pkt *pkt,
 231                                     size_t size)
 232 {
 233         struct device *dev;
 234         dma_addr_t dma_addr;
 235
 236         pkt->va_base = kzalloc(size, GFP_KERNEL);
 237         if (!pkt->va_base) {
 238                 kfree(pkt);
 239                 return -ENOMEM;
 240         }
 241         pkt->buf_size = size;
 242
 243         dev = chan->mbox->dev;
 244         dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
 245                                   DMA_TO_DEVICE);
 246         if (dma_mapping_error(dev, dma_addr)) {
 247                 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
 248                 kfree(pkt->va_base);
 249                 kfree(pkt);
 250                 return -ENOMEM;
 251         }
 252
 253         pkt->pa_base = dma_addr;
 254
 255         return 0;
 256 }
 257
 258 static void mtk_drm_cmdq_pkt_destroy(struct mbox_chan *chan, struct cmdq_pkt *pkt)
 259 {
 260         dma_unmap_single(chan->mbox->dev, pkt->pa_base, pkt->buf_size,
 261                          DMA_TO_DEVICE);
 262         kfree(pkt->va_base);
 263         kfree(pkt);
 264 }
 265
 266 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
 267 {
 268         struct mtk_drm_crtc *mtk_crtc = container_of(cl, struct mtk_drm_crtc, cmdq_cl);
 269         struct cmdq_cb_data *data = mssg;
 270
 271         mtk_crtc->cmdq_vblank_cnt = 0;
 272         mtk_drm_cmdq_pkt_destroy(mtk_crtc->cmdq_chan, data->pkt);
 273 }
 274 #endif
 275
 276 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
 277 {
 278         struct drm_crtc *crtc = &mtk_crtc->base;
 279         struct drm_connector *connector;
 280         struct drm_encoder *encoder;
 281         struct drm_connector_list_iter conn_iter;
 282         unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
 283         int ret;
 284         int i;
 285
 286         if (WARN_ON(!crtc->state))
 287                 return -EINVAL;
 288
 289         width = crtc->state->adjusted_mode.hdisplay;
 290         height = crtc->state->adjusted_mode.vdisplay;
 291         vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
 292
 293         drm_for_each_encoder(encoder, crtc->dev) {
 294                 if (encoder->crtc != crtc)
 295                         continue;
 296
 297                 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 298                 drm_for_each_connector_iter(connector, &conn_iter) {
 299                         if (connector->encoder != encoder)
 300                                 continue;
 301                         if (connector->display_info.bpc != 0 &&
 302                             bpc > connector->display_info.bpc)
 303                                 bpc = connector->display_info.bpc;
 304                 }
 305                 drm_connector_list_iter_end(&conn_iter);
 306         }
 307
 308         ret = pm_runtime_resume_and_get(crtc->dev->dev);
 309         if (ret < 0) {
 310                 DRM_ERROR("Failed to enable power domain: %d\n", ret);
 311                 return ret;
 312         }
 313
 314         ret = mtk_mutex_prepare(mtk_crtc->mutex);
 315         if (ret < 0) {
 316                 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
 317                 goto err_pm_runtime_put;
 318         }
 319
 320         ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
 321         if (ret < 0) {
 322                 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
 323                 goto err_mutex_unprepare;
 324         }
 325
 326         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 327                 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
 328                                       mtk_crtc->ddp_comp[i]->id,
 329                                       mtk_crtc->ddp_comp[i + 1]->id);
 330                 mtk_mutex_add_comp(mtk_crtc->mutex,
 331                                         mtk_crtc->ddp_comp[i]->id);
 332         }
 333         mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 334         mtk_mutex_enable(mtk_crtc->mutex);
 335
 336         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 337                 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
 338
 339                 if (i == 1)
 340                         mtk_ddp_comp_bgclr_in_on(comp);
 341
 342                 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
 343                 mtk_ddp_comp_start(comp);
 344         }
 345
 346         /* Initially configure all planes */
 347         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 348                 struct drm_plane *plane = &mtk_crtc->planes[i];
 349                 struct mtk_plane_state *plane_state;
 350                 struct mtk_ddp_comp *comp;
 351                 unsigned int local_layer;
 352
 353                 plane_state = to_mtk_plane_state(plane->state);
 354                 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
 355                 if (comp)
 356                         mtk_ddp_comp_layer_config(comp, local_layer,
 357                                                   plane_state, NULL);
 358         }
 359
 360         return 0;
 361
 362 err_mutex_unprepare:
 363         mtk_mutex_unprepare(mtk_crtc->mutex);
 364 err_pm_runtime_put:
 365         pm_runtime_put(crtc->dev->dev);
 366         return ret;
 367 }
 368
 369 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
 370 {
 371         struct drm_device *drm = mtk_crtc->base.dev;
 372         struct drm_crtc *crtc = &mtk_crtc->base;
 373         int i;
 374
 375         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 376                 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
 377                 if (i == 1)
 378                         mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
 379         }
 380
 381         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 382                 mtk_mutex_remove_comp(mtk_crtc->mutex,
 383                                            mtk_crtc->ddp_comp[i]->id);
 384         mtk_mutex_disable(mtk_crtc->mutex);
 385         for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
 386                 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
 387                                          mtk_crtc->ddp_comp[i]->id,
 388                                          mtk_crtc->ddp_comp[i + 1]->id);
 389                 mtk_mutex_remove_comp(mtk_crtc->mutex,
 390                                            mtk_crtc->ddp_comp[i]->id);
 391         }
 392         mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
 393         mtk_crtc_ddp_clk_disable(mtk_crtc);
 394         mtk_mutex_unprepare(mtk_crtc->mutex);
 395
 396         pm_runtime_put(drm->dev);
 397
 398         if (crtc->state->event && !crtc->state->active) {
 399                 spin_lock_irq(&crtc->dev->event_lock);
 400                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 401                 crtc->state->event = NULL;
 402                 spin_unlock_irq(&crtc->dev->event_lock);
 403         }
 404 }
 405
 406 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
 407                                 struct cmdq_pkt *cmdq_handle)
 408 {
 409         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 410         struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
 411         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 412         unsigned int i;
 413         unsigned int local_layer;
 414
 415         /*
 416          * TODO: instead of updating the registers here, we should prepare
 417          * working registers in atomic_commit and let the hardware command
 418          * queue update module registers on vblank.
 419          */
 420         if (state->pending_config) {
 421                 mtk_ddp_comp_config(comp, state->pending_width,
 422                                     state->pending_height,
 423                                     state->pending_vrefresh, 0,
 424                                     cmdq_handle);
 425
 426                 state->pending_config = false;
 427         }
 428
 429         if (mtk_crtc->pending_planes) {
 430                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 431                         struct drm_plane *plane = &mtk_crtc->planes[i];
 432                         struct mtk_plane_state *plane_state;
 433
 434                         plane_state = to_mtk_plane_state(plane->state);
 435
 436                         if (!plane_state->pending.config)
 437                                 continue;
 438
 439                         comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
 440                                                           &local_layer);
 441
 442                         if (comp)
 443                                 mtk_ddp_comp_layer_config(comp, local_layer,
 444                                                           plane_state,
 445                                                           cmdq_handle);
 446                         plane_state->pending.config = false;
 447                 }
 448                 mtk_crtc->pending_planes = false;
 449         }
 450
 451         if (mtk_crtc->pending_async_planes) {
 452                 for (i = 0; i < mtk_crtc->layer_nr; i++) {
 453                         struct drm_plane *plane = &mtk_crtc->planes[i];
 454                         struct mtk_plane_state *plane_state;
 455
 456                         plane_state = to_mtk_plane_state(plane->state);
 457
 458                         if (!plane_state->pending.async_config)
 459                                 continue;
 460
 461                         comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
 462                                                           &local_layer);
 463
 464                         if (comp)
 465                                 mtk_ddp_comp_layer_config(comp, local_layer,
 466                                                           plane_state,
 467                                                           cmdq_handle);
 468                         plane_state->pending.async_config = false;
 469                 }
 470                 mtk_crtc->pending_async_planes = false;
 471         }
 472 }
 473
 474 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
 475                                        bool needs_vblank)
 476 {
 477 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 478         struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
 479 #endif
 480         struct drm_crtc *crtc = &mtk_crtc->base;
 481         struct mtk_drm_private *priv = crtc->dev->dev_private;
 482         unsigned int pending_planes = 0, pending_async_planes = 0;
 483         int i;
 484
 485         mutex_lock(&mtk_crtc->hw_lock);
 486         mtk_crtc->config_updating = true;
 487         if (needs_vblank)
 488                 mtk_crtc->pending_needs_vblank = true;
 489
 490         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 491                 struct drm_plane *plane = &mtk_crtc->planes[i];
 492                 struct mtk_plane_state *plane_state;
 493
 494                 plane_state = to_mtk_plane_state(plane->state);
 495                 if (plane_state->pending.dirty) {
 496                         plane_state->pending.config = true;
 497                         plane_state->pending.dirty = false;
 498                         pending_planes |= BIT(i);
 499                 } else if (plane_state->pending.async_dirty) {
 500                         plane_state->pending.async_config = true;
 501                         plane_state->pending.async_dirty = false;
 502                         pending_async_planes |= BIT(i);
 503                 }
 504         }
 505         if (pending_planes)
 506                 mtk_crtc->pending_planes = true;
 507         if (pending_async_planes)
 508                 mtk_crtc->pending_async_planes = true;
 509
 510         if (priv->data->shadow_register) {
 511                 mtk_mutex_acquire(mtk_crtc->mutex);
 512                 mtk_crtc_ddp_config(crtc, NULL);
 513                 mtk_mutex_release(mtk_crtc->mutex);
 514         }
 515 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 516         if (mtk_crtc->cmdq_chan) {
 517                 mbox_flush(mtk_crtc->cmdq_chan, 2000);
 518                 cmdq_handle->cmd_buf_size = 0;
 519                 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
 520                 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
 521                 mtk_crtc_ddp_config(crtc, cmdq_handle);
 522                 cmdq_pkt_finalize(cmdq_handle);
 523                 dma_sync_single_for_device(mtk_crtc->cmdq_chan->mbox->dev,
 524                                             cmdq_handle->pa_base,
 525                                             cmdq_handle->cmd_buf_size,
 526                                             DMA_TO_DEVICE);
 527                 /*
 528                  * CMDQ command should execute in next vblank,
 529                  * If it fail to execute in next 2 vblank, timeout happen.
 530                  */
 531                 mtk_crtc->cmdq_vblank_cnt = 2;
 532                 mbox_send_message(mtk_crtc->cmdq_chan, cmdq_handle);
 533                 mbox_client_txdone(mtk_crtc->cmdq_chan, 0);
 534         }
 535 #endif
 536         mtk_crtc->config_updating = false;
 537         mutex_unlock(&mtk_crtc->hw_lock);
 538 }
 539
 540 static void mtk_crtc_ddp_irq(void *data)
 541 {
 542         struct drm_crtc *crtc = data;
 543         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 544         struct mtk_drm_private *priv = crtc->dev->dev_private;
 545
 546 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 547         if (!priv->data->shadow_register && !mtk_crtc->cmdq_chan)
 548                 mtk_crtc_ddp_config(crtc, NULL);
 549         else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
 550                 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
 551                           drm_crtc_index(&mtk_crtc->base));
 552 #else
 553         if (!priv->data->shadow_register)
 554                 mtk_crtc_ddp_config(crtc, NULL);
 555 #endif
 556         mtk_drm_finish_page_flip(mtk_crtc);
 557 }
 558
 559 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
 560 {
 561         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 562         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 563
 564         mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
 565
 566         return 0;
 567 }
 568
 569 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
 570 {
 571         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 572         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 573
 574         mtk_ddp_comp_disable_vblank(comp);
 575 }
 576
 577 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
 578                              struct mtk_plane_state *state)
 579 {
 580         unsigned int local_layer;
 581         struct mtk_ddp_comp *comp;
 582
 583         comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
 584         if (comp)
 585                 return mtk_ddp_comp_layer_check(comp, local_layer, state);
 586         return 0;
 587 }
 588
 589 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
 590                                struct drm_atomic_state *state)
 591 {
 592         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 593         const struct drm_plane_helper_funcs *plane_helper_funcs =
 594                         plane->helper_private;
 595
 596         if (!mtk_crtc->enabled)
 597                 return;
 598
 599         plane_helper_funcs->atomic_update(plane, state);
 600         mtk_drm_crtc_update_config(mtk_crtc, false);
 601 }
 602
 603 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 604                                        struct drm_atomic_state *state)
 605 {
 606         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 607         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 608         int ret;
 609
 610         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 611
 612         ret = mtk_smi_larb_get(comp->larb_dev);
 613         if (ret) {
 614                 DRM_ERROR("Failed to get larb: %d\n", ret);
 615                 return;
 616         }
 617
 618         ret = mtk_crtc_ddp_hw_init(mtk_crtc);
 619         if (ret) {
 620                 mtk_smi_larb_put(comp->larb_dev);
 621                 return;
 622         }
 623
 624         drm_crtc_vblank_on(crtc);
 625         mtk_crtc->enabled = true;
 626 }
 627
 628 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 629                                         struct drm_atomic_state *state)
 630 {
 631         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 632         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
 633         int i;
 634
 635         DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
 636         if (!mtk_crtc->enabled)
 637                 return;
 638
 639         /* Set all pending plane state to disabled */
 640         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 641                 struct drm_plane *plane = &mtk_crtc->planes[i];
 642                 struct mtk_plane_state *plane_state;
 643
 644                 plane_state = to_mtk_plane_state(plane->state);
 645                 plane_state->pending.enable = false;
 646                 plane_state->pending.config = true;
 647         }
 648         mtk_crtc->pending_planes = true;
 649
 650         mtk_drm_crtc_update_config(mtk_crtc, false);
 651         /* Wait for planes to be disabled */
 652         drm_crtc_wait_one_vblank(crtc);
 653
 654         drm_crtc_vblank_off(crtc);
 655         mtk_crtc_ddp_hw_fini(mtk_crtc);
 656         mtk_smi_larb_put(comp->larb_dev);
 657
 658         mtk_crtc->enabled = false;
 659 }
 660
 661 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 662                                       struct drm_atomic_state *state)
 663 {
 664         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 665                                                                           crtc);
 666         struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
 667         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 668
 669         if (mtk_crtc->event && mtk_crtc_state->base.event)
 670                 DRM_ERROR("new event while there is still a pending event\n");
 671
 672         if (mtk_crtc_state->base.event) {
 673                 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
 674                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 675                 mtk_crtc->event = mtk_crtc_state->base.event;
 676                 mtk_crtc_state->base.event = NULL;
 677         }
 678 }
 679
 680 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 681                                       struct drm_atomic_state *state)
 682 {
 683         struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 684         int i;
 685
 686         if (crtc->state->color_mgmt_changed)
 687                 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 688                         mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
 689                         mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
 690                 }
 691         mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
 692 }
 693
 694 static const struct drm_crtc_funcs mtk_crtc_funcs = {
 695         .set_config             = drm_atomic_helper_set_config,
 696         .page_flip              = drm_atomic_helper_page_flip,
 697         .destroy                = mtk_drm_crtc_destroy,
 698         .reset                  = mtk_drm_crtc_reset,
 699         .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
 700         .atomic_destroy_state   = mtk_drm_crtc_destroy_state,
 701         .enable_vblank          = mtk_drm_crtc_enable_vblank,
 702         .disable_vblank         = mtk_drm_crtc_disable_vblank,
 703 };
 704
 705 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
 706         .mode_fixup     = mtk_drm_crtc_mode_fixup,
 707         .mode_set_nofb  = mtk_drm_crtc_mode_set_nofb,
 708         .atomic_begin   = mtk_drm_crtc_atomic_begin,
 709         .atomic_flush   = mtk_drm_crtc_atomic_flush,
 710         .atomic_enable  = mtk_drm_crtc_atomic_enable,
 711         .atomic_disable = mtk_drm_crtc_atomic_disable,
 712 };
 713
 714 static int mtk_drm_crtc_init(struct drm_device *drm,
 715                              struct mtk_drm_crtc *mtk_crtc,
 716                              unsigned int pipe)
 717 {
 718         struct drm_plane *primary = NULL;
 719         struct drm_plane *cursor = NULL;
 720         int i, ret;
 721
 722         for (i = 0; i < mtk_crtc->layer_nr; i++) {
 723                 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
 724                         primary = &mtk_crtc->planes[i];
 725                 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
 726                         cursor = &mtk_crtc->planes[i];
 727         }
 728
 729         ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
 730                                         &mtk_crtc_funcs, NULL);
 731         if (ret)
 732                 goto err_cleanup_crtc;
 733
 734         drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
 735
 736         return 0;
 737
 738 err_cleanup_crtc:
 739         drm_crtc_cleanup(&mtk_crtc->base);
 740         return ret;
 741 }
 742
 743 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
 744                                         int comp_idx)
 745 {
 746         struct mtk_ddp_comp *comp;
 747
 748         if (comp_idx > 1)
 749                 return 0;
 750
 751         comp = mtk_crtc->ddp_comp[comp_idx];
 752         if (!comp->funcs)
 753                 return 0;
 754
 755         if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
 756                 return 0;
 757
 758         return mtk_ddp_comp_layer_nr(comp);
 759 }
 760
 761 static inline
 762 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
 763                                             unsigned int num_planes)
 764 {
 765         if (plane_idx == 0)
 766                 return DRM_PLANE_TYPE_PRIMARY;
 767         else if (plane_idx == (num_planes - 1))
 768                 return DRM_PLANE_TYPE_CURSOR;
 769         else
 770                 return DRM_PLANE_TYPE_OVERLAY;
 771
 772 }
 773
 774 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
 775                                          struct mtk_drm_crtc *mtk_crtc,
 776                                          int comp_idx, int pipe)
 777 {
 778         int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
 779         struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
 780         int i, ret;
 781
 782         for (i = 0; i < num_planes; i++) {
 783                 ret = mtk_plane_init(drm_dev,
 784                                 &mtk_crtc->planes[mtk_crtc->layer_nr],
 785                                 BIT(pipe),
 786                                 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
 787                                                         num_planes),
 788                                 mtk_ddp_comp_supported_rotations(comp));
 789                 if (ret)
 790                         return ret;
 791
 792                 mtk_crtc->layer_nr++;
 793         }
 794         return 0;
 795 }
 796
 797 int mtk_drm_crtc_create(struct drm_device *drm_dev,
 798                         const enum mtk_ddp_comp_id *path, unsigned int path_len)
 799 {
 800         struct mtk_drm_private *priv = drm_dev->dev_private;
 801         struct device *dev = drm_dev->dev;
 802         struct mtk_drm_crtc *mtk_crtc;
 803         unsigned int num_comp_planes = 0;
 804         int pipe = priv->num_pipes;
 805         int ret;
 806         int i;
 807         bool has_ctm = false;
 808         uint gamma_lut_size = 0;
 809
 810         if (!path)
 811                 return 0;
 812
 813         for (i = 0; i < path_len; i++) {
 814                 enum mtk_ddp_comp_id comp_id = path[i];
 815                 struct device_node *node;
 816                 struct mtk_ddp_comp *comp;
 817
 818                 node = priv->comp_node[comp_id];
 819                 comp = &priv->ddp_comp[comp_id];
 820
 821                 if (!node) {
 822                         dev_info(dev,
 823                                  "Not creating crtc %d because component %d is disabled or missing\n",
 824                                  pipe, comp_id);
 825                         return 0;
 826                 }
 827
 828                 if (!comp->dev) {
 829                         dev_err(dev, "Component %pOF not initialized\n", node);
 830                         return -ENODEV;
 831                 }
 832         }
 833
 834         mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
 835         if (!mtk_crtc)
 836                 return -ENOMEM;
 837
 838         mtk_crtc->mmsys_dev = priv->mmsys_dev;
 839         mtk_crtc->ddp_comp_nr = path_len;
 840         mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
 841                                                 sizeof(*mtk_crtc->ddp_comp),
 842                                                 GFP_KERNEL);
 843         if (!mtk_crtc->ddp_comp)
 844                 return -ENOMEM;
 845
 846         mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
 847         if (IS_ERR(mtk_crtc->mutex)) {
 848                 ret = PTR_ERR(mtk_crtc->mutex);
 849                 dev_err(dev, "Failed to get mutex: %d\n", ret);
 850                 return ret;
 851         }
 852
 853         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 854                 enum mtk_ddp_comp_id comp_id = path[i];
 855                 struct mtk_ddp_comp *comp;
 856
 857                 comp = &priv->ddp_comp[comp_id];
 858                 mtk_crtc->ddp_comp[i] = comp;
 859
 860                 if (comp->funcs) {
 861                         if (comp->funcs->gamma_set)
 862                                 gamma_lut_size = MTK_LUT_SIZE;
 863
 864                         if (comp->funcs->ctm_set)
 865                                 has_ctm = true;
 866                 }
 867         }
 868
 869         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
 870                 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
 871
 872         mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
 873                                         sizeof(struct drm_plane), GFP_KERNEL);
 874
 875         for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 876                 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
 877                                                     pipe);
 878                 if (ret)
 879                         return ret;
 880         }
 881
 882         ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
 883         if (ret < 0)
 884                 return ret;
 885
 886         if (gamma_lut_size)
 887                 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
 888         drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
 889         priv->num_pipes++;
 890         mutex_init(&mtk_crtc->hw_lock);
 891
 892 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 893         mtk_crtc->cmdq_cl.dev = mtk_crtc->mmsys_dev;
 894         mtk_crtc->cmdq_cl.tx_block = false;
 895         mtk_crtc->cmdq_cl.knows_txdone = true;
 896         mtk_crtc->cmdq_cl.rx_callback = ddp_cmdq_cb;
 897         mtk_crtc->cmdq_chan =
 898                         mbox_request_channel(&mtk_crtc->cmdq_cl,
 899                                               drm_crtc_index(&mtk_crtc->base));
 900         if (IS_ERR(mtk_crtc->cmdq_chan)) {
 901                 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
 902                         drm_crtc_index(&mtk_crtc->base));
 903                 mtk_crtc->cmdq_chan = NULL;
 904         }
 905
 906         if (mtk_crtc->cmdq_chan) {
 907                 ret = of_property_read_u32_index(priv->mutex_node,
 908                                                  "mediatek,gce-events",
 909                                                  drm_crtc_index(&mtk_crtc->base),
 910                                                  &mtk_crtc->cmdq_event);
 911                 if (ret) {
 912                         dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
 913                                 drm_crtc_index(&mtk_crtc->base));
 914                         mbox_free_channel(mtk_crtc->cmdq_chan);
 915                         mtk_crtc->cmdq_chan = NULL;
 916                 } else {
 917                         ret = mtk_drm_cmdq_pkt_create(mtk_crtc->cmdq_chan,
 918                                                        &mtk_crtc->cmdq_handle,
 919                                                        PAGE_SIZE);
 920                         if (ret) {
 921                                 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
 922                                         drm_crtc_index(&mtk_crtc->base));
 923                                 mbox_free_channel(mtk_crtc->cmdq_chan);
 924                                 mtk_crtc->cmdq_chan = NULL;
 925                         }
 926                 }
 927         }
 928 #endif
 929         return 0;
 930 }