1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
7 #include <linux/dma-mapping.h>
8 #include <linux/mailbox_controller.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/soc/mediatek/mtk-cmdq.h>
11 #include <linux/soc/mediatek/mtk-mmsys.h>
12 #include <linux/soc/mediatek/mtk-mutex.h>
14 #include <asm/barrier.h>
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_plane_helper.h>
19 #include <drm/drm_probe_helper.h>
20 #include <drm/drm_vblank.h>
22 #include "mtk_drm_drv.h"
23 #include "mtk_drm_crtc.h"
24 #include "mtk_drm_ddp_comp.h"
25 #include "mtk_drm_gem.h"
26 #include "mtk_drm_plane.h"
29 * struct mtk_drm_crtc - MediaTek specific crtc structure.
31 * @enabled: records whether crtc_enable succeeded
32 * @planes: array of 4 drm_plane structures, one for each overlay plane
33 * @pending_planes: whether any plane has pending changes to be applied
34 * @mmsys_dev: pointer to the mmsys device for configuration registers
35 * @mutex: handle to one of the ten disp_mutex streams
36 * @ddp_comp_nr: number of components in ddp_comp
37 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
39 * TODO: Needs update: this header is missing a bunch of member descriptions.
45 bool pending_needs_vblank;
46 struct drm_pending_vblank_event *event;
48 struct drm_plane *planes;
49 unsigned int layer_nr;
51 bool pending_async_planes;
53 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
54 struct cmdq_client cmdq_client;
55 struct cmdq_pkt cmdq_handle;
60 struct device *mmsys_dev;
61 struct mtk_mutex *mutex;
62 unsigned int ddp_comp_nr;
63 struct mtk_ddp_comp **ddp_comp;
65 /* lock for display hardware access */
70 struct mtk_crtc_state {
71 struct drm_crtc_state base;
74 unsigned int pending_width;
75 unsigned int pending_height;
76 unsigned int pending_vrefresh;
79 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
81 return container_of(c, struct mtk_drm_crtc, base);
84 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
86 return container_of(s, struct mtk_crtc_state, base);
89 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
91 struct drm_crtc *crtc = &mtk_crtc->base;
94 spin_lock_irqsave(&crtc->dev->event_lock, flags);
95 drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
96 drm_crtc_vblank_put(crtc);
97 mtk_crtc->event = NULL;
98 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
101 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
103 drm_crtc_handle_vblank(&mtk_crtc->base);
104 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
105 mtk_drm_crtc_finish_page_flip(mtk_crtc);
106 mtk_crtc->pending_needs_vblank = false;
110 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
111 static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt,
117 pkt->va_base = kzalloc(size, GFP_KERNEL);
122 pkt->buf_size = size;
123 pkt->cl = (void *)client;
125 dev = client->chan->mbox->dev;
126 dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
128 if (dma_mapping_error(dev, dma_addr)) {
129 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
135 pkt->pa_base = dma_addr;
140 static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt)
142 struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
144 dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
151 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
153 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
155 mtk_mutex_put(mtk_crtc->mutex);
156 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
157 mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle);
159 if (mtk_crtc->cmdq_client.chan) {
160 mbox_free_channel(mtk_crtc->cmdq_client.chan);
161 mtk_crtc->cmdq_client.chan = NULL;
164 drm_crtc_cleanup(crtc);
167 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
169 struct mtk_crtc_state *state;
172 __drm_atomic_helper_crtc_destroy_state(crtc->state);
174 kfree(to_mtk_crtc_state(crtc->state));
177 state = kzalloc(sizeof(*state), GFP_KERNEL);
179 __drm_atomic_helper_crtc_reset(crtc, &state->base);
182 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
184 struct mtk_crtc_state *state;
186 state = kzalloc(sizeof(*state), GFP_KERNEL);
190 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
192 WARN_ON(state->base.crtc != crtc);
193 state->base.crtc = crtc;
198 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
199 struct drm_crtc_state *state)
201 __drm_atomic_helper_crtc_destroy_state(state);
202 kfree(to_mtk_crtc_state(state));
205 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
206 const struct drm_display_mode *mode,
207 struct drm_display_mode *adjusted_mode)
209 /* Nothing to do here, but this callback is mandatory. */
213 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
215 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
217 state->pending_width = crtc->mode.hdisplay;
218 state->pending_height = crtc->mode.vdisplay;
219 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
220 wmb(); /* Make sure the above parameters are set before update */
221 state->pending_config = true;
224 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
229 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
230 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
232 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
240 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
244 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
248 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
249 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
253 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
254 struct drm_plane *plane,
255 unsigned int *local_layer)
257 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
258 struct mtk_ddp_comp *comp;
260 unsigned int local_index = plane - mtk_crtc->planes;
262 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
263 comp = mtk_crtc->ddp_comp[i];
264 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
265 *local_layer = local_index - count;
268 count += mtk_ddp_comp_layer_nr(comp);
271 WARN(1, "Failed to find component for plane %d\n", plane->index);
275 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
276 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
278 struct cmdq_cb_data *data = mssg;
279 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client);
280 struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client);
281 struct mtk_crtc_state *state;
287 state = to_mtk_crtc_state(mtk_crtc->base.state);
289 state->pending_config = false;
291 if (mtk_crtc->pending_planes) {
292 for (i = 0; i < mtk_crtc->layer_nr; i++) {
293 struct drm_plane *plane = &mtk_crtc->planes[i];
294 struct mtk_plane_state *plane_state;
296 plane_state = to_mtk_plane_state(plane->state);
298 plane_state->pending.config = false;
300 mtk_crtc->pending_planes = false;
303 if (mtk_crtc->pending_async_planes) {
304 for (i = 0; i < mtk_crtc->layer_nr; i++) {
305 struct drm_plane *plane = &mtk_crtc->planes[i];
306 struct mtk_plane_state *plane_state;
308 plane_state = to_mtk_plane_state(plane->state);
310 plane_state->pending.async_config = false;
312 mtk_crtc->pending_async_planes = false;
315 mtk_crtc->cmdq_vblank_cnt = 0;
319 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
321 struct drm_crtc *crtc = &mtk_crtc->base;
322 struct drm_connector *connector;
323 struct drm_encoder *encoder;
324 struct drm_connector_list_iter conn_iter;
325 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
329 if (WARN_ON(!crtc->state))
332 width = crtc->state->adjusted_mode.hdisplay;
333 height = crtc->state->adjusted_mode.vdisplay;
334 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
336 drm_for_each_encoder(encoder, crtc->dev) {
337 if (encoder->crtc != crtc)
340 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
341 drm_for_each_connector_iter(connector, &conn_iter) {
342 if (connector->encoder != encoder)
344 if (connector->display_info.bpc != 0 &&
345 bpc > connector->display_info.bpc)
346 bpc = connector->display_info.bpc;
348 drm_connector_list_iter_end(&conn_iter);
351 ret = pm_runtime_resume_and_get(crtc->dev->dev);
353 DRM_ERROR("Failed to enable power domain: %d\n", ret);
357 ret = mtk_mutex_prepare(mtk_crtc->mutex);
359 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
360 goto err_pm_runtime_put;
363 ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
365 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
366 goto err_mutex_unprepare;
369 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
370 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
371 mtk_crtc->ddp_comp[i]->id,
372 mtk_crtc->ddp_comp[i + 1]->id);
373 mtk_mutex_add_comp(mtk_crtc->mutex,
374 mtk_crtc->ddp_comp[i]->id);
376 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
377 mtk_mutex_enable(mtk_crtc->mutex);
379 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
380 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
383 mtk_ddp_comp_bgclr_in_on(comp);
385 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
386 mtk_ddp_comp_start(comp);
389 /* Initially configure all planes */
390 for (i = 0; i < mtk_crtc->layer_nr; i++) {
391 struct drm_plane *plane = &mtk_crtc->planes[i];
392 struct mtk_plane_state *plane_state;
393 struct mtk_ddp_comp *comp;
394 unsigned int local_layer;
396 plane_state = to_mtk_plane_state(plane->state);
397 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
399 mtk_ddp_comp_layer_config(comp, local_layer,
406 mtk_mutex_unprepare(mtk_crtc->mutex);
408 pm_runtime_put(crtc->dev->dev);
412 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
414 struct drm_device *drm = mtk_crtc->base.dev;
415 struct drm_crtc *crtc = &mtk_crtc->base;
418 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
419 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
421 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
424 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
425 mtk_mutex_remove_comp(mtk_crtc->mutex,
426 mtk_crtc->ddp_comp[i]->id);
427 mtk_mutex_disable(mtk_crtc->mutex);
428 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
429 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
430 mtk_crtc->ddp_comp[i]->id,
431 mtk_crtc->ddp_comp[i + 1]->id);
432 mtk_mutex_remove_comp(mtk_crtc->mutex,
433 mtk_crtc->ddp_comp[i]->id);
435 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
436 mtk_crtc_ddp_clk_disable(mtk_crtc);
437 mtk_mutex_unprepare(mtk_crtc->mutex);
439 pm_runtime_put(drm->dev);
441 if (crtc->state->event && !crtc->state->active) {
442 spin_lock_irq(&crtc->dev->event_lock);
443 drm_crtc_send_vblank_event(crtc, crtc->state->event);
444 crtc->state->event = NULL;
445 spin_unlock_irq(&crtc->dev->event_lock);
449 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
450 struct cmdq_pkt *cmdq_handle)
452 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
453 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
454 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
456 unsigned int local_layer;
459 * TODO: instead of updating the registers here, we should prepare
460 * working registers in atomic_commit and let the hardware command
461 * queue update module registers on vblank.
463 if (state->pending_config) {
464 mtk_ddp_comp_config(comp, state->pending_width,
465 state->pending_height,
466 state->pending_vrefresh, 0,
470 state->pending_config = false;
473 if (mtk_crtc->pending_planes) {
474 for (i = 0; i < mtk_crtc->layer_nr; i++) {
475 struct drm_plane *plane = &mtk_crtc->planes[i];
476 struct mtk_plane_state *plane_state;
478 plane_state = to_mtk_plane_state(plane->state);
480 if (!plane_state->pending.config)
483 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
487 mtk_ddp_comp_layer_config(comp, local_layer,
491 plane_state->pending.config = false;
495 mtk_crtc->pending_planes = false;
498 if (mtk_crtc->pending_async_planes) {
499 for (i = 0; i < mtk_crtc->layer_nr; i++) {
500 struct drm_plane *plane = &mtk_crtc->planes[i];
501 struct mtk_plane_state *plane_state;
503 plane_state = to_mtk_plane_state(plane->state);
505 if (!plane_state->pending.async_config)
508 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
512 mtk_ddp_comp_layer_config(comp, local_layer,
516 plane_state->pending.async_config = false;
520 mtk_crtc->pending_async_planes = false;
524 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
527 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
528 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
530 struct drm_crtc *crtc = &mtk_crtc->base;
531 struct mtk_drm_private *priv = crtc->dev->dev_private;
532 unsigned int pending_planes = 0, pending_async_planes = 0;
535 mutex_lock(&mtk_crtc->hw_lock);
536 mtk_crtc->config_updating = true;
538 mtk_crtc->pending_needs_vblank = true;
540 for (i = 0; i < mtk_crtc->layer_nr; i++) {
541 struct drm_plane *plane = &mtk_crtc->planes[i];
542 struct mtk_plane_state *plane_state;
544 plane_state = to_mtk_plane_state(plane->state);
545 if (plane_state->pending.dirty) {
546 plane_state->pending.config = true;
547 plane_state->pending.dirty = false;
548 pending_planes |= BIT(i);
549 } else if (plane_state->pending.async_dirty) {
550 plane_state->pending.async_config = true;
551 plane_state->pending.async_dirty = false;
552 pending_async_planes |= BIT(i);
556 mtk_crtc->pending_planes = true;
557 if (pending_async_planes)
558 mtk_crtc->pending_async_planes = true;
560 if (priv->data->shadow_register) {
561 mtk_mutex_acquire(mtk_crtc->mutex);
562 mtk_crtc_ddp_config(crtc, NULL);
563 mtk_mutex_release(mtk_crtc->mutex);
565 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
566 if (mtk_crtc->cmdq_client.chan) {
567 mbox_flush(mtk_crtc->cmdq_client.chan, 2000);
568 cmdq_handle->cmd_buf_size = 0;
569 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
570 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
571 mtk_crtc_ddp_config(crtc, cmdq_handle);
572 cmdq_pkt_finalize(cmdq_handle);
573 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev,
574 cmdq_handle->pa_base,
575 cmdq_handle->cmd_buf_size,
578 * CMDQ command should execute in next 3 vblank.
579 * One vblank interrupt before send message (occasionally)
580 * and one vblank interrupt after cmdq done,
581 * so it's timeout after 3 vblank interrupt.
582 * If it fail to execute in next 3 vblank, timeout happen.
584 mtk_crtc->cmdq_vblank_cnt = 3;
586 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
587 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
590 mtk_crtc->config_updating = false;
591 mutex_unlock(&mtk_crtc->hw_lock);
594 static void mtk_crtc_ddp_irq(void *data)
596 struct drm_crtc *crtc = data;
597 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
598 struct mtk_drm_private *priv = crtc->dev->dev_private;
600 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
601 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan)
602 mtk_crtc_ddp_config(crtc, NULL);
603 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
604 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
605 drm_crtc_index(&mtk_crtc->base));
607 if (!priv->data->shadow_register)
608 mtk_crtc_ddp_config(crtc, NULL);
610 mtk_drm_finish_page_flip(mtk_crtc);
613 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
615 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
616 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
618 mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
623 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
625 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
626 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
628 mtk_ddp_comp_disable_vblank(comp);
631 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
632 struct mtk_plane_state *state)
634 unsigned int local_layer;
635 struct mtk_ddp_comp *comp;
637 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
639 return mtk_ddp_comp_layer_check(comp, local_layer, state);
643 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
644 struct drm_atomic_state *state)
646 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
648 if (!mtk_crtc->enabled)
651 mtk_drm_crtc_update_config(mtk_crtc, false);
654 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
655 struct drm_atomic_state *state)
657 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
658 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
661 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
663 ret = pm_runtime_resume_and_get(comp->dev);
665 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
669 ret = mtk_crtc_ddp_hw_init(mtk_crtc);
671 pm_runtime_put(comp->dev);
675 drm_crtc_vblank_on(crtc);
676 mtk_crtc->enabled = true;
679 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
680 struct drm_atomic_state *state)
682 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
683 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
686 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
687 if (!mtk_crtc->enabled)
690 /* Set all pending plane state to disabled */
691 for (i = 0; i < mtk_crtc->layer_nr; i++) {
692 struct drm_plane *plane = &mtk_crtc->planes[i];
693 struct mtk_plane_state *plane_state;
695 plane_state = to_mtk_plane_state(plane->state);
696 plane_state->pending.enable = false;
697 plane_state->pending.config = true;
699 mtk_crtc->pending_planes = true;
701 mtk_drm_crtc_update_config(mtk_crtc, false);
702 /* Wait for planes to be disabled */
703 drm_crtc_wait_one_vblank(crtc);
705 drm_crtc_vblank_off(crtc);
706 mtk_crtc_ddp_hw_fini(mtk_crtc);
707 ret = pm_runtime_put(comp->dev);
709 DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret);
711 mtk_crtc->enabled = false;
714 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
715 struct drm_atomic_state *state)
717 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
719 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
720 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
722 if (mtk_crtc->event && mtk_crtc_state->base.event)
723 DRM_ERROR("new event while there is still a pending event\n");
725 if (mtk_crtc_state->base.event) {
726 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
727 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
728 mtk_crtc->event = mtk_crtc_state->base.event;
729 mtk_crtc_state->base.event = NULL;
733 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
734 struct drm_atomic_state *state)
736 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
739 if (crtc->state->color_mgmt_changed)
740 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
741 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
742 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
744 mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
747 static const struct drm_crtc_funcs mtk_crtc_funcs = {
748 .set_config = drm_atomic_helper_set_config,
749 .page_flip = drm_atomic_helper_page_flip,
750 .destroy = mtk_drm_crtc_destroy,
751 .reset = mtk_drm_crtc_reset,
752 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
753 .atomic_destroy_state = mtk_drm_crtc_destroy_state,
754 .enable_vblank = mtk_drm_crtc_enable_vblank,
755 .disable_vblank = mtk_drm_crtc_disable_vblank,
758 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
759 .mode_fixup = mtk_drm_crtc_mode_fixup,
760 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb,
761 .atomic_begin = mtk_drm_crtc_atomic_begin,
762 .atomic_flush = mtk_drm_crtc_atomic_flush,
763 .atomic_enable = mtk_drm_crtc_atomic_enable,
764 .atomic_disable = mtk_drm_crtc_atomic_disable,
767 static int mtk_drm_crtc_init(struct drm_device *drm,
768 struct mtk_drm_crtc *mtk_crtc,
771 struct drm_plane *primary = NULL;
772 struct drm_plane *cursor = NULL;
775 for (i = 0; i < mtk_crtc->layer_nr; i++) {
776 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
777 primary = &mtk_crtc->planes[i];
778 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
779 cursor = &mtk_crtc->planes[i];
782 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
783 &mtk_crtc_funcs, NULL);
785 goto err_cleanup_crtc;
787 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
792 drm_crtc_cleanup(&mtk_crtc->base);
796 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
799 struct mtk_ddp_comp *comp;
804 comp = mtk_crtc->ddp_comp[comp_idx];
808 if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
811 return mtk_ddp_comp_layer_nr(comp);
815 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
816 unsigned int num_planes)
819 return DRM_PLANE_TYPE_PRIMARY;
820 else if (plane_idx == (num_planes - 1))
821 return DRM_PLANE_TYPE_CURSOR;
823 return DRM_PLANE_TYPE_OVERLAY;
827 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
828 struct mtk_drm_crtc *mtk_crtc,
829 int comp_idx, int pipe)
831 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
832 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
835 for (i = 0; i < num_planes; i++) {
836 ret = mtk_plane_init(drm_dev,
837 &mtk_crtc->planes[mtk_crtc->layer_nr],
839 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
841 mtk_ddp_comp_supported_rotations(comp));
845 mtk_crtc->layer_nr++;
850 int mtk_drm_crtc_create(struct drm_device *drm_dev,
851 const enum mtk_ddp_comp_id *path, unsigned int path_len)
853 struct mtk_drm_private *priv = drm_dev->dev_private;
854 struct device *dev = drm_dev->dev;
855 struct mtk_drm_crtc *mtk_crtc;
856 unsigned int num_comp_planes = 0;
857 int pipe = priv->num_pipes;
860 bool has_ctm = false;
861 uint gamma_lut_size = 0;
866 for (i = 0; i < path_len; i++) {
867 enum mtk_ddp_comp_id comp_id = path[i];
868 struct device_node *node;
869 struct mtk_ddp_comp *comp;
871 node = priv->comp_node[comp_id];
872 comp = &priv->ddp_comp[comp_id];
876 "Not creating crtc %d because component %d is disabled or missing\n",
882 dev_err(dev, "Component %pOF not initialized\n", node);
887 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
891 mtk_crtc->mmsys_dev = priv->mmsys_dev;
892 mtk_crtc->ddp_comp_nr = path_len;
893 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
894 sizeof(*mtk_crtc->ddp_comp),
896 if (!mtk_crtc->ddp_comp)
899 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
900 if (IS_ERR(mtk_crtc->mutex)) {
901 ret = PTR_ERR(mtk_crtc->mutex);
902 dev_err(dev, "Failed to get mutex: %d\n", ret);
906 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
907 enum mtk_ddp_comp_id comp_id = path[i];
908 struct mtk_ddp_comp *comp;
910 comp = &priv->ddp_comp[comp_id];
911 mtk_crtc->ddp_comp[i] = comp;
914 if (comp->funcs->gamma_set)
915 gamma_lut_size = MTK_LUT_SIZE;
917 if (comp->funcs->ctm_set)
922 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
923 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
925 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
926 sizeof(struct drm_plane), GFP_KERNEL);
928 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
929 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
935 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
940 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
941 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
943 mutex_init(&mtk_crtc->hw_lock);
945 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
946 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
947 mtk_crtc->cmdq_client.client.tx_block = false;
948 mtk_crtc->cmdq_client.client.knows_txdone = true;
949 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
950 mtk_crtc->cmdq_client.chan =
951 mbox_request_channel(&mtk_crtc->cmdq_client.client,
952 drm_crtc_index(&mtk_crtc->base));
953 if (IS_ERR(mtk_crtc->cmdq_client.chan)) {
954 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
955 drm_crtc_index(&mtk_crtc->base));
956 mtk_crtc->cmdq_client.chan = NULL;
959 if (mtk_crtc->cmdq_client.chan) {
960 ret = of_property_read_u32_index(priv->mutex_node,
961 "mediatek,gce-events",
962 drm_crtc_index(&mtk_crtc->base),
963 &mtk_crtc->cmdq_event);
965 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
966 drm_crtc_index(&mtk_crtc->base));
967 mbox_free_channel(mtk_crtc->cmdq_client.chan);
968 mtk_crtc->cmdq_client.chan = NULL;
970 ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client,
971 &mtk_crtc->cmdq_handle,
974 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
975 drm_crtc_index(&mtk_crtc->base));
976 mbox_free_channel(mtk_crtc->cmdq_client.chan);
977 mtk_crtc->cmdq_client.chan = NULL;