1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
7 #include <linux/pm_runtime.h>
8 #include <linux/soc/mediatek/mtk-cmdq.h>
9 #include <linux/soc/mediatek/mtk-mmsys.h>
10 #include <linux/soc/mediatek/mtk-mutex.h>
12 #include <asm/barrier.h>
13 #include <soc/mediatek/smi.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_plane_helper.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_vblank.h>
21 #include "mtk_drm_drv.h"
22 #include "mtk_drm_crtc.h"
23 #include "mtk_drm_ddp_comp.h"
24 #include "mtk_drm_gem.h"
25 #include "mtk_drm_plane.h"
28 * struct mtk_drm_crtc - MediaTek specific crtc structure.
30 * @enabled: records whether crtc_enable succeeded
31 * @planes: array of 4 drm_plane structures, one for each overlay plane
32 * @pending_planes: whether any plane has pending changes to be applied
33 * @mmsys_dev: pointer to the mmsys device for configuration registers
34 * @mutex: handle to one of the ten disp_mutex streams
35 * @ddp_comp_nr: number of components in ddp_comp
36 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
38 * TODO: Needs update: this header is missing a bunch of member descriptions.
44 bool pending_needs_vblank;
45 struct drm_pending_vblank_event *event;
47 struct drm_plane *planes;
48 unsigned int layer_nr;
50 bool pending_async_planes;
52 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
53 struct cmdq_client *cmdq_client;
57 struct device *mmsys_dev;
58 struct mtk_mutex *mutex;
59 unsigned int ddp_comp_nr;
60 struct mtk_ddp_comp **ddp_comp;
62 /* lock for display hardware access */
67 struct mtk_crtc_state {
68 struct drm_crtc_state base;
71 unsigned int pending_width;
72 unsigned int pending_height;
73 unsigned int pending_vrefresh;
76 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
78 return container_of(c, struct mtk_drm_crtc, base);
81 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
83 return container_of(s, struct mtk_crtc_state, base);
86 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
88 struct drm_crtc *crtc = &mtk_crtc->base;
91 spin_lock_irqsave(&crtc->dev->event_lock, flags);
92 drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
93 drm_crtc_vblank_put(crtc);
94 mtk_crtc->event = NULL;
95 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
98 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
100 drm_crtc_handle_vblank(&mtk_crtc->base);
101 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
102 mtk_drm_crtc_finish_page_flip(mtk_crtc);
103 mtk_crtc->pending_needs_vblank = false;
107 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
109 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
111 mtk_mutex_put(mtk_crtc->mutex);
113 drm_crtc_cleanup(crtc);
116 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
118 struct mtk_crtc_state *state;
121 __drm_atomic_helper_crtc_destroy_state(crtc->state);
123 kfree(to_mtk_crtc_state(crtc->state));
126 state = kzalloc(sizeof(*state), GFP_KERNEL);
128 __drm_atomic_helper_crtc_reset(crtc, &state->base);
131 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
133 struct mtk_crtc_state *state;
135 state = kzalloc(sizeof(*state), GFP_KERNEL);
139 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
141 WARN_ON(state->base.crtc != crtc);
142 state->base.crtc = crtc;
147 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
148 struct drm_crtc_state *state)
150 __drm_atomic_helper_crtc_destroy_state(state);
151 kfree(to_mtk_crtc_state(state));
154 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
155 const struct drm_display_mode *mode,
156 struct drm_display_mode *adjusted_mode)
158 /* Nothing to do here, but this callback is mandatory. */
162 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
164 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
166 state->pending_width = crtc->mode.hdisplay;
167 state->pending_height = crtc->mode.vdisplay;
168 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
169 wmb(); /* Make sure the above parameters are set before update */
170 state->pending_config = true;
173 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
178 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
179 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
181 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
189 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
193 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
197 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
198 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
202 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
203 struct drm_plane *plane,
204 unsigned int *local_layer)
206 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
207 struct mtk_ddp_comp *comp;
209 unsigned int local_index = plane - mtk_crtc->planes;
211 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
212 comp = mtk_crtc->ddp_comp[i];
213 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
214 *local_layer = local_index - count;
217 count += mtk_ddp_comp_layer_nr(comp);
220 WARN(1, "Failed to find component for plane %d\n", plane->index);
224 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
225 static void ddp_cmdq_cb(struct cmdq_cb_data data)
227 cmdq_pkt_destroy(data.data);
231 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
233 struct drm_crtc *crtc = &mtk_crtc->base;
234 struct drm_connector *connector;
235 struct drm_encoder *encoder;
236 struct drm_connector_list_iter conn_iter;
237 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
241 if (WARN_ON(!crtc->state))
244 width = crtc->state->adjusted_mode.hdisplay;
245 height = crtc->state->adjusted_mode.vdisplay;
246 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
248 drm_for_each_encoder(encoder, crtc->dev) {
249 if (encoder->crtc != crtc)
252 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
253 drm_for_each_connector_iter(connector, &conn_iter) {
254 if (connector->encoder != encoder)
256 if (connector->display_info.bpc != 0 &&
257 bpc > connector->display_info.bpc)
258 bpc = connector->display_info.bpc;
260 drm_connector_list_iter_end(&conn_iter);
263 ret = pm_runtime_resume_and_get(crtc->dev->dev);
265 DRM_ERROR("Failed to enable power domain: %d\n", ret);
269 ret = mtk_mutex_prepare(mtk_crtc->mutex);
271 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
272 goto err_pm_runtime_put;
275 ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
277 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
278 goto err_mutex_unprepare;
281 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
282 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
283 mtk_crtc->ddp_comp[i]->id,
284 mtk_crtc->ddp_comp[i + 1]->id);
285 mtk_mutex_add_comp(mtk_crtc->mutex,
286 mtk_crtc->ddp_comp[i]->id);
288 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
289 mtk_mutex_enable(mtk_crtc->mutex);
291 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
292 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
295 mtk_ddp_comp_bgclr_in_on(comp);
297 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
298 mtk_ddp_comp_start(comp);
301 /* Initially configure all planes */
302 for (i = 0; i < mtk_crtc->layer_nr; i++) {
303 struct drm_plane *plane = &mtk_crtc->planes[i];
304 struct mtk_plane_state *plane_state;
305 struct mtk_ddp_comp *comp;
306 unsigned int local_layer;
308 plane_state = to_mtk_plane_state(plane->state);
309 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
311 mtk_ddp_comp_layer_config(comp, local_layer,
318 mtk_mutex_unprepare(mtk_crtc->mutex);
320 pm_runtime_put(crtc->dev->dev);
324 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
326 struct drm_device *drm = mtk_crtc->base.dev;
327 struct drm_crtc *crtc = &mtk_crtc->base;
330 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
331 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
333 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
336 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
337 mtk_mutex_remove_comp(mtk_crtc->mutex,
338 mtk_crtc->ddp_comp[i]->id);
339 mtk_mutex_disable(mtk_crtc->mutex);
340 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
341 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
342 mtk_crtc->ddp_comp[i]->id,
343 mtk_crtc->ddp_comp[i + 1]->id);
344 mtk_mutex_remove_comp(mtk_crtc->mutex,
345 mtk_crtc->ddp_comp[i]->id);
347 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
348 mtk_crtc_ddp_clk_disable(mtk_crtc);
349 mtk_mutex_unprepare(mtk_crtc->mutex);
351 pm_runtime_put(drm->dev);
353 if (crtc->state->event && !crtc->state->active) {
354 spin_lock_irq(&crtc->dev->event_lock);
355 drm_crtc_send_vblank_event(crtc, crtc->state->event);
356 crtc->state->event = NULL;
357 spin_unlock_irq(&crtc->dev->event_lock);
361 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
362 struct cmdq_pkt *cmdq_handle)
364 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
365 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
366 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
368 unsigned int local_layer;
371 * TODO: instead of updating the registers here, we should prepare
372 * working registers in atomic_commit and let the hardware command
373 * queue update module registers on vblank.
375 if (state->pending_config) {
376 mtk_ddp_comp_config(comp, state->pending_width,
377 state->pending_height,
378 state->pending_vrefresh, 0,
381 state->pending_config = false;
384 if (mtk_crtc->pending_planes) {
385 for (i = 0; i < mtk_crtc->layer_nr; i++) {
386 struct drm_plane *plane = &mtk_crtc->planes[i];
387 struct mtk_plane_state *plane_state;
389 plane_state = to_mtk_plane_state(plane->state);
391 if (!plane_state->pending.config)
394 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
398 mtk_ddp_comp_layer_config(comp, local_layer,
401 plane_state->pending.config = false;
403 mtk_crtc->pending_planes = false;
406 if (mtk_crtc->pending_async_planes) {
407 for (i = 0; i < mtk_crtc->layer_nr; i++) {
408 struct drm_plane *plane = &mtk_crtc->planes[i];
409 struct mtk_plane_state *plane_state;
411 plane_state = to_mtk_plane_state(plane->state);
413 if (!plane_state->pending.async_config)
416 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
420 mtk_ddp_comp_layer_config(comp, local_layer,
423 plane_state->pending.async_config = false;
425 mtk_crtc->pending_async_planes = false;
429 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
432 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
433 struct cmdq_pkt *cmdq_handle;
435 struct drm_crtc *crtc = &mtk_crtc->base;
436 struct mtk_drm_private *priv = crtc->dev->dev_private;
437 unsigned int pending_planes = 0, pending_async_planes = 0;
440 mutex_lock(&mtk_crtc->hw_lock);
441 mtk_crtc->config_updating = true;
443 mtk_crtc->pending_needs_vblank = true;
445 for (i = 0; i < mtk_crtc->layer_nr; i++) {
446 struct drm_plane *plane = &mtk_crtc->planes[i];
447 struct mtk_plane_state *plane_state;
449 plane_state = to_mtk_plane_state(plane->state);
450 if (plane_state->pending.dirty) {
451 plane_state->pending.config = true;
452 plane_state->pending.dirty = false;
453 pending_planes |= BIT(i);
454 } else if (plane_state->pending.async_dirty) {
455 plane_state->pending.async_config = true;
456 plane_state->pending.async_dirty = false;
457 pending_async_planes |= BIT(i);
461 mtk_crtc->pending_planes = true;
462 if (pending_async_planes)
463 mtk_crtc->pending_async_planes = true;
465 if (priv->data->shadow_register) {
466 mtk_mutex_acquire(mtk_crtc->mutex);
467 mtk_crtc_ddp_config(crtc, NULL);
468 mtk_mutex_release(mtk_crtc->mutex);
470 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
471 if (mtk_crtc->cmdq_client) {
472 mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
473 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
474 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
475 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
476 mtk_crtc_ddp_config(crtc, cmdq_handle);
477 cmdq_pkt_finalize(cmdq_handle);
478 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
481 mtk_crtc->config_updating = false;
482 mutex_unlock(&mtk_crtc->hw_lock);
485 static void mtk_crtc_ddp_irq(void *data)
487 struct drm_crtc *crtc = data;
488 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
489 struct mtk_drm_private *priv = crtc->dev->dev_private;
491 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
492 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)
494 if (!priv->data->shadow_register)
496 mtk_crtc_ddp_config(crtc, NULL);
498 mtk_drm_finish_page_flip(mtk_crtc);
501 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
503 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
504 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
506 mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
511 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
513 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
514 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
516 mtk_ddp_comp_disable_vblank(comp);
519 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
520 struct mtk_plane_state *state)
522 unsigned int local_layer;
523 struct mtk_ddp_comp *comp;
525 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
527 return mtk_ddp_comp_layer_check(comp, local_layer, state);
531 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
532 struct drm_atomic_state *state)
534 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
535 const struct drm_plane_helper_funcs *plane_helper_funcs =
536 plane->helper_private;
538 if (!mtk_crtc->enabled)
541 plane_helper_funcs->atomic_update(plane, state);
542 mtk_drm_crtc_update_config(mtk_crtc, false);
545 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
546 struct drm_atomic_state *state)
548 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
549 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
552 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
554 ret = mtk_smi_larb_get(comp->larb_dev);
556 DRM_ERROR("Failed to get larb: %d\n", ret);
560 ret = mtk_crtc_ddp_hw_init(mtk_crtc);
562 mtk_smi_larb_put(comp->larb_dev);
566 drm_crtc_vblank_on(crtc);
567 mtk_crtc->enabled = true;
570 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
571 struct drm_atomic_state *state)
573 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
574 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
577 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
578 if (!mtk_crtc->enabled)
581 /* Set all pending plane state to disabled */
582 for (i = 0; i < mtk_crtc->layer_nr; i++) {
583 struct drm_plane *plane = &mtk_crtc->planes[i];
584 struct mtk_plane_state *plane_state;
586 plane_state = to_mtk_plane_state(plane->state);
587 plane_state->pending.enable = false;
588 plane_state->pending.config = true;
590 mtk_crtc->pending_planes = true;
592 mtk_drm_crtc_update_config(mtk_crtc, false);
593 /* Wait for planes to be disabled */
594 drm_crtc_wait_one_vblank(crtc);
596 drm_crtc_vblank_off(crtc);
597 mtk_crtc_ddp_hw_fini(mtk_crtc);
598 mtk_smi_larb_put(comp->larb_dev);
600 mtk_crtc->enabled = false;
603 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
604 struct drm_atomic_state *state)
606 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
608 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
609 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
611 if (mtk_crtc->event && mtk_crtc_state->base.event)
612 DRM_ERROR("new event while there is still a pending event\n");
614 if (mtk_crtc_state->base.event) {
615 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
616 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
617 mtk_crtc->event = mtk_crtc_state->base.event;
618 mtk_crtc_state->base.event = NULL;
622 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
623 struct drm_atomic_state *state)
625 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
628 if (crtc->state->color_mgmt_changed)
629 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
630 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
631 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
633 mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
636 static const struct drm_crtc_funcs mtk_crtc_funcs = {
637 .set_config = drm_atomic_helper_set_config,
638 .page_flip = drm_atomic_helper_page_flip,
639 .destroy = mtk_drm_crtc_destroy,
640 .reset = mtk_drm_crtc_reset,
641 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
642 .atomic_destroy_state = mtk_drm_crtc_destroy_state,
643 .enable_vblank = mtk_drm_crtc_enable_vblank,
644 .disable_vblank = mtk_drm_crtc_disable_vblank,
647 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
648 .mode_fixup = mtk_drm_crtc_mode_fixup,
649 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb,
650 .atomic_begin = mtk_drm_crtc_atomic_begin,
651 .atomic_flush = mtk_drm_crtc_atomic_flush,
652 .atomic_enable = mtk_drm_crtc_atomic_enable,
653 .atomic_disable = mtk_drm_crtc_atomic_disable,
656 static int mtk_drm_crtc_init(struct drm_device *drm,
657 struct mtk_drm_crtc *mtk_crtc,
660 struct drm_plane *primary = NULL;
661 struct drm_plane *cursor = NULL;
664 for (i = 0; i < mtk_crtc->layer_nr; i++) {
665 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
666 primary = &mtk_crtc->planes[i];
667 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
668 cursor = &mtk_crtc->planes[i];
671 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
672 &mtk_crtc_funcs, NULL);
674 goto err_cleanup_crtc;
676 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
681 drm_crtc_cleanup(&mtk_crtc->base);
685 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
688 struct mtk_ddp_comp *comp;
693 comp = mtk_crtc->ddp_comp[comp_idx];
697 if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
700 return mtk_ddp_comp_layer_nr(comp);
704 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
705 unsigned int num_planes)
708 return DRM_PLANE_TYPE_PRIMARY;
709 else if (plane_idx == (num_planes - 1))
710 return DRM_PLANE_TYPE_CURSOR;
712 return DRM_PLANE_TYPE_OVERLAY;
716 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
717 struct mtk_drm_crtc *mtk_crtc,
718 int comp_idx, int pipe)
720 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
721 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
724 for (i = 0; i < num_planes; i++) {
725 ret = mtk_plane_init(drm_dev,
726 &mtk_crtc->planes[mtk_crtc->layer_nr],
728 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
730 mtk_ddp_comp_supported_rotations(comp));
734 mtk_crtc->layer_nr++;
739 int mtk_drm_crtc_create(struct drm_device *drm_dev,
740 const enum mtk_ddp_comp_id *path, unsigned int path_len)
742 struct mtk_drm_private *priv = drm_dev->dev_private;
743 struct device *dev = drm_dev->dev;
744 struct mtk_drm_crtc *mtk_crtc;
745 unsigned int num_comp_planes = 0;
746 int pipe = priv->num_pipes;
749 bool has_ctm = false;
750 uint gamma_lut_size = 0;
755 for (i = 0; i < path_len; i++) {
756 enum mtk_ddp_comp_id comp_id = path[i];
757 struct device_node *node;
759 node = priv->comp_node[comp_id];
762 "Not creating crtc %d because component %d is disabled or missing\n",
768 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
772 mtk_crtc->mmsys_dev = priv->mmsys_dev;
773 mtk_crtc->ddp_comp_nr = path_len;
774 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
775 sizeof(*mtk_crtc->ddp_comp),
777 if (!mtk_crtc->ddp_comp)
780 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
781 if (IS_ERR(mtk_crtc->mutex)) {
782 ret = PTR_ERR(mtk_crtc->mutex);
783 dev_err(dev, "Failed to get mutex: %d\n", ret);
787 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
788 enum mtk_ddp_comp_id comp_id = path[i];
789 struct mtk_ddp_comp *comp;
790 struct device_node *node;
792 node = priv->comp_node[comp_id];
793 comp = &priv->ddp_comp[comp_id];
795 dev_err(dev, "Component %pOF not initialized\n", node);
800 mtk_crtc->ddp_comp[i] = comp;
803 if (comp->funcs->gamma_set)
804 gamma_lut_size = MTK_LUT_SIZE;
806 if (comp->funcs->ctm_set)
811 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
812 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
814 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
815 sizeof(struct drm_plane), GFP_KERNEL);
817 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
818 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
824 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
829 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
830 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
832 mutex_init(&mtk_crtc->hw_lock);
834 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
835 mtk_crtc->cmdq_client =
836 cmdq_mbox_create(mtk_crtc->mmsys_dev,
837 drm_crtc_index(&mtk_crtc->base));
838 if (IS_ERR(mtk_crtc->cmdq_client)) {
839 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
840 drm_crtc_index(&mtk_crtc->base));
841 mtk_crtc->cmdq_client = NULL;
844 if (mtk_crtc->cmdq_client) {
845 ret = of_property_read_u32_index(priv->mutex_node,
846 "mediatek,gce-events",
847 drm_crtc_index(&mtk_crtc->base),
848 &mtk_crtc->cmdq_event);
850 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
851 drm_crtc_index(&mtk_crtc->base));
852 cmdq_mbox_destroy(mtk_crtc->cmdq_client);
853 mtk_crtc->cmdq_client = NULL;