1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
7 #include <linux/pm_runtime.h>
8 #include <linux/soc/mediatek/mtk-cmdq.h>
9 #include <linux/soc/mediatek/mtk-mmsys.h>
11 #include <asm/barrier.h>
12 #include <soc/mediatek/smi.h>
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_plane_helper.h>
16 #include <drm/drm_probe_helper.h>
17 #include <drm/drm_vblank.h>
19 #include "mtk_drm_drv.h"
20 #include "mtk_drm_crtc.h"
21 #include "mtk_drm_ddp.h"
22 #include "mtk_drm_ddp_comp.h"
23 #include "mtk_drm_gem.h"
24 #include "mtk_drm_plane.h"
27 * struct mtk_drm_crtc - MediaTek specific crtc structure.
29 * @enabled: records whether crtc_enable succeeded
30 * @planes: array of 4 drm_plane structures, one for each overlay plane
31 * @pending_planes: whether any plane has pending changes to be applied
32 * @mmsys_dev: pointer to the mmsys device for configuration registers
33 * @mutex: handle to one of the ten disp_mutex streams
34 * @ddp_comp_nr: number of components in ddp_comp
35 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
41 bool pending_needs_vblank;
42 struct drm_pending_vblank_event *event;
44 struct drm_plane *planes;
45 unsigned int layer_nr;
47 bool pending_async_planes;
49 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
50 struct cmdq_client *cmdq_client;
54 struct device *mmsys_dev;
55 struct mtk_disp_mutex *mutex;
56 unsigned int ddp_comp_nr;
57 struct mtk_ddp_comp **ddp_comp;
59 /* lock for display hardware access */
63 struct mtk_crtc_state {
64 struct drm_crtc_state base;
67 unsigned int pending_width;
68 unsigned int pending_height;
69 unsigned int pending_vrefresh;
72 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
74 return container_of(c, struct mtk_drm_crtc, base);
77 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
79 return container_of(s, struct mtk_crtc_state, base);
82 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
84 struct drm_crtc *crtc = &mtk_crtc->base;
87 spin_lock_irqsave(&crtc->dev->event_lock, flags);
88 drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
89 drm_crtc_vblank_put(crtc);
90 mtk_crtc->event = NULL;
91 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
94 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
96 drm_crtc_handle_vblank(&mtk_crtc->base);
97 if (mtk_crtc->pending_needs_vblank) {
98 mtk_drm_crtc_finish_page_flip(mtk_crtc);
99 mtk_crtc->pending_needs_vblank = false;
103 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
105 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
107 mtk_disp_mutex_put(mtk_crtc->mutex);
109 drm_crtc_cleanup(crtc);
112 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
114 struct mtk_crtc_state *state;
117 __drm_atomic_helper_crtc_destroy_state(crtc->state);
119 kfree(to_mtk_crtc_state(crtc->state));
122 state = kzalloc(sizeof(*state), GFP_KERNEL);
124 __drm_atomic_helper_crtc_reset(crtc, &state->base);
127 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
129 struct mtk_crtc_state *state;
131 state = kzalloc(sizeof(*state), GFP_KERNEL);
135 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
137 WARN_ON(state->base.crtc != crtc);
138 state->base.crtc = crtc;
143 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
144 struct drm_crtc_state *state)
146 __drm_atomic_helper_crtc_destroy_state(state);
147 kfree(to_mtk_crtc_state(state));
150 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
151 const struct drm_display_mode *mode,
152 struct drm_display_mode *adjusted_mode)
154 /* Nothing to do here, but this callback is mandatory. */
158 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
160 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
162 state->pending_width = crtc->mode.hdisplay;
163 state->pending_height = crtc->mode.vdisplay;
164 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
165 wmb(); /* Make sure the above parameters are set before update */
166 state->pending_config = true;
169 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
171 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
172 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
174 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base);
179 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
181 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
182 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
184 mtk_ddp_comp_disable_vblank(comp);
187 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
192 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
193 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk);
195 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
203 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
207 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
211 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
212 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
216 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
217 struct drm_plane *plane,
218 unsigned int *local_layer)
220 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
221 struct mtk_ddp_comp *comp;
223 unsigned int local_index = plane - mtk_crtc->planes;
225 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
226 comp = mtk_crtc->ddp_comp[i];
227 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
228 *local_layer = local_index - count;
231 count += mtk_ddp_comp_layer_nr(comp);
234 WARN(1, "Failed to find component for plane %d\n", plane->index);
238 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
239 static void ddp_cmdq_cb(struct cmdq_cb_data data)
241 cmdq_pkt_destroy(data.data);
245 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
247 struct drm_crtc *crtc = &mtk_crtc->base;
248 struct drm_connector *connector;
249 struct drm_encoder *encoder;
250 struct drm_connector_list_iter conn_iter;
251 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
255 if (WARN_ON(!crtc->state))
258 width = crtc->state->adjusted_mode.hdisplay;
259 height = crtc->state->adjusted_mode.vdisplay;
260 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
262 drm_for_each_encoder(encoder, crtc->dev) {
263 if (encoder->crtc != crtc)
266 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
267 drm_for_each_connector_iter(connector, &conn_iter) {
268 if (connector->encoder != encoder)
270 if (connector->display_info.bpc != 0 &&
271 bpc > connector->display_info.bpc)
272 bpc = connector->display_info.bpc;
274 drm_connector_list_iter_end(&conn_iter);
277 ret = pm_runtime_get_sync(crtc->dev->dev);
279 DRM_ERROR("Failed to enable power domain: %d\n", ret);
283 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex);
285 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
286 goto err_pm_runtime_put;
289 ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
291 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
292 goto err_mutex_unprepare;
295 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
296 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
297 mtk_crtc->ddp_comp[i]->id,
298 mtk_crtc->ddp_comp[i + 1]->id);
299 mtk_disp_mutex_add_comp(mtk_crtc->mutex,
300 mtk_crtc->ddp_comp[i]->id);
302 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
303 mtk_disp_mutex_enable(mtk_crtc->mutex);
305 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
306 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
309 mtk_ddp_comp_bgclr_in_on(comp);
311 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
312 mtk_ddp_comp_start(comp);
315 /* Initially configure all planes */
316 for (i = 0; i < mtk_crtc->layer_nr; i++) {
317 struct drm_plane *plane = &mtk_crtc->planes[i];
318 struct mtk_plane_state *plane_state;
319 struct mtk_ddp_comp *comp;
320 unsigned int local_layer;
322 plane_state = to_mtk_plane_state(plane->state);
323 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
325 mtk_ddp_comp_layer_config(comp, local_layer,
332 mtk_disp_mutex_unprepare(mtk_crtc->mutex);
334 pm_runtime_put(crtc->dev->dev);
338 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
340 struct drm_device *drm = mtk_crtc->base.dev;
341 struct drm_crtc *crtc = &mtk_crtc->base;
344 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
345 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
347 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
350 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
351 mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
352 mtk_crtc->ddp_comp[i]->id);
353 mtk_disp_mutex_disable(mtk_crtc->mutex);
354 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
355 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
356 mtk_crtc->ddp_comp[i]->id,
357 mtk_crtc->ddp_comp[i + 1]->id);
358 mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
359 mtk_crtc->ddp_comp[i]->id);
361 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
362 mtk_crtc_ddp_clk_disable(mtk_crtc);
363 mtk_disp_mutex_unprepare(mtk_crtc->mutex);
365 pm_runtime_put(drm->dev);
367 if (crtc->state->event && !crtc->state->active) {
368 spin_lock_irq(&crtc->dev->event_lock);
369 drm_crtc_send_vblank_event(crtc, crtc->state->event);
370 crtc->state->event = NULL;
371 spin_unlock_irq(&crtc->dev->event_lock);
375 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
376 struct cmdq_pkt *cmdq_handle)
378 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
379 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
380 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
382 unsigned int local_layer;
385 * TODO: instead of updating the registers here, we should prepare
386 * working registers in atomic_commit and let the hardware command
387 * queue update module registers on vblank.
389 if (state->pending_config) {
390 mtk_ddp_comp_config(comp, state->pending_width,
391 state->pending_height,
392 state->pending_vrefresh, 0,
395 state->pending_config = false;
398 if (mtk_crtc->pending_planes) {
399 for (i = 0; i < mtk_crtc->layer_nr; i++) {
400 struct drm_plane *plane = &mtk_crtc->planes[i];
401 struct mtk_plane_state *plane_state;
403 plane_state = to_mtk_plane_state(plane->state);
405 if (!plane_state->pending.config)
408 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
412 mtk_ddp_comp_layer_config(comp, local_layer,
415 plane_state->pending.config = false;
417 mtk_crtc->pending_planes = false;
420 if (mtk_crtc->pending_async_planes) {
421 for (i = 0; i < mtk_crtc->layer_nr; i++) {
422 struct drm_plane *plane = &mtk_crtc->planes[i];
423 struct mtk_plane_state *plane_state;
425 plane_state = to_mtk_plane_state(plane->state);
427 if (!plane_state->pending.async_config)
430 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
434 mtk_ddp_comp_layer_config(comp, local_layer,
437 plane_state->pending.async_config = false;
439 mtk_crtc->pending_async_planes = false;
443 static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
445 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
446 struct cmdq_pkt *cmdq_handle;
448 struct drm_crtc *crtc = &mtk_crtc->base;
449 struct mtk_drm_private *priv = crtc->dev->dev_private;
450 unsigned int pending_planes = 0, pending_async_planes = 0;
453 mutex_lock(&mtk_crtc->hw_lock);
454 for (i = 0; i < mtk_crtc->layer_nr; i++) {
455 struct drm_plane *plane = &mtk_crtc->planes[i];
456 struct mtk_plane_state *plane_state;
458 plane_state = to_mtk_plane_state(plane->state);
459 if (plane_state->pending.dirty) {
460 plane_state->pending.config = true;
461 plane_state->pending.dirty = false;
462 pending_planes |= BIT(i);
463 } else if (plane_state->pending.async_dirty) {
464 plane_state->pending.async_config = true;
465 plane_state->pending.async_dirty = false;
466 pending_async_planes |= BIT(i);
470 mtk_crtc->pending_planes = true;
471 if (pending_async_planes)
472 mtk_crtc->pending_async_planes = true;
474 if (priv->data->shadow_register) {
475 mtk_disp_mutex_acquire(mtk_crtc->mutex);
476 mtk_crtc_ddp_config(crtc, NULL);
477 mtk_disp_mutex_release(mtk_crtc->mutex);
479 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
480 if (mtk_crtc->cmdq_client) {
481 mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
482 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
483 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
484 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
485 mtk_crtc_ddp_config(crtc, cmdq_handle);
486 cmdq_pkt_finalize(cmdq_handle);
487 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
490 mutex_unlock(&mtk_crtc->hw_lock);
493 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
494 struct mtk_plane_state *state)
496 unsigned int local_layer;
497 struct mtk_ddp_comp *comp;
499 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
501 return mtk_ddp_comp_layer_check(comp, local_layer, state);
505 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
506 struct drm_plane_state *new_state)
508 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
509 const struct drm_plane_helper_funcs *plane_helper_funcs =
510 plane->helper_private;
512 if (!mtk_crtc->enabled)
515 plane_helper_funcs->atomic_update(plane, new_state);
516 mtk_drm_crtc_hw_config(mtk_crtc);
519 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
520 struct drm_crtc_state *old_state)
522 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
523 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
526 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
528 ret = mtk_smi_larb_get(comp->larb_dev);
530 DRM_ERROR("Failed to get larb: %d\n", ret);
534 ret = mtk_crtc_ddp_hw_init(mtk_crtc);
536 mtk_smi_larb_put(comp->larb_dev);
540 drm_crtc_vblank_on(crtc);
541 mtk_crtc->enabled = true;
544 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
545 struct drm_crtc_state *old_state)
547 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
548 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
551 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
552 if (!mtk_crtc->enabled)
555 /* Set all pending plane state to disabled */
556 for (i = 0; i < mtk_crtc->layer_nr; i++) {
557 struct drm_plane *plane = &mtk_crtc->planes[i];
558 struct mtk_plane_state *plane_state;
560 plane_state = to_mtk_plane_state(plane->state);
561 plane_state->pending.enable = false;
562 plane_state->pending.config = true;
564 mtk_crtc->pending_planes = true;
566 mtk_drm_crtc_hw_config(mtk_crtc);
567 /* Wait for planes to be disabled */
568 drm_crtc_wait_one_vblank(crtc);
570 drm_crtc_vblank_off(crtc);
571 mtk_crtc_ddp_hw_fini(mtk_crtc);
572 mtk_smi_larb_put(comp->larb_dev);
574 mtk_crtc->enabled = false;
577 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
578 struct drm_crtc_state *old_crtc_state)
580 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
581 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
583 if (mtk_crtc->event && state->base.event)
584 DRM_ERROR("new event while there is still a pending event\n");
586 if (state->base.event) {
587 state->base.event->pipe = drm_crtc_index(crtc);
588 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
589 mtk_crtc->event = state->base.event;
590 state->base.event = NULL;
594 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
595 struct drm_crtc_state *old_crtc_state)
597 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
601 mtk_crtc->pending_needs_vblank = true;
602 if (crtc->state->color_mgmt_changed)
603 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
604 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
605 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
607 mtk_drm_crtc_hw_config(mtk_crtc);
610 static const struct drm_crtc_funcs mtk_crtc_funcs = {
611 .set_config = drm_atomic_helper_set_config,
612 .page_flip = drm_atomic_helper_page_flip,
613 .destroy = mtk_drm_crtc_destroy,
614 .reset = mtk_drm_crtc_reset,
615 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
616 .atomic_destroy_state = mtk_drm_crtc_destroy_state,
617 .gamma_set = drm_atomic_helper_legacy_gamma_set,
618 .enable_vblank = mtk_drm_crtc_enable_vblank,
619 .disable_vblank = mtk_drm_crtc_disable_vblank,
622 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
623 .mode_fixup = mtk_drm_crtc_mode_fixup,
624 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb,
625 .atomic_begin = mtk_drm_crtc_atomic_begin,
626 .atomic_flush = mtk_drm_crtc_atomic_flush,
627 .atomic_enable = mtk_drm_crtc_atomic_enable,
628 .atomic_disable = mtk_drm_crtc_atomic_disable,
631 static int mtk_drm_crtc_init(struct drm_device *drm,
632 struct mtk_drm_crtc *mtk_crtc,
635 struct drm_plane *primary = NULL;
636 struct drm_plane *cursor = NULL;
639 for (i = 0; i < mtk_crtc->layer_nr; i++) {
640 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
641 primary = &mtk_crtc->planes[i];
642 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
643 cursor = &mtk_crtc->planes[i];
646 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
647 &mtk_crtc_funcs, NULL);
649 goto err_cleanup_crtc;
651 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
656 drm_crtc_cleanup(&mtk_crtc->base);
660 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
662 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
663 struct mtk_drm_private *priv = crtc->dev->dev_private;
665 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
666 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)
668 if (!priv->data->shadow_register)
670 mtk_crtc_ddp_config(crtc, NULL);
672 mtk_drm_finish_page_flip(mtk_crtc);
675 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
678 struct mtk_ddp_comp *comp;
683 comp = mtk_crtc->ddp_comp[comp_idx];
687 if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
690 return mtk_ddp_comp_layer_nr(comp);
694 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
695 unsigned int num_planes)
698 return DRM_PLANE_TYPE_PRIMARY;
699 else if (plane_idx == (num_planes - 1))
700 return DRM_PLANE_TYPE_CURSOR;
702 return DRM_PLANE_TYPE_OVERLAY;
706 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
707 struct mtk_drm_crtc *mtk_crtc,
708 int comp_idx, int pipe)
710 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
711 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
714 for (i = 0; i < num_planes; i++) {
715 ret = mtk_plane_init(drm_dev,
716 &mtk_crtc->planes[mtk_crtc->layer_nr],
718 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
720 mtk_ddp_comp_supported_rotations(comp));
724 mtk_crtc->layer_nr++;
729 int mtk_drm_crtc_create(struct drm_device *drm_dev,
730 const enum mtk_ddp_comp_id *path, unsigned int path_len)
732 struct mtk_drm_private *priv = drm_dev->dev_private;
733 struct device *dev = drm_dev->dev;
734 struct mtk_drm_crtc *mtk_crtc;
735 unsigned int num_comp_planes = 0;
736 int pipe = priv->num_pipes;
739 bool has_ctm = false;
740 uint gamma_lut_size = 0;
745 for (i = 0; i < path_len; i++) {
746 enum mtk_ddp_comp_id comp_id = path[i];
747 struct device_node *node;
749 node = priv->comp_node[comp_id];
752 "Not creating crtc %d because component %d is disabled or missing\n",
758 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
762 mtk_crtc->mmsys_dev = priv->mmsys_dev;
763 mtk_crtc->ddp_comp_nr = path_len;
764 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
765 sizeof(*mtk_crtc->ddp_comp),
767 if (!mtk_crtc->ddp_comp)
770 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe);
771 if (IS_ERR(mtk_crtc->mutex)) {
772 ret = PTR_ERR(mtk_crtc->mutex);
773 dev_err(dev, "Failed to get mutex: %d\n", ret);
777 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
778 enum mtk_ddp_comp_id comp_id = path[i];
779 struct mtk_ddp_comp *comp;
780 struct device_node *node;
782 node = priv->comp_node[comp_id];
783 comp = priv->ddp_comp[comp_id];
785 dev_err(dev, "Component %pOF not initialized\n", node);
790 mtk_crtc->ddp_comp[i] = comp;
793 if (comp->funcs->gamma_set)
794 gamma_lut_size = MTK_LUT_SIZE;
796 if (comp->funcs->ctm_set)
801 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
802 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
804 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
805 sizeof(struct drm_plane), GFP_KERNEL);
807 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
808 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
814 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
819 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
820 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
822 mutex_init(&mtk_crtc->hw_lock);
824 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
825 mtk_crtc->cmdq_client =
826 cmdq_mbox_create(mtk_crtc->mmsys_dev,
827 drm_crtc_index(&mtk_crtc->base),
829 if (IS_ERR(mtk_crtc->cmdq_client)) {
830 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
831 drm_crtc_index(&mtk_crtc->base));
832 mtk_crtc->cmdq_client = NULL;
834 ret = of_property_read_u32_index(priv->mutex_node,
835 "mediatek,gce-events",
836 drm_crtc_index(&mtk_crtc->base),
837 &mtk_crtc->cmdq_event);
839 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
840 drm_crtc_index(&mtk_crtc->base));