drivers/gpu/drm/mediatek/mtk_dpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Jie Qiu <jie.qiu@mediatek.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/kernel.h>
  11 #include <linux/media-bus-format.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/of_gpio.h>
  15 #include <linux/of_graph.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/types.h>
  19
  20 #include <video/videomode.h>
  21
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_bridge.h>
  24 #include <drm/drm_bridge_connector.h>
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_edid.h>
  27 #include <drm/drm_of.h>
  28 #include <drm/drm_simple_kms_helper.h>
  29
  30 #include "mtk_disp_drv.h"
  31 #include "mtk_dpi_regs.h"
  32 #include "mtk_drm_ddp_comp.h"
  33
  34 enum mtk_dpi_out_bit_num {
  35         MTK_DPI_OUT_BIT_NUM_8BITS,
  36         MTK_DPI_OUT_BIT_NUM_10BITS,
  37         MTK_DPI_OUT_BIT_NUM_12BITS,
  38         MTK_DPI_OUT_BIT_NUM_16BITS
  39 };
  40
  41 enum mtk_dpi_out_yc_map {
  42         MTK_DPI_OUT_YC_MAP_RGB,
  43         MTK_DPI_OUT_YC_MAP_CYCY,
  44         MTK_DPI_OUT_YC_MAP_YCYC,
  45         MTK_DPI_OUT_YC_MAP_CY,
  46         MTK_DPI_OUT_YC_MAP_YC
  47 };
  48
  49 enum mtk_dpi_out_channel_swap {
  50         MTK_DPI_OUT_CHANNEL_SWAP_RGB,
  51         MTK_DPI_OUT_CHANNEL_SWAP_GBR,
  52         MTK_DPI_OUT_CHANNEL_SWAP_BRG,
  53         MTK_DPI_OUT_CHANNEL_SWAP_RBG,
  54         MTK_DPI_OUT_CHANNEL_SWAP_GRB,
  55         MTK_DPI_OUT_CHANNEL_SWAP_BGR
  56 };
  57
  58 enum mtk_dpi_out_color_format {
  59         MTK_DPI_COLOR_FORMAT_RGB,
  60         MTK_DPI_COLOR_FORMAT_YCBCR_422
  61 };
  62
  63 struct mtk_dpi {
  64         struct drm_encoder encoder;
  65         struct drm_bridge bridge;
  66         struct drm_bridge *next_bridge;
  67         struct drm_connector *connector;
  68         void __iomem *regs;
  69         struct device *dev;
  70         struct clk *engine_clk;
  71         struct clk *pixel_clk;
  72         struct clk *tvd_clk;
  73         int irq;
  74         struct drm_display_mode mode;
  75         const struct mtk_dpi_conf *conf;
  76         enum mtk_dpi_out_color_format color_format;
  77         enum mtk_dpi_out_yc_map yc_map;
  78         enum mtk_dpi_out_bit_num bit_num;
  79         enum mtk_dpi_out_channel_swap channel_swap;
  80         struct pinctrl *pinctrl;
  81         struct pinctrl_state *pins_gpio;
  82         struct pinctrl_state *pins_dpi;
  83         u32 output_fmt;
  84         int refcount;
  85 };
  86
  87 static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
  88 {
  89         return container_of(b, struct mtk_dpi, bridge);
  90 }
  91
  92 enum mtk_dpi_polarity {
  93         MTK_DPI_POLARITY_RISING,
  94         MTK_DPI_POLARITY_FALLING,
  95 };
  96
  97 struct mtk_dpi_polarities {
  98         enum mtk_dpi_polarity de_pol;
  99         enum mtk_dpi_polarity ck_pol;
 100         enum mtk_dpi_polarity hsync_pol;
 101         enum mtk_dpi_polarity vsync_pol;
 102 };
 103
 104 struct mtk_dpi_sync_param {
 105         u32 sync_width;
 106         u32 front_porch;
 107         u32 back_porch;
 108         bool shift_half_line;
 109 };
 110
 111 struct mtk_dpi_yc_limit {
 112         u16 y_top;
 113         u16 y_bottom;
 114         u16 c_top;
 115         u16 c_bottom;
 116 };
 117
 118 /**
 119  * struct mtk_dpi_conf - Configuration of mediatek dpi.
 120  * @cal_factor: Callback function to calculate factor value.
 121  * @reg_h_fre_con: Register address of frequency control.
 122  * @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
 123  * @edge_sel_en: Enable of edge selection.
 124  * @output_fmts: Array of supported output formats.
 125  * @num_output_fmts: Quantity of supported output formats.
 126  * @is_ck_de_pol: Support CK/DE polarity.
 127  * @swap_input_support: Support input swap function.
 128  * @support_direct_pin: IP supports direct connection to dpi panels.
 129  * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this
 130  *                config to enable this feature.
 131  * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
 132  *                  (no shift).
 133  * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
 134  * @channel_swap_shift: Shift value of channel swap.
 135  * @yuv422_en_bit: Enable bit of yuv422.
 136  * @csc_enable_bit: Enable bit of CSC.
 137  * @pixels_per_iter: Quantity of transferred pixels per iteration.
 138  */
 139 struct mtk_dpi_conf {
 140         unsigned int (*cal_factor)(int clock);
 141         u32 reg_h_fre_con;
 142         u32 max_clock_khz;
 143         bool edge_sel_en;
 144         const u32 *output_fmts;
 145         u32 num_output_fmts;
 146         bool is_ck_de_pol;
 147         bool swap_input_support;
 148         bool support_direct_pin;
 149         bool input_2pixel;
 150         u32 dimension_mask;
 151         u32 hvsize_mask;
 152         u32 channel_swap_shift;
 153         u32 yuv422_en_bit;
 154         u32 csc_enable_bit;
 155         u32 pixels_per_iter;
 156 };
 157
 158 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
 159 {
 160         u32 tmp = readl(dpi->regs + offset) & ~mask;
 161
 162         tmp |= (val & mask);
 163         writel(tmp, dpi->regs + offset);
 164 }
 165
 166 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
 167 {
 168         mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
 169 }
 170
 171 static void mtk_dpi_enable(struct mtk_dpi *dpi)
 172 {
 173         mtk_dpi_mask(dpi, DPI_EN, EN, EN);
 174 }
 175
 176 static void mtk_dpi_disable(struct mtk_dpi *dpi)
 177 {
 178         mtk_dpi_mask(dpi, DPI_EN, 0, EN);
 179 }
 180
 181 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
 182                                  struct mtk_dpi_sync_param *sync)
 183 {
 184         mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW,
 185                      dpi->conf->dimension_mask << HPW);
 186         mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP,
 187                      dpi->conf->dimension_mask << HBP);
 188         mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
 189                      dpi->conf->dimension_mask << HFP);
 190 }
 191
 192 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
 193                                  struct mtk_dpi_sync_param *sync,
 194                                  u32 width_addr, u32 porch_addr)
 195 {
 196         mtk_dpi_mask(dpi, width_addr,
 197                      sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
 198                      VSYNC_HALF_LINE_MASK);
 199         mtk_dpi_mask(dpi, width_addr,
 200                      sync->sync_width << VSYNC_WIDTH_SHIFT,
 201                      dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT);
 202         mtk_dpi_mask(dpi, porch_addr,
 203                      sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
 204                      dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT);
 205         mtk_dpi_mask(dpi, porch_addr,
 206                      sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
 207                      dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT);
 208 }
 209
 210 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
 211                                       struct mtk_dpi_sync_param *sync)
 212 {
 213         mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
 214 }
 215
 216 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
 217                                        struct mtk_dpi_sync_param *sync)
 218 {
 219         mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN,
 220                              DPI_TGEN_VPORCH_LEVEN);
 221 }
 222
 223 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi,
 224                                       struct mtk_dpi_sync_param *sync)
 225 {
 226         mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD,
 227                              DPI_TGEN_VPORCH_RODD);
 228 }
 229
 230 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi,
 231                                        struct mtk_dpi_sync_param *sync)
 232 {
 233         mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN,
 234                              DPI_TGEN_VPORCH_REVEN);
 235 }
 236
 237 static void mtk_dpi_config_pol(struct mtk_dpi *dpi,
 238                                struct mtk_dpi_polarities *dpi_pol)
 239 {
 240         unsigned int pol;
 241         unsigned int mask;
 242
 243         mask = HSYNC_POL | VSYNC_POL;
 244         pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
 245               (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
 246         if (dpi->conf->is_ck_de_pol) {
 247                 mask |= CK_POL | DE_POL;
 248                 pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ?
 249                         0 : CK_POL) |
 250                        (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ?
 251                         0 : DE_POL);
 252         }
 253
 254         mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask);
 255 }
 256
 257 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d)
 258 {
 259         mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN);
 260 }
 261
 262 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
 263 {
 264         mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN);
 265 }
 266
 267 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
 268 {
 269         mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE,
 270                      dpi->conf->hvsize_mask << HSIZE);
 271         mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE,
 272                      dpi->conf->hvsize_mask << VSIZE);
 273 }
 274
 275 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi)
 276 {
 277         struct mtk_dpi_yc_limit limit;
 278
 279         if (drm_default_rgb_quant_range(&dpi->mode) ==
 280             HDMI_QUANTIZATION_RANGE_LIMITED) {
 281                 limit.y_bottom = 0x10;
 282                 limit.y_top = 0xfe0;
 283                 limit.c_bottom = 0x10;
 284                 limit.c_top = 0xfe0;
 285         } else {
 286                 limit.y_bottom = 0;
 287                 limit.y_top = 0xfff;
 288                 limit.c_bottom = 0;
 289                 limit.c_top = 0xfff;
 290         }
 291
 292         mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT,
 293                      Y_LIMINT_BOT_MASK);
 294         mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP,
 295                      Y_LIMINT_TOP_MASK);
 296         mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT,
 297                      C_LIMIT_BOT_MASK);
 298         mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP,
 299                      C_LIMIT_TOP_MASK);
 300 }
 301
 302 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi,
 303                                    enum mtk_dpi_out_bit_num num)
 304 {
 305         u32 val;
 306
 307         switch (num) {
 308         case MTK_DPI_OUT_BIT_NUM_8BITS:
 309                 val = OUT_BIT_8;
 310                 break;
 311         case MTK_DPI_OUT_BIT_NUM_10BITS:
 312                 val = OUT_BIT_10;
 313                 break;
 314         case MTK_DPI_OUT_BIT_NUM_12BITS:
 315                 val = OUT_BIT_12;
 316                 break;
 317         case MTK_DPI_OUT_BIT_NUM_16BITS:
 318                 val = OUT_BIT_16;
 319                 break;
 320         default:
 321                 val = OUT_BIT_8;
 322                 break;
 323         }
 324         mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT,
 325                      OUT_BIT_MASK);
 326 }
 327
 328 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi,
 329                                   enum mtk_dpi_out_yc_map map)
 330 {
 331         u32 val;
 332
 333         switch (map) {
 334         case MTK_DPI_OUT_YC_MAP_RGB:
 335                 val = YC_MAP_RGB;
 336                 break;
 337         case MTK_DPI_OUT_YC_MAP_CYCY:
 338                 val = YC_MAP_CYCY;
 339                 break;
 340         case MTK_DPI_OUT_YC_MAP_YCYC:
 341                 val = YC_MAP_YCYC;
 342                 break;
 343         case MTK_DPI_OUT_YC_MAP_CY:
 344                 val = YC_MAP_CY;
 345                 break;
 346         case MTK_DPI_OUT_YC_MAP_YC:
 347                 val = YC_MAP_YC;
 348                 break;
 349         default:
 350                 val = YC_MAP_RGB;
 351                 break;
 352         }
 353
 354         mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK);
 355 }
 356
 357 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
 358                                         enum mtk_dpi_out_channel_swap swap)
 359 {
 360         u32 val;
 361
 362         switch (swap) {
 363         case MTK_DPI_OUT_CHANNEL_SWAP_RGB:
 364                 val = SWAP_RGB;
 365                 break;
 366         case MTK_DPI_OUT_CHANNEL_SWAP_GBR:
 367                 val = SWAP_GBR;
 368                 break;
 369         case MTK_DPI_OUT_CHANNEL_SWAP_BRG:
 370                 val = SWAP_BRG;
 371                 break;
 372         case MTK_DPI_OUT_CHANNEL_SWAP_RBG:
 373                 val = SWAP_RBG;
 374                 break;
 375         case MTK_DPI_OUT_CHANNEL_SWAP_GRB:
 376                 val = SWAP_GRB;
 377                 break;
 378         case MTK_DPI_OUT_CHANNEL_SWAP_BGR:
 379                 val = SWAP_BGR;
 380                 break;
 381         default:
 382                 val = SWAP_RGB;
 383                 break;
 384         }
 385
 386         mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
 387                      val << dpi->conf->channel_swap_shift,
 388                      CH_SWAP_MASK << dpi->conf->channel_swap_shift);
 389 }
 390
 391 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
 392 {
 393         mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0,
 394                      dpi->conf->yuv422_en_bit);
 395 }
 396
 397 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
 398 {
 399         mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0,
 400                      dpi->conf->csc_enable_bit);
 401 }
 402
 403 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 404 {
 405         mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP);
 406 }
 407
 408 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 409 {
 410         mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 411 }
 412
 413 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 414 {
 415         if (dpi->conf->edge_sel_en)
 416                 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 417 }
 418
 419 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 420                                         enum mtk_dpi_out_color_format format)
 421 {
 422         mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
 423
 424         if (format == MTK_DPI_COLOR_FORMAT_YCBCR_422) {
 425                 mtk_dpi_config_yuv422_enable(dpi, true);
 426                 mtk_dpi_config_csc_enable(dpi, true);
 427
 428                 /*
 429                  * If height is smaller than 720, we need to use RGB_TO_BT601
 430                  * to transfer to yuv422. Otherwise, we use RGB_TO_JPEG.
 431                  */
 432                 mtk_dpi_mask(dpi, DPI_MATRIX_SET, dpi->mode.hdisplay <= 720 ?
 433                              MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG,
 434                              INT_MATRIX_SEL_MASK);
 435         } else {
 436                 mtk_dpi_config_yuv422_enable(dpi, false);
 437                 mtk_dpi_config_csc_enable(dpi, false);
 438                 if (dpi->conf->swap_input_support)
 439                         mtk_dpi_config_swap_input(dpi, false);
 440         }
 441 }
 442
 443 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
 444 {
 445         if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
 446             (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) {
 447                 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
 448                              DDR_EN | DDR_4PHASE);
 449                 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
 450                              dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ?
 451                              EDGE_SEL : 0, EDGE_SEL);
 452         } else {
 453                 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0);
 454         }
 455 }
 456
 457 static void mtk_dpi_power_off(struct mtk_dpi *dpi)
 458 {
 459         if (WARN_ON(dpi->refcount == 0))
 460                 return;
 461
 462         if (--dpi->refcount != 0)
 463                 return;
 464
 465         if (dpi->pinctrl && dpi->pins_gpio)
 466                 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
 467
 468         mtk_dpi_disable(dpi);
 469         clk_disable_unprepare(dpi->pixel_clk);
 470         clk_disable_unprepare(dpi->engine_clk);
 471 }
 472
 473 static int mtk_dpi_power_on(struct mtk_dpi *dpi)
 474 {
 475         int ret;
 476
 477         if (++dpi->refcount != 1)
 478                 return 0;
 479
 480         ret = clk_prepare_enable(dpi->engine_clk);
 481         if (ret) {
 482                 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
 483                 goto err_refcount;
 484         }
 485
 486         ret = clk_prepare_enable(dpi->pixel_clk);
 487         if (ret) {
 488                 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
 489                 goto err_pixel;
 490         }
 491
 492         if (dpi->pinctrl && dpi->pins_dpi)
 493                 pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
 494
 495         return 0;
 496
 497 err_pixel:
 498         clk_disable_unprepare(dpi->engine_clk);
 499 err_refcount:
 500         dpi->refcount--;
 501         return ret;
 502 }
 503
 504 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 505                                     struct drm_display_mode *mode)
 506 {
 507         struct mtk_dpi_polarities dpi_pol;
 508         struct mtk_dpi_sync_param hsync;
 509         struct mtk_dpi_sync_param vsync_lodd = { 0 };
 510         struct mtk_dpi_sync_param vsync_leven = { 0 };
 511         struct mtk_dpi_sync_param vsync_rodd = { 0 };
 512         struct mtk_dpi_sync_param vsync_reven = { 0 };
 513         struct videomode vm = { 0 };
 514         unsigned long pll_rate;
 515         unsigned int factor;
 516
 517         /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
 518         factor = dpi->conf->cal_factor(mode->clock);
 519         drm_display_mode_to_videomode(mode, &vm);
 520         pll_rate = vm.pixelclock * factor;
 521
 522         dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
 523                 pll_rate, vm.pixelclock);
 524
 525         clk_set_rate(dpi->tvd_clk, pll_rate);
 526         pll_rate = clk_get_rate(dpi->tvd_clk);
 527
 528         /*
 529          * Depending on the IP version, we may output a different amount of
 530          * pixels for each iteration: divide the clock by this number and
 531          * adjust the display porches accordingly.
 532          */
 533         vm.pixelclock = pll_rate / factor;
 534         vm.pixelclock /= dpi->conf->pixels_per_iter;
 535
 536         if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
 537             (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
 538                 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
 539         else
 540                 clk_set_rate(dpi->pixel_clk, vm.pixelclock);
 541
 542
 543         vm.pixelclock = clk_get_rate(dpi->pixel_clk);
 544
 545         dev_dbg(dpi->dev, "Got  PLL %lu Hz, pixel clock %lu Hz\n",
 546                 pll_rate, vm.pixelclock);
 547
 548         dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
 549         dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
 550         dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ?
 551                             MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
 552         dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
 553                             MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
 554
 555         /*
 556          * Depending on the IP version, we may output a different amount of
 557          * pixels for each iteration: divide the clock by this number and
 558          * adjust the display porches accordingly.
 559          */
 560         hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_iter;
 561         hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_iter;
 562         hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_iter;
 563
 564         hsync.shift_half_line = false;
 565         vsync_lodd.sync_width = vm.vsync_len;
 566         vsync_lodd.back_porch = vm.vback_porch;
 567         vsync_lodd.front_porch = vm.vfront_porch;
 568         vsync_lodd.shift_half_line = false;
 569
 570         if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
 571             mode->flags & DRM_MODE_FLAG_3D_MASK) {
 572                 vsync_leven = vsync_lodd;
 573                 vsync_rodd = vsync_lodd;
 574                 vsync_reven = vsync_lodd;
 575                 vsync_leven.shift_half_line = true;
 576                 vsync_reven.shift_half_line = true;
 577         } else if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
 578                    !(mode->flags & DRM_MODE_FLAG_3D_MASK)) {
 579                 vsync_leven = vsync_lodd;
 580                 vsync_leven.shift_half_line = true;
 581         } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) &&
 582                    mode->flags & DRM_MODE_FLAG_3D_MASK) {
 583                 vsync_rodd = vsync_lodd;
 584         }
 585         mtk_dpi_sw_reset(dpi, true);
 586         mtk_dpi_config_pol(dpi, &dpi_pol);
 587
 588         mtk_dpi_config_hsync(dpi, &hsync);
 589         mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd);
 590         mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd);
 591         mtk_dpi_config_vsync_leven(dpi, &vsync_leven);
 592         mtk_dpi_config_vsync_reven(dpi, &vsync_reven);
 593
 594         mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK));
 595         mtk_dpi_config_interface(dpi, !!(vm.flags &
 596                                          DISPLAY_FLAGS_INTERLACED));
 597         if (vm.flags & DISPLAY_FLAGS_INTERLACED)
 598                 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1);
 599         else
 600                 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
 601
 602         mtk_dpi_config_channel_limit(dpi);
 603         mtk_dpi_config_bit_num(dpi, dpi->bit_num);
 604         mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
 605         mtk_dpi_config_color_format(dpi, dpi->color_format);
 606         if (dpi->conf->support_direct_pin) {
 607                 mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 608                 mtk_dpi_config_2n_h_fre(dpi);
 609                 mtk_dpi_dual_edge(dpi);
 610                 mtk_dpi_config_disable_edge(dpi);
 611         }
 612         if (dpi->conf->input_2pixel) {
 613                 mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
 614                              DPINTF_INPUT_2P_EN);
 615         }
 616         mtk_dpi_sw_reset(dpi, false);
 617
 618         return 0;
 619 }
 620
 621 static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
 622                                                       struct drm_bridge_state *bridge_state,
 623                                                       struct drm_crtc_state *crtc_state,
 624                                                       struct drm_connector_state *conn_state,
 625                                                       unsigned int *num_output_fmts)
 626 {
 627         struct mtk_dpi *dpi = bridge_to_dpi(bridge);
 628         u32 *output_fmts;
 629
 630         *num_output_fmts = 0;
 631
 632         if (!dpi->conf->output_fmts) {
 633                 dev_err(dpi->dev, "output_fmts should not be null\n");
 634                 return NULL;
 635         }
 636
 637         output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts),
 638                              GFP_KERNEL);
 639         if (!output_fmts)
 640                 return NULL;
 641
 642         *num_output_fmts = dpi->conf->num_output_fmts;
 643
 644         memcpy(output_fmts, dpi->conf->output_fmts,
 645                sizeof(*output_fmts) * dpi->conf->num_output_fmts);
 646
 647         return output_fmts;
 648 }
 649
 650 static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 651                                                      struct drm_bridge_state *bridge_state,
 652                                                      struct drm_crtc_state *crtc_state,
 653                                                      struct drm_connector_state *conn_state,
 654                                                      u32 output_fmt,
 655                                                      unsigned int *num_input_fmts)
 656 {
 657         u32 *input_fmts;
 658
 659         *num_input_fmts = 0;
 660
 661         input_fmts = kcalloc(1, sizeof(*input_fmts),
 662                              GFP_KERNEL);
 663         if (!input_fmts)
 664                 return NULL;
 665
 666         *num_input_fmts = 1;
 667         input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
 668
 669         return input_fmts;
 670 }
 671
 672 static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
 673                                        struct drm_bridge_state *bridge_state,
 674                                        struct drm_crtc_state *crtc_state,
 675                                        struct drm_connector_state *conn_state)
 676 {
 677         struct mtk_dpi *dpi = bridge_to_dpi(bridge);
 678         unsigned int out_bus_format;
 679
 680         out_bus_format = bridge_state->output_bus_cfg.format;
 681
 682         if (out_bus_format == MEDIA_BUS_FMT_FIXED)
 683                 if (dpi->conf->num_output_fmts)
 684                         out_bus_format = dpi->conf->output_fmts[0];
 685
 686         dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
 687                 bridge_state->input_bus_cfg.format,
 688                 bridge_state->output_bus_cfg.format);
 689
 690         dpi->output_fmt = out_bus_format;
 691         dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
 692         dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
 693         dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
 694         if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)
 695                 dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422;
 696         else
 697                 dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
 698
 699         return 0;
 700 }
 701
 702 static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
 703                                  enum drm_bridge_attach_flags flags)
 704 {
 705         struct mtk_dpi *dpi = bridge_to_dpi(bridge);
 706
 707         return drm_bridge_attach(bridge->encoder, dpi->next_bridge,
 708                                  &dpi->bridge, flags);
 709 }
 710
 711 static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge,
 712                                 const struct drm_display_mode *mode,
 713                                 const struct drm_display_mode *adjusted_mode)
 714 {
 715         struct mtk_dpi *dpi = bridge_to_dpi(bridge);
 716
 717         drm_mode_copy(&dpi->mode, adjusted_mode);
 718 }
 719
 720 static void mtk_dpi_bridge_disable(struct drm_bridge *bridge)
 721 {
 722         struct mtk_dpi *dpi = bridge_to_dpi(bridge);
 723
 724         mtk_dpi_power_off(dpi);
 725 }
 726
 727 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
 728 {
 729         struct mtk_dpi *dpi = bridge_to_dpi(bridge);
 730
 731         mtk_dpi_power_on(dpi);
 732         mtk_dpi_set_display_mode(dpi, &dpi->mode);
 733         mtk_dpi_enable(dpi);
 734 }
 735
 736 static enum drm_mode_status
 737 mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
 738                           const struct drm_display_info *info,
 739                           const struct drm_display_mode *mode)
 740 {
 741         struct mtk_dpi *dpi = bridge_to_dpi(bridge);
 742
 743         if (mode->clock > dpi->conf->max_clock_khz)
 744                 return MODE_CLOCK_HIGH;
 745
 746         return MODE_OK;
 747 }
 748
 749 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
 750         .attach = mtk_dpi_bridge_attach,
 751         .mode_set = mtk_dpi_bridge_mode_set,
 752         .mode_valid = mtk_dpi_bridge_mode_valid,
 753         .disable = mtk_dpi_bridge_disable,
 754         .enable = mtk_dpi_bridge_enable,
 755         .atomic_check = mtk_dpi_bridge_atomic_check,
 756         .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts,
 757         .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts,
 758         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 759         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 760         .atomic_reset = drm_atomic_helper_bridge_reset,
 761 };
 762
 763 void mtk_dpi_start(struct device *dev)
 764 {
 765         struct mtk_dpi *dpi = dev_get_drvdata(dev);
 766
 767         mtk_dpi_power_on(dpi);
 768 }
 769
 770 void mtk_dpi_stop(struct device *dev)
 771 {
 772         struct mtk_dpi *dpi = dev_get_drvdata(dev);
 773
 774         mtk_dpi_power_off(dpi);
 775 }
 776
 777 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
 778 {
 779         struct mtk_dpi *dpi = dev_get_drvdata(dev);
 780         struct drm_device *drm_dev = data;
 781         int ret;
 782
 783         ret = drm_simple_encoder_init(drm_dev, &dpi->encoder,
 784                                       DRM_MODE_ENCODER_TMDS);
 785         if (ret) {
 786                 dev_err(dev, "Failed to initialize decoder: %d\n", ret);
 787                 return ret;
 788         }
 789
 790         dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->dev);
 791
 792         ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL,
 793                                 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
 794         if (ret)
 795                 goto err_cleanup;
 796
 797         dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder);
 798         if (IS_ERR(dpi->connector)) {
 799                 dev_err(dev, "Unable to create bridge connector\n");
 800                 ret = PTR_ERR(dpi->connector);
 801                 goto err_cleanup;
 802         }
 803         drm_connector_attach_encoder(dpi->connector, &dpi->encoder);
 804
 805         return 0;
 806
 807 err_cleanup:
 808         drm_encoder_cleanup(&dpi->encoder);
 809         return ret;
 810 }
 811
 812 static void mtk_dpi_unbind(struct device *dev, struct device *master,
 813                            void *data)
 814 {
 815         struct mtk_dpi *dpi = dev_get_drvdata(dev);
 816
 817         drm_encoder_cleanup(&dpi->encoder);
 818 }
 819
 820 static const struct component_ops mtk_dpi_component_ops = {
 821         .bind = mtk_dpi_bind,
 822         .unbind = mtk_dpi_unbind,
 823 };
 824
 825 static unsigned int mt8173_calculate_factor(int clock)
 826 {
 827         if (clock <= 27000)
 828                 return 3 << 4;
 829         else if (clock <= 84000)
 830                 return 3 << 3;
 831         else if (clock <= 167000)
 832                 return 3 << 2;
 833         else
 834                 return 3 << 1;
 835 }
 836
 837 static unsigned int mt2701_calculate_factor(int clock)
 838 {
 839         if (clock <= 64000)
 840                 return 4;
 841         else if (clock <= 128000)
 842                 return 2;
 843         else
 844                 return 1;
 845 }
 846
 847 static unsigned int mt8183_calculate_factor(int clock)
 848 {
 849         if (clock <= 27000)
 850                 return 8;
 851         else if (clock <= 167000)
 852                 return 4;
 853         else
 854                 return 2;
 855 }
 856
 857 static unsigned int mt8195_dpintf_calculate_factor(int clock)
 858 {
 859         if (clock < 70000)
 860                 return 4;
 861         else if (clock < 200000)
 862                 return 2;
 863         else
 864                 return 1;
 865 }
 866
 867 static const u32 mt8173_output_fmts[] = {
 868         MEDIA_BUS_FMT_RGB888_1X24,
 869 };
 870
 871 static const u32 mt8183_output_fmts[] = {
 872         MEDIA_BUS_FMT_RGB888_2X12_LE,
 873         MEDIA_BUS_FMT_RGB888_2X12_BE,
 874 };
 875
 876 static const u32 mt8195_output_fmts[] = {
 877         MEDIA_BUS_FMT_RGB888_1X24,
 878         MEDIA_BUS_FMT_YUYV8_1X16,
 879 };
 880
 881 static const struct mtk_dpi_conf mt8173_conf = {
 882         .cal_factor = mt8173_calculate_factor,
 883         .reg_h_fre_con = 0xe0,
 884         .max_clock_khz = 300000,
 885         .output_fmts = mt8173_output_fmts,
 886         .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
 887         .pixels_per_iter = 1,
 888         .is_ck_de_pol = true,
 889         .swap_input_support = true,
 890         .support_direct_pin = true,
 891         .dimension_mask = HPW_MASK,
 892         .hvsize_mask = HSIZE_MASK,
 893         .channel_swap_shift = CH_SWAP,
 894         .yuv422_en_bit = YUV422_EN,
 895         .csc_enable_bit = CSC_ENABLE,
 896 };
 897
 898 static const struct mtk_dpi_conf mt2701_conf = {
 899         .cal_factor = mt2701_calculate_factor,
 900         .reg_h_fre_con = 0xb0,
 901         .edge_sel_en = true,
 902         .max_clock_khz = 150000,
 903         .output_fmts = mt8173_output_fmts,
 904         .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
 905         .pixels_per_iter = 1,
 906         .is_ck_de_pol = true,
 907         .swap_input_support = true,
 908         .support_direct_pin = true,
 909         .dimension_mask = HPW_MASK,
 910         .hvsize_mask = HSIZE_MASK,
 911         .channel_swap_shift = CH_SWAP,
 912         .yuv422_en_bit = YUV422_EN,
 913         .csc_enable_bit = CSC_ENABLE,
 914 };
 915
 916 static const struct mtk_dpi_conf mt8183_conf = {
 917         .cal_factor = mt8183_calculate_factor,
 918         .reg_h_fre_con = 0xe0,
 919         .max_clock_khz = 100000,
 920         .output_fmts = mt8183_output_fmts,
 921         .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
 922         .pixels_per_iter = 1,
 923         .is_ck_de_pol = true,
 924         .swap_input_support = true,
 925         .support_direct_pin = true,
 926         .dimension_mask = HPW_MASK,
 927         .hvsize_mask = HSIZE_MASK,
 928         .channel_swap_shift = CH_SWAP,
 929         .yuv422_en_bit = YUV422_EN,
 930         .csc_enable_bit = CSC_ENABLE,
 931 };
 932
 933 static const struct mtk_dpi_conf mt8192_conf = {
 934         .cal_factor = mt8183_calculate_factor,
 935         .reg_h_fre_con = 0xe0,
 936         .max_clock_khz = 150000,
 937         .output_fmts = mt8183_output_fmts,
 938         .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
 939         .pixels_per_iter = 1,
 940         .is_ck_de_pol = true,
 941         .swap_input_support = true,
 942         .support_direct_pin = true,
 943         .dimension_mask = HPW_MASK,
 944         .hvsize_mask = HSIZE_MASK,
 945         .channel_swap_shift = CH_SWAP,
 946         .yuv422_en_bit = YUV422_EN,
 947         .csc_enable_bit = CSC_ENABLE,
 948 };
 949
 950 static const struct mtk_dpi_conf mt8195_dpintf_conf = {
 951         .cal_factor = mt8195_dpintf_calculate_factor,
 952         .max_clock_khz = 600000,
 953         .output_fmts = mt8195_output_fmts,
 954         .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
 955         .pixels_per_iter = 4,
 956         .input_2pixel = true,
 957         .dimension_mask = DPINTF_HPW_MASK,
 958         .hvsize_mask = DPINTF_HSIZE_MASK,
 959         .channel_swap_shift = DPINTF_CH_SWAP,
 960         .yuv422_en_bit = DPINTF_YUV422_EN,
 961         .csc_enable_bit = DPINTF_CSC_ENABLE,
 962 };
 963
 964 static int mtk_dpi_probe(struct platform_device *pdev)
 965 {
 966         struct device *dev = &pdev->dev;
 967         struct mtk_dpi *dpi;
 968         struct resource *mem;
 969         int ret;
 970
 971         dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
 972         if (!dpi)
 973                 return -ENOMEM;
 974
 975         dpi->dev = dev;
 976         dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
 977         dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
 978
 979         dpi->pinctrl = devm_pinctrl_get(&pdev->dev);
 980         if (IS_ERR(dpi->pinctrl)) {
 981                 dpi->pinctrl = NULL;
 982                 dev_dbg(&pdev->dev, "Cannot find pinctrl!\n");
 983         }
 984         if (dpi->pinctrl) {
 985                 dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep");
 986                 if (IS_ERR(dpi->pins_gpio)) {
 987                         dpi->pins_gpio = NULL;
 988                         dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n");
 989                 }
 990                 if (dpi->pins_gpio)
 991                         pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
 992
 993                 dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default");
 994                 if (IS_ERR(dpi->pins_dpi)) {
 995                         dpi->pins_dpi = NULL;
 996                         dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n");
 997                 }
 998         }
 999         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1000         dpi->regs = devm_ioremap_resource(dev, mem);
1001         if (IS_ERR(dpi->regs)) {
1002                 ret = PTR_ERR(dpi->regs);
1003                 dev_err(dev, "Failed to ioremap mem resource: %d\n", ret);
1004                 return ret;
1005         }
1006
1007         dpi->engine_clk = devm_clk_get(dev, "engine");
1008         if (IS_ERR(dpi->engine_clk)) {
1009                 ret = PTR_ERR(dpi->engine_clk);
1010                 if (ret != -EPROBE_DEFER)
1011                         dev_err(dev, "Failed to get engine clock: %d\n", ret);
1012
1013                 return ret;
1014         }
1015
1016         dpi->pixel_clk = devm_clk_get(dev, "pixel");
1017         if (IS_ERR(dpi->pixel_clk)) {
1018                 ret = PTR_ERR(dpi->pixel_clk);
1019                 if (ret != -EPROBE_DEFER)
1020                         dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1021
1022                 return ret;
1023         }
1024
1025         dpi->tvd_clk = devm_clk_get(dev, "pll");
1026         if (IS_ERR(dpi->tvd_clk)) {
1027                 ret = PTR_ERR(dpi->tvd_clk);
1028                 if (ret != -EPROBE_DEFER)
1029                         dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
1030
1031                 return ret;
1032         }
1033
1034         dpi->irq = platform_get_irq(pdev, 0);
1035         if (dpi->irq <= 0)
1036                 return -EINVAL;
1037
1038         ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1039                                           NULL, &dpi->next_bridge);
1040         if (ret)
1041                 return ret;
1042
1043         dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node);
1044
1045         platform_set_drvdata(pdev, dpi);
1046
1047         dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
1048         dpi->bridge.of_node = dev->of_node;
1049         dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
1050
1051         drm_bridge_add(&dpi->bridge);
1052
1053         ret = component_add(dev, &mtk_dpi_component_ops);
1054         if (ret) {
1055                 drm_bridge_remove(&dpi->bridge);
1056                 dev_err(dev, "Failed to add component: %d\n", ret);
1057                 return ret;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int mtk_dpi_remove(struct platform_device *pdev)
1064 {
1065         struct mtk_dpi *dpi = platform_get_drvdata(pdev);
1066
1067         component_del(&pdev->dev, &mtk_dpi_component_ops);
1068         drm_bridge_remove(&dpi->bridge);
1069
1070         return 0;
1071 }
1072
1073 static const struct of_device_id mtk_dpi_of_ids[] = {
1074         { .compatible = "mediatek,mt2701-dpi",
1075           .data = &mt2701_conf,
1076         },
1077         { .compatible = "mediatek,mt8173-dpi",
1078           .data = &mt8173_conf,
1079         },
1080         { .compatible = "mediatek,mt8183-dpi",
1081           .data = &mt8183_conf,
1082         },
1083         { .compatible = "mediatek,mt8192-dpi",
1084           .data = &mt8192_conf,
1085         },
1086         { .compatible = "mediatek,mt8195-dp-intf",
1087           .data = &mt8195_dpintf_conf,
1088         },
1089         { },
1090 };
1091 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
1092
1093 struct platform_driver mtk_dpi_driver = {
1094         .probe = mtk_dpi_probe,
1095         .remove = mtk_dpi_remove,
1096         .driver = {
1097                 .name = "mediatek-dpi",
1098                 .of_match_table = mtk_dpi_of_ids,
1099         },
1100 };