1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
7 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/platform_device.h>
16 #define TR_CONFIG 0x00
17 #define CLEAR_CEC_IRQ BIT(15)
19 #define CEC_CKGEN 0x04
20 #define CEC_32K_PDN BIT(19)
24 #define HDMI_PORD BIT(25)
25 #define HDMI_HTPLG BIT(24)
26 #define HDMI_PORD_INT_EN BIT(9)
27 #define HDMI_HTPLG_INT_EN BIT(8)
29 #define RX_GEN_WD 0x58
30 #define HDMI_PORD_INT_32K_STATUS BIT(26)
31 #define RX_RISC_INT_32K_STATUS BIT(25)
32 #define HDMI_HTPLG_INT_32K_STATUS BIT(24)
33 #define HDMI_PORD_INT_32K_CLR BIT(18)
34 #define RX_INT_32K_CLR BIT(17)
35 #define HDMI_HTPLG_INT_32K_CLR BIT(16)
36 #define HDMI_PORD_INT_32K_STA_MASK BIT(10)
37 #define RX_RISC_INT_32K_STA_MASK BIT(9)
38 #define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
39 #define HDMI_PORD_INT_32K_EN BIT(2)
40 #define RX_INT_32K_EN BIT(1)
41 #define HDMI_HTPLG_INT_32K_EN BIT(0)
43 #define NORMAL_INT_CTRL 0x5C
44 #define HDMI_HTPLG_INT_STA BIT(0)
45 #define HDMI_PORD_INT_STA BIT(1)
46 #define HDMI_HTPLG_INT_CLR BIT(16)
47 #define HDMI_PORD_INT_CLR BIT(17)
48 #define HDMI_FULL_INT_CLR BIT(20)
55 void (*hpd_event)(bool hpd, struct device *dev);
56 struct device *hdmi_dev;
60 static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
63 void __iomem *reg = cec->regs + offset;
71 static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
74 void __iomem *reg = cec->regs + offset;
82 static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
83 unsigned int val, unsigned int mask)
85 u32 tmp = readl(cec->regs + offset) & ~mask;
88 writel(tmp, cec->regs + offset);
91 void mtk_cec_set_hpd_event(struct device *dev,
92 void (*hpd_event)(bool hpd, struct device *dev),
93 struct device *hdmi_dev)
95 struct mtk_cec *cec = dev_get_drvdata(dev);
98 spin_lock_irqsave(&cec->lock, flags);
99 cec->hdmi_dev = hdmi_dev;
100 cec->hpd_event = hpd_event;
101 spin_unlock_irqrestore(&cec->lock, flags);
104 bool mtk_cec_hpd_high(struct device *dev)
106 struct mtk_cec *cec = dev_get_drvdata(dev);
109 status = readl(cec->regs + RX_EVENT);
111 return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
114 static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
116 mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
117 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
118 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
119 mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
120 HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
121 RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
124 static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
126 mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
129 static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
131 mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
134 static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
136 mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
137 mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
138 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
139 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
140 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
142 mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
143 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
144 mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
145 mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
146 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
149 static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
151 void (*hpd_event)(bool hpd, struct device *dev);
152 struct device *hdmi_dev;
155 spin_lock_irqsave(&cec->lock, flags);
156 hpd_event = cec->hpd_event;
157 hdmi_dev = cec->hdmi_dev;
158 spin_unlock_irqrestore(&cec->lock, flags);
161 hpd_event(hpd, hdmi_dev);
164 static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
166 struct device *dev = arg;
167 struct mtk_cec *cec = dev_get_drvdata(dev);
170 mtk_cec_clear_htplg_irq(cec);
171 hpd = mtk_cec_hpd_high(dev);
173 if (cec->hpd != hpd) {
174 dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
177 mtk_cec_hpd_event(cec, hpd);
182 static int mtk_cec_probe(struct platform_device *pdev)
184 struct device *dev = &pdev->dev;
186 struct resource *res;
189 cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
193 platform_set_drvdata(pdev, cec);
194 spin_lock_init(&cec->lock);
196 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
197 cec->regs = devm_ioremap_resource(dev, res);
198 if (IS_ERR(cec->regs)) {
199 ret = PTR_ERR(cec->regs);
200 dev_err(dev, "Failed to ioremap cec: %d\n", ret);
204 cec->clk = devm_clk_get(dev, NULL);
205 if (IS_ERR(cec->clk)) {
206 ret = PTR_ERR(cec->clk);
207 dev_err(dev, "Failed to get cec clock: %d\n", ret);
211 cec->irq = platform_get_irq(pdev, 0);
215 ret = devm_request_threaded_irq(dev, cec->irq, NULL,
216 mtk_cec_htplg_isr_thread,
217 IRQF_SHARED | IRQF_TRIGGER_LOW |
218 IRQF_ONESHOT, "hdmi hpd", dev);
220 dev_err(dev, "Failed to register cec irq: %d\n", ret);
224 ret = clk_prepare_enable(cec->clk);
226 dev_err(dev, "Failed to enable cec clock: %d\n", ret);
230 mtk_cec_htplg_irq_init(cec);
231 mtk_cec_htplg_irq_enable(cec);
236 static int mtk_cec_remove(struct platform_device *pdev)
238 struct mtk_cec *cec = platform_get_drvdata(pdev);
240 mtk_cec_htplg_irq_disable(cec);
241 clk_disable_unprepare(cec->clk);
245 static const struct of_device_id mtk_cec_of_ids[] = {
246 { .compatible = "mediatek,mt8173-cec", },
249 MODULE_DEVICE_TABLE(of, mtk_cec_of_ids);
251 struct platform_driver mtk_cec_driver = {
252 .probe = mtk_cec_probe,
253 .remove = mtk_cec_remove,
255 .name = "mediatek-cec",
256 .of_match_table = mtk_cec_of_ids,