1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Ingenic JZ47xx KMS driver - Register definitions and private API
5 // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
7 #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
8 #define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H
10 #include <linux/bitops.h>
11 #include <linux/types.h>
13 #define JZ_REG_LCD_CFG 0x00
14 #define JZ_REG_LCD_VSYNC 0x04
15 #define JZ_REG_LCD_HSYNC 0x08
16 #define JZ_REG_LCD_VAT 0x0C
17 #define JZ_REG_LCD_DAH 0x10
18 #define JZ_REG_LCD_DAV 0x14
19 #define JZ_REG_LCD_PS 0x18
20 #define JZ_REG_LCD_CLS 0x1C
21 #define JZ_REG_LCD_SPL 0x20
22 #define JZ_REG_LCD_REV 0x24
23 #define JZ_REG_LCD_CTRL 0x30
24 #define JZ_REG_LCD_STATE 0x34
25 #define JZ_REG_LCD_IID 0x38
26 #define JZ_REG_LCD_DA0 0x40
27 #define JZ_REG_LCD_SA0 0x44
28 #define JZ_REG_LCD_FID0 0x48
29 #define JZ_REG_LCD_CMD0 0x4C
30 #define JZ_REG_LCD_DA1 0x50
31 #define JZ_REG_LCD_SA1 0x54
32 #define JZ_REG_LCD_FID1 0x58
33 #define JZ_REG_LCD_CMD1 0x5C
34 #define JZ_REG_LCD_RGBC 0x90
35 #define JZ_REG_LCD_OSDC 0x100
36 #define JZ_REG_LCD_OSDCTRL 0x104
37 #define JZ_REG_LCD_OSDS 0x108
38 #define JZ_REG_LCD_BGC 0x10c
39 #define JZ_REG_LCD_KEY0 0x110
40 #define JZ_REG_LCD_KEY1 0x114
41 #define JZ_REG_LCD_ALPHA 0x118
42 #define JZ_REG_LCD_IPUR 0x11c
43 #define JZ_REG_LCD_XYP0 0x120
44 #define JZ_REG_LCD_XYP1 0x124
45 #define JZ_REG_LCD_SIZE0 0x128
46 #define JZ_REG_LCD_SIZE1 0x12c
48 #define JZ_LCD_CFG_SLCD BIT(31)
49 #define JZ_LCD_CFG_PS_DISABLE BIT(23)
50 #define JZ_LCD_CFG_CLS_DISABLE BIT(22)
51 #define JZ_LCD_CFG_SPL_DISABLE BIT(21)
52 #define JZ_LCD_CFG_REV_DISABLE BIT(20)
53 #define JZ_LCD_CFG_HSYNCM BIT(19)
54 #define JZ_LCD_CFG_PCLKM BIT(18)
55 #define JZ_LCD_CFG_INV BIT(17)
56 #define JZ_LCD_CFG_SYNC_DIR BIT(16)
57 #define JZ_LCD_CFG_PS_POLARITY BIT(15)
58 #define JZ_LCD_CFG_CLS_POLARITY BIT(14)
59 #define JZ_LCD_CFG_SPL_POLARITY BIT(13)
60 #define JZ_LCD_CFG_REV_POLARITY BIT(12)
61 #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
62 #define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
63 #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
64 #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
65 #define JZ_LCD_CFG_18_BIT BIT(7)
66 #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
68 #define JZ_LCD_CFG_MODE_GENERIC_16BIT 0
69 #define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7)
70 #define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6)
72 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1
73 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2
74 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3
76 #define JZ_LCD_CFG_MODE_TV_OUT_P 4
77 #define JZ_LCD_CFG_MODE_TV_OUT_I 6
79 #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8
80 #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9
81 #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10
82 #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11
84 #define JZ_LCD_CFG_MODE_8BIT_SERIAL 12
85 #define JZ_LCD_CFG_MODE_LCM 13
87 #define JZ_LCD_VSYNC_VPS_OFFSET 16
88 #define JZ_LCD_VSYNC_VPE_OFFSET 0
90 #define JZ_LCD_HSYNC_HPS_OFFSET 16
91 #define JZ_LCD_HSYNC_HPE_OFFSET 0
93 #define JZ_LCD_VAT_HT_OFFSET 16
94 #define JZ_LCD_VAT_VT_OFFSET 0
96 #define JZ_LCD_DAH_HDS_OFFSET 16
97 #define JZ_LCD_DAH_HDE_OFFSET 0
99 #define JZ_LCD_DAV_VDS_OFFSET 16
100 #define JZ_LCD_DAV_VDE_OFFSET 0
102 #define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
103 #define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
104 #define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
105 #define JZ_LCD_CTRL_RGB555 BIT(27)
106 #define JZ_LCD_CTRL_OFUP BIT(26)
107 #define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
108 #define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
109 #define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
110 #define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
111 #define JZ_LCD_CTRL_EOF_IRQ BIT(13)
112 #define JZ_LCD_CTRL_SOF_IRQ BIT(12)
113 #define JZ_LCD_CTRL_OFU_IRQ BIT(11)
114 #define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
115 #define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
116 #define JZ_LCD_CTRL_DD_IRQ BIT(8)
117 #define JZ_LCD_CTRL_QDD_IRQ BIT(7)
118 #define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
119 #define JZ_LCD_CTRL_LSB_FISRT BIT(5)
120 #define JZ_LCD_CTRL_DISABLE BIT(4)
121 #define JZ_LCD_CTRL_ENABLE BIT(3)
122 #define JZ_LCD_CTRL_BPP_1 0x0
123 #define JZ_LCD_CTRL_BPP_2 0x1
124 #define JZ_LCD_CTRL_BPP_4 0x2
125 #define JZ_LCD_CTRL_BPP_8 0x3
126 #define JZ_LCD_CTRL_BPP_15_16 0x4
127 #define JZ_LCD_CTRL_BPP_18_24 0x5
128 #define JZ_LCD_CTRL_BPP_24_COMP 0x6
129 #define JZ_LCD_CTRL_BPP_30 0x7
130 #define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7)
132 #define JZ_LCD_CMD_SOF_IRQ BIT(31)
133 #define JZ_LCD_CMD_EOF_IRQ BIT(30)
134 #define JZ_LCD_CMD_ENABLE_PAL BIT(28)
136 #define JZ_LCD_SYNC_MASK 0x3ff
138 #define JZ_LCD_STATE_EOF_IRQ BIT(5)
139 #define JZ_LCD_STATE_SOF_IRQ BIT(4)
140 #define JZ_LCD_STATE_DISABLED BIT(0)
142 #define JZ_LCD_RGBC_ODD_RGB (0x0 << 4)
143 #define JZ_LCD_RGBC_ODD_RBG (0x1 << 4)
144 #define JZ_LCD_RGBC_ODD_GRB (0x2 << 4)
145 #define JZ_LCD_RGBC_ODD_GBR (0x3 << 4)
146 #define JZ_LCD_RGBC_ODD_BRG (0x4 << 4)
147 #define JZ_LCD_RGBC_ODD_BGR (0x5 << 4)
148 #define JZ_LCD_RGBC_EVEN_RGB (0x0 << 0)
149 #define JZ_LCD_RGBC_EVEN_RBG (0x1 << 0)
150 #define JZ_LCD_RGBC_EVEN_GRB (0x2 << 0)
151 #define JZ_LCD_RGBC_EVEN_GBR (0x3 << 0)
152 #define JZ_LCD_RGBC_EVEN_BRG (0x4 << 0)
153 #define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0)
155 #define JZ_LCD_OSDC_OSDEN BIT(0)
156 #define JZ_LCD_OSDC_F0EN BIT(3)
157 #define JZ_LCD_OSDC_F1EN BIT(4)
159 #define JZ_LCD_OSDCTRL_IPU BIT(15)
160 #define JZ_LCD_OSDCTRL_RGB555 BIT(4)
161 #define JZ_LCD_OSDCTRL_CHANGE BIT(3)
162 #define JZ_LCD_OSDCTRL_BPP_15_16 0x4
163 #define JZ_LCD_OSDCTRL_BPP_18_24 0x5
164 #define JZ_LCD_OSDCTRL_BPP_24_COMP 0x6
165 #define JZ_LCD_OSDCTRL_BPP_30 0x7
166 #define JZ_LCD_OSDCTRL_BPP_MASK (JZ_LCD_OSDCTRL_RGB555 | 0x7)
168 #define JZ_LCD_OSDS_READY BIT(0)
170 #define JZ_LCD_IPUR_IPUREN BIT(31)
171 #define JZ_LCD_IPUR_IPUR_LSB 0
173 #define JZ_LCD_XYP01_XPOS_LSB 0
174 #define JZ_LCD_XYP01_YPOS_LSB 16
176 #define JZ_LCD_SIZE01_WIDTH_LSB 0
177 #define JZ_LCD_SIZE01_HEIGHT_LSB 16
181 struct drm_plane_state;
182 struct platform_driver;
184 void ingenic_drm_plane_config(struct device *dev,
185 struct drm_plane *plane, u32 fourcc);
186 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane);
188 extern struct platform_driver *ingenic_ipu_driver_ptr;
190 #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */