1 // SPDX-License-Identifier: GPL-2.0
3 // Ingenic JZ47xx KMS driver
5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
8 #include <linux/dma-mapping.h>
9 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
14 #include <drm/drm_atomic.h>
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_gem_cma_helper.h>
20 #include <drm/drm_fb_cma_helper.h>
21 #include <drm/drm_fb_helper.h>
22 #include <drm/drm_fourcc.h>
23 #include <drm/drm_gem_framebuffer_helper.h>
24 #include <drm/drm_irq.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_panel.h>
27 #include <drm/drm_plane.h>
28 #include <drm/drm_plane_helper.h>
29 #include <drm/drm_probe_helper.h>
30 #include <drm/drm_vblank.h>
32 #define JZ_REG_LCD_CFG 0x00
33 #define JZ_REG_LCD_VSYNC 0x04
34 #define JZ_REG_LCD_HSYNC 0x08
35 #define JZ_REG_LCD_VAT 0x0C
36 #define JZ_REG_LCD_DAH 0x10
37 #define JZ_REG_LCD_DAV 0x14
38 #define JZ_REG_LCD_PS 0x18
39 #define JZ_REG_LCD_CLS 0x1C
40 #define JZ_REG_LCD_SPL 0x20
41 #define JZ_REG_LCD_REV 0x24
42 #define JZ_REG_LCD_CTRL 0x30
43 #define JZ_REG_LCD_STATE 0x34
44 #define JZ_REG_LCD_IID 0x38
45 #define JZ_REG_LCD_DA0 0x40
46 #define JZ_REG_LCD_SA0 0x44
47 #define JZ_REG_LCD_FID0 0x48
48 #define JZ_REG_LCD_CMD0 0x4C
49 #define JZ_REG_LCD_DA1 0x50
50 #define JZ_REG_LCD_SA1 0x54
51 #define JZ_REG_LCD_FID1 0x58
52 #define JZ_REG_LCD_CMD1 0x5C
54 #define JZ_LCD_CFG_SLCD BIT(31)
55 #define JZ_LCD_CFG_PS_DISABLE BIT(23)
56 #define JZ_LCD_CFG_CLS_DISABLE BIT(22)
57 #define JZ_LCD_CFG_SPL_DISABLE BIT(21)
58 #define JZ_LCD_CFG_REV_DISABLE BIT(20)
59 #define JZ_LCD_CFG_HSYNCM BIT(19)
60 #define JZ_LCD_CFG_PCLKM BIT(18)
61 #define JZ_LCD_CFG_INV BIT(17)
62 #define JZ_LCD_CFG_SYNC_DIR BIT(16)
63 #define JZ_LCD_CFG_PS_POLARITY BIT(15)
64 #define JZ_LCD_CFG_CLS_POLARITY BIT(14)
65 #define JZ_LCD_CFG_SPL_POLARITY BIT(13)
66 #define JZ_LCD_CFG_REV_POLARITY BIT(12)
67 #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
68 #define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
69 #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
70 #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
71 #define JZ_LCD_CFG_18_BIT BIT(7)
72 #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
74 #define JZ_LCD_CFG_MODE_GENERIC_16BIT 0
75 #define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7)
76 #define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6)
78 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1
79 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2
80 #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3
82 #define JZ_LCD_CFG_MODE_TV_OUT_P 4
83 #define JZ_LCD_CFG_MODE_TV_OUT_I 6
85 #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8
86 #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9
87 #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10
88 #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11
90 #define JZ_LCD_CFG_MODE_8BIT_SERIAL 12
91 #define JZ_LCD_CFG_MODE_LCM 13
93 #define JZ_LCD_VSYNC_VPS_OFFSET 16
94 #define JZ_LCD_VSYNC_VPE_OFFSET 0
96 #define JZ_LCD_HSYNC_HPS_OFFSET 16
97 #define JZ_LCD_HSYNC_HPE_OFFSET 0
99 #define JZ_LCD_VAT_HT_OFFSET 16
100 #define JZ_LCD_VAT_VT_OFFSET 0
102 #define JZ_LCD_DAH_HDS_OFFSET 16
103 #define JZ_LCD_DAH_HDE_OFFSET 0
105 #define JZ_LCD_DAV_VDS_OFFSET 16
106 #define JZ_LCD_DAV_VDE_OFFSET 0
108 #define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
109 #define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
110 #define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
111 #define JZ_LCD_CTRL_RGB555 BIT(27)
112 #define JZ_LCD_CTRL_OFUP BIT(26)
113 #define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
114 #define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
115 #define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
116 #define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
117 #define JZ_LCD_CTRL_EOF_IRQ BIT(13)
118 #define JZ_LCD_CTRL_SOF_IRQ BIT(12)
119 #define JZ_LCD_CTRL_OFU_IRQ BIT(11)
120 #define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
121 #define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
122 #define JZ_LCD_CTRL_DD_IRQ BIT(8)
123 #define JZ_LCD_CTRL_QDD_IRQ BIT(7)
124 #define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
125 #define JZ_LCD_CTRL_LSB_FISRT BIT(5)
126 #define JZ_LCD_CTRL_DISABLE BIT(4)
127 #define JZ_LCD_CTRL_ENABLE BIT(3)
128 #define JZ_LCD_CTRL_BPP_1 0x0
129 #define JZ_LCD_CTRL_BPP_2 0x1
130 #define JZ_LCD_CTRL_BPP_4 0x2
131 #define JZ_LCD_CTRL_BPP_8 0x3
132 #define JZ_LCD_CTRL_BPP_15_16 0x4
133 #define JZ_LCD_CTRL_BPP_18_24 0x5
134 #define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | (0x7 << 0))
136 #define JZ_LCD_CMD_SOF_IRQ BIT(31)
137 #define JZ_LCD_CMD_EOF_IRQ BIT(30)
138 #define JZ_LCD_CMD_ENABLE_PAL BIT(28)
140 #define JZ_LCD_SYNC_MASK 0x3ff
142 #define JZ_LCD_STATE_EOF_IRQ BIT(5)
143 #define JZ_LCD_STATE_SOF_IRQ BIT(4)
144 #define JZ_LCD_STATE_DISABLED BIT(0)
146 struct ingenic_dma_hwdesc {
158 struct drm_device drm;
159 struct drm_plane primary;
160 struct drm_crtc crtc;
161 struct drm_encoder encoder;
165 struct clk *lcd_clk, *pix_clk;
167 struct ingenic_dma_hwdesc *dma_hwdesc;
168 dma_addr_t dma_hwdesc_phys;
171 static const u32 ingenic_drm_primary_formats[] = {
177 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
182 case JZ_REG_LCD_FID0:
183 case JZ_REG_LCD_CMD0:
185 case JZ_REG_LCD_FID1:
186 case JZ_REG_LCD_CMD1:
193 static const struct regmap_config ingenic_drm_regmap_config = {
198 .max_register = JZ_REG_LCD_CMD1,
199 .writeable_reg = ingenic_drm_writeable_reg,
202 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
204 return container_of(drm, struct ingenic_drm, drm);
207 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
209 return container_of(crtc, struct ingenic_drm, crtc);
212 static inline struct ingenic_drm *
213 drm_encoder_get_priv(struct drm_encoder *encoder)
215 return container_of(encoder, struct ingenic_drm, encoder);
218 static inline struct ingenic_drm *drm_plane_get_priv(struct drm_plane *plane)
220 return container_of(plane, struct ingenic_drm, primary);
223 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
224 struct drm_crtc_state *state)
226 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
228 regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
230 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
231 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
234 drm_crtc_vblank_on(crtc);
237 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
238 struct drm_crtc_state *state)
240 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
243 drm_crtc_vblank_off(crtc);
245 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
246 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
248 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
249 var & JZ_LCD_STATE_DISABLED,
253 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
254 struct drm_display_mode *mode)
256 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
258 vpe = mode->vsync_end - mode->vsync_start;
259 vds = mode->vtotal - mode->vsync_start;
260 vde = vds + mode->vdisplay;
261 vt = vde + mode->vsync_start - mode->vdisplay;
263 hpe = mode->hsync_end - mode->hsync_start;
264 hds = mode->htotal - mode->hsync_start;
265 hde = hds + mode->hdisplay;
266 ht = hde + mode->hsync_start - mode->hdisplay;
268 regmap_write(priv->map, JZ_REG_LCD_VSYNC,
269 0 << JZ_LCD_VSYNC_VPS_OFFSET |
270 vpe << JZ_LCD_VSYNC_VPE_OFFSET);
272 regmap_write(priv->map, JZ_REG_LCD_HSYNC,
273 0 << JZ_LCD_HSYNC_HPS_OFFSET |
274 hpe << JZ_LCD_HSYNC_HPE_OFFSET);
276 regmap_write(priv->map, JZ_REG_LCD_VAT,
277 ht << JZ_LCD_VAT_HT_OFFSET |
278 vt << JZ_LCD_VAT_VT_OFFSET);
280 regmap_write(priv->map, JZ_REG_LCD_DAH,
281 hds << JZ_LCD_DAH_HDS_OFFSET |
282 hde << JZ_LCD_DAH_HDE_OFFSET);
283 regmap_write(priv->map, JZ_REG_LCD_DAV,
284 vds << JZ_LCD_DAV_VDS_OFFSET |
285 vde << JZ_LCD_DAV_VDE_OFFSET);
288 static void ingenic_drm_crtc_update_ctrl(struct ingenic_drm *priv,
289 const struct drm_format_info *finfo)
291 unsigned int ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
293 switch (finfo->format) {
294 case DRM_FORMAT_XRGB1555:
295 ctrl |= JZ_LCD_CTRL_RGB555;
297 case DRM_FORMAT_RGB565:
298 ctrl |= JZ_LCD_CTRL_BPP_15_16;
300 case DRM_FORMAT_XRGB8888:
301 ctrl |= JZ_LCD_CTRL_BPP_18_24;
305 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
306 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16 |
307 JZ_LCD_CTRL_BPP_MASK, ctrl);
310 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
311 struct drm_crtc_state *state)
313 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
316 if (!drm_atomic_crtc_needs_modeset(state))
319 rate = clk_round_rate(priv->pix_clk,
320 state->adjusted_mode.clock * 1000);
327 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
328 struct drm_crtc_state *oldstate)
330 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
331 struct drm_crtc_state *state = crtc->state;
332 struct drm_pending_vblank_event *event = state->event;
333 struct drm_framebuffer *drm_fb = crtc->primary->state->fb;
334 const struct drm_format_info *finfo;
336 if (drm_atomic_crtc_needs_modeset(state)) {
337 finfo = drm_format_info(drm_fb->format->format);
339 ingenic_drm_crtc_update_timings(priv, &state->mode);
340 ingenic_drm_crtc_update_ctrl(priv, finfo);
342 clk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000);
344 regmap_write(priv->map, JZ_REG_LCD_DA0, priv->dma_hwdesc->next);
350 spin_lock_irq(&crtc->dev->event_lock);
351 if (drm_crtc_vblank_get(crtc) == 0)
352 drm_crtc_arm_vblank_event(crtc, event);
354 drm_crtc_send_vblank_event(crtc, event);
355 spin_unlock_irq(&crtc->dev->event_lock);
359 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
360 struct drm_plane_state *oldstate)
362 struct ingenic_drm *priv = drm_plane_get_priv(plane);
363 struct drm_plane_state *state = plane->state;
364 unsigned int width, height, cpp;
366 width = state->crtc->state->adjusted_mode.hdisplay;
367 height = state->crtc->state->adjusted_mode.vdisplay;
368 cpp = state->fb->format->cpp[plane->index];
370 priv->dma_hwdesc->addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
371 priv->dma_hwdesc->cmd = width * height * cpp / 4;
372 priv->dma_hwdesc->cmd |= JZ_LCD_CMD_EOF_IRQ;
375 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
376 struct drm_crtc_state *crtc_state,
377 struct drm_connector_state *conn_state)
379 struct ingenic_drm *priv = drm_encoder_get_priv(encoder);
380 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
381 struct drm_display_info *info = &conn_state->connector->display_info;
382 unsigned int cfg = JZ_LCD_CFG_PS_DISABLE
383 | JZ_LCD_CFG_CLS_DISABLE
384 | JZ_LCD_CFG_SPL_DISABLE
385 | JZ_LCD_CFG_REV_DISABLE;
387 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
388 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
389 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
390 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
391 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
392 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
393 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
394 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
396 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) {
397 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
398 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
400 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
402 switch (*info->bus_formats) {
403 case MEDIA_BUS_FMT_RGB565_1X16:
404 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
406 case MEDIA_BUS_FMT_RGB666_1X18:
407 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
409 case MEDIA_BUS_FMT_RGB888_1X24:
410 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
417 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
420 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
421 struct drm_crtc_state *crtc_state,
422 struct drm_connector_state *conn_state)
424 struct drm_display_info *info = &conn_state->connector->display_info;
426 if (info->num_bus_formats != 1)
429 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
432 switch (*info->bus_formats) {
433 case MEDIA_BUS_FMT_RGB565_1X16:
434 case MEDIA_BUS_FMT_RGB666_1X18:
435 case MEDIA_BUS_FMT_RGB888_1X24:
442 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
444 struct ingenic_drm *priv = arg;
447 regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
449 regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
450 JZ_LCD_STATE_EOF_IRQ, 0);
452 if (state & JZ_LCD_STATE_EOF_IRQ)
453 drm_crtc_handle_vblank(&priv->crtc);
458 static void ingenic_drm_release(struct drm_device *drm)
460 struct ingenic_drm *priv = drm_device_get_priv(drm);
462 drm_mode_config_cleanup(drm);
467 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
469 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
471 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
472 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
477 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
479 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
481 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
484 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
486 static struct drm_driver ingenic_drm_driver_data = {
487 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME
489 .name = "ingenic-drm",
490 .desc = "DRM module for Ingenic SoCs",
496 .fops = &ingenic_drm_fops,
498 .dumb_create = drm_gem_cma_dumb_create,
499 .gem_free_object_unlocked = drm_gem_cma_free_object,
500 .gem_vm_ops = &drm_gem_cma_vm_ops,
502 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
503 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
504 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
505 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
506 .gem_prime_vmap = drm_gem_cma_prime_vmap,
507 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
508 .gem_prime_mmap = drm_gem_cma_prime_mmap,
510 .irq_handler = ingenic_drm_irq_handler,
511 .release = ingenic_drm_release,
514 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = {
515 .update_plane = drm_atomic_helper_update_plane,
516 .disable_plane = drm_atomic_helper_disable_plane,
517 .reset = drm_atomic_helper_plane_reset,
518 .destroy = drm_plane_cleanup,
520 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
521 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
524 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = {
525 .set_config = drm_atomic_helper_set_config,
526 .page_flip = drm_atomic_helper_page_flip,
527 .reset = drm_atomic_helper_crtc_reset,
528 .destroy = drm_crtc_cleanup,
530 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
531 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
533 .enable_vblank = ingenic_drm_enable_vblank,
534 .disable_vblank = ingenic_drm_disable_vblank,
536 .gamma_set = drm_atomic_helper_legacy_gamma_set,
539 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {
540 .atomic_update = ingenic_drm_plane_atomic_update,
541 .prepare_fb = drm_gem_fb_prepare_fb,
544 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = {
545 .atomic_enable = ingenic_drm_crtc_atomic_enable,
546 .atomic_disable = ingenic_drm_crtc_atomic_disable,
547 .atomic_flush = ingenic_drm_crtc_atomic_flush,
548 .atomic_check = ingenic_drm_crtc_atomic_check,
551 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = {
552 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set,
553 .atomic_check = ingenic_drm_encoder_atomic_check,
556 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = {
557 .fb_create = drm_gem_fb_create,
558 .output_poll_changed = drm_fb_helper_output_poll_changed,
559 .atomic_check = drm_atomic_helper_check,
560 .atomic_commit = drm_atomic_helper_commit,
563 static const struct drm_encoder_funcs ingenic_drm_encoder_funcs = {
564 .destroy = drm_encoder_cleanup,
567 static void ingenic_drm_free_dma_hwdesc(void *d)
569 struct ingenic_drm *priv = d;
571 dma_free_coherent(priv->dev, sizeof(*priv->dma_hwdesc),
572 priv->dma_hwdesc, priv->dma_hwdesc_phys);
575 static int ingenic_drm_probe(struct platform_device *pdev)
577 const struct jz_soc_info *soc_info;
578 struct device *dev = &pdev->dev;
579 struct ingenic_drm *priv;
580 struct clk *parent_clk;
581 struct drm_bridge *bridge;
582 struct drm_panel *panel;
583 struct drm_device *drm;
584 struct resource *mem;
589 soc_info = of_device_get_match_data(dev);
591 dev_err(dev, "Missing platform data\n");
595 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
601 drm->dev_private = priv;
603 platform_set_drvdata(pdev, priv);
605 ret = devm_drm_dev_init(dev, drm, &ingenic_drm_driver_data);
611 drm_mode_config_init(drm);
612 drm->mode_config.min_width = 0;
613 drm->mode_config.min_height = 0;
614 drm->mode_config.max_width = 800;
615 drm->mode_config.max_height = 600;
616 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
618 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
619 base = devm_ioremap_resource(dev, mem);
621 dev_err(dev, "Failed to get memory resource");
622 return PTR_ERR(base);
625 priv->map = devm_regmap_init_mmio(dev, base,
626 &ingenic_drm_regmap_config);
627 if (IS_ERR(priv->map)) {
628 dev_err(dev, "Failed to create regmap");
629 return PTR_ERR(priv->map);
632 irq = platform_get_irq(pdev, 0);
634 dev_err(dev, "Failed to get platform irq");
638 if (soc_info->needs_dev_clk) {
639 priv->lcd_clk = devm_clk_get(dev, "lcd");
640 if (IS_ERR(priv->lcd_clk)) {
641 dev_err(dev, "Failed to get lcd clock");
642 return PTR_ERR(priv->lcd_clk);
646 priv->pix_clk = devm_clk_get(dev, "lcd_pclk");
647 if (IS_ERR(priv->pix_clk)) {
648 dev_err(dev, "Failed to get pixel clock");
649 return PTR_ERR(priv->pix_clk);
652 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, &panel, &bridge);
654 if (ret != -EPROBE_DEFER)
655 dev_err(dev, "Failed to get panel handle");
660 bridge = devm_drm_panel_bridge_add(dev, panel,
661 DRM_MODE_CONNECTOR_Unknown);
664 priv->dma_hwdesc = dma_alloc_coherent(dev, sizeof(*priv->dma_hwdesc),
665 &priv->dma_hwdesc_phys,
667 if (!priv->dma_hwdesc)
670 ret = devm_add_action_or_reset(dev, ingenic_drm_free_dma_hwdesc, priv);
674 priv->dma_hwdesc->next = priv->dma_hwdesc_phys;
675 priv->dma_hwdesc->id = 0xdeafbead;
677 drm_plane_helper_add(&priv->primary, &ingenic_drm_plane_helper_funcs);
679 ret = drm_universal_plane_init(drm, &priv->primary,
680 0, &ingenic_drm_primary_plane_funcs,
681 ingenic_drm_primary_formats,
682 ARRAY_SIZE(ingenic_drm_primary_formats),
683 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
685 dev_err(dev, "Failed to register primary plane: %i", ret);
689 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs);
691 ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->primary,
692 NULL, &ingenic_drm_crtc_funcs, NULL);
694 dev_err(dev, "Failed to init CRTC: %i", ret);
698 priv->encoder.possible_crtcs = 1;
700 drm_encoder_helper_add(&priv->encoder,
701 &ingenic_drm_encoder_helper_funcs);
703 ret = drm_encoder_init(drm, &priv->encoder, &ingenic_drm_encoder_funcs,
704 DRM_MODE_ENCODER_DPI, NULL);
706 dev_err(dev, "Failed to init encoder: %i", ret);
710 ret = drm_bridge_attach(&priv->encoder, bridge, NULL);
712 dev_err(dev, "Unable to attach bridge");
716 ret = drm_irq_install(drm, irq);
718 dev_err(dev, "Unable to install IRQ handler");
722 ret = drm_vblank_init(drm, 1);
724 dev_err(dev, "Failed calling drm_vblank_init()");
728 drm_mode_config_reset(drm);
730 ret = clk_prepare_enable(priv->pix_clk);
732 dev_err(dev, "Unable to start pixel clock");
737 parent_clk = clk_get_parent(priv->lcd_clk);
738 parent_rate = clk_get_rate(parent_clk);
740 /* LCD Device clock must be 3x the pixel clock for STN panels,
741 * or 1.5x the pixel clock for TFT panels. To avoid having to
742 * check for the LCD device clock everytime we do a mode change,
743 * we set the LCD device clock to the highest rate possible.
745 ret = clk_set_rate(priv->lcd_clk, parent_rate);
747 dev_err(dev, "Unable to set LCD clock rate");
748 goto err_pixclk_disable;
751 ret = clk_prepare_enable(priv->lcd_clk);
753 dev_err(dev, "Unable to start lcd clock");
754 goto err_pixclk_disable;
758 ret = drm_dev_register(drm, 0);
760 dev_err(dev, "Failed to register DRM driver");
761 goto err_devclk_disable;
764 ret = drm_fbdev_generic_setup(drm, 32);
766 dev_warn(dev, "Unable to start fbdev emulation: %i", ret);
772 clk_disable_unprepare(priv->lcd_clk);
774 clk_disable_unprepare(priv->pix_clk);
778 static int ingenic_drm_remove(struct platform_device *pdev)
780 struct ingenic_drm *priv = platform_get_drvdata(pdev);
783 clk_disable_unprepare(priv->lcd_clk);
784 clk_disable_unprepare(priv->pix_clk);
786 drm_dev_unregister(&priv->drm);
787 drm_atomic_helper_shutdown(&priv->drm);
792 static const struct jz_soc_info jz4740_soc_info = {
793 .needs_dev_clk = true,
796 static const struct jz_soc_info jz4725b_soc_info = {
797 .needs_dev_clk = false,
800 static const struct of_device_id ingenic_drm_of_match[] = {
801 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info },
802 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info },
806 static struct platform_driver ingenic_drm_driver = {
808 .name = "ingenic-drm",
809 .of_match_table = of_match_ptr(ingenic_drm_of_match),
811 .probe = ingenic_drm_probe,
812 .remove = ingenic_drm_remove,
814 module_platform_driver(ingenic_drm_driver);
816 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
817 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n");
818 MODULE_LICENSE("GPL v2");