drivers/gpu/drm/ingenic/ingenic-drm-drv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Ingenic JZ47xx KMS driver
   4 //
   5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
   6
   7 #include "ingenic-drm.h"
   8
   9 #include <linux/component.h>
  10 #include <linux/clk.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dma-noncoherent.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_reserved_mem.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_bridge.h>
  24 #include <drm/drm_crtc.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_damage_helper.h>
  27 #include <drm/drm_drv.h>
  28 #include <drm/drm_gem_cma_helper.h>
  29 #include <drm/drm_fb_cma_helper.h>
  30 #include <drm/drm_fb_helper.h>
  31 #include <drm/drm_fourcc.h>
  32 #include <drm/drm_gem_framebuffer_helper.h>
  33 #include <drm/drm_irq.h>
  34 #include <drm/drm_managed.h>
  35 #include <drm/drm_of.h>
  36 #include <drm/drm_panel.h>
  37 #include <drm/drm_plane.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_probe_helper.h>
  40 #include <drm/drm_simple_kms_helper.h>
  41 #include <drm/drm_vblank.h>
  42
  43 struct ingenic_dma_hwdesc {
  44         u32 next;
  45         u32 addr;
  46         u32 id;
  47         u32 cmd;
  48 } __aligned(16);
  49
  50 struct ingenic_dma_hwdescs {
  51         struct ingenic_dma_hwdesc hwdesc_f0;
  52         struct ingenic_dma_hwdesc hwdesc_f1;
  53 };
  54
  55 struct jz_soc_info {
  56         bool needs_dev_clk;
  57         bool has_osd;
  58         unsigned int max_width, max_height;
  59 };
  60
  61 struct ingenic_drm {
  62         struct drm_device drm;
  63         /*
  64          * f1 (aka. foreground1) is our primary plane, on top of which
  65          * f0 (aka. foreground0) can be overlayed. Z-order is fixed in
  66          * hardware and cannot be changed.
  67          */
  68         struct drm_plane f0, f1, *ipu_plane;
  69         struct drm_crtc crtc;
  70
  71         struct device *dev;
  72         struct regmap *map;
  73         struct clk *lcd_clk, *pix_clk;
  74         const struct jz_soc_info *soc_info;
  75
  76         struct ingenic_dma_hwdescs *dma_hwdescs;
  77         dma_addr_t dma_hwdescs_phys;
  78
  79         bool panel_is_sharp;
  80         bool no_vblank;
  81
  82         /*
  83          * clk_mutex is used to synchronize the pixel clock rate update with
  84          * the VBLANK. When the pixel clock's parent clock needs to be updated,
  85          * clock_nb's notifier function will lock the mutex, then wait until the
  86          * next VBLANK. At that point, the parent clock's rate can be updated,
  87          * and the mutex is then unlocked. If an atomic commit happens in the
  88          * meantime, it will lock on the mutex, effectively waiting until the
  89          * clock update process finishes. Finally, the pixel clock's rate will
  90          * be recomputed when the mutex has been released, in the pending atomic
  91          * commit, or a future one.
  92          */
  93         struct mutex clk_mutex;
  94         bool update_clk_rate;
  95         struct notifier_block clock_nb;
  96 };
  97
  98 static const u32 ingenic_drm_primary_formats[] = {
  99         DRM_FORMAT_XRGB1555,
 100         DRM_FORMAT_RGB565,
 101         DRM_FORMAT_XRGB8888,
 102 };
 103
 104 static bool ingenic_drm_cached_gem_buf;
 105 module_param_named(cached_gem_buffers, ingenic_drm_cached_gem_buf, bool, 0400);
 106 MODULE_PARM_DESC(cached_gem_buffers,
 107                  "Enable fully cached GEM buffers [default=false]");
 108
 109 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
 110 {
 111         switch (reg) {
 112         case JZ_REG_LCD_IID:
 113         case JZ_REG_LCD_SA0:
 114         case JZ_REG_LCD_FID0:
 115         case JZ_REG_LCD_CMD0:
 116         case JZ_REG_LCD_SA1:
 117         case JZ_REG_LCD_FID1:
 118         case JZ_REG_LCD_CMD1:
 119                 return false;
 120         default:
 121                 return true;
 122         }
 123 }
 124
 125 static const struct regmap_config ingenic_drm_regmap_config = {
 126         .reg_bits = 32,
 127         .val_bits = 32,
 128         .reg_stride = 4,
 129
 130         .max_register = JZ_REG_LCD_SIZE1,
 131         .writeable_reg = ingenic_drm_writeable_reg,
 132 };
 133
 134 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
 135 {
 136         return container_of(drm, struct ingenic_drm, drm);
 137 }
 138
 139 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
 140 {
 141         return container_of(crtc, struct ingenic_drm, crtc);
 142 }
 143
 144 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb)
 145 {
 146         return container_of(nb, struct ingenic_drm, clock_nb);
 147 }
 148
 149 static int ingenic_drm_update_pixclk(struct notifier_block *nb,
 150                                      unsigned long action,
 151                                      void *data)
 152 {
 153         struct ingenic_drm *priv = drm_nb_get_priv(nb);
 154
 155         switch (action) {
 156         case PRE_RATE_CHANGE:
 157                 mutex_lock(&priv->clk_mutex);
 158                 priv->update_clk_rate = true;
 159                 drm_crtc_wait_one_vblank(&priv->crtc);
 160                 return NOTIFY_OK;
 161         default:
 162                 mutex_unlock(&priv->clk_mutex);
 163                 return NOTIFY_OK;
 164         }
 165 }
 166
 167 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 168                                            struct drm_crtc_state *state)
 169 {
 170         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 171
 172         regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
 173
 174         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 175                            JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
 176                            JZ_LCD_CTRL_ENABLE);
 177
 178         drm_crtc_vblank_on(crtc);
 179 }
 180
 181 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 182                                             struct drm_crtc_state *state)
 183 {
 184         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 185         unsigned int var;
 186
 187         drm_crtc_vblank_off(crtc);
 188
 189         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 190                            JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
 191
 192         regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
 193                                  var & JZ_LCD_STATE_DISABLED,
 194                                  1000, 0);
 195 }
 196
 197 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
 198                                             struct drm_display_mode *mode)
 199 {
 200         unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
 201
 202         vpe = mode->vsync_end - mode->vsync_start;
 203         vds = mode->vtotal - mode->vsync_start;
 204         vde = vds + mode->vdisplay;
 205         vt = vde + mode->vsync_start - mode->vdisplay;
 206
 207         hpe = mode->hsync_end - mode->hsync_start;
 208         hds = mode->htotal - mode->hsync_start;
 209         hde = hds + mode->hdisplay;
 210         ht = hde + mode->hsync_start - mode->hdisplay;
 211
 212         regmap_write(priv->map, JZ_REG_LCD_VSYNC,
 213                      0 << JZ_LCD_VSYNC_VPS_OFFSET |
 214                      vpe << JZ_LCD_VSYNC_VPE_OFFSET);
 215
 216         regmap_write(priv->map, JZ_REG_LCD_HSYNC,
 217                      0 << JZ_LCD_HSYNC_HPS_OFFSET |
 218                      hpe << JZ_LCD_HSYNC_HPE_OFFSET);
 219
 220         regmap_write(priv->map, JZ_REG_LCD_VAT,
 221                      ht << JZ_LCD_VAT_HT_OFFSET |
 222                      vt << JZ_LCD_VAT_VT_OFFSET);
 223
 224         regmap_write(priv->map, JZ_REG_LCD_DAH,
 225                      hds << JZ_LCD_DAH_HDS_OFFSET |
 226                      hde << JZ_LCD_DAH_HDE_OFFSET);
 227         regmap_write(priv->map, JZ_REG_LCD_DAV,
 228                      vds << JZ_LCD_DAV_VDS_OFFSET |
 229                      vde << JZ_LCD_DAV_VDE_OFFSET);
 230
 231         if (priv->panel_is_sharp) {
 232                 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
 233                 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
 234                 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
 235                 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
 236         }
 237
 238         regmap_set_bits(priv->map, JZ_REG_LCD_CTRL,
 239                         JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16);
 240
 241         /*
 242          * IPU restart - specify how much time the LCDC will wait before
 243          * transferring a new frame from the IPU. The value is the one
 244          * suggested in the programming manual.
 245          */
 246         regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN |
 247                      (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB);
 248 }
 249
 250 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
 251                                          struct drm_crtc_state *state)
 252 {
 253         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 254         struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL;
 255
 256         if (drm_atomic_crtc_needs_modeset(state) && priv->soc_info->has_osd) {
 257                 f1_state = drm_atomic_get_plane_state(state->state, &priv->f1);
 258                 if (IS_ERR(f1_state))
 259                         return PTR_ERR(f1_state);
 260
 261                 f0_state = drm_atomic_get_plane_state(state->state, &priv->f0);
 262                 if (IS_ERR(f0_state))
 263                         return PTR_ERR(f0_state);
 264
 265                 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) {
 266                         ipu_state = drm_atomic_get_plane_state(state->state, priv->ipu_plane);
 267                         if (IS_ERR(ipu_state))
 268                                 return PTR_ERR(ipu_state);
 269
 270                         /* IPU and F1 planes cannot be enabled at the same time. */
 271                         if (f1_state->fb && ipu_state->fb) {
 272                                 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n");
 273                                 return -EINVAL;
 274                         }
 275                 }
 276
 277                 /* If all the planes are disabled, we won't get a VBLANK IRQ */
 278                 priv->no_vblank = !f1_state->fb && !f0_state->fb &&
 279                                   !(ipu_state && ipu_state->fb);
 280         }
 281
 282         return 0;
 283 }
 284
 285 static enum drm_mode_status
 286 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
 287 {
 288         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 289         long rate;
 290
 291         if (mode->hdisplay > priv->soc_info->max_width)
 292                 return MODE_BAD_HVALUE;
 293         if (mode->vdisplay > priv->soc_info->max_height)
 294                 return MODE_BAD_VVALUE;
 295
 296         rate = clk_round_rate(priv->pix_clk, mode->clock * 1000);
 297         if (rate < 0)
 298                 return MODE_CLOCK_RANGE;
 299
 300         return MODE_OK;
 301 }
 302
 303 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 304                                           struct drm_crtc_state *oldstate)
 305 {
 306         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 307         u32 ctrl = 0;
 308
 309         if (priv->soc_info->has_osd &&
 310             drm_atomic_crtc_needs_modeset(crtc->state)) {
 311                 /*
 312                  * If IPU plane is enabled, enable IPU as source for the F1
 313                  * plane; otherwise use regular DMA.
 314                  */
 315                 if (priv->ipu_plane && priv->ipu_plane->state->fb)
 316                         ctrl |= JZ_LCD_OSDCTRL_IPU;
 317
 318                 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
 319                                    JZ_LCD_OSDCTRL_IPU, ctrl);
 320         }
 321 }
 322
 323 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 324                                           struct drm_crtc_state *oldstate)
 325 {
 326         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 327         struct drm_crtc_state *state = crtc->state;
 328         struct drm_pending_vblank_event *event = state->event;
 329
 330         if (drm_atomic_crtc_needs_modeset(state)) {
 331                 ingenic_drm_crtc_update_timings(priv, &state->mode);
 332                 priv->update_clk_rate = true;
 333         }
 334
 335         if (priv->update_clk_rate) {
 336                 mutex_lock(&priv->clk_mutex);
 337                 clk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000);
 338                 priv->update_clk_rate = false;
 339                 mutex_unlock(&priv->clk_mutex);
 340         }
 341
 342         if (event) {
 343                 state->event = NULL;
 344
 345                 spin_lock_irq(&crtc->dev->event_lock);
 346                 if (drm_crtc_vblank_get(crtc) == 0)
 347                         drm_crtc_arm_vblank_event(crtc, event);
 348                 else
 349                         drm_crtc_send_vblank_event(crtc, event);
 350                 spin_unlock_irq(&crtc->dev->event_lock);
 351         }
 352 }
 353
 354 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane,
 355                                           struct drm_plane_state *state)
 356 {
 357         struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 358         struct drm_crtc_state *crtc_state;
 359         struct drm_crtc *crtc = state->crtc ?: plane->state->crtc;
 360         int ret;
 361
 362         if (!crtc)
 363                 return 0;
 364
 365         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 366         if (WARN_ON(!crtc_state))
 367                 return -EINVAL;
 368
 369         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 370                                                   DRM_PLANE_HELPER_NO_SCALING,
 371                                                   DRM_PLANE_HELPER_NO_SCALING,
 372                                                   priv->soc_info->has_osd,
 373                                                   true);
 374         if (ret)
 375                 return ret;
 376
 377         /*
 378          * If OSD is not available, check that the width/height match.
 379          * Note that state->src_* are in 16.16 fixed-point format.
 380          */
 381         if (!priv->soc_info->has_osd &&
 382             (state->src_x != 0 ||
 383              (state->src_w >> 16) != state->crtc_w ||
 384              (state->src_h >> 16) != state->crtc_h))
 385                 return -EINVAL;
 386
 387         /*
 388          * Require full modeset if enabling or disabling a plane, or changing
 389          * its position, size or depth.
 390          */
 391         if (priv->soc_info->has_osd &&
 392             (!plane->state->fb || !state->fb ||
 393              plane->state->crtc_x != state->crtc_x ||
 394              plane->state->crtc_y != state->crtc_y ||
 395              plane->state->crtc_w != state->crtc_w ||
 396              plane->state->crtc_h != state->crtc_h ||
 397              plane->state->fb->format->format != state->fb->format->format))
 398                 crtc_state->mode_changed = true;
 399
 400         drm_atomic_helper_check_plane_damage(state->state, state);
 401
 402         return 0;
 403 }
 404
 405 static void ingenic_drm_plane_enable(struct ingenic_drm *priv,
 406                                      struct drm_plane *plane)
 407 {
 408         unsigned int en_bit;
 409
 410         if (priv->soc_info->has_osd) {
 411                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 412                         en_bit = JZ_LCD_OSDC_F1EN;
 413                 else
 414                         en_bit = JZ_LCD_OSDC_F0EN;
 415
 416                 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
 417         }
 418 }
 419
 420 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane)
 421 {
 422         struct ingenic_drm *priv = dev_get_drvdata(dev);
 423         unsigned int en_bit;
 424
 425         if (priv->soc_info->has_osd) {
 426                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 427                         en_bit = JZ_LCD_OSDC_F1EN;
 428                 else
 429                         en_bit = JZ_LCD_OSDC_F0EN;
 430
 431                 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
 432         }
 433 }
 434
 435 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane,
 436                                              struct drm_plane_state *old_state)
 437 {
 438         struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 439
 440         ingenic_drm_plane_disable(priv->dev, plane);
 441 }
 442
 443 void ingenic_drm_plane_config(struct device *dev,
 444                               struct drm_plane *plane, u32 fourcc)
 445 {
 446         struct ingenic_drm *priv = dev_get_drvdata(dev);
 447         struct drm_plane_state *state = plane->state;
 448         unsigned int xy_reg, size_reg;
 449         unsigned int ctrl = 0;
 450
 451         ingenic_drm_plane_enable(priv, plane);
 452
 453         if (priv->soc_info->has_osd &&
 454             plane->type == DRM_PLANE_TYPE_PRIMARY) {
 455                 switch (fourcc) {
 456                 case DRM_FORMAT_XRGB1555:
 457                         ctrl |= JZ_LCD_OSDCTRL_RGB555;
 458                         fallthrough;
 459                 case DRM_FORMAT_RGB565:
 460                         ctrl |= JZ_LCD_OSDCTRL_BPP_15_16;
 461                         break;
 462                 case DRM_FORMAT_XRGB8888:
 463                         ctrl |= JZ_LCD_OSDCTRL_BPP_18_24;
 464                         break;
 465                 }
 466
 467                 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
 468                                    JZ_LCD_OSDCTRL_BPP_MASK, ctrl);
 469         } else {
 470                 switch (fourcc) {
 471                 case DRM_FORMAT_XRGB1555:
 472                         ctrl |= JZ_LCD_CTRL_RGB555;
 473                         fallthrough;
 474                 case DRM_FORMAT_RGB565:
 475                         ctrl |= JZ_LCD_CTRL_BPP_15_16;
 476                         break;
 477                 case DRM_FORMAT_XRGB8888:
 478                         ctrl |= JZ_LCD_CTRL_BPP_18_24;
 479                         break;
 480                 }
 481
 482                 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 483                                    JZ_LCD_CTRL_BPP_MASK, ctrl);
 484         }
 485
 486         if (priv->soc_info->has_osd) {
 487                 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 488                         xy_reg = JZ_REG_LCD_XYP1;
 489                         size_reg = JZ_REG_LCD_SIZE1;
 490                 } else {
 491                         xy_reg = JZ_REG_LCD_XYP0;
 492                         size_reg = JZ_REG_LCD_SIZE0;
 493                 }
 494
 495                 regmap_write(priv->map, xy_reg,
 496                              state->crtc_x << JZ_LCD_XYP01_XPOS_LSB |
 497                              state->crtc_y << JZ_LCD_XYP01_YPOS_LSB);
 498                 regmap_write(priv->map, size_reg,
 499                              state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB |
 500                              state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB);
 501         }
 502 }
 503
 504 void ingenic_drm_sync_data(struct device *dev,
 505                            struct drm_plane_state *old_state,
 506                            struct drm_plane_state *state)
 507 {
 508         const struct drm_format_info *finfo = state->fb->format;
 509         struct ingenic_drm *priv = dev_get_drvdata(dev);
 510         struct drm_atomic_helper_damage_iter iter;
 511         unsigned int offset, i;
 512         struct drm_rect clip;
 513         dma_addr_t paddr;
 514         void *addr;
 515
 516         if (!ingenic_drm_cached_gem_buf)
 517                 return;
 518
 519         drm_atomic_helper_damage_iter_init(&iter, old_state, state);
 520
 521         drm_atomic_for_each_plane_damage(&iter, &clip) {
 522                 for (i = 0; i < finfo->num_planes; i++) {
 523                         paddr = drm_fb_cma_get_gem_addr(state->fb, state, i);
 524                         addr = phys_to_virt(paddr);
 525
 526                         /* Ignore x1/x2 values, invalidate complete lines */
 527                         offset = clip.y1 * state->fb->pitches[i];
 528
 529                         dma_cache_sync(priv->dev, addr + offset,
 530                                        (clip.y2 - clip.y1) * state->fb->pitches[i],
 531                                        DMA_TO_DEVICE);
 532                 }
 533         }
 534 }
 535
 536 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
 537                                             struct drm_plane_state *oldstate)
 538 {
 539         struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 540         struct drm_plane_state *state = plane->state;
 541         struct ingenic_dma_hwdesc *hwdesc;
 542         unsigned int width, height, cpp;
 543         dma_addr_t addr;
 544
 545         if (state && state->fb) {
 546                 ingenic_drm_sync_data(priv->dev, oldstate, state);
 547
 548                 addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
 549                 width = state->src_w >> 16;
 550                 height = state->src_h >> 16;
 551                 cpp = state->fb->format->cpp[0];
 552
 553                 if (priv->soc_info->has_osd && plane->type == DRM_PLANE_TYPE_OVERLAY)
 554                         hwdesc = &priv->dma_hwdescs->hwdesc_f0;
 555                 else
 556                         hwdesc = &priv->dma_hwdescs->hwdesc_f1;
 557
 558                 hwdesc->addr = addr;
 559                 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
 560
 561                 if (drm_atomic_crtc_needs_modeset(state->crtc->state))
 562                         ingenic_drm_plane_config(priv->dev, plane,
 563                                                  state->fb->format->format);
 564         }
 565 }
 566
 567 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
 568                                                 struct drm_crtc_state *crtc_state,
 569                                                 struct drm_connector_state *conn_state)
 570 {
 571         struct ingenic_drm *priv = drm_device_get_priv(encoder->dev);
 572         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 573         struct drm_connector *conn = conn_state->connector;
 574         struct drm_display_info *info = &conn->display_info;
 575         unsigned int cfg;
 576
 577         priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
 578
 579         if (priv->panel_is_sharp) {
 580                 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
 581         } else {
 582                 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
 583                     | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
 584         }
 585
 586         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 587                 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
 588         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 589                 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
 590         if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
 591                 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
 592         if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 593                 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
 594
 595         if (!priv->panel_is_sharp) {
 596                 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) {
 597                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 598                                 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
 599                         else
 600                                 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
 601                 } else {
 602                         switch (*info->bus_formats) {
 603                         case MEDIA_BUS_FMT_RGB565_1X16:
 604                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
 605                                 break;
 606                         case MEDIA_BUS_FMT_RGB666_1X18:
 607                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
 608                                 break;
 609                         case MEDIA_BUS_FMT_RGB888_1X24:
 610                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
 611                                 break;
 612                         case MEDIA_BUS_FMT_RGB888_3X8:
 613                                 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
 614                                 break;
 615                         default:
 616                                 break;
 617                         }
 618                 }
 619         }
 620
 621         regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
 622 }
 623
 624 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
 625                                             struct drm_crtc_state *crtc_state,
 626                                             struct drm_connector_state *conn_state)
 627 {
 628         struct drm_display_info *info = &conn_state->connector->display_info;
 629
 630         if (info->num_bus_formats != 1)
 631                 return -EINVAL;
 632
 633         if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
 634                 return 0;
 635
 636         switch (*info->bus_formats) {
 637         case MEDIA_BUS_FMT_RGB565_1X16:
 638         case MEDIA_BUS_FMT_RGB666_1X18:
 639         case MEDIA_BUS_FMT_RGB888_1X24:
 640         case MEDIA_BUS_FMT_RGB888_3X8:
 641                 return 0;
 642         default:
 643                 return -EINVAL;
 644         }
 645 }
 646
 647 static void ingenic_drm_atomic_helper_commit_tail(struct drm_atomic_state *old_state)
 648 {
 649         /*
 650          * Just your regular drm_atomic_helper_commit_tail(), but only calls
 651          * drm_atomic_helper_wait_for_vblanks() if priv->no_vblank.
 652          */
 653         struct drm_device *dev = old_state->dev;
 654         struct ingenic_drm *priv = drm_device_get_priv(dev);
 655
 656         drm_atomic_helper_commit_modeset_disables(dev, old_state);
 657
 658         drm_atomic_helper_commit_planes(dev, old_state, 0);
 659
 660         drm_atomic_helper_commit_modeset_enables(dev, old_state);
 661
 662         drm_atomic_helper_commit_hw_done(old_state);
 663
 664         if (!priv->no_vblank)
 665                 drm_atomic_helper_wait_for_vblanks(dev, old_state);
 666
 667         drm_atomic_helper_cleanup_planes(dev, old_state);
 668 }
 669
 670 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
 671 {
 672         struct ingenic_drm *priv = drm_device_get_priv(arg);
 673         unsigned int state;
 674
 675         regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
 676
 677         regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
 678                            JZ_LCD_STATE_EOF_IRQ, 0);
 679
 680         if (state & JZ_LCD_STATE_EOF_IRQ)
 681                 drm_crtc_handle_vblank(&priv->crtc);
 682
 683         return IRQ_HANDLED;
 684 }
 685
 686 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
 687 {
 688         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 689
 690         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 691                            JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
 692
 693         return 0;
 694 }
 695
 696 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
 697 {
 698         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 699
 700         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
 701 }
 702
 703 static struct drm_framebuffer *
 704 ingenic_drm_gem_fb_create(struct drm_device *dev, struct drm_file *file,
 705                           const struct drm_mode_fb_cmd2 *mode_cmd)
 706 {
 707         if (ingenic_drm_cached_gem_buf)
 708                 return drm_gem_fb_create_with_dirty(dev, file, mode_cmd);
 709
 710         return drm_gem_fb_create(dev, file, mode_cmd);
 711 }
 712
 713 static int ingenic_drm_gem_mmap(struct drm_gem_object *obj,
 714                                 struct vm_area_struct *vma)
 715 {
 716         struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(obj);
 717         struct device *dev = cma_obj->base.dev->dev;
 718         unsigned long attrs;
 719         int ret;
 720
 721         if (ingenic_drm_cached_gem_buf)
 722                 attrs = DMA_ATTR_NON_CONSISTENT;
 723         else
 724                 attrs = DMA_ATTR_WRITE_COMBINE;
 725
 726         /*
 727          * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
 728          * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
 729          * the whole buffer.
 730          */
 731         vma->vm_flags &= ~VM_PFNMAP;
 732         vma->vm_pgoff = 0;
 733         vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
 734
 735         ret = dma_mmap_attrs(dev, vma, cma_obj->vaddr, cma_obj->paddr,
 736                              vma->vm_end - vma->vm_start, attrs);
 737         if (ret)
 738                 drm_gem_vm_close(vma);
 739
 740         return ret;
 741 }
 742
 743 static int ingenic_drm_gem_cma_mmap(struct file *filp,
 744                                     struct vm_area_struct *vma)
 745 {
 746         int ret;
 747
 748         ret = drm_gem_mmap(filp, vma);
 749         if (ret)
 750                 return ret;
 751
 752         return ingenic_drm_gem_mmap(vma->vm_private_data, vma);
 753 }
 754
 755 static const struct file_operations ingenic_drm_fops = {
 756         .owner          = THIS_MODULE,
 757         .open           = drm_open,
 758         .release        = drm_release,
 759         .unlocked_ioctl = drm_ioctl,
 760         .compat_ioctl   = drm_compat_ioctl,
 761         .poll           = drm_poll,
 762         .read           = drm_read,
 763         .llseek         = noop_llseek,
 764         .mmap           = ingenic_drm_gem_cma_mmap,
 765 };
 766
 767 static struct drm_driver ingenic_drm_driver_data = {
 768         .driver_features        = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
 769         .name                   = "ingenic-drm",
 770         .desc                   = "DRM module for Ingenic SoCs",
 771         .date                   = "20200716",
 772         .major                  = 1,
 773         .minor                  = 1,
 774         .patchlevel             = 0,
 775
 776         .fops                   = &ingenic_drm_fops,
 777         DRM_GEM_CMA_DRIVER_OPS,
 778
 779         .irq_handler            = ingenic_drm_irq_handler,
 780 };
 781
 782 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = {
 783         .update_plane           = drm_atomic_helper_update_plane,
 784         .disable_plane          = drm_atomic_helper_disable_plane,
 785         .reset                  = drm_atomic_helper_plane_reset,
 786         .destroy                = drm_plane_cleanup,
 787
 788         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 789         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 790 };
 791
 792 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = {
 793         .set_config             = drm_atomic_helper_set_config,
 794         .page_flip              = drm_atomic_helper_page_flip,
 795         .reset                  = drm_atomic_helper_crtc_reset,
 796         .destroy                = drm_crtc_cleanup,
 797
 798         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 799         .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
 800
 801         .enable_vblank          = ingenic_drm_enable_vblank,
 802         .disable_vblank         = ingenic_drm_disable_vblank,
 803
 804         .gamma_set              = drm_atomic_helper_legacy_gamma_set,
 805 };
 806
 807 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {
 808         .atomic_update          = ingenic_drm_plane_atomic_update,
 809         .atomic_check           = ingenic_drm_plane_atomic_check,
 810         .atomic_disable         = ingenic_drm_plane_atomic_disable,
 811         .prepare_fb             = drm_gem_fb_prepare_fb,
 812 };
 813
 814 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = {
 815         .atomic_enable          = ingenic_drm_crtc_atomic_enable,
 816         .atomic_disable         = ingenic_drm_crtc_atomic_disable,
 817         .atomic_begin           = ingenic_drm_crtc_atomic_begin,
 818         .atomic_flush           = ingenic_drm_crtc_atomic_flush,
 819         .atomic_check           = ingenic_drm_crtc_atomic_check,
 820         .mode_valid             = ingenic_drm_crtc_mode_valid,
 821 };
 822
 823 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = {
 824         .atomic_mode_set        = ingenic_drm_encoder_atomic_mode_set,
 825         .atomic_check           = ingenic_drm_encoder_atomic_check,
 826 };
 827
 828 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = {
 829         .fb_create              = ingenic_drm_gem_fb_create,
 830         .output_poll_changed    = drm_fb_helper_output_poll_changed,
 831         .atomic_check           = drm_atomic_helper_check,
 832         .atomic_commit          = drm_atomic_helper_commit,
 833 };
 834
 835 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = {
 836         .atomic_commit_tail = ingenic_drm_atomic_helper_commit_tail,
 837 };
 838
 839 static void ingenic_drm_unbind_all(void *d)
 840 {
 841         struct ingenic_drm *priv = d;
 842
 843         component_unbind_all(priv->dev, &priv->drm);
 844 }
 845
 846 static void __maybe_unused ingenic_drm_release_rmem(void *d)
 847 {
 848         of_reserved_mem_device_release(d);
 849 }
 850
 851 static int ingenic_drm_bind(struct device *dev, bool has_components)
 852 {
 853         struct platform_device *pdev = to_platform_device(dev);
 854         const struct jz_soc_info *soc_info;
 855         struct ingenic_drm *priv;
 856         struct clk *parent_clk;
 857         struct drm_bridge *bridge;
 858         struct drm_panel *panel;
 859         struct drm_encoder *encoder;
 860         struct drm_device *drm;
 861         void __iomem *base;
 862         long parent_rate;
 863         unsigned int i, clone_mask = 0;
 864         dma_addr_t dma_hwdesc_phys_f0, dma_hwdesc_phys_f1;
 865         int ret, irq;
 866
 867         soc_info = of_device_get_match_data(dev);
 868         if (!soc_info) {
 869                 dev_err(dev, "Missing platform data\n");
 870                 return -EINVAL;
 871         }
 872
 873         if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) {
 874                 ret = of_reserved_mem_device_init(dev);
 875
 876                 if (ret && ret != -ENODEV)
 877                         dev_warn(dev, "Failed to get reserved memory: %d\n", ret);
 878
 879                 if (!ret) {
 880                         ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev);
 881                         if (ret)
 882                                 return ret;
 883                 }
 884         }
 885
 886         priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data,
 887                                   struct ingenic_drm, drm);
 888         if (IS_ERR(priv))
 889                 return PTR_ERR(priv);
 890
 891         priv->soc_info = soc_info;
 892         priv->dev = dev;
 893         drm = &priv->drm;
 894
 895         platform_set_drvdata(pdev, priv);
 896
 897         ret = drmm_mode_config_init(drm);
 898         if (ret)
 899                 return ret;
 900
 901         drm->mode_config.min_width = 0;
 902         drm->mode_config.min_height = 0;
 903         drm->mode_config.max_width = soc_info->max_width;
 904         drm->mode_config.max_height = 4095;
 905         drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
 906         drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers;
 907
 908         base = devm_platform_ioremap_resource(pdev, 0);
 909         if (IS_ERR(base)) {
 910                 dev_err(dev, "Failed to get memory resource\n");
 911                 return PTR_ERR(base);
 912         }
 913
 914         priv->map = devm_regmap_init_mmio(dev, base,
 915                                           &ingenic_drm_regmap_config);
 916         if (IS_ERR(priv->map)) {
 917                 dev_err(dev, "Failed to create regmap\n");
 918                 return PTR_ERR(priv->map);
 919         }
 920
 921         irq = platform_get_irq(pdev, 0);
 922         if (irq < 0)
 923                 return irq;
 924
 925         if (soc_info->needs_dev_clk) {
 926                 priv->lcd_clk = devm_clk_get(dev, "lcd");
 927                 if (IS_ERR(priv->lcd_clk)) {
 928                         dev_err(dev, "Failed to get lcd clock\n");
 929                         return PTR_ERR(priv->lcd_clk);
 930                 }
 931         }
 932
 933         priv->pix_clk = devm_clk_get(dev, "lcd_pclk");
 934         if (IS_ERR(priv->pix_clk)) {
 935                 dev_err(dev, "Failed to get pixel clock\n");
 936                 return PTR_ERR(priv->pix_clk);
 937         }
 938
 939         priv->dma_hwdescs = dmam_alloc_coherent(dev,
 940                                                 sizeof(*priv->dma_hwdescs),
 941                                                 &priv->dma_hwdescs_phys,
 942                                                 GFP_KERNEL);
 943         if (!priv->dma_hwdescs)
 944                 return -ENOMEM;
 945
 946
 947         /* Configure DMA hwdesc for foreground0 plane */
 948         dma_hwdesc_phys_f0 = priv->dma_hwdescs_phys
 949                 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0);
 950         priv->dma_hwdescs->hwdesc_f0.next = dma_hwdesc_phys_f0;
 951         priv->dma_hwdescs->hwdesc_f0.id = 0xf0;
 952
 953         /* Configure DMA hwdesc for foreground1 plane */
 954         dma_hwdesc_phys_f1 = priv->dma_hwdescs_phys
 955                 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f1);
 956         priv->dma_hwdescs->hwdesc_f1.next = dma_hwdesc_phys_f1;
 957         priv->dma_hwdescs->hwdesc_f1.id = 0xf1;
 958
 959         if (soc_info->has_osd)
 960                 priv->ipu_plane = drm_plane_from_index(drm, 0);
 961
 962         drm_plane_helper_add(&priv->f1, &ingenic_drm_plane_helper_funcs);
 963
 964         ret = drm_universal_plane_init(drm, &priv->f1, 1,
 965                                        &ingenic_drm_primary_plane_funcs,
 966                                        ingenic_drm_primary_formats,
 967                                        ARRAY_SIZE(ingenic_drm_primary_formats),
 968                                        NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
 969         if (ret) {
 970                 dev_err(dev, "Failed to register plane: %i\n", ret);
 971                 return ret;
 972         }
 973
 974         drm_plane_enable_fb_damage_clips(&priv->f1);
 975
 976         drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs);
 977
 978         ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->f1,
 979                                         NULL, &ingenic_drm_crtc_funcs, NULL);
 980         if (ret) {
 981                 dev_err(dev, "Failed to init CRTC: %i\n", ret);
 982                 return ret;
 983         }
 984
 985         if (soc_info->has_osd) {
 986                 drm_plane_helper_add(&priv->f0,
 987                                      &ingenic_drm_plane_helper_funcs);
 988
 989                 ret = drm_universal_plane_init(drm, &priv->f0, 1,
 990                                                &ingenic_drm_primary_plane_funcs,
 991                                                ingenic_drm_primary_formats,
 992                                                ARRAY_SIZE(ingenic_drm_primary_formats),
 993                                                NULL, DRM_PLANE_TYPE_OVERLAY,
 994                                                NULL);
 995                 if (ret) {
 996                         dev_err(dev, "Failed to register overlay plane: %i\n",
 997                                 ret);
 998                         return ret;
 999                 }
1000
1001                 drm_plane_enable_fb_damage_clips(&priv->f0);
1002
1003                 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) {
1004                         ret = component_bind_all(dev, drm);
1005                         if (ret) {
1006                                 if (ret != -EPROBE_DEFER)
1007                                         dev_err(dev, "Failed to bind components: %i\n", ret);
1008                                 return ret;
1009                         }
1010
1011                         ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv);
1012                         if (ret)
1013                                 return ret;
1014
1015                         priv->ipu_plane = drm_plane_from_index(drm, 2);
1016                         if (!priv->ipu_plane) {
1017                                 dev_err(dev, "Failed to retrieve IPU plane\n");
1018                                 return -EINVAL;
1019                         }
1020                 }
1021         }
1022
1023         for (i = 0; ; i++) {
1024                 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge);
1025                 if (ret) {
1026                         if (ret == -ENODEV)
1027                                 break; /* we're done */
1028                         if (ret != -EPROBE_DEFER)
1029                                 dev_err(dev, "Failed to get bridge handle\n");
1030                         return ret;
1031                 }
1032
1033                 if (panel)
1034                         bridge = devm_drm_panel_bridge_add_typed(dev, panel,
1035                                                                  DRM_MODE_CONNECTOR_DPI);
1036
1037                 encoder = devm_kzalloc(dev, sizeof(*encoder), GFP_KERNEL);
1038                 if (!encoder)
1039                         return -ENOMEM;
1040
1041                 encoder->possible_crtcs = 1;
1042
1043                 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs);
1044
1045                 ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_DPI);
1046                 if (ret) {
1047                         dev_err(dev, "Failed to init encoder: %d\n", ret);
1048                         return ret;
1049                 }
1050
1051                 ret = drm_bridge_attach(encoder, bridge, NULL, 0);
1052                 if (ret) {
1053                         dev_err(dev, "Unable to attach bridge\n");
1054                         return ret;
1055                 }
1056         }
1057
1058         drm_for_each_encoder(encoder, drm) {
1059                 clone_mask |= BIT(drm_encoder_index(encoder));
1060         }
1061
1062         drm_for_each_encoder(encoder, drm) {
1063                 encoder->possible_clones = clone_mask;
1064         }
1065
1066         ret = drm_irq_install(drm, irq);
1067         if (ret) {
1068                 dev_err(dev, "Unable to install IRQ handler\n");
1069                 return ret;
1070         }
1071
1072         ret = drm_vblank_init(drm, 1);
1073         if (ret) {
1074                 dev_err(dev, "Failed calling drm_vblank_init()\n");
1075                 return ret;
1076         }
1077
1078         drm_mode_config_reset(drm);
1079
1080         ret = clk_prepare_enable(priv->pix_clk);
1081         if (ret) {
1082                 dev_err(dev, "Unable to start pixel clock\n");
1083                 return ret;
1084         }
1085
1086         if (priv->lcd_clk) {
1087                 parent_clk = clk_get_parent(priv->lcd_clk);
1088                 parent_rate = clk_get_rate(parent_clk);
1089
1090                 /* LCD Device clock must be 3x the pixel clock for STN panels,
1091                  * or 1.5x the pixel clock for TFT panels. To avoid having to
1092                  * check for the LCD device clock everytime we do a mode change,
1093                  * we set the LCD device clock to the highest rate possible.
1094                  */
1095                 ret = clk_set_rate(priv->lcd_clk, parent_rate);
1096                 if (ret) {
1097                         dev_err(dev, "Unable to set LCD clock rate\n");
1098                         goto err_pixclk_disable;
1099                 }
1100
1101                 ret = clk_prepare_enable(priv->lcd_clk);
1102                 if (ret) {
1103                         dev_err(dev, "Unable to start lcd clock\n");
1104                         goto err_pixclk_disable;
1105                 }
1106         }
1107
1108         /* Set address of our DMA descriptor chain */
1109         regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_phys_f0);
1110         regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_phys_f1);
1111
1112         /* Enable OSD if available */
1113         if (soc_info->has_osd)
1114                 regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN);
1115
1116         mutex_init(&priv->clk_mutex);
1117         priv->clock_nb.notifier_call = ingenic_drm_update_pixclk;
1118
1119         parent_clk = clk_get_parent(priv->pix_clk);
1120         ret = clk_notifier_register(parent_clk, &priv->clock_nb);
1121         if (ret) {
1122                 dev_err(dev, "Unable to register clock notifier\n");
1123                 goto err_devclk_disable;
1124         }
1125
1126         ret = drm_dev_register(drm, 0);
1127         if (ret) {
1128                 dev_err(dev, "Failed to register DRM driver\n");
1129                 goto err_clk_notifier_unregister;
1130         }
1131
1132         drm_fbdev_generic_setup(drm, 32);
1133
1134         return 0;
1135
1136 err_clk_notifier_unregister:
1137         clk_notifier_unregister(parent_clk, &priv->clock_nb);
1138 err_devclk_disable:
1139         if (priv->lcd_clk)
1140                 clk_disable_unprepare(priv->lcd_clk);
1141 err_pixclk_disable:
1142         clk_disable_unprepare(priv->pix_clk);
1143         return ret;
1144 }
1145
1146 static int ingenic_drm_bind_with_components(struct device *dev)
1147 {
1148         return ingenic_drm_bind(dev, true);
1149 }
1150
1151 static int compare_of(struct device *dev, void *data)
1152 {
1153         return dev->of_node == data;
1154 }
1155
1156 static void ingenic_drm_unbind(struct device *dev)
1157 {
1158         struct ingenic_drm *priv = dev_get_drvdata(dev);
1159         struct clk *parent_clk = clk_get_parent(priv->pix_clk);
1160
1161         clk_notifier_unregister(parent_clk, &priv->clock_nb);
1162         if (priv->lcd_clk)
1163                 clk_disable_unprepare(priv->lcd_clk);
1164         clk_disable_unprepare(priv->pix_clk);
1165
1166         drm_dev_unregister(&priv->drm);
1167         drm_atomic_helper_shutdown(&priv->drm);
1168 }
1169
1170 static const struct component_master_ops ingenic_master_ops = {
1171         .bind = ingenic_drm_bind_with_components,
1172         .unbind = ingenic_drm_unbind,
1173 };
1174
1175 static int ingenic_drm_probe(struct platform_device *pdev)
1176 {
1177         struct device *dev = &pdev->dev;
1178         struct component_match *match = NULL;
1179         struct device_node *np;
1180
1181         if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1182                 return ingenic_drm_bind(dev, false);
1183
1184         /* IPU is at port address 8 */
1185         np = of_graph_get_remote_node(dev->of_node, 8, 0);
1186         if (!np)
1187                 return ingenic_drm_bind(dev, false);
1188
1189         drm_of_component_match_add(dev, &match, compare_of, np);
1190         of_node_put(np);
1191
1192         return component_master_add_with_match(dev, &ingenic_master_ops, match);
1193 }
1194
1195 static int ingenic_drm_remove(struct platform_device *pdev)
1196 {
1197         struct device *dev = &pdev->dev;
1198
1199         if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1200                 ingenic_drm_unbind(dev);
1201         else
1202                 component_master_del(dev, &ingenic_master_ops);
1203
1204         return 0;
1205 }
1206
1207 static const struct jz_soc_info jz4740_soc_info = {
1208         .needs_dev_clk = true,
1209         .has_osd = false,
1210         .max_width = 800,
1211         .max_height = 600,
1212 };
1213
1214 static const struct jz_soc_info jz4725b_soc_info = {
1215         .needs_dev_clk = false,
1216         .has_osd = true,
1217         .max_width = 800,
1218         .max_height = 600,
1219 };
1220
1221 static const struct jz_soc_info jz4770_soc_info = {
1222         .needs_dev_clk = false,
1223         .has_osd = true,
1224         .max_width = 1280,
1225         .max_height = 720,
1226 };
1227
1228 static const struct of_device_id ingenic_drm_of_match[] = {
1229         { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info },
1230         { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info },
1231         { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info },
1232         { /* sentinel */ },
1233 };
1234 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
1235
1236 static struct platform_driver ingenic_drm_driver = {
1237         .driver = {
1238                 .name = "ingenic-drm",
1239                 .of_match_table = of_match_ptr(ingenic_drm_of_match),
1240         },
1241         .probe = ingenic_drm_probe,
1242         .remove = ingenic_drm_remove,
1243 };
1244
1245 static int ingenic_drm_init(void)
1246 {
1247         int err;
1248
1249         if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) {
1250                 err = platform_driver_register(ingenic_ipu_driver_ptr);
1251                 if (err)
1252                         return err;
1253         }
1254
1255         return platform_driver_register(&ingenic_drm_driver);
1256 }
1257 module_init(ingenic_drm_init);
1258
1259 static void ingenic_drm_exit(void)
1260 {
1261         platform_driver_unregister(&ingenic_drm_driver);
1262
1263         if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1264                 platform_driver_unregister(ingenic_ipu_driver_ptr);
1265 }
1266 module_exit(ingenic_drm_exit);
1267
1268 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
1269 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n");
1270 MODULE_LICENSE("GPL v2");