drivers/gpu/drm/ingenic/ingenic-drm-drv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Ingenic JZ47xx KMS driver
   4 //
   5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
   6
   7 #include "ingenic-drm.h"
   8
   9 #include <linux/component.h>
  10 #include <linux/clk.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dma-noncoherent.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_reserved_mem.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_bridge.h>
  24 #include <drm/drm_crtc.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_damage_helper.h>
  27 #include <drm/drm_drv.h>
  28 #include <drm/drm_gem_cma_helper.h>
  29 #include <drm/drm_fb_cma_helper.h>
  30 #include <drm/drm_fb_helper.h>
  31 #include <drm/drm_fourcc.h>
  32 #include <drm/drm_gem_framebuffer_helper.h>
  33 #include <drm/drm_irq.h>
  34 #include <drm/drm_managed.h>
  35 #include <drm/drm_of.h>
  36 #include <drm/drm_panel.h>
  37 #include <drm/drm_plane.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_probe_helper.h>
  40 #include <drm/drm_simple_kms_helper.h>
  41 #include <drm/drm_vblank.h>
  42
  43 struct ingenic_dma_hwdesc {
  44         u32 next;
  45         u32 addr;
  46         u32 id;
  47         u32 cmd;
  48 } __aligned(16);
  49
  50 struct ingenic_dma_hwdescs {
  51         struct ingenic_dma_hwdesc hwdesc_f0;
  52         struct ingenic_dma_hwdesc hwdesc_f1;
  53 };
  54
  55 struct jz_soc_info {
  56         bool needs_dev_clk;
  57         bool has_osd;
  58         unsigned int max_width, max_height;
  59         const u32 *formats_f0, *formats_f1;
  60         unsigned int num_formats_f0, num_formats_f1;
  61 };
  62
  63 struct ingenic_drm {
  64         struct drm_device drm;
  65         /*
  66          * f1 (aka. foreground1) is our primary plane, on top of which
  67          * f0 (aka. foreground0) can be overlayed. Z-order is fixed in
  68          * hardware and cannot be changed.
  69          */
  70         struct drm_plane f0, f1, *ipu_plane;
  71         struct drm_crtc crtc;
  72
  73         struct device *dev;
  74         struct regmap *map;
  75         struct clk *lcd_clk, *pix_clk;
  76         const struct jz_soc_info *soc_info;
  77
  78         struct ingenic_dma_hwdescs *dma_hwdescs;
  79         dma_addr_t dma_hwdescs_phys;
  80
  81         bool panel_is_sharp;
  82         bool no_vblank;
  83
  84         /*
  85          * clk_mutex is used to synchronize the pixel clock rate update with
  86          * the VBLANK. When the pixel clock's parent clock needs to be updated,
  87          * clock_nb's notifier function will lock the mutex, then wait until the
  88          * next VBLANK. At that point, the parent clock's rate can be updated,
  89          * and the mutex is then unlocked. If an atomic commit happens in the
  90          * meantime, it will lock on the mutex, effectively waiting until the
  91          * clock update process finishes. Finally, the pixel clock's rate will
  92          * be recomputed when the mutex has been released, in the pending atomic
  93          * commit, or a future one.
  94          */
  95         struct mutex clk_mutex;
  96         bool update_clk_rate;
  97         struct notifier_block clock_nb;
  98 };
  99
 100 static bool ingenic_drm_cached_gem_buf;
 101 module_param_named(cached_gem_buffers, ingenic_drm_cached_gem_buf, bool, 0400);
 102 MODULE_PARM_DESC(cached_gem_buffers,
 103                  "Enable fully cached GEM buffers [default=false]");
 104
 105 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
 106 {
 107         switch (reg) {
 108         case JZ_REG_LCD_IID:
 109         case JZ_REG_LCD_SA0:
 110         case JZ_REG_LCD_FID0:
 111         case JZ_REG_LCD_CMD0:
 112         case JZ_REG_LCD_SA1:
 113         case JZ_REG_LCD_FID1:
 114         case JZ_REG_LCD_CMD1:
 115                 return false;
 116         default:
 117                 return true;
 118         }
 119 }
 120
 121 static const struct regmap_config ingenic_drm_regmap_config = {
 122         .reg_bits = 32,
 123         .val_bits = 32,
 124         .reg_stride = 4,
 125
 126         .max_register = JZ_REG_LCD_SIZE1,
 127         .writeable_reg = ingenic_drm_writeable_reg,
 128 };
 129
 130 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
 131 {
 132         return container_of(drm, struct ingenic_drm, drm);
 133 }
 134
 135 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
 136 {
 137         return container_of(crtc, struct ingenic_drm, crtc);
 138 }
 139
 140 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb)
 141 {
 142         return container_of(nb, struct ingenic_drm, clock_nb);
 143 }
 144
 145 static int ingenic_drm_update_pixclk(struct notifier_block *nb,
 146                                      unsigned long action,
 147                                      void *data)
 148 {
 149         struct ingenic_drm *priv = drm_nb_get_priv(nb);
 150
 151         switch (action) {
 152         case PRE_RATE_CHANGE:
 153                 mutex_lock(&priv->clk_mutex);
 154                 priv->update_clk_rate = true;
 155                 drm_crtc_wait_one_vblank(&priv->crtc);
 156                 return NOTIFY_OK;
 157         default:
 158                 mutex_unlock(&priv->clk_mutex);
 159                 return NOTIFY_OK;
 160         }
 161 }
 162
 163 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
 164                                            struct drm_crtc_state *state)
 165 {
 166         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 167
 168         regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
 169
 170         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 171                            JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
 172                            JZ_LCD_CTRL_ENABLE);
 173
 174         drm_crtc_vblank_on(crtc);
 175 }
 176
 177 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
 178                                             struct drm_crtc_state *state)
 179 {
 180         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 181         unsigned int var;
 182
 183         drm_crtc_vblank_off(crtc);
 184
 185         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 186                            JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
 187
 188         regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
 189                                  var & JZ_LCD_STATE_DISABLED,
 190                                  1000, 0);
 191 }
 192
 193 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
 194                                             struct drm_display_mode *mode)
 195 {
 196         unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
 197
 198         vpe = mode->vsync_end - mode->vsync_start;
 199         vds = mode->vtotal - mode->vsync_start;
 200         vde = vds + mode->vdisplay;
 201         vt = vde + mode->vsync_start - mode->vdisplay;
 202
 203         hpe = mode->hsync_end - mode->hsync_start;
 204         hds = mode->htotal - mode->hsync_start;
 205         hde = hds + mode->hdisplay;
 206         ht = hde + mode->hsync_start - mode->hdisplay;
 207
 208         regmap_write(priv->map, JZ_REG_LCD_VSYNC,
 209                      0 << JZ_LCD_VSYNC_VPS_OFFSET |
 210                      vpe << JZ_LCD_VSYNC_VPE_OFFSET);
 211
 212         regmap_write(priv->map, JZ_REG_LCD_HSYNC,
 213                      0 << JZ_LCD_HSYNC_HPS_OFFSET |
 214                      hpe << JZ_LCD_HSYNC_HPE_OFFSET);
 215
 216         regmap_write(priv->map, JZ_REG_LCD_VAT,
 217                      ht << JZ_LCD_VAT_HT_OFFSET |
 218                      vt << JZ_LCD_VAT_VT_OFFSET);
 219
 220         regmap_write(priv->map, JZ_REG_LCD_DAH,
 221                      hds << JZ_LCD_DAH_HDS_OFFSET |
 222                      hde << JZ_LCD_DAH_HDE_OFFSET);
 223         regmap_write(priv->map, JZ_REG_LCD_DAV,
 224                      vds << JZ_LCD_DAV_VDS_OFFSET |
 225                      vde << JZ_LCD_DAV_VDE_OFFSET);
 226
 227         if (priv->panel_is_sharp) {
 228                 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
 229                 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
 230                 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
 231                 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
 232         }
 233
 234         regmap_set_bits(priv->map, JZ_REG_LCD_CTRL,
 235                         JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16);
 236
 237         /*
 238          * IPU restart - specify how much time the LCDC will wait before
 239          * transferring a new frame from the IPU. The value is the one
 240          * suggested in the programming manual.
 241          */
 242         regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN |
 243                      (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB);
 244 }
 245
 246 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
 247                                          struct drm_crtc_state *state)
 248 {
 249         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 250         struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL;
 251
 252         if (drm_atomic_crtc_needs_modeset(state) && priv->soc_info->has_osd) {
 253                 f1_state = drm_atomic_get_plane_state(state->state, &priv->f1);
 254                 if (IS_ERR(f1_state))
 255                         return PTR_ERR(f1_state);
 256
 257                 f0_state = drm_atomic_get_plane_state(state->state, &priv->f0);
 258                 if (IS_ERR(f0_state))
 259                         return PTR_ERR(f0_state);
 260
 261                 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) {
 262                         ipu_state = drm_atomic_get_plane_state(state->state, priv->ipu_plane);
 263                         if (IS_ERR(ipu_state))
 264                                 return PTR_ERR(ipu_state);
 265
 266                         /* IPU and F1 planes cannot be enabled at the same time. */
 267                         if (f1_state->fb && ipu_state->fb) {
 268                                 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n");
 269                                 return -EINVAL;
 270                         }
 271                 }
 272
 273                 /* If all the planes are disabled, we won't get a VBLANK IRQ */
 274                 priv->no_vblank = !f1_state->fb && !f0_state->fb &&
 275                                   !(ipu_state && ipu_state->fb);
 276         }
 277
 278         return 0;
 279 }
 280
 281 static enum drm_mode_status
 282 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
 283 {
 284         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 285         long rate;
 286
 287         if (mode->hdisplay > priv->soc_info->max_width)
 288                 return MODE_BAD_HVALUE;
 289         if (mode->vdisplay > priv->soc_info->max_height)
 290                 return MODE_BAD_VVALUE;
 291
 292         rate = clk_round_rate(priv->pix_clk, mode->clock * 1000);
 293         if (rate < 0)
 294                 return MODE_CLOCK_RANGE;
 295
 296         return MODE_OK;
 297 }
 298
 299 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 300                                           struct drm_crtc_state *oldstate)
 301 {
 302         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 303         u32 ctrl = 0;
 304
 305         if (priv->soc_info->has_osd &&
 306             drm_atomic_crtc_needs_modeset(crtc->state)) {
 307                 /*
 308                  * If IPU plane is enabled, enable IPU as source for the F1
 309                  * plane; otherwise use regular DMA.
 310                  */
 311                 if (priv->ipu_plane && priv->ipu_plane->state->fb)
 312                         ctrl |= JZ_LCD_OSDCTRL_IPU;
 313
 314                 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
 315                                    JZ_LCD_OSDCTRL_IPU, ctrl);
 316         }
 317 }
 318
 319 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 320                                           struct drm_crtc_state *oldstate)
 321 {
 322         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 323         struct drm_crtc_state *state = crtc->state;
 324         struct drm_pending_vblank_event *event = state->event;
 325
 326         if (drm_atomic_crtc_needs_modeset(state)) {
 327                 ingenic_drm_crtc_update_timings(priv, &state->mode);
 328                 priv->update_clk_rate = true;
 329         }
 330
 331         if (priv->update_clk_rate) {
 332                 mutex_lock(&priv->clk_mutex);
 333                 clk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000);
 334                 priv->update_clk_rate = false;
 335                 mutex_unlock(&priv->clk_mutex);
 336         }
 337
 338         if (event) {
 339                 state->event = NULL;
 340
 341                 spin_lock_irq(&crtc->dev->event_lock);
 342                 if (drm_crtc_vblank_get(crtc) == 0)
 343                         drm_crtc_arm_vblank_event(crtc, event);
 344                 else
 345                         drm_crtc_send_vblank_event(crtc, event);
 346                 spin_unlock_irq(&crtc->dev->event_lock);
 347         }
 348 }
 349
 350 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane,
 351                                           struct drm_plane_state *state)
 352 {
 353         struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 354         struct drm_crtc_state *crtc_state;
 355         struct drm_crtc *crtc = state->crtc ?: plane->state->crtc;
 356         int ret;
 357
 358         if (!crtc)
 359                 return 0;
 360
 361         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 362         if (WARN_ON(!crtc_state))
 363                 return -EINVAL;
 364
 365         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 366                                                   DRM_PLANE_HELPER_NO_SCALING,
 367                                                   DRM_PLANE_HELPER_NO_SCALING,
 368                                                   priv->soc_info->has_osd,
 369                                                   true);
 370         if (ret)
 371                 return ret;
 372
 373         /*
 374          * If OSD is not available, check that the width/height match.
 375          * Note that state->src_* are in 16.16 fixed-point format.
 376          */
 377         if (!priv->soc_info->has_osd &&
 378             (state->src_x != 0 ||
 379              (state->src_w >> 16) != state->crtc_w ||
 380              (state->src_h >> 16) != state->crtc_h))
 381                 return -EINVAL;
 382
 383         /*
 384          * Require full modeset if enabling or disabling a plane, or changing
 385          * its position, size or depth.
 386          */
 387         if (priv->soc_info->has_osd &&
 388             (!plane->state->fb || !state->fb ||
 389              plane->state->crtc_x != state->crtc_x ||
 390              plane->state->crtc_y != state->crtc_y ||
 391              plane->state->crtc_w != state->crtc_w ||
 392              plane->state->crtc_h != state->crtc_h ||
 393              plane->state->fb->format->format != state->fb->format->format))
 394                 crtc_state->mode_changed = true;
 395
 396         drm_atomic_helper_check_plane_damage(state->state, state);
 397
 398         return 0;
 399 }
 400
 401 static void ingenic_drm_plane_enable(struct ingenic_drm *priv,
 402                                      struct drm_plane *plane)
 403 {
 404         unsigned int en_bit;
 405
 406         if (priv->soc_info->has_osd) {
 407                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 408                         en_bit = JZ_LCD_OSDC_F1EN;
 409                 else
 410                         en_bit = JZ_LCD_OSDC_F0EN;
 411
 412                 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
 413         }
 414 }
 415
 416 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane)
 417 {
 418         struct ingenic_drm *priv = dev_get_drvdata(dev);
 419         unsigned int en_bit;
 420
 421         if (priv->soc_info->has_osd) {
 422                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 423                         en_bit = JZ_LCD_OSDC_F1EN;
 424                 else
 425                         en_bit = JZ_LCD_OSDC_F0EN;
 426
 427                 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit);
 428         }
 429 }
 430
 431 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane,
 432                                              struct drm_plane_state *old_state)
 433 {
 434         struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 435
 436         ingenic_drm_plane_disable(priv->dev, plane);
 437 }
 438
 439 void ingenic_drm_plane_config(struct device *dev,
 440                               struct drm_plane *plane, u32 fourcc)
 441 {
 442         struct ingenic_drm *priv = dev_get_drvdata(dev);
 443         struct drm_plane_state *state = plane->state;
 444         unsigned int xy_reg, size_reg;
 445         unsigned int ctrl = 0;
 446
 447         ingenic_drm_plane_enable(priv, plane);
 448
 449         if (priv->soc_info->has_osd &&
 450             plane->type == DRM_PLANE_TYPE_PRIMARY) {
 451                 switch (fourcc) {
 452                 case DRM_FORMAT_XRGB1555:
 453                         ctrl |= JZ_LCD_OSDCTRL_RGB555;
 454                         fallthrough;
 455                 case DRM_FORMAT_RGB565:
 456                         ctrl |= JZ_LCD_OSDCTRL_BPP_15_16;
 457                         break;
 458                 case DRM_FORMAT_RGB888:
 459                         ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP;
 460                         break;
 461                 case DRM_FORMAT_XRGB8888:
 462                         ctrl |= JZ_LCD_OSDCTRL_BPP_18_24;
 463                         break;
 464                 case DRM_FORMAT_XRGB2101010:
 465                         ctrl |= JZ_LCD_OSDCTRL_BPP_30;
 466                         break;
 467                 }
 468
 469                 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
 470                                    JZ_LCD_OSDCTRL_BPP_MASK, ctrl);
 471         } else {
 472                 switch (fourcc) {
 473                 case DRM_FORMAT_XRGB1555:
 474                         ctrl |= JZ_LCD_CTRL_RGB555;
 475                         fallthrough;
 476                 case DRM_FORMAT_RGB565:
 477                         ctrl |= JZ_LCD_CTRL_BPP_15_16;
 478                         break;
 479                 case DRM_FORMAT_RGB888:
 480                         ctrl |= JZ_LCD_CTRL_BPP_24_COMP;
 481                         break;
 482                 case DRM_FORMAT_XRGB8888:
 483                         ctrl |= JZ_LCD_CTRL_BPP_18_24;
 484                         break;
 485                 case DRM_FORMAT_XRGB2101010:
 486                         ctrl |= JZ_LCD_CTRL_BPP_30;
 487                         break;
 488                 }
 489
 490                 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 491                                    JZ_LCD_CTRL_BPP_MASK, ctrl);
 492         }
 493
 494         if (priv->soc_info->has_osd) {
 495                 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 496                         xy_reg = JZ_REG_LCD_XYP1;
 497                         size_reg = JZ_REG_LCD_SIZE1;
 498                 } else {
 499                         xy_reg = JZ_REG_LCD_XYP0;
 500                         size_reg = JZ_REG_LCD_SIZE0;
 501                 }
 502
 503                 regmap_write(priv->map, xy_reg,
 504                              state->crtc_x << JZ_LCD_XYP01_XPOS_LSB |
 505                              state->crtc_y << JZ_LCD_XYP01_YPOS_LSB);
 506                 regmap_write(priv->map, size_reg,
 507                              state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB |
 508                              state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB);
 509         }
 510 }
 511
 512 void ingenic_drm_sync_data(struct device *dev,
 513                            struct drm_plane_state *old_state,
 514                            struct drm_plane_state *state)
 515 {
 516         const struct drm_format_info *finfo = state->fb->format;
 517         struct ingenic_drm *priv = dev_get_drvdata(dev);
 518         struct drm_atomic_helper_damage_iter iter;
 519         unsigned int offset, i;
 520         struct drm_rect clip;
 521         dma_addr_t paddr;
 522         void *addr;
 523
 524         if (!ingenic_drm_cached_gem_buf)
 525                 return;
 526
 527         drm_atomic_helper_damage_iter_init(&iter, old_state, state);
 528
 529         drm_atomic_for_each_plane_damage(&iter, &clip) {
 530                 for (i = 0; i < finfo->num_planes; i++) {
 531                         paddr = drm_fb_cma_get_gem_addr(state->fb, state, i);
 532                         addr = phys_to_virt(paddr);
 533
 534                         /* Ignore x1/x2 values, invalidate complete lines */
 535                         offset = clip.y1 * state->fb->pitches[i];
 536
 537                         dma_cache_sync(priv->dev, addr + offset,
 538                                        (clip.y2 - clip.y1) * state->fb->pitches[i],
 539                                        DMA_TO_DEVICE);
 540                 }
 541         }
 542 }
 543
 544 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane,
 545                                             struct drm_plane_state *oldstate)
 546 {
 547         struct ingenic_drm *priv = drm_device_get_priv(plane->dev);
 548         struct drm_plane_state *state = plane->state;
 549         struct ingenic_dma_hwdesc *hwdesc;
 550         unsigned int width, height, cpp;
 551         dma_addr_t addr;
 552
 553         if (state && state->fb) {
 554                 ingenic_drm_sync_data(priv->dev, oldstate, state);
 555
 556                 addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
 557                 width = state->src_w >> 16;
 558                 height = state->src_h >> 16;
 559                 cpp = state->fb->format->cpp[0];
 560
 561                 if (priv->soc_info->has_osd && plane->type == DRM_PLANE_TYPE_OVERLAY)
 562                         hwdesc = &priv->dma_hwdescs->hwdesc_f0;
 563                 else
 564                         hwdesc = &priv->dma_hwdescs->hwdesc_f1;
 565
 566                 hwdesc->addr = addr;
 567                 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4);
 568
 569                 if (drm_atomic_crtc_needs_modeset(state->crtc->state))
 570                         ingenic_drm_plane_config(priv->dev, plane,
 571                                                  state->fb->format->format);
 572         }
 573 }
 574
 575 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder,
 576                                                 struct drm_crtc_state *crtc_state,
 577                                                 struct drm_connector_state *conn_state)
 578 {
 579         struct ingenic_drm *priv = drm_device_get_priv(encoder->dev);
 580         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 581         struct drm_connector *conn = conn_state->connector;
 582         struct drm_display_info *info = &conn->display_info;
 583         unsigned int cfg;
 584
 585         priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
 586
 587         if (priv->panel_is_sharp) {
 588                 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
 589         } else {
 590                 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
 591                     | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
 592         }
 593
 594         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 595                 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
 596         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 597                 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
 598         if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
 599                 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
 600         if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 601                 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
 602
 603         if (!priv->panel_is_sharp) {
 604                 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) {
 605                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 606                                 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
 607                         else
 608                                 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
 609                 } else {
 610                         switch (*info->bus_formats) {
 611                         case MEDIA_BUS_FMT_RGB565_1X16:
 612                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
 613                                 break;
 614                         case MEDIA_BUS_FMT_RGB666_1X18:
 615                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
 616                                 break;
 617                         case MEDIA_BUS_FMT_RGB888_1X24:
 618                                 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
 619                                 break;
 620                         case MEDIA_BUS_FMT_RGB888_3X8:
 621                                 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
 622                                 break;
 623                         default:
 624                                 break;
 625                         }
 626                 }
 627         }
 628
 629         regmap_write(priv->map, JZ_REG_LCD_CFG, cfg);
 630 }
 631
 632 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder,
 633                                             struct drm_crtc_state *crtc_state,
 634                                             struct drm_connector_state *conn_state)
 635 {
 636         struct drm_display_info *info = &conn_state->connector->display_info;
 637
 638         if (info->num_bus_formats != 1)
 639                 return -EINVAL;
 640
 641         if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV)
 642                 return 0;
 643
 644         switch (*info->bus_formats) {
 645         case MEDIA_BUS_FMT_RGB565_1X16:
 646         case MEDIA_BUS_FMT_RGB666_1X18:
 647         case MEDIA_BUS_FMT_RGB888_1X24:
 648         case MEDIA_BUS_FMT_RGB888_3X8:
 649                 return 0;
 650         default:
 651                 return -EINVAL;
 652         }
 653 }
 654
 655 static void ingenic_drm_atomic_helper_commit_tail(struct drm_atomic_state *old_state)
 656 {
 657         /*
 658          * Just your regular drm_atomic_helper_commit_tail(), but only calls
 659          * drm_atomic_helper_wait_for_vblanks() if priv->no_vblank.
 660          */
 661         struct drm_device *dev = old_state->dev;
 662         struct ingenic_drm *priv = drm_device_get_priv(dev);
 663
 664         drm_atomic_helper_commit_modeset_disables(dev, old_state);
 665
 666         drm_atomic_helper_commit_planes(dev, old_state, 0);
 667
 668         drm_atomic_helper_commit_modeset_enables(dev, old_state);
 669
 670         drm_atomic_helper_commit_hw_done(old_state);
 671
 672         if (!priv->no_vblank)
 673                 drm_atomic_helper_wait_for_vblanks(dev, old_state);
 674
 675         drm_atomic_helper_cleanup_planes(dev, old_state);
 676 }
 677
 678 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg)
 679 {
 680         struct ingenic_drm *priv = drm_device_get_priv(arg);
 681         unsigned int state;
 682
 683         regmap_read(priv->map, JZ_REG_LCD_STATE, &state);
 684
 685         regmap_update_bits(priv->map, JZ_REG_LCD_STATE,
 686                            JZ_LCD_STATE_EOF_IRQ, 0);
 687
 688         if (state & JZ_LCD_STATE_EOF_IRQ)
 689                 drm_crtc_handle_vblank(&priv->crtc);
 690
 691         return IRQ_HANDLED;
 692 }
 693
 694 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
 695 {
 696         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 697
 698         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
 699                            JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ);
 700
 701         return 0;
 702 }
 703
 704 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc)
 705 {
 706         struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
 707
 708         regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0);
 709 }
 710
 711 static struct drm_framebuffer *
 712 ingenic_drm_gem_fb_create(struct drm_device *dev, struct drm_file *file,
 713                           const struct drm_mode_fb_cmd2 *mode_cmd)
 714 {
 715         if (ingenic_drm_cached_gem_buf)
 716                 return drm_gem_fb_create_with_dirty(dev, file, mode_cmd);
 717
 718         return drm_gem_fb_create(dev, file, mode_cmd);
 719 }
 720
 721 static int ingenic_drm_gem_mmap(struct drm_gem_object *obj,
 722                                 struct vm_area_struct *vma)
 723 {
 724         struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(obj);
 725         struct device *dev = cma_obj->base.dev->dev;
 726         unsigned long attrs;
 727         int ret;
 728
 729         if (ingenic_drm_cached_gem_buf)
 730                 attrs = DMA_ATTR_NON_CONSISTENT;
 731         else
 732                 attrs = DMA_ATTR_WRITE_COMBINE;
 733
 734         /*
 735          * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
 736          * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
 737          * the whole buffer.
 738          */
 739         vma->vm_flags &= ~VM_PFNMAP;
 740         vma->vm_pgoff = 0;
 741         vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
 742
 743         ret = dma_mmap_attrs(dev, vma, cma_obj->vaddr, cma_obj->paddr,
 744                              vma->vm_end - vma->vm_start, attrs);
 745         if (ret)
 746                 drm_gem_vm_close(vma);
 747
 748         return ret;
 749 }
 750
 751 static int ingenic_drm_gem_cma_mmap(struct file *filp,
 752                                     struct vm_area_struct *vma)
 753 {
 754         int ret;
 755
 756         ret = drm_gem_mmap(filp, vma);
 757         if (ret)
 758                 return ret;
 759
 760         return ingenic_drm_gem_mmap(vma->vm_private_data, vma);
 761 }
 762
 763 static const struct file_operations ingenic_drm_fops = {
 764         .owner          = THIS_MODULE,
 765         .open           = drm_open,
 766         .release        = drm_release,
 767         .unlocked_ioctl = drm_ioctl,
 768         .compat_ioctl   = drm_compat_ioctl,
 769         .poll           = drm_poll,
 770         .read           = drm_read,
 771         .llseek         = noop_llseek,
 772         .mmap           = ingenic_drm_gem_cma_mmap,
 773 };
 774
 775 static struct drm_driver ingenic_drm_driver_data = {
 776         .driver_features        = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
 777         .name                   = "ingenic-drm",
 778         .desc                   = "DRM module for Ingenic SoCs",
 779         .date                   = "20200716",
 780         .major                  = 1,
 781         .minor                  = 1,
 782         .patchlevel             = 0,
 783
 784         .fops                   = &ingenic_drm_fops,
 785         DRM_GEM_CMA_DRIVER_OPS,
 786
 787         .irq_handler            = ingenic_drm_irq_handler,
 788 };
 789
 790 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = {
 791         .update_plane           = drm_atomic_helper_update_plane,
 792         .disable_plane          = drm_atomic_helper_disable_plane,
 793         .reset                  = drm_atomic_helper_plane_reset,
 794         .destroy                = drm_plane_cleanup,
 795
 796         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 797         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 798 };
 799
 800 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = {
 801         .set_config             = drm_atomic_helper_set_config,
 802         .page_flip              = drm_atomic_helper_page_flip,
 803         .reset                  = drm_atomic_helper_crtc_reset,
 804         .destroy                = drm_crtc_cleanup,
 805
 806         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 807         .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
 808
 809         .enable_vblank          = ingenic_drm_enable_vblank,
 810         .disable_vblank         = ingenic_drm_disable_vblank,
 811
 812         .gamma_set              = drm_atomic_helper_legacy_gamma_set,
 813 };
 814
 815 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {
 816         .atomic_update          = ingenic_drm_plane_atomic_update,
 817         .atomic_check           = ingenic_drm_plane_atomic_check,
 818         .atomic_disable         = ingenic_drm_plane_atomic_disable,
 819         .prepare_fb             = drm_gem_fb_prepare_fb,
 820 };
 821
 822 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = {
 823         .atomic_enable          = ingenic_drm_crtc_atomic_enable,
 824         .atomic_disable         = ingenic_drm_crtc_atomic_disable,
 825         .atomic_begin           = ingenic_drm_crtc_atomic_begin,
 826         .atomic_flush           = ingenic_drm_crtc_atomic_flush,
 827         .atomic_check           = ingenic_drm_crtc_atomic_check,
 828         .mode_valid             = ingenic_drm_crtc_mode_valid,
 829 };
 830
 831 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = {
 832         .atomic_mode_set        = ingenic_drm_encoder_atomic_mode_set,
 833         .atomic_check           = ingenic_drm_encoder_atomic_check,
 834 };
 835
 836 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = {
 837         .fb_create              = ingenic_drm_gem_fb_create,
 838         .output_poll_changed    = drm_fb_helper_output_poll_changed,
 839         .atomic_check           = drm_atomic_helper_check,
 840         .atomic_commit          = drm_atomic_helper_commit,
 841 };
 842
 843 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = {
 844         .atomic_commit_tail = ingenic_drm_atomic_helper_commit_tail,
 845 };
 846
 847 static void ingenic_drm_unbind_all(void *d)
 848 {
 849         struct ingenic_drm *priv = d;
 850
 851         component_unbind_all(priv->dev, &priv->drm);
 852 }
 853
 854 static void __maybe_unused ingenic_drm_release_rmem(void *d)
 855 {
 856         of_reserved_mem_device_release(d);
 857 }
 858
 859 static int ingenic_drm_bind(struct device *dev, bool has_components)
 860 {
 861         struct platform_device *pdev = to_platform_device(dev);
 862         const struct jz_soc_info *soc_info;
 863         struct ingenic_drm *priv;
 864         struct clk *parent_clk;
 865         struct drm_bridge *bridge;
 866         struct drm_panel *panel;
 867         struct drm_encoder *encoder;
 868         struct drm_device *drm;
 869         void __iomem *base;
 870         long parent_rate;
 871         unsigned int i, clone_mask = 0;
 872         dma_addr_t dma_hwdesc_phys_f0, dma_hwdesc_phys_f1;
 873         int ret, irq;
 874
 875         soc_info = of_device_get_match_data(dev);
 876         if (!soc_info) {
 877                 dev_err(dev, "Missing platform data\n");
 878                 return -EINVAL;
 879         }
 880
 881         if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) {
 882                 ret = of_reserved_mem_device_init(dev);
 883
 884                 if (ret && ret != -ENODEV)
 885                         dev_warn(dev, "Failed to get reserved memory: %d\n", ret);
 886
 887                 if (!ret) {
 888                         ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev);
 889                         if (ret)
 890                                 return ret;
 891                 }
 892         }
 893
 894         priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data,
 895                                   struct ingenic_drm, drm);
 896         if (IS_ERR(priv))
 897                 return PTR_ERR(priv);
 898
 899         priv->soc_info = soc_info;
 900         priv->dev = dev;
 901         drm = &priv->drm;
 902
 903         platform_set_drvdata(pdev, priv);
 904
 905         ret = drmm_mode_config_init(drm);
 906         if (ret)
 907                 return ret;
 908
 909         drm->mode_config.min_width = 0;
 910         drm->mode_config.min_height = 0;
 911         drm->mode_config.max_width = soc_info->max_width;
 912         drm->mode_config.max_height = 4095;
 913         drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
 914         drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers;
 915
 916         base = devm_platform_ioremap_resource(pdev, 0);
 917         if (IS_ERR(base)) {
 918                 dev_err(dev, "Failed to get memory resource\n");
 919                 return PTR_ERR(base);
 920         }
 921
 922         priv->map = devm_regmap_init_mmio(dev, base,
 923                                           &ingenic_drm_regmap_config);
 924         if (IS_ERR(priv->map)) {
 925                 dev_err(dev, "Failed to create regmap\n");
 926                 return PTR_ERR(priv->map);
 927         }
 928
 929         irq = platform_get_irq(pdev, 0);
 930         if (irq < 0)
 931                 return irq;
 932
 933         if (soc_info->needs_dev_clk) {
 934                 priv->lcd_clk = devm_clk_get(dev, "lcd");
 935                 if (IS_ERR(priv->lcd_clk)) {
 936                         dev_err(dev, "Failed to get lcd clock\n");
 937                         return PTR_ERR(priv->lcd_clk);
 938                 }
 939         }
 940
 941         priv->pix_clk = devm_clk_get(dev, "lcd_pclk");
 942         if (IS_ERR(priv->pix_clk)) {
 943                 dev_err(dev, "Failed to get pixel clock\n");
 944                 return PTR_ERR(priv->pix_clk);
 945         }
 946
 947         priv->dma_hwdescs = dmam_alloc_coherent(dev,
 948                                                 sizeof(*priv->dma_hwdescs),
 949                                                 &priv->dma_hwdescs_phys,
 950                                                 GFP_KERNEL);
 951         if (!priv->dma_hwdescs)
 952                 return -ENOMEM;
 953
 954
 955         /* Configure DMA hwdesc for foreground0 plane */
 956         dma_hwdesc_phys_f0 = priv->dma_hwdescs_phys
 957                 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0);
 958         priv->dma_hwdescs->hwdesc_f0.next = dma_hwdesc_phys_f0;
 959         priv->dma_hwdescs->hwdesc_f0.id = 0xf0;
 960
 961         /* Configure DMA hwdesc for foreground1 plane */
 962         dma_hwdesc_phys_f1 = priv->dma_hwdescs_phys
 963                 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f1);
 964         priv->dma_hwdescs->hwdesc_f1.next = dma_hwdesc_phys_f1;
 965         priv->dma_hwdescs->hwdesc_f1.id = 0xf1;
 966
 967         if (soc_info->has_osd)
 968                 priv->ipu_plane = drm_plane_from_index(drm, 0);
 969
 970         drm_plane_helper_add(&priv->f1, &ingenic_drm_plane_helper_funcs);
 971
 972         ret = drm_universal_plane_init(drm, &priv->f1, 1,
 973                                        &ingenic_drm_primary_plane_funcs,
 974                                        priv->soc_info->formats_f1,
 975                                        priv->soc_info->num_formats_f1,
 976                                        NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
 977         if (ret) {
 978                 dev_err(dev, "Failed to register plane: %i\n", ret);
 979                 return ret;
 980         }
 981
 982         drm_plane_enable_fb_damage_clips(&priv->f1);
 983
 984         drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs);
 985
 986         ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->f1,
 987                                         NULL, &ingenic_drm_crtc_funcs, NULL);
 988         if (ret) {
 989                 dev_err(dev, "Failed to init CRTC: %i\n", ret);
 990                 return ret;
 991         }
 992
 993         if (soc_info->has_osd) {
 994                 drm_plane_helper_add(&priv->f0,
 995                                      &ingenic_drm_plane_helper_funcs);
 996
 997                 ret = drm_universal_plane_init(drm, &priv->f0, 1,
 998                                                &ingenic_drm_primary_plane_funcs,
 999                                                priv->soc_info->formats_f0,
1000                                                priv->soc_info->num_formats_f0,
1001                                                NULL, DRM_PLANE_TYPE_OVERLAY,
1002                                                NULL);
1003                 if (ret) {
1004                         dev_err(dev, "Failed to register overlay plane: %i\n",
1005                                 ret);
1006                         return ret;
1007                 }
1008
1009                 drm_plane_enable_fb_damage_clips(&priv->f0);
1010
1011                 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) {
1012                         ret = component_bind_all(dev, drm);
1013                         if (ret) {
1014                                 if (ret != -EPROBE_DEFER)
1015                                         dev_err(dev, "Failed to bind components: %i\n", ret);
1016                                 return ret;
1017                         }
1018
1019                         ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv);
1020                         if (ret)
1021                                 return ret;
1022
1023                         priv->ipu_plane = drm_plane_from_index(drm, 2);
1024                         if (!priv->ipu_plane) {
1025                                 dev_err(dev, "Failed to retrieve IPU plane\n");
1026                                 return -EINVAL;
1027                         }
1028                 }
1029         }
1030
1031         for (i = 0; ; i++) {
1032                 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge);
1033                 if (ret) {
1034                         if (ret == -ENODEV)
1035                                 break; /* we're done */
1036                         if (ret != -EPROBE_DEFER)
1037                                 dev_err(dev, "Failed to get bridge handle\n");
1038                         return ret;
1039                 }
1040
1041                 if (panel)
1042                         bridge = devm_drm_panel_bridge_add_typed(dev, panel,
1043                                                                  DRM_MODE_CONNECTOR_DPI);
1044
1045                 encoder = devm_kzalloc(dev, sizeof(*encoder), GFP_KERNEL);
1046                 if (!encoder)
1047                         return -ENOMEM;
1048
1049                 encoder->possible_crtcs = 1;
1050
1051                 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs);
1052
1053                 ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_DPI);
1054                 if (ret) {
1055                         dev_err(dev, "Failed to init encoder: %d\n", ret);
1056                         return ret;
1057                 }
1058
1059                 ret = drm_bridge_attach(encoder, bridge, NULL, 0);
1060                 if (ret) {
1061                         dev_err(dev, "Unable to attach bridge\n");
1062                         return ret;
1063                 }
1064         }
1065
1066         drm_for_each_encoder(encoder, drm) {
1067                 clone_mask |= BIT(drm_encoder_index(encoder));
1068         }
1069
1070         drm_for_each_encoder(encoder, drm) {
1071                 encoder->possible_clones = clone_mask;
1072         }
1073
1074         ret = drm_irq_install(drm, irq);
1075         if (ret) {
1076                 dev_err(dev, "Unable to install IRQ handler\n");
1077                 return ret;
1078         }
1079
1080         ret = drm_vblank_init(drm, 1);
1081         if (ret) {
1082                 dev_err(dev, "Failed calling drm_vblank_init()\n");
1083                 return ret;
1084         }
1085
1086         drm_mode_config_reset(drm);
1087
1088         ret = clk_prepare_enable(priv->pix_clk);
1089         if (ret) {
1090                 dev_err(dev, "Unable to start pixel clock\n");
1091                 return ret;
1092         }
1093
1094         if (priv->lcd_clk) {
1095                 parent_clk = clk_get_parent(priv->lcd_clk);
1096                 parent_rate = clk_get_rate(parent_clk);
1097
1098                 /* LCD Device clock must be 3x the pixel clock for STN panels,
1099                  * or 1.5x the pixel clock for TFT panels. To avoid having to
1100                  * check for the LCD device clock everytime we do a mode change,
1101                  * we set the LCD device clock to the highest rate possible.
1102                  */
1103                 ret = clk_set_rate(priv->lcd_clk, parent_rate);
1104                 if (ret) {
1105                         dev_err(dev, "Unable to set LCD clock rate\n");
1106                         goto err_pixclk_disable;
1107                 }
1108
1109                 ret = clk_prepare_enable(priv->lcd_clk);
1110                 if (ret) {
1111                         dev_err(dev, "Unable to start lcd clock\n");
1112                         goto err_pixclk_disable;
1113                 }
1114         }
1115
1116         /* Set address of our DMA descriptor chain */
1117         regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_phys_f0);
1118         regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_phys_f1);
1119
1120         /* Enable OSD if available */
1121         if (soc_info->has_osd)
1122                 regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN);
1123
1124         mutex_init(&priv->clk_mutex);
1125         priv->clock_nb.notifier_call = ingenic_drm_update_pixclk;
1126
1127         parent_clk = clk_get_parent(priv->pix_clk);
1128         ret = clk_notifier_register(parent_clk, &priv->clock_nb);
1129         if (ret) {
1130                 dev_err(dev, "Unable to register clock notifier\n");
1131                 goto err_devclk_disable;
1132         }
1133
1134         ret = drm_dev_register(drm, 0);
1135         if (ret) {
1136                 dev_err(dev, "Failed to register DRM driver\n");
1137                 goto err_clk_notifier_unregister;
1138         }
1139
1140         drm_fbdev_generic_setup(drm, 32);
1141
1142         return 0;
1143
1144 err_clk_notifier_unregister:
1145         clk_notifier_unregister(parent_clk, &priv->clock_nb);
1146 err_devclk_disable:
1147         if (priv->lcd_clk)
1148                 clk_disable_unprepare(priv->lcd_clk);
1149 err_pixclk_disable:
1150         clk_disable_unprepare(priv->pix_clk);
1151         return ret;
1152 }
1153
1154 static int ingenic_drm_bind_with_components(struct device *dev)
1155 {
1156         return ingenic_drm_bind(dev, true);
1157 }
1158
1159 static int compare_of(struct device *dev, void *data)
1160 {
1161         return dev->of_node == data;
1162 }
1163
1164 static void ingenic_drm_unbind(struct device *dev)
1165 {
1166         struct ingenic_drm *priv = dev_get_drvdata(dev);
1167         struct clk *parent_clk = clk_get_parent(priv->pix_clk);
1168
1169         clk_notifier_unregister(parent_clk, &priv->clock_nb);
1170         if (priv->lcd_clk)
1171                 clk_disable_unprepare(priv->lcd_clk);
1172         clk_disable_unprepare(priv->pix_clk);
1173
1174         drm_dev_unregister(&priv->drm);
1175         drm_atomic_helper_shutdown(&priv->drm);
1176 }
1177
1178 static const struct component_master_ops ingenic_master_ops = {
1179         .bind = ingenic_drm_bind_with_components,
1180         .unbind = ingenic_drm_unbind,
1181 };
1182
1183 static int ingenic_drm_probe(struct platform_device *pdev)
1184 {
1185         struct device *dev = &pdev->dev;
1186         struct component_match *match = NULL;
1187         struct device_node *np;
1188
1189         if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1190                 return ingenic_drm_bind(dev, false);
1191
1192         /* IPU is at port address 8 */
1193         np = of_graph_get_remote_node(dev->of_node, 8, 0);
1194         if (!np)
1195                 return ingenic_drm_bind(dev, false);
1196
1197         drm_of_component_match_add(dev, &match, compare_of, np);
1198         of_node_put(np);
1199
1200         return component_master_add_with_match(dev, &ingenic_master_ops, match);
1201 }
1202
1203 static int ingenic_drm_remove(struct platform_device *pdev)
1204 {
1205         struct device *dev = &pdev->dev;
1206
1207         if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1208                 ingenic_drm_unbind(dev);
1209         else
1210                 component_master_del(dev, &ingenic_master_ops);
1211
1212         return 0;
1213 }
1214
1215 static const u32 jz4740_formats[] = {
1216         DRM_FORMAT_XRGB1555,
1217         DRM_FORMAT_RGB565,
1218         DRM_FORMAT_XRGB8888,
1219 };
1220
1221 static const u32 jz4725b_formats_f1[] = {
1222         DRM_FORMAT_XRGB1555,
1223         DRM_FORMAT_RGB565,
1224         DRM_FORMAT_XRGB8888,
1225 };
1226
1227 static const u32 jz4725b_formats_f0[] = {
1228         DRM_FORMAT_XRGB1555,
1229         DRM_FORMAT_RGB565,
1230         DRM_FORMAT_XRGB8888,
1231 };
1232
1233 static const u32 jz4770_formats_f1[] = {
1234         DRM_FORMAT_XRGB1555,
1235         DRM_FORMAT_RGB565,
1236         DRM_FORMAT_RGB888,
1237         DRM_FORMAT_XRGB8888,
1238         DRM_FORMAT_XRGB2101010,
1239 };
1240
1241 static const u32 jz4770_formats_f0[] = {
1242         DRM_FORMAT_XRGB1555,
1243         DRM_FORMAT_RGB565,
1244         DRM_FORMAT_RGB888,
1245         DRM_FORMAT_XRGB8888,
1246         DRM_FORMAT_XRGB2101010,
1247 };
1248
1249 static const struct jz_soc_info jz4740_soc_info = {
1250         .needs_dev_clk = true,
1251         .has_osd = false,
1252         .max_width = 800,
1253         .max_height = 600,
1254         .formats_f1 = jz4740_formats,
1255         .num_formats_f1 = ARRAY_SIZE(jz4740_formats),
1256         /* JZ4740 has only one plane */
1257 };
1258
1259 static const struct jz_soc_info jz4725b_soc_info = {
1260         .needs_dev_clk = false,
1261         .has_osd = true,
1262         .max_width = 800,
1263         .max_height = 600,
1264         .formats_f1 = jz4725b_formats_f1,
1265         .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1),
1266         .formats_f0 = jz4725b_formats_f0,
1267         .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0),
1268 };
1269
1270 static const struct jz_soc_info jz4770_soc_info = {
1271         .needs_dev_clk = false,
1272         .has_osd = true,
1273         .max_width = 1280,
1274         .max_height = 720,
1275         .formats_f1 = jz4770_formats_f1,
1276         .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1),
1277         .formats_f0 = jz4770_formats_f0,
1278         .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0),
1279 };
1280
1281 static const struct of_device_id ingenic_drm_of_match[] = {
1282         { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info },
1283         { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info },
1284         { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info },
1285         { /* sentinel */ },
1286 };
1287 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
1288
1289 static struct platform_driver ingenic_drm_driver = {
1290         .driver = {
1291                 .name = "ingenic-drm",
1292                 .of_match_table = of_match_ptr(ingenic_drm_of_match),
1293         },
1294         .probe = ingenic_drm_probe,
1295         .remove = ingenic_drm_remove,
1296 };
1297
1298 static int ingenic_drm_init(void)
1299 {
1300         int err;
1301
1302         if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) {
1303                 err = platform_driver_register(ingenic_ipu_driver_ptr);
1304                 if (err)
1305                         return err;
1306         }
1307
1308         return platform_driver_register(&ingenic_drm_driver);
1309 }
1310 module_init(ingenic_drm_init);
1311
1312 static void ingenic_drm_exit(void)
1313 {
1314         platform_driver_unregister(&ingenic_drm_driver);
1315
1316         if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU))
1317                 platform_driver_unregister(ingenic_ipu_driver_ptr);
1318 }
1319 module_exit(ingenic_drm_exit);
1320
1321 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
1322 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n");
1323 MODULE_LICENSE("GPL v2");