1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX IPUv3 DP Overlay Planes
5 * Copyright (C) 2013 Philipp Zabel, Pengutronix
8 #include <drm/drm_atomic.h>
9 #include <drm/drm_atomic_helper.h>
10 #include <drm/drm_blend.h>
11 #include <drm/drm_fb_dma_helper.h>
12 #include <drm/drm_fourcc.h>
13 #include <drm/drm_framebuffer.h>
14 #include <drm/drm_gem_atomic_helper.h>
15 #include <drm/drm_gem_cma_helper.h>
16 #include <drm/drm_managed.h>
18 #include <video/imx-ipu-v3.h>
21 #include "ipuv3-plane.h"
23 struct ipu_plane_state {
24 struct drm_plane_state base;
28 static inline struct ipu_plane_state *
29 to_ipu_plane_state(struct drm_plane_state *p)
31 return container_of(p, struct ipu_plane_state, base);
34 static unsigned int ipu_src_rect_width(const struct drm_plane_state *state)
36 return ALIGN(drm_rect_width(&state->src) >> 16, 8);
39 static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p)
41 return container_of(p, struct ipu_plane, base);
44 static const uint32_t ipu_plane_all_formats[] = {
77 DRM_FORMAT_RGBX8888_A8,
78 DRM_FORMAT_BGRX8888_A8,
81 static const uint32_t ipu_plane_rgb_formats[] = {
100 DRM_FORMAT_RGB888_A8,
101 DRM_FORMAT_BGR888_A8,
102 DRM_FORMAT_RGBX8888_A8,
103 DRM_FORMAT_BGRX8888_A8,
106 static const uint64_t ipu_format_modifiers[] = {
107 DRM_FORMAT_MOD_LINEAR,
108 DRM_FORMAT_MOD_INVALID
111 static const uint64_t pre_format_modifiers[] = {
112 DRM_FORMAT_MOD_LINEAR,
113 DRM_FORMAT_MOD_VIVANTE_TILED,
114 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
115 DRM_FORMAT_MOD_INVALID
118 int ipu_plane_irq(struct ipu_plane *ipu_plane)
120 return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
124 static inline unsigned long
125 drm_plane_state_to_eba(struct drm_plane_state *state, int plane)
127 struct drm_framebuffer *fb = state->fb;
128 struct drm_gem_cma_object *cma_obj;
129 int x = state->src.x1 >> 16;
130 int y = state->src.y1 >> 16;
132 cma_obj = drm_fb_dma_get_gem_obj(fb, plane);
135 return cma_obj->paddr + fb->offsets[plane] + fb->pitches[plane] * y +
136 fb->format->cpp[plane] * x;
139 static inline unsigned long
140 drm_plane_state_to_ubo(struct drm_plane_state *state)
142 struct drm_framebuffer *fb = state->fb;
143 struct drm_gem_cma_object *cma_obj;
144 unsigned long eba = drm_plane_state_to_eba(state, 0);
145 int x = state->src.x1 >> 16;
146 int y = state->src.y1 >> 16;
148 cma_obj = drm_fb_dma_get_gem_obj(fb, 1);
151 x /= fb->format->hsub;
152 y /= fb->format->vsub;
154 return cma_obj->paddr + fb->offsets[1] + fb->pitches[1] * y +
155 fb->format->cpp[1] * x - eba;
158 static inline unsigned long
159 drm_plane_state_to_vbo(struct drm_plane_state *state)
161 struct drm_framebuffer *fb = state->fb;
162 struct drm_gem_cma_object *cma_obj;
163 unsigned long eba = drm_plane_state_to_eba(state, 0);
164 int x = state->src.x1 >> 16;
165 int y = state->src.y1 >> 16;
167 cma_obj = drm_fb_dma_get_gem_obj(fb, 2);
170 x /= fb->format->hsub;
171 y /= fb->format->vsub;
173 return cma_obj->paddr + fb->offsets[2] + fb->pitches[2] * y +
174 fb->format->cpp[2] * x - eba;
177 static void ipu_plane_put_resources(struct drm_device *dev, void *ptr)
179 struct ipu_plane *ipu_plane = ptr;
181 if (!IS_ERR_OR_NULL(ipu_plane->dp))
182 ipu_dp_put(ipu_plane->dp);
183 if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
184 ipu_dmfc_put(ipu_plane->dmfc);
185 if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
186 ipu_idmac_put(ipu_plane->ipu_ch);
187 if (!IS_ERR_OR_NULL(ipu_plane->alpha_ch))
188 ipu_idmac_put(ipu_plane->alpha_ch);
191 static int ipu_plane_get_resources(struct drm_device *dev,
192 struct ipu_plane *ipu_plane)
197 ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
198 if (IS_ERR(ipu_plane->ipu_ch)) {
199 ret = PTR_ERR(ipu_plane->ipu_ch);
200 DRM_ERROR("failed to get idmac channel: %d\n", ret);
204 ret = drmm_add_action_or_reset(dev, ipu_plane_put_resources, ipu_plane);
208 alpha_ch = ipu_channel_alpha_channel(ipu_plane->dma);
210 ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch);
211 if (IS_ERR(ipu_plane->alpha_ch)) {
212 ret = PTR_ERR(ipu_plane->alpha_ch);
213 DRM_ERROR("failed to get alpha idmac channel %d: %d\n",
219 ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
220 if (IS_ERR(ipu_plane->dmfc)) {
221 ret = PTR_ERR(ipu_plane->dmfc);
222 DRM_ERROR("failed to get dmfc: ret %d\n", ret);
226 if (ipu_plane->dp_flow >= 0) {
227 ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
228 if (IS_ERR(ipu_plane->dp)) {
229 ret = PTR_ERR(ipu_plane->dp);
230 DRM_ERROR("failed to get dp flow: %d\n", ret);
238 static bool ipu_plane_separate_alpha(struct ipu_plane *ipu_plane)
240 switch (ipu_plane->base.state->fb->format->format) {
241 case DRM_FORMAT_RGB565_A8:
242 case DRM_FORMAT_BGR565_A8:
243 case DRM_FORMAT_RGB888_A8:
244 case DRM_FORMAT_BGR888_A8:
245 case DRM_FORMAT_RGBX8888_A8:
246 case DRM_FORMAT_BGRX8888_A8:
253 static void ipu_plane_enable(struct ipu_plane *ipu_plane)
256 ipu_dp_enable(ipu_plane->ipu);
257 ipu_dmfc_enable_channel(ipu_plane->dmfc);
258 ipu_idmac_enable_channel(ipu_plane->ipu_ch);
259 if (ipu_plane_separate_alpha(ipu_plane))
260 ipu_idmac_enable_channel(ipu_plane->alpha_ch);
262 ipu_dp_enable_channel(ipu_plane->dp);
265 void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel)
269 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
271 ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
272 if (ret == -ETIMEDOUT) {
273 DRM_ERROR("[PLANE:%d] IDMAC timeout\n",
274 ipu_plane->base.base.id);
277 if (ipu_plane->dp && disable_dp_channel)
278 ipu_dp_disable_channel(ipu_plane->dp, false);
279 ipu_idmac_disable_channel(ipu_plane->ipu_ch);
280 if (ipu_plane->alpha_ch)
281 ipu_idmac_disable_channel(ipu_plane->alpha_ch);
282 ipu_dmfc_disable_channel(ipu_plane->dmfc);
284 ipu_dp_disable(ipu_plane->ipu);
285 if (ipu_prg_present(ipu_plane->ipu))
286 ipu_prg_channel_disable(ipu_plane->ipu_ch);
289 void ipu_plane_disable_deferred(struct drm_plane *plane)
291 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
293 if (ipu_plane->disabling) {
294 ipu_plane->disabling = false;
295 ipu_plane_disable(ipu_plane, false);
299 static void ipu_plane_state_reset(struct drm_plane *plane)
301 struct ipu_plane_state *ipu_state;
304 ipu_state = to_ipu_plane_state(plane->state);
305 __drm_atomic_helper_plane_destroy_state(plane->state);
310 ipu_state = kzalloc(sizeof(*ipu_state), GFP_KERNEL);
313 __drm_atomic_helper_plane_reset(plane, &ipu_state->base);
316 static struct drm_plane_state *
317 ipu_plane_duplicate_state(struct drm_plane *plane)
319 struct ipu_plane_state *state;
321 if (WARN_ON(!plane->state))
324 state = kmalloc(sizeof(*state), GFP_KERNEL);
326 __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
331 static void ipu_plane_destroy_state(struct drm_plane *plane,
332 struct drm_plane_state *state)
334 struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
336 __drm_atomic_helper_plane_destroy_state(state);
340 static bool ipu_plane_format_mod_supported(struct drm_plane *plane,
341 uint32_t format, uint64_t modifier)
343 struct ipu_soc *ipu = to_ipu_plane(plane)->ipu;
345 /* linear is supported for all planes and formats */
346 if (modifier == DRM_FORMAT_MOD_LINEAR)
350 * Without a PRG the possible modifiers list only includes the linear
351 * modifier, so we always take the early return from this function and
352 * only end up here if the PRG is present.
354 return ipu_prg_format_supported(ipu, format, modifier);
357 static const struct drm_plane_funcs ipu_plane_funcs = {
358 .update_plane = drm_atomic_helper_update_plane,
359 .disable_plane = drm_atomic_helper_disable_plane,
360 .reset = ipu_plane_state_reset,
361 .atomic_duplicate_state = ipu_plane_duplicate_state,
362 .atomic_destroy_state = ipu_plane_destroy_state,
363 .format_mod_supported = ipu_plane_format_mod_supported,
366 static int ipu_plane_atomic_check(struct drm_plane *plane,
367 struct drm_atomic_state *state)
369 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
371 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
373 struct drm_crtc_state *crtc_state;
374 struct device *dev = plane->dev->dev;
375 struct drm_framebuffer *fb = new_state->fb;
376 struct drm_framebuffer *old_fb = old_state->fb;
377 unsigned long eba, ubo, vbo, old_ubo, old_vbo, alpha_eba;
378 bool can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
385 if (WARN_ON(!new_state->crtc))
389 drm_atomic_get_existing_crtc_state(state,
391 if (WARN_ON(!crtc_state))
394 ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,
395 DRM_PLANE_NO_SCALING,
396 DRM_PLANE_NO_SCALING,
401 /* nothing to check when disabling or disabled */
402 if (!crtc_state->enable)
405 switch (plane->type) {
406 case DRM_PLANE_TYPE_PRIMARY:
407 /* full plane minimum width is 13 pixels */
408 if (drm_rect_width(&new_state->dst) < 13)
411 case DRM_PLANE_TYPE_OVERLAY:
414 dev_warn(dev, "Unsupported plane type %d\n", plane->type);
418 if (drm_rect_height(&new_state->dst) < 2)
422 * We support resizing active plane or changing its format by
423 * forcing CRTC mode change in plane's ->atomic_check callback
424 * and disabling all affected active planes in CRTC's ->atomic_disable
425 * callback. The planes will be reenabled in plane's ->atomic_update
429 (drm_rect_width(&new_state->dst) != drm_rect_width(&old_state->dst) ||
430 drm_rect_height(&new_state->dst) != drm_rect_height(&old_state->dst) ||
431 fb->format != old_fb->format))
432 crtc_state->mode_changed = true;
434 eba = drm_plane_state_to_eba(new_state, 0);
439 if (fb->pitches[0] < 1 || fb->pitches[0] > 16384)
442 if (old_fb && fb->pitches[0] != old_fb->pitches[0])
443 crtc_state->mode_changed = true;
445 if (ALIGN(fb->width, 8) * fb->format->cpp[0] >
446 fb->pitches[0] + fb->offsets[0]) {
447 dev_warn(dev, "pitch is not big enough for 8 pixels alignment");
451 switch (fb->format->format) {
452 case DRM_FORMAT_YUV420:
453 case DRM_FORMAT_YVU420:
454 case DRM_FORMAT_YUV422:
455 case DRM_FORMAT_YVU422:
456 case DRM_FORMAT_YUV444:
457 case DRM_FORMAT_YVU444:
459 * Multiplanar formats have to meet the following restrictions:
460 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
461 * - EBA, UBO and VBO are a multiple of 8
462 * - UBO and VBO are unsigned and not larger than 0xfffff8
463 * - Only EBA may be changed while scanout is active
464 * - The strides of U and V planes must be identical.
466 vbo = drm_plane_state_to_vbo(new_state);
468 if (vbo & 0x7 || vbo > 0xfffff8)
471 if (old_fb && (fb->format == old_fb->format)) {
472 old_vbo = drm_plane_state_to_vbo(old_state);
474 crtc_state->mode_changed = true;
477 if (fb->pitches[1] != fb->pitches[2])
481 case DRM_FORMAT_NV12:
482 case DRM_FORMAT_NV16:
483 ubo = drm_plane_state_to_ubo(new_state);
485 if (ubo & 0x7 || ubo > 0xfffff8)
488 if (old_fb && (fb->format == old_fb->format)) {
489 old_ubo = drm_plane_state_to_ubo(old_state);
491 crtc_state->mode_changed = true;
494 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
497 if (old_fb && old_fb->pitches[1] != fb->pitches[1])
498 crtc_state->mode_changed = true;
501 * The x/y offsets must be even in case of horizontal/vertical
502 * chroma subsampling.
504 if (((new_state->src.x1 >> 16) & (fb->format->hsub - 1)) ||
505 ((new_state->src.y1 >> 16) & (fb->format->vsub - 1)))
508 case DRM_FORMAT_RGB565_A8:
509 case DRM_FORMAT_BGR565_A8:
510 case DRM_FORMAT_RGB888_A8:
511 case DRM_FORMAT_BGR888_A8:
512 case DRM_FORMAT_RGBX8888_A8:
513 case DRM_FORMAT_BGRX8888_A8:
514 alpha_eba = drm_plane_state_to_eba(new_state, 1);
518 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
521 if (old_fb && old_fb->pitches[1] != fb->pitches[1])
522 crtc_state->mode_changed = true;
529 static void ipu_plane_atomic_disable(struct drm_plane *plane,
530 struct drm_atomic_state *state)
532 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
535 ipu_dp_disable_channel(ipu_plane->dp, true);
536 ipu_plane->disabling = true;
539 static int ipu_chan_assign_axi_id(int ipu_chan)
542 case IPUV3_CHANNEL_MEM_BG_SYNC:
544 case IPUV3_CHANNEL_MEM_FG_SYNC:
546 case IPUV3_CHANNEL_MEM_DC_SYNC:
553 static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride,
554 u8 *burstsize, u8 *num_bursts)
556 const unsigned int width_bytes = width * cpp;
557 unsigned int npb, bursts;
559 /* Maximum number of pixels per burst without overshooting stride */
560 for (npb = 64 / cpp; npb > 0; --npb) {
561 if (round_up(width_bytes, npb * cpp) <= stride)
566 /* Maximum number of consecutive bursts without overshooting stride */
567 for (bursts = 8; bursts > 1; bursts /= 2) {
568 if (round_up(width_bytes, npb * cpp * bursts) <= stride)
571 *num_bursts = bursts;
574 static void ipu_plane_atomic_update(struct drm_plane *plane,
575 struct drm_atomic_state *state)
577 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
579 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
580 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
582 struct ipu_plane_state *ipu_state = to_ipu_plane_state(new_state);
583 struct drm_crtc_state *crtc_state = new_state->crtc->state;
584 struct drm_framebuffer *fb = new_state->fb;
585 struct drm_rect *dst = &new_state->dst;
586 unsigned long eba, ubo, vbo;
587 unsigned long alpha_eba = 0;
588 enum ipu_color_space ics;
589 unsigned int axi_id = 0;
590 const struct drm_format_info *info;
591 u8 burstsize, num_bursts;
595 if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG)
596 ipu_dp_set_window_pos(ipu_plane->dp, dst->x1, dst->y1);
598 switch (ipu_plane->dp_flow) {
599 case IPU_DP_FLOW_SYNC_BG:
600 if (new_state->normalized_zpos == 1) {
601 ipu_dp_set_global_alpha(ipu_plane->dp,
602 !fb->format->has_alpha, 0xff,
605 ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
608 case IPU_DP_FLOW_SYNC_FG:
609 if (new_state->normalized_zpos == 1) {
610 ipu_dp_set_global_alpha(ipu_plane->dp,
611 !fb->format->has_alpha, 0xff,
617 eba = drm_plane_state_to_eba(new_state, 0);
620 * Configure PRG channel and attached PRE, this changes the EBA to an
621 * internal SRAM location.
623 if (ipu_state->use_pre) {
624 axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
625 ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id,
626 ipu_src_rect_width(new_state),
627 drm_rect_height(&new_state->src) >> 16,
628 fb->pitches[0], fb->format->format,
632 if (!old_state->fb ||
633 old_state->fb->format->format != fb->format->format ||
634 old_state->color_encoding != new_state->color_encoding ||
635 old_state->color_range != new_state->color_range) {
636 ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
637 switch (ipu_plane->dp_flow) {
638 case IPU_DP_FLOW_SYNC_BG:
639 ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
640 new_state->color_range, ics,
641 IPUV3_COLORSPACE_RGB);
643 case IPU_DP_FLOW_SYNC_FG:
644 ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
645 new_state->color_range, ics,
646 IPUV3_COLORSPACE_UNKNOWN);
651 if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) {
652 /* nothing to do if PRE is used */
653 if (ipu_state->use_pre)
655 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
656 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
657 ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
658 if (ipu_plane_separate_alpha(ipu_plane)) {
659 active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch);
660 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active,
662 ipu_idmac_select_buffer(ipu_plane->alpha_ch, !active);
667 ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
668 switch (ipu_plane->dp_flow) {
669 case IPU_DP_FLOW_SYNC_BG:
670 ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
671 DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
672 IPUV3_COLORSPACE_RGB);
674 case IPU_DP_FLOW_SYNC_FG:
675 ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
676 DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
677 IPUV3_COLORSPACE_UNKNOWN);
681 ipu_dmfc_config_wait4eot(ipu_plane->dmfc, ALIGN(drm_rect_width(dst), 8));
683 width = ipu_src_rect_width(new_state);
684 height = drm_rect_height(&new_state->src) >> 16;
685 info = drm_format_info(fb->format->format);
686 ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
687 &burstsize, &num_bursts);
689 ipu_cpmem_zero(ipu_plane->ipu_ch);
690 ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height);
691 ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
692 ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
693 ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
694 ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
695 ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
696 ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
697 ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
699 switch (fb->format->format) {
700 case DRM_FORMAT_YUV420:
701 case DRM_FORMAT_YVU420:
702 case DRM_FORMAT_YUV422:
703 case DRM_FORMAT_YVU422:
704 case DRM_FORMAT_YUV444:
705 case DRM_FORMAT_YVU444:
706 ubo = drm_plane_state_to_ubo(new_state);
707 vbo = drm_plane_state_to_vbo(new_state);
708 if (fb->format->format == DRM_FORMAT_YVU420 ||
709 fb->format->format == DRM_FORMAT_YVU422 ||
710 fb->format->format == DRM_FORMAT_YVU444)
713 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
714 fb->pitches[1], ubo, vbo);
716 dev_dbg(ipu_plane->base.dev->dev,
717 "phy = %lu %lu %lu, x = %d, y = %d", eba, ubo, vbo,
718 new_state->src.x1 >> 16, new_state->src.y1 >> 16);
720 case DRM_FORMAT_NV12:
721 case DRM_FORMAT_NV16:
722 ubo = drm_plane_state_to_ubo(new_state);
724 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
725 fb->pitches[1], ubo, ubo);
727 dev_dbg(ipu_plane->base.dev->dev,
728 "phy = %lu %lu, x = %d, y = %d", eba, ubo,
729 new_state->src.x1 >> 16, new_state->src.y1 >> 16);
731 case DRM_FORMAT_RGB565_A8:
732 case DRM_FORMAT_BGR565_A8:
733 case DRM_FORMAT_RGB888_A8:
734 case DRM_FORMAT_BGR888_A8:
735 case DRM_FORMAT_RGBX8888_A8:
736 case DRM_FORMAT_BGRX8888_A8:
737 alpha_eba = drm_plane_state_to_eba(new_state, 1);
740 dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d",
741 eba, alpha_eba, new_state->src.x1 >> 16,
742 new_state->src.y1 >> 16);
744 ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
746 ipu_cpmem_zero(ipu_plane->alpha_ch);
747 ipu_cpmem_set_resolution(ipu_plane->alpha_ch,
748 ipu_src_rect_width(new_state),
749 drm_rect_height(&new_state->src) >> 16);
750 ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
751 ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
752 ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1);
753 ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]);
754 ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16);
755 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba);
756 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba);
759 dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d",
760 eba, new_state->src.x1 >> 16, new_state->src.y1 >> 16);
763 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
764 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
765 ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
766 ipu_plane_enable(ipu_plane);
769 static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
770 .atomic_check = ipu_plane_atomic_check,
771 .atomic_disable = ipu_plane_atomic_disable,
772 .atomic_update = ipu_plane_atomic_update,
775 bool ipu_plane_atomic_update_pending(struct drm_plane *plane)
777 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
778 struct drm_plane_state *state = plane->state;
779 struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
781 /* disabled crtcs must not block the update */
785 if (ipu_state->use_pre)
786 return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
789 * Pretend no update is pending in the non-PRE/PRG case. For this to
790 * happen, an atomic update would have to be deferred until after the
791 * start of the next frame and simultaneously interrupt latency would
792 * have to be high enough to let the atomic update finish and issue an
793 * event before the previous end of frame interrupt handler can be
798 int ipu_planes_assign_pre(struct drm_device *dev,
799 struct drm_atomic_state *state)
801 struct drm_crtc_state *old_crtc_state, *crtc_state;
802 struct drm_plane_state *plane_state;
803 struct ipu_plane_state *ipu_state;
804 struct ipu_plane *ipu_plane;
805 struct drm_plane *plane;
806 struct drm_crtc *crtc;
807 int available_pres = ipu_prg_max_active_channels();
810 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
811 ret = drm_atomic_add_affected_planes(state, crtc);
817 * We are going over the planes in 2 passes: first we assign PREs to
818 * planes with a tiling modifier, which need the PREs to resolve into
819 * linear. Any failure to assign a PRE there is fatal. In the second
820 * pass we try to assign PREs to linear FBs, to improve memory access
821 * patterns for them. Failure at this point is non-fatal, as we can
822 * scan out linear FBs without a PRE.
824 for_each_new_plane_in_state(state, plane, plane_state, i) {
825 ipu_state = to_ipu_plane_state(plane_state);
826 ipu_plane = to_ipu_plane(plane);
828 if (!plane_state->fb) {
829 ipu_state->use_pre = false;
833 if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||
834 plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)
837 if (!ipu_prg_present(ipu_plane->ipu) || !available_pres)
840 if (!ipu_prg_format_supported(ipu_plane->ipu,
841 plane_state->fb->format->format,
842 plane_state->fb->modifier))
845 ipu_state->use_pre = true;
849 for_each_new_plane_in_state(state, plane, plane_state, i) {
850 ipu_state = to_ipu_plane_state(plane_state);
851 ipu_plane = to_ipu_plane(plane);
853 if (!plane_state->fb) {
854 ipu_state->use_pre = false;
858 if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&
859 plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)
862 /* make sure that modifier is initialized */
863 plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;
865 if (ipu_prg_present(ipu_plane->ipu) && available_pres &&
866 ipu_prg_format_supported(ipu_plane->ipu,
867 plane_state->fb->format->format,
868 plane_state->fb->modifier)) {
869 ipu_state->use_pre = true;
872 ipu_state->use_pre = false;
879 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
880 int dma, int dp, unsigned int possible_crtcs,
881 enum drm_plane_type type)
883 struct ipu_plane *ipu_plane;
884 const uint64_t *modifiers = ipu_format_modifiers;
885 unsigned int zpos = (type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
886 unsigned int format_count;
887 const uint32_t *formats;
890 DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
891 dma, dp, possible_crtcs);
893 if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG) {
894 formats = ipu_plane_all_formats;
895 format_count = ARRAY_SIZE(ipu_plane_all_formats);
897 formats = ipu_plane_rgb_formats;
898 format_count = ARRAY_SIZE(ipu_plane_rgb_formats);
901 if (ipu_prg_present(ipu))
902 modifiers = pre_format_modifiers;
904 ipu_plane = drmm_universal_plane_alloc(dev, struct ipu_plane, base,
905 possible_crtcs, &ipu_plane_funcs,
906 formats, format_count, modifiers,
908 if (IS_ERR(ipu_plane)) {
909 DRM_ERROR("failed to allocate and initialize %s plane\n",
910 zpos ? "overlay" : "primary");
914 ipu_plane->ipu = ipu;
915 ipu_plane->dma = dma;
916 ipu_plane->dp_flow = dp;
918 drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs);
920 if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG)
921 ret = drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0,
924 ret = drm_plane_create_zpos_immutable_property(&ipu_plane->base,
929 ret = drm_plane_create_color_properties(&ipu_plane->base,
930 BIT(DRM_COLOR_YCBCR_BT601) |
931 BIT(DRM_COLOR_YCBCR_BT709),
932 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
933 DRM_COLOR_YCBCR_BT601,
934 DRM_COLOR_YCBCR_LIMITED_RANGE);
938 ret = ipu_plane_get_resources(dev, ipu_plane);
940 DRM_ERROR("failed to get %s plane resources: %pe\n",
941 zpos ? "overlay" : "primary", &ret);