2 * i.MX drm driver - Television Encoder (TVEv2)
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/component.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spinlock.h>
24 #include <linux/videodev2.h>
26 #include <drm/drm_fb_helper.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <video/imx-ipu-v3.h>
32 #define TVE_COM_CONF_REG 0x00
33 #define TVE_TVDAC0_CONT_REG 0x28
34 #define TVE_TVDAC1_CONT_REG 0x2c
35 #define TVE_TVDAC2_CONT_REG 0x30
36 #define TVE_CD_CONT_REG 0x34
37 #define TVE_INT_CONT_REG 0x64
38 #define TVE_STAT_REG 0x68
39 #define TVE_TST_MODE_REG 0x6c
40 #define TVE_MV_CONT_REG 0xdc
42 /* TVE_COM_CONF_REG */
43 #define TVE_SYNC_CH_2_EN BIT(22)
44 #define TVE_SYNC_CH_1_EN BIT(21)
45 #define TVE_SYNC_CH_0_EN BIT(20)
46 #define TVE_TV_OUT_MODE_MASK (0x7 << 12)
47 #define TVE_TV_OUT_DISABLE (0x0 << 12)
48 #define TVE_TV_OUT_CVBS_0 (0x1 << 12)
49 #define TVE_TV_OUT_CVBS_2 (0x2 << 12)
50 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
51 #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
52 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
53 #define TVE_TV_OUT_YPBPR (0x6 << 12)
54 #define TVE_TV_OUT_RGB (0x7 << 12)
55 #define TVE_TV_STAND_MASK (0xf << 8)
56 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
57 #define TVE_P2I_CONV_EN BIT(7)
58 #define TVE_INP_VIDEO_FORM BIT(6)
59 #define TVE_INP_YCBCR_422 (0x0 << 6)
60 #define TVE_INP_YCBCR_444 (0x1 << 6)
61 #define TVE_DATA_SOURCE_MASK (0x3 << 4)
62 #define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
63 #define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
64 #define TVE_DATA_SOURCE_EXT (0x2 << 4)
65 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
66 #define TVE_IPU_CLK_EN_OFS 3
67 #define TVE_IPU_CLK_EN BIT(3)
68 #define TVE_DAC_SAMP_RATE_OFS 1
69 #define TVE_DAC_SAMP_RATE_WIDTH 2
70 #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
71 #define TVE_DAC_FULL_RATE (0x0 << 1)
72 #define TVE_DAC_DIV2_RATE (0x1 << 1)
73 #define TVE_DAC_DIV4_RATE (0x2 << 1)
76 /* TVE_TVDACx_CONT_REG */
77 #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
80 #define TVE_CD_CH_2_SM_EN BIT(22)
81 #define TVE_CD_CH_1_SM_EN BIT(21)
82 #define TVE_CD_CH_0_SM_EN BIT(20)
83 #define TVE_CD_CH_2_LM_EN BIT(18)
84 #define TVE_CD_CH_1_LM_EN BIT(17)
85 #define TVE_CD_CH_0_LM_EN BIT(16)
86 #define TVE_CD_CH_2_REF_LVL BIT(10)
87 #define TVE_CD_CH_1_REF_LVL BIT(9)
88 #define TVE_CD_CH_0_REF_LVL BIT(8)
89 #define TVE_CD_EN BIT(0)
91 /* TVE_INT_CONT_REG */
92 #define TVE_FRAME_END_IEN BIT(13)
93 #define TVE_CD_MON_END_IEN BIT(2)
94 #define TVE_CD_SM_IEN BIT(1)
95 #define TVE_CD_LM_IEN BIT(0)
97 /* TVE_TST_MODE_REG */
98 #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
100 #define con_to_tve(x) container_of(x, struct imx_tve, connector)
101 #define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
109 struct drm_connector connector;
110 struct drm_encoder encoder;
112 spinlock_t lock; /* register lock */
116 struct regmap *regmap;
117 struct regulator *dac_reg;
118 struct i2c_adapter *ddc;
120 struct clk *di_sel_clk;
121 struct clk_hw clk_hw_di;
127 static void tve_lock(void *__tve)
128 __acquires(&tve->lock)
130 struct imx_tve *tve = __tve;
132 spin_lock(&tve->lock);
135 static void tve_unlock(void *__tve)
136 __releases(&tve->lock)
138 struct imx_tve *tve = __tve;
140 spin_unlock(&tve->lock);
143 static void tve_enable(struct imx_tve *tve)
149 clk_prepare_enable(tve->clk);
150 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
151 TVE_IPU_CLK_EN | TVE_EN,
152 TVE_IPU_CLK_EN | TVE_EN);
155 /* clear interrupt status register */
156 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
158 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
159 if (tve->mode == TVE_MODE_VGA)
160 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
162 regmap_write(tve->regmap, TVE_INT_CONT_REG,
168 static void tve_disable(struct imx_tve *tve)
173 tve->enabled = false;
174 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
175 TVE_IPU_CLK_EN | TVE_EN, 0);
176 clk_disable_unprepare(tve->clk);
180 static int tve_setup_tvout(struct imx_tve *tve)
185 static int tve_setup_vga(struct imx_tve *tve)
191 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
192 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
193 TVE_TVDAC_GAIN_MASK, 0x0a);
194 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
195 TVE_TVDAC_GAIN_MASK, 0x0a);
196 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
197 TVE_TVDAC_GAIN_MASK, 0x0a);
199 /* set configuration register */
200 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
201 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
202 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
203 val |= TVE_TV_STAND_HD_1080P30 | 0;
204 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
205 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
206 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
208 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
212 /* set test mode (as documented) */
213 ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
214 TVE_TVDAC_TEST_MODE_MASK, 1);
219 static enum drm_connector_status imx_tve_connector_detect(
220 struct drm_connector *connector, bool force)
222 return connector_status_connected;
225 static int imx_tve_connector_get_modes(struct drm_connector *connector)
227 struct imx_tve *tve = con_to_tve(connector);
234 edid = drm_get_edid(connector, tve->ddc);
236 drm_mode_connector_update_edid_property(connector, edid);
237 ret = drm_add_edid_modes(connector, edid);
244 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
245 struct drm_display_mode *mode)
247 struct imx_tve *tve = con_to_tve(connector);
250 /* pixel clock with 2x oversampling */
251 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
252 if (rate == mode->clock)
255 /* pixel clock without oversampling */
256 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
257 if (rate == mode->clock)
260 dev_warn(tve->dev, "ignoring mode %dx%d\n",
261 mode->hdisplay, mode->vdisplay);
266 static struct drm_encoder *imx_tve_connector_best_encoder(
267 struct drm_connector *connector)
269 struct imx_tve *tve = con_to_tve(connector);
271 return &tve->encoder;
274 static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
276 struct imx_tve *tve = enc_to_tve(encoder);
279 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
280 TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
282 dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
285 static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
286 const struct drm_display_mode *mode,
287 struct drm_display_mode *adjusted_mode)
292 static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
294 struct imx_tve *tve = enc_to_tve(encoder);
300 imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
301 tve->hsync_pin, tve->vsync_pin);
304 imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
309 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
310 struct drm_display_mode *mode,
311 struct drm_display_mode *adjusted_mode)
313 struct imx_tve *tve = enc_to_tve(encoder);
314 unsigned long rounded_rate;
321 * we should try 4k * mode->clock first,
322 * and enable 4x oversampling for lower resolutions
324 rate = 2000UL * mode->clock;
325 clk_set_rate(tve->clk, rate);
326 rounded_rate = clk_get_rate(tve->clk);
327 if (rounded_rate >= rate)
329 clk_set_rate(tve->di_clk, rounded_rate / div);
331 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
333 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
337 if (tve->mode == TVE_MODE_VGA)
340 tve_setup_tvout(tve);
343 static void imx_tve_encoder_commit(struct drm_encoder *encoder)
345 struct imx_tve *tve = enc_to_tve(encoder);
350 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
352 struct imx_tve *tve = enc_to_tve(encoder);
357 static struct drm_connector_funcs imx_tve_connector_funcs = {
358 .dpms = drm_helper_connector_dpms,
359 .fill_modes = drm_helper_probe_single_connector_modes,
360 .detect = imx_tve_connector_detect,
361 .destroy = imx_drm_connector_destroy,
364 static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
365 .get_modes = imx_tve_connector_get_modes,
366 .best_encoder = imx_tve_connector_best_encoder,
367 .mode_valid = imx_tve_connector_mode_valid,
370 static struct drm_encoder_funcs imx_tve_encoder_funcs = {
371 .destroy = imx_drm_encoder_destroy,
374 static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
375 .dpms = imx_tve_encoder_dpms,
376 .mode_fixup = imx_tve_encoder_mode_fixup,
377 .prepare = imx_tve_encoder_prepare,
378 .mode_set = imx_tve_encoder_mode_set,
379 .commit = imx_tve_encoder_commit,
380 .disable = imx_tve_encoder_disable,
383 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
385 struct imx_tve *tve = data;
388 regmap_read(tve->regmap, TVE_STAT_REG, &val);
390 /* clear interrupt status register */
391 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
396 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
397 unsigned long parent_rate)
399 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
403 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
407 switch (val & TVE_DAC_SAMP_RATE_MASK) {
408 case TVE_DAC_DIV4_RATE:
409 return parent_rate / 4;
410 case TVE_DAC_DIV2_RATE:
411 return parent_rate / 2;
412 case TVE_DAC_FULL_RATE:
420 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
421 unsigned long *prate)
433 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
434 unsigned long parent_rate)
436 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
441 div = parent_rate / rate;
443 val = TVE_DAC_DIV4_RATE;
445 val = TVE_DAC_DIV2_RATE;
447 val = TVE_DAC_FULL_RATE;
449 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
450 TVE_DAC_SAMP_RATE_MASK, val);
453 dev_err(tve->dev, "failed to set divider: %d\n", ret);
460 static struct clk_ops clk_tve_di_ops = {
461 .round_rate = clk_tve_di_round_rate,
462 .set_rate = clk_tve_di_set_rate,
463 .recalc_rate = clk_tve_di_recalc_rate,
466 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
468 const char *tve_di_parent[1];
469 struct clk_init_data init = {
471 .ops = &clk_tve_di_ops,
476 tve_di_parent[0] = __clk_get_name(tve->clk);
477 init.parent_names = (const char **)&tve_di_parent;
479 tve->clk_hw_di.init = &init;
480 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
481 if (IS_ERR(tve->di_clk)) {
482 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
483 PTR_ERR(tve->di_clk));
484 return PTR_ERR(tve->di_clk);
490 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
495 encoder_type = tve->mode == TVE_MODE_VGA ?
496 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
498 ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
503 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
504 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
507 drm_connector_helper_add(&tve->connector,
508 &imx_tve_connector_helper_funcs);
509 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
510 DRM_MODE_CONNECTOR_VGA);
512 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
517 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
519 return (reg % 4 == 0) && (reg <= 0xdc);
522 static struct regmap_config tve_regmap_config = {
527 .readable_reg = imx_tve_readable_reg,
530 .unlock = tve_unlock,
532 .max_register = 0xdc,
535 static const char * const imx_tve_modes[] = {
536 [TVE_MODE_TVOUT] = "tvout",
537 [TVE_MODE_VGA] = "vga",
540 static const int of_get_tve_mode(struct device_node *np)
545 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
549 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
550 if (!strcasecmp(bm, imx_tve_modes[i]))
556 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
558 struct platform_device *pdev = to_platform_device(dev);
559 struct drm_device *drm = data;
560 struct device_node *np = dev->of_node;
561 struct device_node *ddc_node;
563 struct resource *res;
569 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
574 spin_lock_init(&tve->lock);
576 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
578 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
579 of_node_put(ddc_node);
582 tve->mode = of_get_tve_mode(np);
583 if (tve->mode != TVE_MODE_VGA) {
584 dev_err(dev, "only VGA mode supported, currently\n");
588 if (tve->mode == TVE_MODE_VGA) {
589 ret = of_property_read_u32(np, "fsl,hsync-pin",
593 dev_err(dev, "failed to get vsync pin\n");
597 ret |= of_property_read_u32(np, "fsl,vsync-pin",
601 dev_err(dev, "failed to get vsync pin\n");
606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
607 base = devm_ioremap_resource(dev, res);
609 return PTR_ERR(base);
611 tve_regmap_config.lock_arg = tve;
612 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
614 if (IS_ERR(tve->regmap)) {
615 dev_err(dev, "failed to init regmap: %ld\n",
616 PTR_ERR(tve->regmap));
617 return PTR_ERR(tve->regmap);
620 irq = platform_get_irq(pdev, 0);
622 dev_err(dev, "failed to get irq\n");
626 ret = devm_request_threaded_irq(dev, irq, NULL,
627 imx_tve_irq_handler, IRQF_ONESHOT,
630 dev_err(dev, "failed to request irq: %d\n", ret);
634 tve->dac_reg = devm_regulator_get(dev, "dac");
635 if (!IS_ERR(tve->dac_reg)) {
636 regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
637 ret = regulator_enable(tve->dac_reg);
642 tve->clk = devm_clk_get(dev, "tve");
643 if (IS_ERR(tve->clk)) {
644 dev_err(dev, "failed to get high speed tve clock: %ld\n",
646 return PTR_ERR(tve->clk);
649 /* this is the IPU DI clock input selector, can be parented to tve_di */
650 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
651 if (IS_ERR(tve->di_sel_clk)) {
652 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
653 PTR_ERR(tve->di_sel_clk));
654 return PTR_ERR(tve->di_sel_clk);
657 ret = tve_clk_init(tve, base);
661 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
663 dev_err(dev, "failed to read configuration register: %d\n",
667 if (val != 0x00100000) {
668 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
672 /* disable cable detection for VGA mode */
673 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
675 ret = imx_tve_register(drm, tve);
679 dev_set_drvdata(dev, tve);
684 static void imx_tve_unbind(struct device *dev, struct device *master,
687 struct imx_tve *tve = dev_get_drvdata(dev);
689 tve->connector.funcs->destroy(&tve->connector);
690 tve->encoder.funcs->destroy(&tve->encoder);
692 if (!IS_ERR(tve->dac_reg))
693 regulator_disable(tve->dac_reg);
696 static const struct component_ops imx_tve_ops = {
697 .bind = imx_tve_bind,
698 .unbind = imx_tve_unbind,
701 static int imx_tve_probe(struct platform_device *pdev)
703 return component_add(&pdev->dev, &imx_tve_ops);
706 static int imx_tve_remove(struct platform_device *pdev)
708 component_del(&pdev->dev, &imx_tve_ops);
712 static const struct of_device_id imx_tve_dt_ids[] = {
713 { .compatible = "fsl,imx53-tve", },
717 static struct platform_driver imx_tve_driver = {
718 .probe = imx_tve_probe,
719 .remove = imx_tve_remove,
721 .of_match_table = imx_tve_dt_ids,
726 module_platform_driver(imx_tve_driver);
728 MODULE_DESCRIPTION("i.MX Television Encoder driver");
729 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
730 MODULE_LICENSE("GPL");
731 MODULE_ALIAS("platform:imx-tve");