drivers/gpu/drm/i915/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/slab.h>
  28
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_crtc.h>
  31 #include <drm/drm_edid.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <drm/i915_drm.h>
  34
  35 #include "i915_drv.h"
  36 #include "intel_connector.h"
  37 #include "intel_drv.h"
  38 #include "intel_dsi.h"
  39 #include "intel_panel.h"
  40
  41 /* return pixels in terms of txbyteclkhs */
  42 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  43                        u16 burst_mode_ratio)
  44 {
  45         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  46                                          8 * 100), lane_count);
  47 }
  48
  49 /* return pixels equvalent to txbyteclkhs */
  50 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  51                         u16 burst_mode_ratio)
  52 {
  53         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  54                                                 (bpp * burst_mode_ratio));
  55 }
  56
  57 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  58 {
  59         /* It just so happens the VBT matches register contents. */
  60         switch (fmt) {
  61         case VID_MODE_FORMAT_RGB888:
  62                 return MIPI_DSI_FMT_RGB888;
  63         case VID_MODE_FORMAT_RGB666:
  64                 return MIPI_DSI_FMT_RGB666;
  65         case VID_MODE_FORMAT_RGB666_PACKED:
  66                 return MIPI_DSI_FMT_RGB666_PACKED;
  67         case VID_MODE_FORMAT_RGB565:
  68                 return MIPI_DSI_FMT_RGB565;
  69         default:
  70                 MISSING_CASE(fmt);
  71                 return MIPI_DSI_FMT_RGB666;
  72         }
  73 }
  74
  75 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  76 {
  77         struct drm_encoder *encoder = &intel_dsi->base.base;
  78         struct drm_device *dev = encoder->dev;
  79         struct drm_i915_private *dev_priv = to_i915(dev);
  80         u32 mask;
  81
  82         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  83                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  84
  85         if (intel_wait_for_register(&dev_priv->uncore,
  86                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  87                                     100))
  88                 DRM_ERROR("DPI FIFOs are not empty\n");
  89 }
  90
  91 static void write_data(struct drm_i915_private *dev_priv,
  92                        i915_reg_t reg,
  93                        const u8 *data, u32 len)
  94 {
  95         u32 i, j;
  96
  97         for (i = 0; i < len; i += 4) {
  98                 u32 val = 0;
  99
 100                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 101                         val |= *data++ << 8 * j;
 102
 103                 I915_WRITE(reg, val);
 104         }
 105 }
 106
 107 static void read_data(struct drm_i915_private *dev_priv,
 108                       i915_reg_t reg,
 109                       u8 *data, u32 len)
 110 {
 111         u32 i, j;
 112
 113         for (i = 0; i < len; i += 4) {
 114                 u32 val = I915_READ(reg);
 115
 116                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 117                         *data++ = val >> 8 * j;
 118         }
 119 }
 120
 121 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 122                                        const struct mipi_dsi_msg *msg)
 123 {
 124         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 125         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 126         struct drm_i915_private *dev_priv = to_i915(dev);
 127         enum port port = intel_dsi_host->port;
 128         struct mipi_dsi_packet packet;
 129         ssize_t ret;
 130         const u8 *header, *data;
 131         i915_reg_t data_reg, ctrl_reg;
 132         u32 data_mask, ctrl_mask;
 133
 134         ret = mipi_dsi_create_packet(&packet, msg);
 135         if (ret < 0)
 136                 return ret;
 137
 138         header = packet.header;
 139         data = packet.payload;
 140
 141         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 142                 data_reg = MIPI_LP_GEN_DATA(port);
 143                 data_mask = LP_DATA_FIFO_FULL;
 144                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 145                 ctrl_mask = LP_CTRL_FIFO_FULL;
 146         } else {
 147                 data_reg = MIPI_HS_GEN_DATA(port);
 148                 data_mask = HS_DATA_FIFO_FULL;
 149                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 150                 ctrl_mask = HS_CTRL_FIFO_FULL;
 151         }
 152
 153         /* note: this is never true for reads */
 154         if (packet.payload_length) {
 155                 if (intel_wait_for_register(&dev_priv->uncore,
 156                                             MIPI_GEN_FIFO_STAT(port),
 157                                             data_mask, 0,
 158                                             50))
 159                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 160
 161                 write_data(dev_priv, data_reg, packet.payload,
 162                            packet.payload_length);
 163         }
 164
 165         if (msg->rx_len) {
 166                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 167         }
 168
 169         if (intel_wait_for_register(&dev_priv->uncore,
 170                                     MIPI_GEN_FIFO_STAT(port),
 171                                     ctrl_mask, 0,
 172                                     50)) {
 173                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 174         }
 175
 176         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 177
 178         /* ->rx_len is set only for reads */
 179         if (msg->rx_len) {
 180                 data_mask = GEN_READ_DATA_AVAIL;
 181                 if (intel_wait_for_register(&dev_priv->uncore,
 182                                             MIPI_INTR_STAT(port),
 183                                             data_mask, data_mask,
 184                                             50))
 185                         DRM_ERROR("Timeout waiting for read data.\n");
 186
 187                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 188         }
 189
 190         /* XXX: fix for reads and writes */
 191         return 4 + packet.payload_length;
 192 }
 193
 194 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 195                                  struct mipi_dsi_device *dsi)
 196 {
 197         return 0;
 198 }
 199
 200 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 201                                  struct mipi_dsi_device *dsi)
 202 {
 203         return 0;
 204 }
 205
 206 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 207         .attach = intel_dsi_host_attach,
 208         .detach = intel_dsi_host_detach,
 209         .transfer = intel_dsi_host_transfer,
 210 };
 211
 212 /*
 213  * send a video mode command
 214  *
 215  * XXX: commands with data in MIPI_DPI_DATA?
 216  */
 217 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 218                         enum port port)
 219 {
 220         struct drm_encoder *encoder = &intel_dsi->base.base;
 221         struct drm_device *dev = encoder->dev;
 222         struct drm_i915_private *dev_priv = to_i915(dev);
 223         u32 mask;
 224
 225         /* XXX: pipe, hs */
 226         if (hs)
 227                 cmd &= ~DPI_LP_MODE;
 228         else
 229                 cmd |= DPI_LP_MODE;
 230
 231         /* clear bit */
 232         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 233
 234         /* XXX: old code skips write if control unchanged */
 235         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 236                 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
 237
 238         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 239
 240         mask = SPL_PKT_SENT_INTERRUPT;
 241         if (intel_wait_for_register(&dev_priv->uncore,
 242                                     MIPI_INTR_STAT(port), mask, mask,
 243                                     100))
 244                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 245
 246         return 0;
 247 }
 248
 249 static void band_gap_reset(struct drm_i915_private *dev_priv)
 250 {
 251         mutex_lock(&dev_priv->sb_lock);
 252
 253         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 254         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 255         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 256         udelay(150);
 257         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 258         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 259
 260         mutex_unlock(&dev_priv->sb_lock);
 261 }
 262
 263 static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
 264 {
 265         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 266         u32 tmp;
 267
 268         tmp = I915_READ(PIPEMISC(crtc->pipe));
 269
 270         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
 271         case PIPEMISC_DITHER_6_BPC:
 272                 return 18;
 273         case PIPEMISC_DITHER_8_BPC:
 274                 return 24;
 275         case PIPEMISC_DITHER_10_BPC:
 276                 return 30;
 277         case PIPEMISC_DITHER_12_BPC:
 278                 return 36;
 279         default:
 280                 MISSING_CASE(tmp);
 281                 return 0;
 282         }
 283 }
 284
 285 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 286                                     struct intel_crtc_state *pipe_config,
 287                                     struct drm_connector_state *conn_state)
 288 {
 289         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 290         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 291                                                    base);
 292         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 293         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 294         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 295         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 296         int ret;
 297
 298         DRM_DEBUG_KMS("\n");
 299         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 300
 301         if (fixed_mode) {
 302                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 303
 304                 if (HAS_GMCH(dev_priv))
 305                         intel_gmch_panel_fitting(crtc, pipe_config,
 306                                                  conn_state->scaling_mode);
 307                 else
 308                         intel_pch_panel_fitting(crtc, pipe_config,
 309                                                 conn_state->scaling_mode);
 310         }
 311
 312         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 313                 return -EINVAL;
 314
 315         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 316         adjusted_mode->flags = 0;
 317
 318         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 319                 pipe_config->pipe_bpp = 24;
 320         else
 321                 pipe_config->pipe_bpp = 18;
 322
 323         if (IS_GEN9_LP(dev_priv)) {
 324                 /* Enable Frame time stamp based scanline reporting */
 325                 adjusted_mode->private_flags |=
 326                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 327
 328                 /* Dual link goes to DSI transcoder A. */
 329                 if (intel_dsi->ports == BIT(PORT_C))
 330                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 331                 else
 332                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 333
 334                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 335                 if (ret)
 336                         return -EINVAL;
 337         } else {
 338                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 339                 if (ret)
 340                         return -EINVAL;
 341         }
 342
 343         pipe_config->clock_set = true;
 344
 345         return 0;
 346 }
 347
 348 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 349 {
 350         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 351         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 352         enum port port;
 353         u32 tmp;
 354         bool cold_boot = false;
 355
 356         /* Set the MIPI mode
 357          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 358          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 359          */
 360         for_each_dsi_port(port, intel_dsi->ports) {
 361                 tmp = I915_READ(MIPI_CTRL(port));
 362                 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
 363         }
 364
 365         /* Put the IO into reset */
 366         tmp = I915_READ(MIPI_CTRL(PORT_A));
 367         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 368         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 369
 370         /* Program LP Wake */
 371         for_each_dsi_port(port, intel_dsi->ports) {
 372                 tmp = I915_READ(MIPI_CTRL(port));
 373                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 374                         tmp &= ~GLK_LP_WAKE;
 375                 else
 376                         tmp |= GLK_LP_WAKE;
 377                 I915_WRITE(MIPI_CTRL(port), tmp);
 378         }
 379
 380         /* Wait for Pwr ACK */
 381         for_each_dsi_port(port, intel_dsi->ports) {
 382                 if (intel_wait_for_register(&dev_priv->uncore,
 383                                             MIPI_CTRL(port),
 384                                             GLK_MIPIIO_PORT_POWERED,
 385                                             GLK_MIPIIO_PORT_POWERED,
 386                                             20))
 387                         DRM_ERROR("MIPIO port is powergated\n");
 388         }
 389
 390         /* Check for cold boot scenario */
 391         for_each_dsi_port(port, intel_dsi->ports) {
 392                 cold_boot |=
 393                         !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY);
 394         }
 395
 396         return cold_boot;
 397 }
 398
 399 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 400 {
 401         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 402         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 403         enum port port;
 404         u32 val;
 405
 406         /* Wait for MIPI PHY status bit to set */
 407         for_each_dsi_port(port, intel_dsi->ports) {
 408                 if (intel_wait_for_register(&dev_priv->uncore,
 409                                             MIPI_CTRL(port),
 410                                             GLK_PHY_STATUS_PORT_READY,
 411                                             GLK_PHY_STATUS_PORT_READY,
 412                                             20))
 413                         DRM_ERROR("PHY is not ON\n");
 414         }
 415
 416         /* Get IO out of reset */
 417         val = I915_READ(MIPI_CTRL(PORT_A));
 418         I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
 419
 420         /* Get IO out of Low power state*/
 421         for_each_dsi_port(port, intel_dsi->ports) {
 422                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 423                         val = I915_READ(MIPI_DEVICE_READY(port));
 424                         val &= ~ULPS_STATE_MASK;
 425                         val |= DEVICE_READY;
 426                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 427                         usleep_range(10, 15);
 428                 } else {
 429                         /* Enter ULPS */
 430                         val = I915_READ(MIPI_DEVICE_READY(port));
 431                         val &= ~ULPS_STATE_MASK;
 432                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 433                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 434
 435                         /* Wait for ULPS active */
 436                         if (intel_wait_for_register(&dev_priv->uncore,
 437                                                     MIPI_CTRL(port),
 438                                                     GLK_ULPS_NOT_ACTIVE,
 439                                                     0,
 440                                                     20))
 441                                 DRM_ERROR("ULPS not active\n");
 442
 443                         /* Exit ULPS */
 444                         val = I915_READ(MIPI_DEVICE_READY(port));
 445                         val &= ~ULPS_STATE_MASK;
 446                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 447                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 448
 449                         /* Enter Normal Mode */
 450                         val = I915_READ(MIPI_DEVICE_READY(port));
 451                         val &= ~ULPS_STATE_MASK;
 452                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 453                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 454
 455                         val = I915_READ(MIPI_CTRL(port));
 456                         val &= ~GLK_LP_WAKE;
 457                         I915_WRITE(MIPI_CTRL(port), val);
 458                 }
 459         }
 460
 461         /* Wait for Stop state */
 462         for_each_dsi_port(port, intel_dsi->ports) {
 463                 if (intel_wait_for_register(&dev_priv->uncore,
 464                                             MIPI_CTRL(port),
 465                                             GLK_DATA_LANE_STOP_STATE,
 466                                             GLK_DATA_LANE_STOP_STATE,
 467                                             20))
 468                         DRM_ERROR("Date lane not in STOP state\n");
 469         }
 470
 471         /* Wait for AFE LATCH */
 472         for_each_dsi_port(port, intel_dsi->ports) {
 473                 if (intel_wait_for_register(&dev_priv->uncore,
 474                                             BXT_MIPI_PORT_CTRL(port),
 475                                             AFE_LATCHOUT,
 476                                             AFE_LATCHOUT,
 477                                             20))
 478                         DRM_ERROR("D-PHY not entering LP-11 state\n");
 479         }
 480 }
 481
 482 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 483 {
 484         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 485         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 486         enum port port;
 487         u32 val;
 488
 489         DRM_DEBUG_KMS("\n");
 490
 491         /* Enable MIPI PHY transparent latch */
 492         for_each_dsi_port(port, intel_dsi->ports) {
 493                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 494                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 495                 usleep_range(2000, 2500);
 496         }
 497
 498         /* Clear ULPS and set device ready */
 499         for_each_dsi_port(port, intel_dsi->ports) {
 500                 val = I915_READ(MIPI_DEVICE_READY(port));
 501                 val &= ~ULPS_STATE_MASK;
 502                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 503                 usleep_range(2000, 2500);
 504                 val |= DEVICE_READY;
 505                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 506         }
 507 }
 508
 509 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 510 {
 511         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 512         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 513         enum port port;
 514         u32 val;
 515
 516         DRM_DEBUG_KMS("\n");
 517
 518         mutex_lock(&dev_priv->sb_lock);
 519         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 520          * needed everytime after power gate */
 521         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 522         mutex_unlock(&dev_priv->sb_lock);
 523
 524         /* bandgap reset is needed after everytime we do power gate */
 525         band_gap_reset(dev_priv);
 526
 527         for_each_dsi_port(port, intel_dsi->ports) {
 528
 529                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 530                 usleep_range(2500, 3000);
 531
 532                 /* Enable MIPI PHY transparent latch
 533                  * Common bit for both MIPI Port A & MIPI Port C
 534                  * No similar bit in MIPI Port C reg
 535                  */
 536                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 537                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 538                 usleep_range(1000, 1500);
 539
 540                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 541                 usleep_range(2500, 3000);
 542
 543                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 544                 usleep_range(2500, 3000);
 545         }
 546 }
 547
 548 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 549 {
 550         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 551
 552         if (IS_GEMINILAKE(dev_priv))
 553                 glk_dsi_device_ready(encoder);
 554         else if (IS_GEN9_LP(dev_priv))
 555                 bxt_dsi_device_ready(encoder);
 556         else
 557                 vlv_dsi_device_ready(encoder);
 558 }
 559
 560 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 561 {
 562         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 563         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 564         enum port port;
 565         u32 val;
 566
 567         /* Enter ULPS */
 568         for_each_dsi_port(port, intel_dsi->ports) {
 569                 val = I915_READ(MIPI_DEVICE_READY(port));
 570                 val &= ~ULPS_STATE_MASK;
 571                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 572                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 573         }
 574
 575         /* Wait for MIPI PHY status bit to unset */
 576         for_each_dsi_port(port, intel_dsi->ports) {
 577                 if (intel_wait_for_register(&dev_priv->uncore,
 578                                             MIPI_CTRL(port),
 579                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 580                         DRM_ERROR("PHY is not turning OFF\n");
 581         }
 582
 583         /* Wait for Pwr ACK bit to unset */
 584         for_each_dsi_port(port, intel_dsi->ports) {
 585                 if (intel_wait_for_register(&dev_priv->uncore,
 586                                             MIPI_CTRL(port),
 587                                             GLK_MIPIIO_PORT_POWERED, 0, 20))
 588                         DRM_ERROR("MIPI IO Port is not powergated\n");
 589         }
 590 }
 591
 592 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 593 {
 594         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 595         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 596         enum port port;
 597         u32 tmp;
 598
 599         /* Put the IO into reset */
 600         tmp = I915_READ(MIPI_CTRL(PORT_A));
 601         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 602         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 603
 604         /* Wait for MIPI PHY status bit to unset */
 605         for_each_dsi_port(port, intel_dsi->ports) {
 606                 if (intel_wait_for_register(&dev_priv->uncore,
 607                                             MIPI_CTRL(port),
 608                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 609                         DRM_ERROR("PHY is not turning OFF\n");
 610         }
 611
 612         /* Clear MIPI mode */
 613         for_each_dsi_port(port, intel_dsi->ports) {
 614                 tmp = I915_READ(MIPI_CTRL(port));
 615                 tmp &= ~GLK_MIPIIO_ENABLE;
 616                 I915_WRITE(MIPI_CTRL(port), tmp);
 617         }
 618 }
 619
 620 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 621 {
 622         glk_dsi_enter_low_power_mode(encoder);
 623         glk_dsi_disable_mipi_io(encoder);
 624 }
 625
 626 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 627 {
 628         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 629         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 630         enum port port;
 631
 632         DRM_DEBUG_KMS("\n");
 633         for_each_dsi_port(port, intel_dsi->ports) {
 634                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 635                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 636                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 637                 u32 val;
 638
 639                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 640                                                         ULPS_STATE_ENTER);
 641                 usleep_range(2000, 2500);
 642
 643                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 644                                                         ULPS_STATE_EXIT);
 645                 usleep_range(2000, 2500);
 646
 647                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 648                                                         ULPS_STATE_ENTER);
 649                 usleep_range(2000, 2500);
 650
 651                 /*
 652                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 653                  * Port A only. MIPI Port C has no similar bit for checking.
 654                  */
 655                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 656                     intel_wait_for_register(&dev_priv->uncore,
 657                                             port_ctrl, AFE_LATCHOUT, 0,
 658                                             30))
 659                         DRM_ERROR("DSI LP not going Low\n");
 660
 661                 /* Disable MIPI PHY transparent latch */
 662                 val = I915_READ(port_ctrl);
 663                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 664                 usleep_range(1000, 1500);
 665
 666                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 667                 usleep_range(2000, 2500);
 668         }
 669 }
 670
 671 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 672                                   const struct intel_crtc_state *crtc_state)
 673 {
 674         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 675         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 676         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 677         enum port port;
 678
 679         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 680                 u32 temp;
 681                 if (IS_GEN9_LP(dev_priv)) {
 682                         for_each_dsi_port(port, intel_dsi->ports) {
 683                                 temp = I915_READ(MIPI_CTRL(port));
 684                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 685                                         intel_dsi->pixel_overlap <<
 686                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 687                                 I915_WRITE(MIPI_CTRL(port), temp);
 688                         }
 689                 } else {
 690                         temp = I915_READ(VLV_CHICKEN_3);
 691                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 692                                         intel_dsi->pixel_overlap <<
 693                                         PIXEL_OVERLAP_CNT_SHIFT;
 694                         I915_WRITE(VLV_CHICKEN_3, temp);
 695                 }
 696         }
 697
 698         for_each_dsi_port(port, intel_dsi->ports) {
 699                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 700                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 701                 u32 temp;
 702
 703                 temp = I915_READ(port_ctrl);
 704
 705                 temp &= ~LANE_CONFIGURATION_MASK;
 706                 temp &= ~DUAL_LINK_MODE_MASK;
 707
 708                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 709                         temp |= (intel_dsi->dual_link - 1)
 710                                                 << DUAL_LINK_MODE_SHIFT;
 711                         if (IS_BROXTON(dev_priv))
 712                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 713                         else
 714                                 temp |= crtc->pipe ?
 715                                         LANE_CONFIGURATION_DUAL_LINK_B :
 716                                         LANE_CONFIGURATION_DUAL_LINK_A;
 717                 }
 718
 719                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 720                         temp |= DITHERING_ENABLE;
 721
 722                 /* assert ip_tg_enable signal */
 723                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 724                 POSTING_READ(port_ctrl);
 725         }
 726 }
 727
 728 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 729 {
 730         struct drm_device *dev = encoder->base.dev;
 731         struct drm_i915_private *dev_priv = to_i915(dev);
 732         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 733         enum port port;
 734
 735         for_each_dsi_port(port, intel_dsi->ports) {
 736                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 737                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 738                 u32 temp;
 739
 740                 /* de-assert ip_tg_enable signal */
 741                 temp = I915_READ(port_ctrl);
 742                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 743                 POSTING_READ(port_ctrl);
 744         }
 745 }
 746
 747 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 748                               const struct intel_crtc_state *pipe_config);
 749 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 750
 751 /*
 752  * Panel enable/disable sequences from the VBT spec.
 753  *
 754  * Note the spec has AssertReset / DeassertReset swapped from their
 755  * usual naming. We use the normal names to avoid confusion (so below
 756  * they are swapped compared to the spec).
 757  *
 758  * Steps starting with MIPI refer to VBT sequences, note that for v2
 759  * VBTs several steps which have a VBT in v2 are expected to be handled
 760  * directly by the driver, by directly driving gpios for example.
 761  *
 762  * v2 video mode seq         v3 video mode seq         command mode seq
 763  * - power on                - MIPIPanelPowerOn        - power on
 764  * - wait t1+t2                                        - wait t1+t2
 765  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 766  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 767  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 768  *                                                     - MIPITearOn
 769  *                                                     - MIPIDisplayOn
 770  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 771  * - MIPIDisplayOn           - MIPIDisplayOn
 772  * - wait t5                                           - wait t5
 773  * - backlight on            - MIPIBacklightOn         - backlight on
 774  * ...                       ...                       ... issue mem cmds ...
 775  * - backlight off           - MIPIBacklightOff        - backlight off
 776  * - wait t6                                           - wait t6
 777  * - MIPIDisplayOff
 778  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 779  *                                                     - MIPITearOff
 780  *                           - MIPIDisplayOff          - MIPIDisplayOff
 781  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 782  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 783  * - wait t3                                           - wait t3
 784  * - power off               - MIPIPanelPowerOff       - power off
 785  * - wait t4                                           - wait t4
 786  */
 787
 788 /*
 789  * DSI port enable has to be done before pipe and plane enable, so we do it in
 790  * the pre_enable hook instead of the enable hook.
 791  */
 792 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 793                                  const struct intel_crtc_state *pipe_config,
 794                                  const struct drm_connector_state *conn_state)
 795 {
 796         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 797         struct drm_crtc *crtc = pipe_config->base.crtc;
 798         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 800         int pipe = intel_crtc->pipe;
 801         enum port port;
 802         u32 val;
 803         bool glk_cold_boot = false;
 804
 805         DRM_DEBUG_KMS("\n");
 806
 807         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 808
 809         /*
 810          * The BIOS may leave the PLL in a wonky state where it doesn't
 811          * lock. It needs to be fully powered down to fix it.
 812          */
 813         if (IS_GEN9_LP(dev_priv)) {
 814                 bxt_dsi_pll_disable(encoder);
 815                 bxt_dsi_pll_enable(encoder, pipe_config);
 816         } else {
 817                 vlv_dsi_pll_disable(encoder);
 818                 vlv_dsi_pll_enable(encoder, pipe_config);
 819         }
 820
 821         if (IS_BROXTON(dev_priv)) {
 822                 /* Add MIPI IO reset programming for modeset */
 823                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 824                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 825                                         val | MIPIO_RST_CTRL);
 826
 827                 /* Power up DSI regulator */
 828                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 829                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 830         }
 831
 832         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 833                 u32 val;
 834
 835                 /* Disable DPOunit clock gating, can stall pipe */
 836                 val = I915_READ(DSPCLK_GATE_D);
 837                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 838                 I915_WRITE(DSPCLK_GATE_D, val);
 839         }
 840
 841         if (!IS_GEMINILAKE(dev_priv))
 842                 intel_dsi_prepare(encoder, pipe_config);
 843
 844         /* Power on, try both CRC pmic gpio and VBT */
 845         if (intel_dsi->gpio_panel)
 846                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 847         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 848         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 849
 850         /* Deassert reset */
 851         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 852
 853         if (IS_GEMINILAKE(dev_priv)) {
 854                 glk_cold_boot = glk_dsi_enable_io(encoder);
 855
 856                 /* Prepare port in cold boot(s3/s4) scenario */
 857                 if (glk_cold_boot)
 858                         intel_dsi_prepare(encoder, pipe_config);
 859         }
 860
 861         /* Put device in ready state (LP-11) */
 862         intel_dsi_device_ready(encoder);
 863
 864         /* Prepare port in normal boot scenario */
 865         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 866                 intel_dsi_prepare(encoder, pipe_config);
 867
 868         /* Send initialization commands in LP mode */
 869         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 870
 871         /* Enable port in pre-enable phase itself because as per hw team
 872          * recommendation, port should be enabled befor plane & pipe */
 873         if (is_cmd_mode(intel_dsi)) {
 874                 for_each_dsi_port(port, intel_dsi->ports)
 875                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 876                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 877                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 878         } else {
 879                 msleep(20); /* XXX */
 880                 for_each_dsi_port(port, intel_dsi->ports)
 881                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 882                 intel_dsi_msleep(intel_dsi, 100);
 883
 884                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 885
 886                 intel_dsi_port_enable(encoder, pipe_config);
 887         }
 888
 889         intel_panel_enable_backlight(pipe_config, conn_state);
 890         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 891 }
 892
 893 /*
 894  * DSI port disable has to be done after pipe and plane disable, so we do it in
 895  * the post_disable hook.
 896  */
 897 static void intel_dsi_disable(struct intel_encoder *encoder,
 898                               const struct intel_crtc_state *old_crtc_state,
 899                               const struct drm_connector_state *old_conn_state)
 900 {
 901         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 902         enum port port;
 903
 904         DRM_DEBUG_KMS("\n");
 905
 906         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 907         intel_panel_disable_backlight(old_conn_state);
 908
 909         /*
 910          * According to the spec we should send SHUTDOWN before
 911          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 912          * has shown that the v3 sequence works for v2 VBTs too
 913          */
 914         if (is_vid_mode(intel_dsi)) {
 915                 /* Send Shutdown command to the panel in LP mode */
 916                 for_each_dsi_port(port, intel_dsi->ports)
 917                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 918                 msleep(10);
 919         }
 920 }
 921
 922 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 923 {
 924         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 925
 926         if (IS_GEMINILAKE(dev_priv))
 927                 glk_dsi_clear_device_ready(encoder);
 928         else
 929                 vlv_dsi_clear_device_ready(encoder);
 930 }
 931
 932 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 933                                    const struct intel_crtc_state *pipe_config,
 934                                    const struct drm_connector_state *conn_state)
 935 {
 936         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 937         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 938         enum port port;
 939         u32 val;
 940
 941         DRM_DEBUG_KMS("\n");
 942
 943         if (is_vid_mode(intel_dsi)) {
 944                 for_each_dsi_port(port, intel_dsi->ports)
 945                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 946
 947                 intel_dsi_port_disable(encoder);
 948                 usleep_range(2000, 5000);
 949         }
 950
 951         intel_dsi_unprepare(encoder);
 952
 953         /*
 954          * if disable packets are sent before sending shutdown packet then in
 955          * some next enable sequence send turn on packet error is observed
 956          */
 957         if (is_cmd_mode(intel_dsi))
 958                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 959         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 960
 961         /* Transition to LP-00 */
 962         intel_dsi_clear_device_ready(encoder);
 963
 964         if (IS_BROXTON(dev_priv)) {
 965                 /* Power down DSI regulator to save power */
 966                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 967                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
 968
 969                 /* Add MIPI IO reset programming for modeset */
 970                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 971                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 972                                 val & ~MIPIO_RST_CTRL);
 973         }
 974
 975         if (IS_GEN9_LP(dev_priv)) {
 976                 bxt_dsi_pll_disable(encoder);
 977         } else {
 978                 u32 val;
 979
 980                 vlv_dsi_pll_disable(encoder);
 981
 982                 val = I915_READ(DSPCLK_GATE_D);
 983                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 984                 I915_WRITE(DSPCLK_GATE_D, val);
 985         }
 986
 987         /* Assert reset */
 988         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 989
 990         /* Power off, try both CRC pmic gpio and VBT */
 991         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
 992         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 993         if (intel_dsi->gpio_panel)
 994                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 995
 996         /*
 997          * FIXME As we do with eDP, just make a note of the time here
 998          * and perform the wait before the next panel power on.
 999          */
1000         intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
1001 }
1002
1003 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1004                                    enum pipe *pipe)
1005 {
1006         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1007         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1008         intel_wakeref_t wakeref;
1009         enum port port;
1010         bool active = false;
1011
1012         DRM_DEBUG_KMS("\n");
1013
1014         wakeref = intel_display_power_get_if_enabled(dev_priv,
1015                                                      encoder->power_domain);
1016         if (!wakeref)
1017                 return false;
1018
1019         /*
1020          * On Broxton the PLL needs to be enabled with a valid divider
1021          * configuration, otherwise accessing DSI registers will hang the
1022          * machine. See BSpec North Display Engine registers/MIPI[BXT].
1023          */
1024         if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
1025                 goto out_put_power;
1026
1027         /* XXX: this only works for one DSI output */
1028         for_each_dsi_port(port, intel_dsi->ports) {
1029                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
1030                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1031                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
1032
1033                 /*
1034                  * Due to some hardware limitations on VLV/CHV, the DPI enable
1035                  * bit in port C control register does not get set. As a
1036                  * workaround, check pipe B conf instead.
1037                  */
1038                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1039                     port == PORT_C)
1040                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1041
1042                 /* Try command mode if video mode not enabled */
1043                 if (!enabled) {
1044                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1045                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1046                 }
1047
1048                 if (!enabled)
1049                         continue;
1050
1051                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1052                         continue;
1053
1054                 if (IS_GEN9_LP(dev_priv)) {
1055                         u32 tmp = I915_READ(MIPI_CTRL(port));
1056                         tmp &= BXT_PIPE_SELECT_MASK;
1057                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1058
1059                         if (WARN_ON(tmp > PIPE_C))
1060                                 continue;
1061
1062                         *pipe = tmp;
1063                 } else {
1064                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1065                 }
1066
1067                 active = true;
1068                 break;
1069         }
1070
1071 out_put_power:
1072         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1073
1074         return active;
1075 }
1076
1077 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1078                                     struct intel_crtc_state *pipe_config)
1079 {
1080         struct drm_device *dev = encoder->base.dev;
1081         struct drm_i915_private *dev_priv = to_i915(dev);
1082         struct drm_display_mode *adjusted_mode =
1083                                         &pipe_config->base.adjusted_mode;
1084         struct drm_display_mode *adjusted_mode_sw;
1085         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1086         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1087         unsigned int lane_count = intel_dsi->lane_count;
1088         unsigned int bpp, fmt;
1089         enum port port;
1090         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1091         u16 hfp_sw, hsync_sw, hbp_sw;
1092         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1093                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1094
1095         /* FIXME: hw readout should not depend on SW state */
1096         adjusted_mode_sw = &crtc->config->base.adjusted_mode;
1097
1098         /*
1099          * Atleast one port is active as encoder->get_config called only if
1100          * encoder->get_hw_state() returns true.
1101          */
1102         for_each_dsi_port(port, intel_dsi->ports) {
1103                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1104                         break;
1105         }
1106
1107         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1108         bpp = mipi_dsi_pixel_format_to_bpp(
1109                         pixel_format_from_register_bits(fmt));
1110
1111         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1112
1113         /* Enable Frame time stamo based scanline reporting */
1114         adjusted_mode->private_flags |=
1115                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1116
1117         /* In terms of pixels */
1118         adjusted_mode->crtc_hdisplay =
1119                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1120         adjusted_mode->crtc_vdisplay =
1121                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1122         adjusted_mode->crtc_vtotal =
1123                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1124
1125         hactive = adjusted_mode->crtc_hdisplay;
1126         hfp = I915_READ(MIPI_HFP_COUNT(port));
1127
1128         /*
1129          * Meaningful for video mode non-burst sync pulse mode only,
1130          * can be zero for non-burst sync events and burst modes
1131          */
1132         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1133         hbp = I915_READ(MIPI_HBP_COUNT(port));
1134
1135         /* harizontal values are in terms of high speed byte clock */
1136         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1137                                                 intel_dsi->burst_mode_ratio);
1138         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1139                                                 intel_dsi->burst_mode_ratio);
1140         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1141                                                 intel_dsi->burst_mode_ratio);
1142
1143         if (intel_dsi->dual_link) {
1144                 hfp *= 2;
1145                 hsync *= 2;
1146                 hbp *= 2;
1147         }
1148
1149         /* vertical values are in terms of lines */
1150         vfp = I915_READ(MIPI_VFP_COUNT(port));
1151         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1152         vbp = I915_READ(MIPI_VBP_COUNT(port));
1153
1154         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1155         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1156         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1157         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1158         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1159
1160         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1161         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1162         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1163         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1164
1165         /*
1166          * In BXT DSI there is no regs programmed with few horizontal timings
1167          * in Pixels but txbyteclkhs.. So retrieval process adds some
1168          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1169          * Actually here for the given adjusted_mode, we are calculating the
1170          * value programmed to the port and then back to the horizontal timing
1171          * param in pixels. This is the expected value, including roundup errors
1172          * And if that is same as retrieved value from port, then
1173          * (HW state) adjusted_mode's horizontal timings are corrected to
1174          * match with SW state to nullify the errors.
1175          */
1176         /* Calculating the value programmed to the Port register */
1177         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1178                                         adjusted_mode_sw->crtc_hdisplay;
1179         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1180                                         adjusted_mode_sw->crtc_hsync_start;
1181         hbp_sw = adjusted_mode_sw->crtc_htotal -
1182                                         adjusted_mode_sw->crtc_hsync_end;
1183
1184         if (intel_dsi->dual_link) {
1185                 hfp_sw /= 2;
1186                 hsync_sw /= 2;
1187                 hbp_sw /= 2;
1188         }
1189
1190         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1191                                                 intel_dsi->burst_mode_ratio);
1192         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1193                             intel_dsi->burst_mode_ratio);
1194         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1195                                                 intel_dsi->burst_mode_ratio);
1196
1197         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1198         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1199                                                 intel_dsi->burst_mode_ratio);
1200         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1201                                                 intel_dsi->burst_mode_ratio);
1202         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1203                                                 intel_dsi->burst_mode_ratio);
1204
1205         if (intel_dsi->dual_link) {
1206                 hfp_sw *= 2;
1207                 hsync_sw *= 2;
1208                 hbp_sw *= 2;
1209         }
1210
1211         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1212                                                         hsync_sw + hbp_sw;
1213         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1214         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1215         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1216         crtc_hblank_end_sw = crtc_htotal_sw;
1217
1218         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1219                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1220
1221         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1222                 adjusted_mode->crtc_hsync_start =
1223                                         adjusted_mode_sw->crtc_hsync_start;
1224
1225         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1226                 adjusted_mode->crtc_hsync_end =
1227                                         adjusted_mode_sw->crtc_hsync_end;
1228
1229         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1230                 adjusted_mode->crtc_hblank_start =
1231                                         adjusted_mode_sw->crtc_hblank_start;
1232
1233         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1234                 adjusted_mode->crtc_hblank_end =
1235                                         adjusted_mode_sw->crtc_hblank_end;
1236 }
1237
1238 static void intel_dsi_get_config(struct intel_encoder *encoder,
1239                                  struct intel_crtc_state *pipe_config)
1240 {
1241         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1242         u32 pclk;
1243         DRM_DEBUG_KMS("\n");
1244
1245         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1246
1247         if (IS_GEN9_LP(dev_priv)) {
1248                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1249                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1250         } else {
1251                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1252         }
1253
1254         if (pclk) {
1255                 pipe_config->base.adjusted_mode.crtc_clock = pclk;
1256                 pipe_config->port_clock = pclk;
1257         }
1258 }
1259
1260 /* return txclkesc cycles in terms of divider and duration in us */
1261 static u16 txclkesc(u32 divider, unsigned int us)
1262 {
1263         switch (divider) {
1264         case ESCAPE_CLOCK_DIVIDER_1:
1265         default:
1266                 return 20 * us;
1267         case ESCAPE_CLOCK_DIVIDER_2:
1268                 return 10 * us;
1269         case ESCAPE_CLOCK_DIVIDER_4:
1270                 return 5 * us;
1271         }
1272 }
1273
1274 static void set_dsi_timings(struct drm_encoder *encoder,
1275                             const struct drm_display_mode *adjusted_mode)
1276 {
1277         struct drm_device *dev = encoder->dev;
1278         struct drm_i915_private *dev_priv = to_i915(dev);
1279         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1280         enum port port;
1281         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1282         unsigned int lane_count = intel_dsi->lane_count;
1283
1284         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1285
1286         hactive = adjusted_mode->crtc_hdisplay;
1287         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1288         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1289         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1290
1291         if (intel_dsi->dual_link) {
1292                 hactive /= 2;
1293                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1294                         hactive += intel_dsi->pixel_overlap;
1295                 hfp /= 2;
1296                 hsync /= 2;
1297                 hbp /= 2;
1298         }
1299
1300         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1301         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1302         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1303
1304         /* horizontal values are in terms of high speed byte clock */
1305         hactive = txbyteclkhs(hactive, bpp, lane_count,
1306                               intel_dsi->burst_mode_ratio);
1307         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1308         hsync = txbyteclkhs(hsync, bpp, lane_count,
1309                             intel_dsi->burst_mode_ratio);
1310         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1311
1312         for_each_dsi_port(port, intel_dsi->ports) {
1313                 if (IS_GEN9_LP(dev_priv)) {
1314                         /*
1315                          * Program hdisplay and vdisplay on MIPI transcoder.
1316                          * This is different from calculated hactive and
1317                          * vactive, as they are calculated per channel basis,
1318                          * whereas these values should be based on resolution.
1319                          */
1320                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1321                                    adjusted_mode->crtc_hdisplay);
1322                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1323                                    adjusted_mode->crtc_vdisplay);
1324                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1325                                    adjusted_mode->crtc_vtotal);
1326                 }
1327
1328                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1329                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1330
1331                 /* meaningful for video mode non-burst sync pulse mode only,
1332                  * can be zero for non-burst sync events and burst modes */
1333                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1334                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1335
1336                 /* vertical values are in terms of lines */
1337                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1338                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1339                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1340         }
1341 }
1342
1343 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1344 {
1345         switch (fmt) {
1346         case MIPI_DSI_FMT_RGB888:
1347                 return VID_MODE_FORMAT_RGB888;
1348         case MIPI_DSI_FMT_RGB666:
1349                 return VID_MODE_FORMAT_RGB666;
1350         case MIPI_DSI_FMT_RGB666_PACKED:
1351                 return VID_MODE_FORMAT_RGB666_PACKED;
1352         case MIPI_DSI_FMT_RGB565:
1353                 return VID_MODE_FORMAT_RGB565;
1354         default:
1355                 MISSING_CASE(fmt);
1356                 return VID_MODE_FORMAT_RGB666;
1357         }
1358 }
1359
1360 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1361                               const struct intel_crtc_state *pipe_config)
1362 {
1363         struct drm_encoder *encoder = &intel_encoder->base;
1364         struct drm_device *dev = encoder->dev;
1365         struct drm_i915_private *dev_priv = to_i915(dev);
1366         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1367         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1368         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1369         enum port port;
1370         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1371         u32 val, tmp;
1372         u16 mode_hdisplay;
1373
1374         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1375
1376         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1377
1378         if (intel_dsi->dual_link) {
1379                 mode_hdisplay /= 2;
1380                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1381                         mode_hdisplay += intel_dsi->pixel_overlap;
1382         }
1383
1384         for_each_dsi_port(port, intel_dsi->ports) {
1385                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1386                         /*
1387                          * escape clock divider, 20MHz, shared for A and C.
1388                          * device ready must be off when doing this! txclkesc?
1389                          */
1390                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1391                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1392                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1393                                         ESCAPE_CLOCK_DIVIDER_1);
1394
1395                         /* read request priority is per pipe */
1396                         tmp = I915_READ(MIPI_CTRL(port));
1397                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1398                         I915_WRITE(MIPI_CTRL(port), tmp |
1399                                         READ_REQUEST_PRIORITY_HIGH);
1400                 } else if (IS_GEN9_LP(dev_priv)) {
1401                         enum pipe pipe = intel_crtc->pipe;
1402
1403                         tmp = I915_READ(MIPI_CTRL(port));
1404                         tmp &= ~BXT_PIPE_SELECT_MASK;
1405
1406                         tmp |= BXT_PIPE_SELECT(pipe);
1407                         I915_WRITE(MIPI_CTRL(port), tmp);
1408                 }
1409
1410                 /* XXX: why here, why like this? handling in irq handler?! */
1411                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1412                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1413
1414                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1415
1416                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1417                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1418                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1419         }
1420
1421         set_dsi_timings(encoder, adjusted_mode);
1422
1423         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1424         if (is_cmd_mode(intel_dsi)) {
1425                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1426                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1427         } else {
1428                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1429                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1430         }
1431
1432         tmp = 0;
1433         if (intel_dsi->eotp_pkt == 0)
1434                 tmp |= EOT_DISABLE;
1435         if (intel_dsi->clock_stop)
1436                 tmp |= CLOCKSTOP;
1437
1438         if (IS_GEN9_LP(dev_priv)) {
1439                 tmp |= BXT_DPHY_DEFEATURE_EN;
1440                 if (!is_cmd_mode(intel_dsi))
1441                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1442         }
1443
1444         for_each_dsi_port(port, intel_dsi->ports) {
1445                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1446
1447                 /* timeouts for recovery. one frame IIUC. if counter expires,
1448                  * EOT and stop state. */
1449
1450                 /*
1451                  * In burst mode, value greater than one DPI line Time in byte
1452                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1453                  * said value is recommended.
1454                  *
1455                  * In non-burst mode, Value greater than one DPI frame time in
1456                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1457                  * said value is recommended.
1458                  *
1459                  * In DBI only mode, value greater than one DBI frame time in
1460                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1461                  * said value is recommended.
1462                  */
1463
1464                 if (is_vid_mode(intel_dsi) &&
1465                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1466                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1467                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1468                                             intel_dsi->lane_count,
1469                                             intel_dsi->burst_mode_ratio) + 1);
1470                 } else {
1471                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1472                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1473                                             adjusted_mode->crtc_htotal,
1474                                             bpp, intel_dsi->lane_count,
1475                                             intel_dsi->burst_mode_ratio) + 1);
1476                 }
1477                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1478                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1479                                                 intel_dsi->turn_arnd_val);
1480                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1481                                                 intel_dsi->rst_timer_val);
1482
1483                 /* dphy stuff */
1484
1485                 /* in terms of low power clock */
1486                 I915_WRITE(MIPI_INIT_COUNT(port),
1487                                 txclkesc(intel_dsi->escape_clk_div, 100));
1488
1489                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1490                         /*
1491                          * BXT spec says write MIPI_INIT_COUNT for
1492                          * both the ports, even if only one is
1493                          * getting used. So write the other port
1494                          * if not in dual link mode.
1495                          */
1496                         I915_WRITE(MIPI_INIT_COUNT(port ==
1497                                                 PORT_A ? PORT_C : PORT_A),
1498                                         intel_dsi->init_count);
1499                 }
1500
1501                 /* recovery disables */
1502                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1503
1504                 /* in terms of low power clock */
1505                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1506
1507                 /* in terms of txbyteclkhs. actual high to low switch +
1508                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1509                  *
1510                  * XXX: write MIPI_STOP_STATE_STALL?
1511                  */
1512                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1513                                                 intel_dsi->hs_to_lp_count);
1514
1515                 /* XXX: low power clock equivalence in terms of byte clock.
1516                  * the number of byte clocks occupied in one low power clock.
1517                  * based on txbyteclkhs and txclkesc.
1518                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1519                  * ) / 105.???
1520                  */
1521                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1522
1523                 if (IS_GEMINILAKE(dev_priv)) {
1524                         I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1525                                         intel_dsi->lp_byte_clk);
1526                         /* Shadow of DPHY reg */
1527                         I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1528                                         intel_dsi->dphy_reg);
1529                 }
1530
1531                 /* the bw essential for transmitting 16 long packets containing
1532                  * 252 bytes meant for dcs write memory command is programmed in
1533                  * this register in terms of byte clocks. based on dsi transfer
1534                  * rate and the number of lanes configured the time taken to
1535                  * transmit 16 long packets in a dsi stream varies. */
1536                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1537
1538                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1539                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1540                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1541
1542                 if (is_vid_mode(intel_dsi))
1543                         /* Some panels might have resolution which is not a
1544                          * multiple of 64 like 1366 x 768. Enable RANDOM
1545                          * resolution support for such panels by default */
1546                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1547                                 intel_dsi->video_frmt_cfg_bits |
1548                                 intel_dsi->video_mode_format |
1549                                 IP_TG_CONFIG |
1550                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1551         }
1552 }
1553
1554 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1555 {
1556         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1557         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1558         enum port port;
1559         u32 val;
1560
1561         if (IS_GEMINILAKE(dev_priv))
1562                 return;
1563
1564         for_each_dsi_port(port, intel_dsi->ports) {
1565                 /* Panel commands can be sent when clock is in LP11 */
1566                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1567
1568                 if (IS_GEN9_LP(dev_priv))
1569                         bxt_dsi_reset_clocks(encoder, port);
1570                 else
1571                         vlv_dsi_reset_clocks(encoder, port);
1572                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1573
1574                 val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1575                 val &= ~VID_MODE_FORMAT_MASK;
1576                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1577
1578                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1579         }
1580 }
1581
1582 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1583 {
1584         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1585
1586         /* dispose of the gpios */
1587         if (intel_dsi->gpio_panel)
1588                 gpiod_put(intel_dsi->gpio_panel);
1589
1590         intel_encoder_destroy(encoder);
1591 }
1592
1593 static const struct drm_encoder_funcs intel_dsi_funcs = {
1594         .destroy = intel_dsi_encoder_destroy,
1595 };
1596
1597 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1598         .get_modes = intel_dsi_get_modes,
1599         .mode_valid = intel_dsi_mode_valid,
1600         .atomic_check = intel_digital_connector_atomic_check,
1601 };
1602
1603 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1604         .late_register = intel_connector_register,
1605         .early_unregister = intel_connector_unregister,
1606         .destroy = intel_connector_destroy,
1607         .fill_modes = drm_helper_probe_single_connector_modes,
1608         .atomic_get_property = intel_digital_connector_atomic_get_property,
1609         .atomic_set_property = intel_digital_connector_atomic_set_property,
1610         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1611         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1612 };
1613
1614 static enum drm_panel_orientation
1615 vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector)
1616 {
1617         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1618         struct intel_encoder *encoder = connector->encoder;
1619         enum intel_display_power_domain power_domain;
1620         enum drm_panel_orientation orientation;
1621         struct intel_plane *plane;
1622         struct intel_crtc *crtc;
1623         intel_wakeref_t wakeref;
1624         enum pipe pipe;
1625         u32 val;
1626
1627         if (!encoder->get_hw_state(encoder, &pipe))
1628                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1629
1630         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1631         plane = to_intel_plane(crtc->base.primary);
1632
1633         power_domain = POWER_DOMAIN_PIPE(pipe);
1634         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1635         if (!wakeref)
1636                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1637
1638         val = I915_READ(DSPCNTR(plane->i9xx_plane));
1639
1640         if (!(val & DISPLAY_PLANE_ENABLE))
1641                 orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1642         else if (val & DISPPLANE_ROTATE_180)
1643                 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1644         else
1645                 orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
1646
1647         intel_display_power_put(dev_priv, power_domain, wakeref);
1648
1649         return orientation;
1650 }
1651
1652 static enum drm_panel_orientation
1653 vlv_dsi_get_panel_orientation(struct intel_connector *connector)
1654 {
1655         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1656         enum drm_panel_orientation orientation;
1657
1658         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1659                 orientation = vlv_dsi_get_hw_panel_orientation(connector);
1660                 if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
1661                         return orientation;
1662         }
1663
1664         return intel_dsi_get_panel_orientation(connector);
1665 }
1666
1667 static void intel_dsi_add_properties(struct intel_connector *connector)
1668 {
1669         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1670
1671         if (connector->panel.fixed_mode) {
1672                 u32 allowed_scalers;
1673
1674                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1675                 if (!HAS_GMCH(dev_priv))
1676                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1677
1678                 drm_connector_attach_scaling_mode_property(&connector->base,
1679                                                                 allowed_scalers);
1680
1681                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1682
1683                 connector->base.display_info.panel_orientation =
1684                         vlv_dsi_get_panel_orientation(connector);
1685                 drm_connector_init_panel_orientation_property(
1686                                 &connector->base,
1687                                 connector->panel.fixed_mode->hdisplay,
1688                                 connector->panel.fixed_mode->vdisplay);
1689         }
1690 }
1691
1692 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1693 {
1694         struct drm_device *dev = &dev_priv->drm;
1695         struct intel_dsi *intel_dsi;
1696         struct intel_encoder *intel_encoder;
1697         struct drm_encoder *encoder;
1698         struct intel_connector *intel_connector;
1699         struct drm_connector *connector;
1700         struct drm_display_mode *fixed_mode;
1701         enum port port;
1702
1703         DRM_DEBUG_KMS("\n");
1704
1705         /* There is no detection method for MIPI so rely on VBT */
1706         if (!intel_bios_is_dsi_present(dev_priv, &port))
1707                 return;
1708
1709         if (IS_GEN9_LP(dev_priv))
1710                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1711         else
1712                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1713
1714         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1715         if (!intel_dsi)
1716                 return;
1717
1718         intel_connector = intel_connector_alloc();
1719         if (!intel_connector) {
1720                 kfree(intel_dsi);
1721                 return;
1722         }
1723
1724         intel_encoder = &intel_dsi->base;
1725         encoder = &intel_encoder->base;
1726         intel_dsi->attached_connector = intel_connector;
1727
1728         connector = &intel_connector->base;
1729
1730         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1731                          "DSI %c", port_name(port));
1732
1733         intel_encoder->compute_config = intel_dsi_compute_config;
1734         intel_encoder->pre_enable = intel_dsi_pre_enable;
1735         intel_encoder->disable = intel_dsi_disable;
1736         intel_encoder->post_disable = intel_dsi_post_disable;
1737         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1738         intel_encoder->get_config = intel_dsi_get_config;
1739         intel_encoder->update_pipe = intel_panel_update_backlight;
1740
1741         intel_connector->get_hw_state = intel_connector_get_hw_state;
1742
1743         intel_encoder->port = port;
1744
1745         /*
1746          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1747          * port C. BXT isn't limited like this.
1748          */
1749         if (IS_GEN9_LP(dev_priv))
1750                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1751         else if (port == PORT_A)
1752                 intel_encoder->crtc_mask = BIT(PIPE_A);
1753         else
1754                 intel_encoder->crtc_mask = BIT(PIPE_B);
1755
1756         if (dev_priv->vbt.dsi.config->dual_link)
1757                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1758         else
1759                 intel_dsi->ports = BIT(port);
1760
1761         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1762         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1763
1764         /* Create a DSI host (and a device) for each port. */
1765         for_each_dsi_port(port, intel_dsi->ports) {
1766                 struct intel_dsi_host *host;
1767
1768                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1769                                            port);
1770                 if (!host)
1771                         goto err;
1772
1773                 intel_dsi->dsi_hosts[port] = host;
1774         }
1775
1776         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1777                 DRM_DEBUG_KMS("no device found\n");
1778                 goto err;
1779         }
1780
1781         /*
1782          * In case of BYT with CRC PMIC, we need to use GPIO for
1783          * Panel control.
1784          */
1785         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1786             (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1787                 intel_dsi->gpio_panel =
1788                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1789
1790                 if (IS_ERR(intel_dsi->gpio_panel)) {
1791                         DRM_ERROR("Failed to own gpio for panel control\n");
1792                         intel_dsi->gpio_panel = NULL;
1793                 }
1794         }
1795
1796         intel_encoder->type = INTEL_OUTPUT_DSI;
1797         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1798         intel_encoder->cloneable = 0;
1799         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1800                            DRM_MODE_CONNECTOR_DSI);
1801
1802         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1803
1804         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1805         connector->interlace_allowed = false;
1806         connector->doublescan_allowed = false;
1807
1808         intel_connector_attach_encoder(intel_connector, intel_encoder);
1809
1810         mutex_lock(&dev->mode_config.mutex);
1811         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1812         mutex_unlock(&dev->mode_config.mutex);
1813
1814         if (!fixed_mode) {
1815                 DRM_DEBUG_KMS("no fixed mode\n");
1816                 goto err;
1817         }
1818
1819         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1820         intel_panel_setup_backlight(connector, INVALID_PIPE);
1821
1822         intel_dsi_add_properties(intel_connector);
1823
1824         return;
1825
1826 err:
1827         drm_encoder_cleanup(&intel_encoder->base);
1828         kfree(intel_dsi);
1829         kfree(intel_connector);
1830 }