drivers/gpu/drm/i915/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_mipi_dsi.h>
  32 #include <linux/slab.h>
  33 #include <linux/gpio/consumer.h>
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36 #include "intel_dsi.h"
  37
  38 /* return pixels in terms of txbyteclkhs */
  39 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  40                        u16 burst_mode_ratio)
  41 {
  42         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  43                                          8 * 100), lane_count);
  44 }
  45
  46 /* return pixels equvalent to txbyteclkhs */
  47 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  48                         u16 burst_mode_ratio)
  49 {
  50         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  51                                                 (bpp * burst_mode_ratio));
  52 }
  53
  54 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  55 {
  56         /* It just so happens the VBT matches register contents. */
  57         switch (fmt) {
  58         case VID_MODE_FORMAT_RGB888:
  59                 return MIPI_DSI_FMT_RGB888;
  60         case VID_MODE_FORMAT_RGB666:
  61                 return MIPI_DSI_FMT_RGB666;
  62         case VID_MODE_FORMAT_RGB666_PACKED:
  63                 return MIPI_DSI_FMT_RGB666_PACKED;
  64         case VID_MODE_FORMAT_RGB565:
  65                 return MIPI_DSI_FMT_RGB565;
  66         default:
  67                 MISSING_CASE(fmt);
  68                 return MIPI_DSI_FMT_RGB666;
  69         }
  70 }
  71
  72 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  73 {
  74         struct drm_encoder *encoder = &intel_dsi->base.base;
  75         struct drm_device *dev = encoder->dev;
  76         struct drm_i915_private *dev_priv = to_i915(dev);
  77         u32 mask;
  78
  79         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  80                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  81
  82         if (intel_wait_for_register(dev_priv,
  83                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  84                                     100))
  85                 DRM_ERROR("DPI FIFOs are not empty\n");
  86 }
  87
  88 static void write_data(struct drm_i915_private *dev_priv,
  89                        i915_reg_t reg,
  90                        const u8 *data, u32 len)
  91 {
  92         u32 i, j;
  93
  94         for (i = 0; i < len; i += 4) {
  95                 u32 val = 0;
  96
  97                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  98                         val |= *data++ << 8 * j;
  99
 100                 I915_WRITE(reg, val);
 101         }
 102 }
 103
 104 static void read_data(struct drm_i915_private *dev_priv,
 105                       i915_reg_t reg,
 106                       u8 *data, u32 len)
 107 {
 108         u32 i, j;
 109
 110         for (i = 0; i < len; i += 4) {
 111                 u32 val = I915_READ(reg);
 112
 113                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 114                         *data++ = val >> 8 * j;
 115         }
 116 }
 117
 118 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 119                                        const struct mipi_dsi_msg *msg)
 120 {
 121         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 122         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 123         struct drm_i915_private *dev_priv = to_i915(dev);
 124         enum port port = intel_dsi_host->port;
 125         struct mipi_dsi_packet packet;
 126         ssize_t ret;
 127         const u8 *header, *data;
 128         i915_reg_t data_reg, ctrl_reg;
 129         u32 data_mask, ctrl_mask;
 130
 131         ret = mipi_dsi_create_packet(&packet, msg);
 132         if (ret < 0)
 133                 return ret;
 134
 135         header = packet.header;
 136         data = packet.payload;
 137
 138         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 139                 data_reg = MIPI_LP_GEN_DATA(port);
 140                 data_mask = LP_DATA_FIFO_FULL;
 141                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 142                 ctrl_mask = LP_CTRL_FIFO_FULL;
 143         } else {
 144                 data_reg = MIPI_HS_GEN_DATA(port);
 145                 data_mask = HS_DATA_FIFO_FULL;
 146                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 147                 ctrl_mask = HS_CTRL_FIFO_FULL;
 148         }
 149
 150         /* note: this is never true for reads */
 151         if (packet.payload_length) {
 152                 if (intel_wait_for_register(dev_priv,
 153                                             MIPI_GEN_FIFO_STAT(port),
 154                                             data_mask, 0,
 155                                             50))
 156                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 157
 158                 write_data(dev_priv, data_reg, packet.payload,
 159                            packet.payload_length);
 160         }
 161
 162         if (msg->rx_len) {
 163                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 164         }
 165
 166         if (intel_wait_for_register(dev_priv,
 167                                     MIPI_GEN_FIFO_STAT(port),
 168                                     ctrl_mask, 0,
 169                                     50)) {
 170                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 171         }
 172
 173         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 174
 175         /* ->rx_len is set only for reads */
 176         if (msg->rx_len) {
 177                 data_mask = GEN_READ_DATA_AVAIL;
 178                 if (intel_wait_for_register(dev_priv,
 179                                             MIPI_INTR_STAT(port),
 180                                             data_mask, data_mask,
 181                                             50))
 182                         DRM_ERROR("Timeout waiting for read data.\n");
 183
 184                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 185         }
 186
 187         /* XXX: fix for reads and writes */
 188         return 4 + packet.payload_length;
 189 }
 190
 191 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 192                                  struct mipi_dsi_device *dsi)
 193 {
 194         return 0;
 195 }
 196
 197 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 198                                  struct mipi_dsi_device *dsi)
 199 {
 200         return 0;
 201 }
 202
 203 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 204         .attach = intel_dsi_host_attach,
 205         .detach = intel_dsi_host_detach,
 206         .transfer = intel_dsi_host_transfer,
 207 };
 208
 209 /*
 210  * send a video mode command
 211  *
 212  * XXX: commands with data in MIPI_DPI_DATA?
 213  */
 214 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 215                         enum port port)
 216 {
 217         struct drm_encoder *encoder = &intel_dsi->base.base;
 218         struct drm_device *dev = encoder->dev;
 219         struct drm_i915_private *dev_priv = to_i915(dev);
 220         u32 mask;
 221
 222         /* XXX: pipe, hs */
 223         if (hs)
 224                 cmd &= ~DPI_LP_MODE;
 225         else
 226                 cmd |= DPI_LP_MODE;
 227
 228         /* clear bit */
 229         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 230
 231         /* XXX: old code skips write if control unchanged */
 232         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 233                 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
 234
 235         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 236
 237         mask = SPL_PKT_SENT_INTERRUPT;
 238         if (intel_wait_for_register(dev_priv,
 239                                     MIPI_INTR_STAT(port), mask, mask,
 240                                     100))
 241                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 242
 243         return 0;
 244 }
 245
 246 static void band_gap_reset(struct drm_i915_private *dev_priv)
 247 {
 248         mutex_lock(&dev_priv->sb_lock);
 249
 250         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 251         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 252         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 253         udelay(150);
 254         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 255         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 256
 257         mutex_unlock(&dev_priv->sb_lock);
 258 }
 259
 260 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 261                                      struct intel_crtc_state *pipe_config,
 262                                      struct drm_connector_state *conn_state)
 263 {
 264         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 265         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 266                                                    base);
 267         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 268         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 269         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 270         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 271         int ret;
 272
 273         DRM_DEBUG_KMS("\n");
 274         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 275
 276         if (fixed_mode) {
 277                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 278
 279                 if (HAS_GMCH_DISPLAY(dev_priv))
 280                         intel_gmch_panel_fitting(crtc, pipe_config,
 281                                                  conn_state->scaling_mode);
 282                 else
 283                         intel_pch_panel_fitting(crtc, pipe_config,
 284                                                 conn_state->scaling_mode);
 285         }
 286
 287         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 288                 return false;
 289
 290         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 291         adjusted_mode->flags = 0;
 292
 293         if (IS_GEN9_LP(dev_priv)) {
 294                 /* Enable Frame time stamp based scanline reporting */
 295                 adjusted_mode->private_flags |=
 296                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 297
 298                 /* Dual link goes to DSI transcoder A. */
 299                 if (intel_dsi->ports == BIT(PORT_C))
 300                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 301                 else
 302                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 303
 304                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 305                 if (ret)
 306                         return false;
 307         } else {
 308                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 309                 if (ret)
 310                         return false;
 311         }
 312
 313         pipe_config->clock_set = true;
 314
 315         return true;
 316 }
 317
 318 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 319 {
 320         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 321         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 322         enum port port;
 323         u32 tmp;
 324         bool cold_boot = false;
 325
 326         /* Set the MIPI mode
 327          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 328          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 329          */
 330         for_each_dsi_port(port, intel_dsi->ports) {
 331                 tmp = I915_READ(MIPI_CTRL(port));
 332                 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
 333         }
 334
 335         /* Put the IO into reset */
 336         tmp = I915_READ(MIPI_CTRL(PORT_A));
 337         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 338         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 339
 340         /* Program LP Wake */
 341         for_each_dsi_port(port, intel_dsi->ports) {
 342                 tmp = I915_READ(MIPI_CTRL(port));
 343                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 344                         tmp &= ~GLK_LP_WAKE;
 345                 else
 346                         tmp |= GLK_LP_WAKE;
 347                 I915_WRITE(MIPI_CTRL(port), tmp);
 348         }
 349
 350         /* Wait for Pwr ACK */
 351         for_each_dsi_port(port, intel_dsi->ports) {
 352                 if (intel_wait_for_register(dev_priv,
 353                                 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
 354                                 GLK_MIPIIO_PORT_POWERED, 20))
 355                         DRM_ERROR("MIPIO port is powergated\n");
 356         }
 357
 358         /* Check for cold boot scenario */
 359         for_each_dsi_port(port, intel_dsi->ports) {
 360                 cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
 361                                                         DEVICE_READY);
 362         }
 363
 364         return cold_boot;
 365 }
 366
 367 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 368 {
 369         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 370         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 371         enum port port;
 372         u32 val;
 373
 374         /* Wait for MIPI PHY status bit to set */
 375         for_each_dsi_port(port, intel_dsi->ports) {
 376                 if (intel_wait_for_register(dev_priv,
 377                                 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
 378                                 GLK_PHY_STATUS_PORT_READY, 20))
 379                         DRM_ERROR("PHY is not ON\n");
 380         }
 381
 382         /* Get IO out of reset */
 383         val = I915_READ(MIPI_CTRL(PORT_A));
 384         I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
 385
 386         /* Get IO out of Low power state*/
 387         for_each_dsi_port(port, intel_dsi->ports) {
 388                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 389                         val = I915_READ(MIPI_DEVICE_READY(port));
 390                         val &= ~ULPS_STATE_MASK;
 391                         val |= DEVICE_READY;
 392                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 393                         usleep_range(10, 15);
 394                 } else {
 395                         /* Enter ULPS */
 396                         val = I915_READ(MIPI_DEVICE_READY(port));
 397                         val &= ~ULPS_STATE_MASK;
 398                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 399                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 400
 401                         /* Wait for ULPS active */
 402                         if (intel_wait_for_register(dev_priv,
 403                                 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
 404                                 DRM_ERROR("ULPS not active\n");
 405
 406                         /* Exit ULPS */
 407                         val = I915_READ(MIPI_DEVICE_READY(port));
 408                         val &= ~ULPS_STATE_MASK;
 409                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 410                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 411
 412                         /* Enter Normal Mode */
 413                         val = I915_READ(MIPI_DEVICE_READY(port));
 414                         val &= ~ULPS_STATE_MASK;
 415                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 416                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 417
 418                         val = I915_READ(MIPI_CTRL(port));
 419                         val &= ~GLK_LP_WAKE;
 420                         I915_WRITE(MIPI_CTRL(port), val);
 421                 }
 422         }
 423
 424         /* Wait for Stop state */
 425         for_each_dsi_port(port, intel_dsi->ports) {
 426                 if (intel_wait_for_register(dev_priv,
 427                                 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
 428                                 GLK_DATA_LANE_STOP_STATE, 20))
 429                         DRM_ERROR("Date lane not in STOP state\n");
 430         }
 431
 432         /* Wait for AFE LATCH */
 433         for_each_dsi_port(port, intel_dsi->ports) {
 434                 if (intel_wait_for_register(dev_priv,
 435                                 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
 436                                 AFE_LATCHOUT, 20))
 437                         DRM_ERROR("D-PHY not entering LP-11 state\n");
 438         }
 439 }
 440
 441 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 442 {
 443         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 444         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 445         enum port port;
 446         u32 val;
 447
 448         DRM_DEBUG_KMS("\n");
 449
 450         /* Enable MIPI PHY transparent latch */
 451         for_each_dsi_port(port, intel_dsi->ports) {
 452                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 453                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 454                 usleep_range(2000, 2500);
 455         }
 456
 457         /* Clear ULPS and set device ready */
 458         for_each_dsi_port(port, intel_dsi->ports) {
 459                 val = I915_READ(MIPI_DEVICE_READY(port));
 460                 val &= ~ULPS_STATE_MASK;
 461                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 462                 usleep_range(2000, 2500);
 463                 val |= DEVICE_READY;
 464                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 465         }
 466 }
 467
 468 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 469 {
 470         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 471         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 472         enum port port;
 473         u32 val;
 474
 475         DRM_DEBUG_KMS("\n");
 476
 477         mutex_lock(&dev_priv->sb_lock);
 478         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 479          * needed everytime after power gate */
 480         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 481         mutex_unlock(&dev_priv->sb_lock);
 482
 483         /* bandgap reset is needed after everytime we do power gate */
 484         band_gap_reset(dev_priv);
 485
 486         for_each_dsi_port(port, intel_dsi->ports) {
 487
 488                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 489                 usleep_range(2500, 3000);
 490
 491                 /* Enable MIPI PHY transparent latch
 492                  * Common bit for both MIPI Port A & MIPI Port C
 493                  * No similar bit in MIPI Port C reg
 494                  */
 495                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 496                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 497                 usleep_range(1000, 1500);
 498
 499                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 500                 usleep_range(2500, 3000);
 501
 502                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 503                 usleep_range(2500, 3000);
 504         }
 505 }
 506
 507 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 508 {
 509         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 510
 511         if (IS_GEMINILAKE(dev_priv))
 512                 glk_dsi_device_ready(encoder);
 513         else if (IS_GEN9_LP(dev_priv))
 514                 bxt_dsi_device_ready(encoder);
 515         else
 516                 vlv_dsi_device_ready(encoder);
 517 }
 518
 519 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 520 {
 521         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 522         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 523         enum port port;
 524         u32 val;
 525
 526         /* Enter ULPS */
 527         for_each_dsi_port(port, intel_dsi->ports) {
 528                 val = I915_READ(MIPI_DEVICE_READY(port));
 529                 val &= ~ULPS_STATE_MASK;
 530                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 531                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 532         }
 533
 534         /* Wait for MIPI PHY status bit to unset */
 535         for_each_dsi_port(port, intel_dsi->ports) {
 536                 if (intel_wait_for_register(dev_priv,
 537                                             MIPI_CTRL(port),
 538                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 539                         DRM_ERROR("PHY is not turning OFF\n");
 540         }
 541
 542         /* Wait for Pwr ACK bit to unset */
 543         for_each_dsi_port(port, intel_dsi->ports) {
 544                 if (intel_wait_for_register(dev_priv,
 545                                             MIPI_CTRL(port),
 546                                             GLK_MIPIIO_PORT_POWERED, 0, 20))
 547                         DRM_ERROR("MIPI IO Port is not powergated\n");
 548         }
 549 }
 550
 551 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 552 {
 553         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 554         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 555         enum port port;
 556         u32 tmp;
 557
 558         /* Put the IO into reset */
 559         tmp = I915_READ(MIPI_CTRL(PORT_A));
 560         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 561         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 562
 563         /* Wait for MIPI PHY status bit to unset */
 564         for_each_dsi_port(port, intel_dsi->ports) {
 565                 if (intel_wait_for_register(dev_priv,
 566                                             MIPI_CTRL(port),
 567                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 568                         DRM_ERROR("PHY is not turning OFF\n");
 569         }
 570
 571         /* Clear MIPI mode */
 572         for_each_dsi_port(port, intel_dsi->ports) {
 573                 tmp = I915_READ(MIPI_CTRL(port));
 574                 tmp &= ~GLK_MIPIIO_ENABLE;
 575                 I915_WRITE(MIPI_CTRL(port), tmp);
 576         }
 577 }
 578
 579 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 580 {
 581         glk_dsi_enter_low_power_mode(encoder);
 582         glk_dsi_disable_mipi_io(encoder);
 583 }
 584
 585 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 586 {
 587         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 588         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 589         enum port port;
 590
 591         DRM_DEBUG_KMS("\n");
 592         for_each_dsi_port(port, intel_dsi->ports) {
 593                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 594                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 595                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 596                 u32 val;
 597
 598                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 599                                                         ULPS_STATE_ENTER);
 600                 usleep_range(2000, 2500);
 601
 602                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 603                                                         ULPS_STATE_EXIT);
 604                 usleep_range(2000, 2500);
 605
 606                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 607                                                         ULPS_STATE_ENTER);
 608                 usleep_range(2000, 2500);
 609
 610                 /*
 611                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 612                  * Port A only. MIPI Port C has no similar bit for checking.
 613                  */
 614                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 615                     intel_wait_for_register(dev_priv,
 616                                             port_ctrl, AFE_LATCHOUT, 0,
 617                                             30))
 618                         DRM_ERROR("DSI LP not going Low\n");
 619
 620                 /* Disable MIPI PHY transparent latch */
 621                 val = I915_READ(port_ctrl);
 622                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 623                 usleep_range(1000, 1500);
 624
 625                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 626                 usleep_range(2000, 2500);
 627         }
 628 }
 629
 630 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 631                                   const struct intel_crtc_state *crtc_state)
 632 {
 633         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 634         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 635         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 636         enum port port;
 637
 638         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 639                 u32 temp;
 640                 if (IS_GEN9_LP(dev_priv)) {
 641                         for_each_dsi_port(port, intel_dsi->ports) {
 642                                 temp = I915_READ(MIPI_CTRL(port));
 643                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 644                                         intel_dsi->pixel_overlap <<
 645                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 646                                 I915_WRITE(MIPI_CTRL(port), temp);
 647                         }
 648                 } else {
 649                         temp = I915_READ(VLV_CHICKEN_3);
 650                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 651                                         intel_dsi->pixel_overlap <<
 652                                         PIXEL_OVERLAP_CNT_SHIFT;
 653                         I915_WRITE(VLV_CHICKEN_3, temp);
 654                 }
 655         }
 656
 657         for_each_dsi_port(port, intel_dsi->ports) {
 658                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 659                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 660                 u32 temp;
 661
 662                 temp = I915_READ(port_ctrl);
 663
 664                 temp &= ~LANE_CONFIGURATION_MASK;
 665                 temp &= ~DUAL_LINK_MODE_MASK;
 666
 667                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 668                         temp |= (intel_dsi->dual_link - 1)
 669                                                 << DUAL_LINK_MODE_SHIFT;
 670                         if (IS_BROXTON(dev_priv))
 671                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 672                         else
 673                                 temp |= crtc->pipe ?
 674                                         LANE_CONFIGURATION_DUAL_LINK_B :
 675                                         LANE_CONFIGURATION_DUAL_LINK_A;
 676                 }
 677                 /* assert ip_tg_enable signal */
 678                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 679                 POSTING_READ(port_ctrl);
 680         }
 681 }
 682
 683 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 684 {
 685         struct drm_device *dev = encoder->base.dev;
 686         struct drm_i915_private *dev_priv = to_i915(dev);
 687         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 688         enum port port;
 689
 690         for_each_dsi_port(port, intel_dsi->ports) {
 691                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 692                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 693                 u32 temp;
 694
 695                 /* de-assert ip_tg_enable signal */
 696                 temp = I915_READ(port_ctrl);
 697                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 698                 POSTING_READ(port_ctrl);
 699         }
 700 }
 701
 702 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 703                               const struct intel_crtc_state *pipe_config);
 704 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 705
 706 /*
 707  * Panel enable/disable sequences from the VBT spec.
 708  *
 709  * Note the spec has AssertReset / DeassertReset swapped from their
 710  * usual naming. We use the normal names to avoid confusion (so below
 711  * they are swapped compared to the spec).
 712  *
 713  * Steps starting with MIPI refer to VBT sequences, note that for v2
 714  * VBTs several steps which have a VBT in v2 are expected to be handled
 715  * directly by the driver, by directly driving gpios for example.
 716  *
 717  * v2 video mode seq         v3 video mode seq         command mode seq
 718  * - power on                - MIPIPanelPowerOn        - power on
 719  * - wait t1+t2                                        - wait t1+t2
 720  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 721  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 722  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 723  *                                                     - MIPITearOn
 724  *                                                     - MIPIDisplayOn
 725  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 726  * - MIPIDisplayOn           - MIPIDisplayOn
 727  * - wait t5                                           - wait t5
 728  * - backlight on            - MIPIBacklightOn         - backlight on
 729  * ...                       ...                       ... issue mem cmds ...
 730  * - backlight off           - MIPIBacklightOff        - backlight off
 731  * - wait t6                                           - wait t6
 732  * - MIPIDisplayOff
 733  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 734  *                                                     - MIPITearOff
 735  *                           - MIPIDisplayOff          - MIPIDisplayOff
 736  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 737  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 738  * - wait t3                                           - wait t3
 739  * - power off               - MIPIPanelPowerOff       - power off
 740  * - wait t4                                           - wait t4
 741  */
 742
 743 /*
 744  * DSI port enable has to be done before pipe and plane enable, so we do it in
 745  * the pre_enable hook instead of the enable hook.
 746  */
 747 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 748                                  const struct intel_crtc_state *pipe_config,
 749                                  const struct drm_connector_state *conn_state)
 750 {
 751         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 752         struct drm_crtc *crtc = pipe_config->base.crtc;
 753         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 755         int pipe = intel_crtc->pipe;
 756         enum port port;
 757         u32 val;
 758         bool glk_cold_boot = false;
 759
 760         DRM_DEBUG_KMS("\n");
 761
 762         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 763
 764         /*
 765          * The BIOS may leave the PLL in a wonky state where it doesn't
 766          * lock. It needs to be fully powered down to fix it.
 767          */
 768         if (IS_GEN9_LP(dev_priv)) {
 769                 bxt_dsi_pll_disable(encoder);
 770                 bxt_dsi_pll_enable(encoder, pipe_config);
 771         } else {
 772                 vlv_dsi_pll_disable(encoder);
 773                 vlv_dsi_pll_enable(encoder, pipe_config);
 774         }
 775
 776         if (IS_BROXTON(dev_priv)) {
 777                 /* Add MIPI IO reset programming for modeset */
 778                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 779                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 780                                         val | MIPIO_RST_CTRL);
 781
 782                 /* Power up DSI regulator */
 783                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 784                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 785         }
 786
 787         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 788                 u32 val;
 789
 790                 /* Disable DPOunit clock gating, can stall pipe */
 791                 val = I915_READ(DSPCLK_GATE_D);
 792                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 793                 I915_WRITE(DSPCLK_GATE_D, val);
 794         }
 795
 796         if (!IS_GEMINILAKE(dev_priv))
 797                 intel_dsi_prepare(encoder, pipe_config);
 798
 799         /* Power on, try both CRC pmic gpio and VBT */
 800         if (intel_dsi->gpio_panel)
 801                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 802         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 803         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 804
 805         /* Deassert reset */
 806         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 807
 808         if (IS_GEMINILAKE(dev_priv)) {
 809                 glk_cold_boot = glk_dsi_enable_io(encoder);
 810
 811                 /* Prepare port in cold boot(s3/s4) scenario */
 812                 if (glk_cold_boot)
 813                         intel_dsi_prepare(encoder, pipe_config);
 814         }
 815
 816         /* Put device in ready state (LP-11) */
 817         intel_dsi_device_ready(encoder);
 818
 819         /* Prepare port in normal boot scenario */
 820         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 821                 intel_dsi_prepare(encoder, pipe_config);
 822
 823         /* Send initialization commands in LP mode */
 824         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 825
 826         /* Enable port in pre-enable phase itself because as per hw team
 827          * recommendation, port should be enabled befor plane & pipe */
 828         if (is_cmd_mode(intel_dsi)) {
 829                 for_each_dsi_port(port, intel_dsi->ports)
 830                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 831                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 832                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 833         } else {
 834                 msleep(20); /* XXX */
 835                 for_each_dsi_port(port, intel_dsi->ports)
 836                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 837                 intel_dsi_msleep(intel_dsi, 100);
 838
 839                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 840
 841                 intel_dsi_port_enable(encoder, pipe_config);
 842         }
 843
 844         intel_panel_enable_backlight(pipe_config, conn_state);
 845         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 846 }
 847
 848 /*
 849  * DSI port disable has to be done after pipe and plane disable, so we do it in
 850  * the post_disable hook.
 851  */
 852 static void intel_dsi_disable(struct intel_encoder *encoder,
 853                               const struct intel_crtc_state *old_crtc_state,
 854                               const struct drm_connector_state *old_conn_state)
 855 {
 856         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 857         enum port port;
 858
 859         DRM_DEBUG_KMS("\n");
 860
 861         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 862         intel_panel_disable_backlight(old_conn_state);
 863
 864         /*
 865          * According to the spec we should send SHUTDOWN before
 866          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 867          * has shown that the v3 sequence works for v2 VBTs too
 868          */
 869         if (is_vid_mode(intel_dsi)) {
 870                 /* Send Shutdown command to the panel in LP mode */
 871                 for_each_dsi_port(port, intel_dsi->ports)
 872                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 873                 msleep(10);
 874         }
 875 }
 876
 877 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 878 {
 879         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 880
 881         if (IS_GEMINILAKE(dev_priv))
 882                 glk_dsi_clear_device_ready(encoder);
 883         else
 884                 vlv_dsi_clear_device_ready(encoder);
 885 }
 886
 887 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 888                                    const struct intel_crtc_state *pipe_config,
 889                                    const struct drm_connector_state *conn_state)
 890 {
 891         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 892         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 893         enum port port;
 894         u32 val;
 895
 896         DRM_DEBUG_KMS("\n");
 897
 898         if (is_vid_mode(intel_dsi)) {
 899                 for_each_dsi_port(port, intel_dsi->ports)
 900                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 901
 902                 intel_dsi_port_disable(encoder);
 903                 usleep_range(2000, 5000);
 904         }
 905
 906         intel_dsi_unprepare(encoder);
 907
 908         /*
 909          * if disable packets are sent before sending shutdown packet then in
 910          * some next enable sequence send turn on packet error is observed
 911          */
 912         if (is_cmd_mode(intel_dsi))
 913                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 914         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 915
 916         /* Transition to LP-00 */
 917         intel_dsi_clear_device_ready(encoder);
 918
 919         if (IS_BROXTON(dev_priv)) {
 920                 /* Power down DSI regulator to save power */
 921                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 922                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
 923
 924                 /* Add MIPI IO reset programming for modeset */
 925                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 926                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 927                                 val & ~MIPIO_RST_CTRL);
 928         }
 929
 930         if (IS_GEN9_LP(dev_priv)) {
 931                 bxt_dsi_pll_disable(encoder);
 932         } else {
 933                 u32 val;
 934
 935                 vlv_dsi_pll_disable(encoder);
 936
 937                 val = I915_READ(DSPCLK_GATE_D);
 938                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 939                 I915_WRITE(DSPCLK_GATE_D, val);
 940         }
 941
 942         /* Assert reset */
 943         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 944
 945         /* Power off, try both CRC pmic gpio and VBT */
 946         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
 947         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 948         if (intel_dsi->gpio_panel)
 949                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 950
 951         /*
 952          * FIXME As we do with eDP, just make a note of the time here
 953          * and perform the wait before the next panel power on.
 954          */
 955         intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
 956 }
 957
 958 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 959                                    enum pipe *pipe)
 960 {
 961         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 962         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 963         enum port port;
 964         bool active = false;
 965
 966         DRM_DEBUG_KMS("\n");
 967
 968         if (!intel_display_power_get_if_enabled(dev_priv,
 969                                                 encoder->power_domain))
 970                 return false;
 971
 972         /*
 973          * On Broxton the PLL needs to be enabled with a valid divider
 974          * configuration, otherwise accessing DSI registers will hang the
 975          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 976          */
 977         if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
 978                 goto out_put_power;
 979
 980         /* XXX: this only works for one DSI output */
 981         for_each_dsi_port(port, intel_dsi->ports) {
 982                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
 983                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 984                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 985
 986                 /*
 987                  * Due to some hardware limitations on VLV/CHV, the DPI enable
 988                  * bit in port C control register does not get set. As a
 989                  * workaround, check pipe B conf instead.
 990                  */
 991                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 992                     port == PORT_C)
 993                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
 994
 995                 /* Try command mode if video mode not enabled */
 996                 if (!enabled) {
 997                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 998                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
 999                 }
1000
1001                 if (!enabled)
1002                         continue;
1003
1004                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1005                         continue;
1006
1007                 if (IS_GEN9_LP(dev_priv)) {
1008                         u32 tmp = I915_READ(MIPI_CTRL(port));
1009                         tmp &= BXT_PIPE_SELECT_MASK;
1010                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1011
1012                         if (WARN_ON(tmp > PIPE_C))
1013                                 continue;
1014
1015                         *pipe = tmp;
1016                 } else {
1017                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1018                 }
1019
1020                 active = true;
1021                 break;
1022         }
1023
1024 out_put_power:
1025         intel_display_power_put(dev_priv, encoder->power_domain);
1026
1027         return active;
1028 }
1029
1030 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1031                                     struct intel_crtc_state *pipe_config)
1032 {
1033         struct drm_device *dev = encoder->base.dev;
1034         struct drm_i915_private *dev_priv = to_i915(dev);
1035         struct drm_display_mode *adjusted_mode =
1036                                         &pipe_config->base.adjusted_mode;
1037         struct drm_display_mode *adjusted_mode_sw;
1038         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1039         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1040         unsigned int lane_count = intel_dsi->lane_count;
1041         unsigned int bpp, fmt;
1042         enum port port;
1043         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1044         u16 hfp_sw, hsync_sw, hbp_sw;
1045         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1046                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1047
1048         /* FIXME: hw readout should not depend on SW state */
1049         adjusted_mode_sw = &crtc->config->base.adjusted_mode;
1050
1051         /*
1052          * Atleast one port is active as encoder->get_config called only if
1053          * encoder->get_hw_state() returns true.
1054          */
1055         for_each_dsi_port(port, intel_dsi->ports) {
1056                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1057                         break;
1058         }
1059
1060         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1061         pipe_config->pipe_bpp =
1062                         mipi_dsi_pixel_format_to_bpp(
1063                                 pixel_format_from_register_bits(fmt));
1064         bpp = pipe_config->pipe_bpp;
1065
1066         /* Enable Frame time stamo based scanline reporting */
1067         adjusted_mode->private_flags |=
1068                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1069
1070         /* In terms of pixels */
1071         adjusted_mode->crtc_hdisplay =
1072                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1073         adjusted_mode->crtc_vdisplay =
1074                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1075         adjusted_mode->crtc_vtotal =
1076                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1077
1078         hactive = adjusted_mode->crtc_hdisplay;
1079         hfp = I915_READ(MIPI_HFP_COUNT(port));
1080
1081         /*
1082          * Meaningful for video mode non-burst sync pulse mode only,
1083          * can be zero for non-burst sync events and burst modes
1084          */
1085         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1086         hbp = I915_READ(MIPI_HBP_COUNT(port));
1087
1088         /* harizontal values are in terms of high speed byte clock */
1089         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1090                                                 intel_dsi->burst_mode_ratio);
1091         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1092                                                 intel_dsi->burst_mode_ratio);
1093         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1094                                                 intel_dsi->burst_mode_ratio);
1095
1096         if (intel_dsi->dual_link) {
1097                 hfp *= 2;
1098                 hsync *= 2;
1099                 hbp *= 2;
1100         }
1101
1102         /* vertical values are in terms of lines */
1103         vfp = I915_READ(MIPI_VFP_COUNT(port));
1104         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1105         vbp = I915_READ(MIPI_VBP_COUNT(port));
1106
1107         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1108         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1109         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1110         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1111         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1112
1113         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1114         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1115         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1116         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1117
1118         /*
1119          * In BXT DSI there is no regs programmed with few horizontal timings
1120          * in Pixels but txbyteclkhs.. So retrieval process adds some
1121          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1122          * Actually here for the given adjusted_mode, we are calculating the
1123          * value programmed to the port and then back to the horizontal timing
1124          * param in pixels. This is the expected value, including roundup errors
1125          * And if that is same as retrieved value from port, then
1126          * (HW state) adjusted_mode's horizontal timings are corrected to
1127          * match with SW state to nullify the errors.
1128          */
1129         /* Calculating the value programmed to the Port register */
1130         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1131                                         adjusted_mode_sw->crtc_hdisplay;
1132         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1133                                         adjusted_mode_sw->crtc_hsync_start;
1134         hbp_sw = adjusted_mode_sw->crtc_htotal -
1135                                         adjusted_mode_sw->crtc_hsync_end;
1136
1137         if (intel_dsi->dual_link) {
1138                 hfp_sw /= 2;
1139                 hsync_sw /= 2;
1140                 hbp_sw /= 2;
1141         }
1142
1143         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1144                                                 intel_dsi->burst_mode_ratio);
1145         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1146                             intel_dsi->burst_mode_ratio);
1147         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1148                                                 intel_dsi->burst_mode_ratio);
1149
1150         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1151         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1152                                                 intel_dsi->burst_mode_ratio);
1153         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1154                                                 intel_dsi->burst_mode_ratio);
1155         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1156                                                 intel_dsi->burst_mode_ratio);
1157
1158         if (intel_dsi->dual_link) {
1159                 hfp_sw *= 2;
1160                 hsync_sw *= 2;
1161                 hbp_sw *= 2;
1162         }
1163
1164         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1165                                                         hsync_sw + hbp_sw;
1166         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1167         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1168         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1169         crtc_hblank_end_sw = crtc_htotal_sw;
1170
1171         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1172                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1173
1174         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1175                 adjusted_mode->crtc_hsync_start =
1176                                         adjusted_mode_sw->crtc_hsync_start;
1177
1178         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1179                 adjusted_mode->crtc_hsync_end =
1180                                         adjusted_mode_sw->crtc_hsync_end;
1181
1182         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1183                 adjusted_mode->crtc_hblank_start =
1184                                         adjusted_mode_sw->crtc_hblank_start;
1185
1186         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1187                 adjusted_mode->crtc_hblank_end =
1188                                         adjusted_mode_sw->crtc_hblank_end;
1189 }
1190
1191 static void intel_dsi_get_config(struct intel_encoder *encoder,
1192                                  struct intel_crtc_state *pipe_config)
1193 {
1194         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1195         u32 pclk;
1196         DRM_DEBUG_KMS("\n");
1197
1198         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1199
1200         if (IS_GEN9_LP(dev_priv)) {
1201                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1202                 pclk = bxt_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1203                                         pipe_config);
1204         } else {
1205                 pclk = vlv_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1206                                         pipe_config);
1207         }
1208
1209         if (pclk) {
1210                 pipe_config->base.adjusted_mode.crtc_clock = pclk;
1211                 pipe_config->port_clock = pclk;
1212         }
1213 }
1214
1215 /* return txclkesc cycles in terms of divider and duration in us */
1216 static u16 txclkesc(u32 divider, unsigned int us)
1217 {
1218         switch (divider) {
1219         case ESCAPE_CLOCK_DIVIDER_1:
1220         default:
1221                 return 20 * us;
1222         case ESCAPE_CLOCK_DIVIDER_2:
1223                 return 10 * us;
1224         case ESCAPE_CLOCK_DIVIDER_4:
1225                 return 5 * us;
1226         }
1227 }
1228
1229 static void set_dsi_timings(struct drm_encoder *encoder,
1230                             const struct drm_display_mode *adjusted_mode)
1231 {
1232         struct drm_device *dev = encoder->dev;
1233         struct drm_i915_private *dev_priv = to_i915(dev);
1234         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1235         enum port port;
1236         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1237         unsigned int lane_count = intel_dsi->lane_count;
1238
1239         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1240
1241         hactive = adjusted_mode->crtc_hdisplay;
1242         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1243         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1244         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1245
1246         if (intel_dsi->dual_link) {
1247                 hactive /= 2;
1248                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1249                         hactive += intel_dsi->pixel_overlap;
1250                 hfp /= 2;
1251                 hsync /= 2;
1252                 hbp /= 2;
1253         }
1254
1255         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1256         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1257         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1258
1259         /* horizontal values are in terms of high speed byte clock */
1260         hactive = txbyteclkhs(hactive, bpp, lane_count,
1261                               intel_dsi->burst_mode_ratio);
1262         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1263         hsync = txbyteclkhs(hsync, bpp, lane_count,
1264                             intel_dsi->burst_mode_ratio);
1265         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1266
1267         for_each_dsi_port(port, intel_dsi->ports) {
1268                 if (IS_GEN9_LP(dev_priv)) {
1269                         /*
1270                          * Program hdisplay and vdisplay on MIPI transcoder.
1271                          * This is different from calculated hactive and
1272                          * vactive, as they are calculated per channel basis,
1273                          * whereas these values should be based on resolution.
1274                          */
1275                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1276                                    adjusted_mode->crtc_hdisplay);
1277                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1278                                    adjusted_mode->crtc_vdisplay);
1279                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1280                                    adjusted_mode->crtc_vtotal);
1281                 }
1282
1283                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1284                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1285
1286                 /* meaningful for video mode non-burst sync pulse mode only,
1287                  * can be zero for non-burst sync events and burst modes */
1288                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1289                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1290
1291                 /* vertical values are in terms of lines */
1292                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1293                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1294                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1295         }
1296 }
1297
1298 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1299 {
1300         switch (fmt) {
1301         case MIPI_DSI_FMT_RGB888:
1302                 return VID_MODE_FORMAT_RGB888;
1303         case MIPI_DSI_FMT_RGB666:
1304                 return VID_MODE_FORMAT_RGB666;
1305         case MIPI_DSI_FMT_RGB666_PACKED:
1306                 return VID_MODE_FORMAT_RGB666_PACKED;
1307         case MIPI_DSI_FMT_RGB565:
1308                 return VID_MODE_FORMAT_RGB565;
1309         default:
1310                 MISSING_CASE(fmt);
1311                 return VID_MODE_FORMAT_RGB666;
1312         }
1313 }
1314
1315 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1316                               const struct intel_crtc_state *pipe_config)
1317 {
1318         struct drm_encoder *encoder = &intel_encoder->base;
1319         struct drm_device *dev = encoder->dev;
1320         struct drm_i915_private *dev_priv = to_i915(dev);
1321         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1322         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1323         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1324         enum port port;
1325         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1326         u32 val, tmp;
1327         u16 mode_hdisplay;
1328
1329         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1330
1331         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1332
1333         if (intel_dsi->dual_link) {
1334                 mode_hdisplay /= 2;
1335                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1336                         mode_hdisplay += intel_dsi->pixel_overlap;
1337         }
1338
1339         for_each_dsi_port(port, intel_dsi->ports) {
1340                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1341                         /*
1342                          * escape clock divider, 20MHz, shared for A and C.
1343                          * device ready must be off when doing this! txclkesc?
1344                          */
1345                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1346                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1347                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1348                                         ESCAPE_CLOCK_DIVIDER_1);
1349
1350                         /* read request priority is per pipe */
1351                         tmp = I915_READ(MIPI_CTRL(port));
1352                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1353                         I915_WRITE(MIPI_CTRL(port), tmp |
1354                                         READ_REQUEST_PRIORITY_HIGH);
1355                 } else if (IS_GEN9_LP(dev_priv)) {
1356                         enum pipe pipe = intel_crtc->pipe;
1357
1358                         tmp = I915_READ(MIPI_CTRL(port));
1359                         tmp &= ~BXT_PIPE_SELECT_MASK;
1360
1361                         tmp |= BXT_PIPE_SELECT(pipe);
1362                         I915_WRITE(MIPI_CTRL(port), tmp);
1363                 }
1364
1365                 /* XXX: why here, why like this? handling in irq handler?! */
1366                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1367                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1368
1369                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1370
1371                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1372                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1373                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1374         }
1375
1376         set_dsi_timings(encoder, adjusted_mode);
1377
1378         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1379         if (is_cmd_mode(intel_dsi)) {
1380                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1381                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1382         } else {
1383                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1384                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1385         }
1386
1387         tmp = 0;
1388         if (intel_dsi->eotp_pkt == 0)
1389                 tmp |= EOT_DISABLE;
1390         if (intel_dsi->clock_stop)
1391                 tmp |= CLOCKSTOP;
1392
1393         if (IS_GEN9_LP(dev_priv)) {
1394                 tmp |= BXT_DPHY_DEFEATURE_EN;
1395                 if (!is_cmd_mode(intel_dsi))
1396                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1397         }
1398
1399         for_each_dsi_port(port, intel_dsi->ports) {
1400                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1401
1402                 /* timeouts for recovery. one frame IIUC. if counter expires,
1403                  * EOT and stop state. */
1404
1405                 /*
1406                  * In burst mode, value greater than one DPI line Time in byte
1407                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1408                  * said value is recommended.
1409                  *
1410                  * In non-burst mode, Value greater than one DPI frame time in
1411                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1412                  * said value is recommended.
1413                  *
1414                  * In DBI only mode, value greater than one DBI frame time in
1415                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1416                  * said value is recommended.
1417                  */
1418
1419                 if (is_vid_mode(intel_dsi) &&
1420                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1421                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1422                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1423                                             intel_dsi->lane_count,
1424                                             intel_dsi->burst_mode_ratio) + 1);
1425                 } else {
1426                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1427                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1428                                             adjusted_mode->crtc_htotal,
1429                                             bpp, intel_dsi->lane_count,
1430                                             intel_dsi->burst_mode_ratio) + 1);
1431                 }
1432                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1433                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1434                                                 intel_dsi->turn_arnd_val);
1435                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1436                                                 intel_dsi->rst_timer_val);
1437
1438                 /* dphy stuff */
1439
1440                 /* in terms of low power clock */
1441                 I915_WRITE(MIPI_INIT_COUNT(port),
1442                                 txclkesc(intel_dsi->escape_clk_div, 100));
1443
1444                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1445                         /*
1446                          * BXT spec says write MIPI_INIT_COUNT for
1447                          * both the ports, even if only one is
1448                          * getting used. So write the other port
1449                          * if not in dual link mode.
1450                          */
1451                         I915_WRITE(MIPI_INIT_COUNT(port ==
1452                                                 PORT_A ? PORT_C : PORT_A),
1453                                         intel_dsi->init_count);
1454                 }
1455
1456                 /* recovery disables */
1457                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1458
1459                 /* in terms of low power clock */
1460                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1461
1462                 /* in terms of txbyteclkhs. actual high to low switch +
1463                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1464                  *
1465                  * XXX: write MIPI_STOP_STATE_STALL?
1466                  */
1467                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1468                                                 intel_dsi->hs_to_lp_count);
1469
1470                 /* XXX: low power clock equivalence in terms of byte clock.
1471                  * the number of byte clocks occupied in one low power clock.
1472                  * based on txbyteclkhs and txclkesc.
1473                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1474                  * ) / 105.???
1475                  */
1476                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1477
1478                 if (IS_GEMINILAKE(dev_priv)) {
1479                         I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1480                                         intel_dsi->lp_byte_clk);
1481                         /* Shadow of DPHY reg */
1482                         I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1483                                         intel_dsi->dphy_reg);
1484                 }
1485
1486                 /* the bw essential for transmitting 16 long packets containing
1487                  * 252 bytes meant for dcs write memory command is programmed in
1488                  * this register in terms of byte clocks. based on dsi transfer
1489                  * rate and the number of lanes configured the time taken to
1490                  * transmit 16 long packets in a dsi stream varies. */
1491                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1492
1493                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1494                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1495                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1496
1497                 if (is_vid_mode(intel_dsi))
1498                         /* Some panels might have resolution which is not a
1499                          * multiple of 64 like 1366 x 768. Enable RANDOM
1500                          * resolution support for such panels by default */
1501                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1502                                 intel_dsi->video_frmt_cfg_bits |
1503                                 intel_dsi->video_mode_format |
1504                                 IP_TG_CONFIG |
1505                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1506         }
1507 }
1508
1509 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1512         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1513         enum port port;
1514         u32 val;
1515
1516         if (IS_GEMINILAKE(dev_priv))
1517                 return;
1518
1519         for_each_dsi_port(port, intel_dsi->ports) {
1520                 /* Panel commands can be sent when clock is in LP11 */
1521                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1522
1523                 if (IS_GEN9_LP(dev_priv))
1524                         bxt_dsi_reset_clocks(encoder, port);
1525                 else
1526                         vlv_dsi_reset_clocks(encoder, port);
1527                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1528
1529                 val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1530                 val &= ~VID_MODE_FORMAT_MASK;
1531                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1532
1533                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1534         }
1535 }
1536
1537 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1538 {
1539         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1540
1541         /* dispose of the gpios */
1542         if (intel_dsi->gpio_panel)
1543                 gpiod_put(intel_dsi->gpio_panel);
1544
1545         intel_encoder_destroy(encoder);
1546 }
1547
1548 static const struct drm_encoder_funcs intel_dsi_funcs = {
1549         .destroy = intel_dsi_encoder_destroy,
1550 };
1551
1552 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1553         .get_modes = intel_dsi_get_modes,
1554         .mode_valid = intel_dsi_mode_valid,
1555         .atomic_check = intel_digital_connector_atomic_check,
1556 };
1557
1558 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1559         .late_register = intel_connector_register,
1560         .early_unregister = intel_connector_unregister,
1561         .destroy = intel_connector_destroy,
1562         .fill_modes = drm_helper_probe_single_connector_modes,
1563         .atomic_get_property = intel_digital_connector_atomic_get_property,
1564         .atomic_set_property = intel_digital_connector_atomic_set_property,
1565         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1566         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1567 };
1568
1569 static enum drm_panel_orientation
1570 vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector)
1571 {
1572         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1573         struct intel_encoder *encoder = connector->encoder;
1574         enum intel_display_power_domain power_domain;
1575         enum drm_panel_orientation orientation;
1576         struct intel_plane *plane;
1577         struct intel_crtc *crtc;
1578         enum pipe pipe;
1579         u32 val;
1580
1581         if (!encoder->get_hw_state(encoder, &pipe))
1582                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1583
1584         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1585         plane = to_intel_plane(crtc->base.primary);
1586
1587         power_domain = POWER_DOMAIN_PIPE(pipe);
1588         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1589                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1590
1591         val = I915_READ(DSPCNTR(plane->i9xx_plane));
1592
1593         if (!(val & DISPLAY_PLANE_ENABLE))
1594                 orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1595         else if (val & DISPPLANE_ROTATE_180)
1596                 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1597         else
1598                 orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
1599
1600         intel_display_power_put(dev_priv, power_domain);
1601
1602         return orientation;
1603 }
1604
1605 static enum drm_panel_orientation
1606 vlv_dsi_get_panel_orientation(struct intel_connector *connector)
1607 {
1608         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1609         enum drm_panel_orientation orientation;
1610
1611         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1612                 orientation = vlv_dsi_get_hw_panel_orientation(connector);
1613                 if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
1614                         return orientation;
1615         }
1616
1617         return intel_dsi_get_panel_orientation(connector);
1618 }
1619
1620 static void intel_dsi_add_properties(struct intel_connector *connector)
1621 {
1622         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1623
1624         if (connector->panel.fixed_mode) {
1625                 u32 allowed_scalers;
1626
1627                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1628                 if (!HAS_GMCH_DISPLAY(dev_priv))
1629                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1630
1631                 drm_connector_attach_scaling_mode_property(&connector->base,
1632                                                                 allowed_scalers);
1633
1634                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1635
1636                 connector->base.display_info.panel_orientation =
1637                         vlv_dsi_get_panel_orientation(connector);
1638                 drm_connector_init_panel_orientation_property(
1639                                 &connector->base,
1640                                 connector->panel.fixed_mode->hdisplay,
1641                                 connector->panel.fixed_mode->vdisplay);
1642         }
1643 }
1644
1645 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1646 {
1647         struct drm_device *dev = &dev_priv->drm;
1648         struct intel_dsi *intel_dsi;
1649         struct intel_encoder *intel_encoder;
1650         struct drm_encoder *encoder;
1651         struct intel_connector *intel_connector;
1652         struct drm_connector *connector;
1653         struct drm_display_mode *scan, *fixed_mode = NULL;
1654         enum port port;
1655
1656         DRM_DEBUG_KMS("\n");
1657
1658         /* There is no detection method for MIPI so rely on VBT */
1659         if (!intel_bios_is_dsi_present(dev_priv, &port))
1660                 return;
1661
1662         if (IS_GEN9_LP(dev_priv))
1663                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1664         else
1665                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1666
1667         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1668         if (!intel_dsi)
1669                 return;
1670
1671         intel_connector = intel_connector_alloc();
1672         if (!intel_connector) {
1673                 kfree(intel_dsi);
1674                 return;
1675         }
1676
1677         intel_encoder = &intel_dsi->base;
1678         encoder = &intel_encoder->base;
1679         intel_dsi->attached_connector = intel_connector;
1680
1681         connector = &intel_connector->base;
1682
1683         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1684                          "DSI %c", port_name(port));
1685
1686         intel_encoder->compute_config = intel_dsi_compute_config;
1687         intel_encoder->pre_enable = intel_dsi_pre_enable;
1688         intel_encoder->disable = intel_dsi_disable;
1689         intel_encoder->post_disable = intel_dsi_post_disable;
1690         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1691         intel_encoder->get_config = intel_dsi_get_config;
1692
1693         intel_connector->get_hw_state = intel_connector_get_hw_state;
1694
1695         intel_encoder->port = port;
1696
1697         /*
1698          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1699          * port C. BXT isn't limited like this.
1700          */
1701         if (IS_GEN9_LP(dev_priv))
1702                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1703         else if (port == PORT_A)
1704                 intel_encoder->crtc_mask = BIT(PIPE_A);
1705         else
1706                 intel_encoder->crtc_mask = BIT(PIPE_B);
1707
1708         if (dev_priv->vbt.dsi.config->dual_link)
1709                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1710         else
1711                 intel_dsi->ports = BIT(port);
1712
1713         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1714         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1715
1716         /* Create a DSI host (and a device) for each port. */
1717         for_each_dsi_port(port, intel_dsi->ports) {
1718                 struct intel_dsi_host *host;
1719
1720                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1721                                            port);
1722                 if (!host)
1723                         goto err;
1724
1725                 intel_dsi->dsi_hosts[port] = host;
1726         }
1727
1728         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1729                 DRM_DEBUG_KMS("no device found\n");
1730                 goto err;
1731         }
1732
1733         /*
1734          * In case of BYT with CRC PMIC, we need to use GPIO for
1735          * Panel control.
1736          */
1737         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1738             (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1739                 intel_dsi->gpio_panel =
1740                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1741
1742                 if (IS_ERR(intel_dsi->gpio_panel)) {
1743                         DRM_ERROR("Failed to own gpio for panel control\n");
1744                         intel_dsi->gpio_panel = NULL;
1745                 }
1746         }
1747
1748         intel_encoder->type = INTEL_OUTPUT_DSI;
1749         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1750         intel_encoder->cloneable = 0;
1751         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1752                            DRM_MODE_CONNECTOR_DSI);
1753
1754         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1755
1756         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1757         connector->interlace_allowed = false;
1758         connector->doublescan_allowed = false;
1759
1760         intel_connector_attach_encoder(intel_connector, intel_encoder);
1761
1762         mutex_lock(&dev->mode_config.mutex);
1763         intel_dsi_vbt_get_modes(intel_dsi);
1764         list_for_each_entry(scan, &connector->probed_modes, head) {
1765                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1766                         fixed_mode = drm_mode_duplicate(dev, scan);
1767                         break;
1768                 }
1769         }
1770         mutex_unlock(&dev->mode_config.mutex);
1771
1772         if (!fixed_mode) {
1773                 DRM_DEBUG_KMS("no fixed mode\n");
1774                 goto err;
1775         }
1776
1777         connector->display_info.width_mm = fixed_mode->width_mm;
1778         connector->display_info.height_mm = fixed_mode->height_mm;
1779
1780         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1781         intel_panel_setup_backlight(connector, INVALID_PIPE);
1782
1783         intel_dsi_add_properties(intel_connector);
1784
1785         return;
1786
1787 err:
1788         drm_encoder_cleanup(&intel_encoder->base);
1789         kfree(intel_dsi);
1790         kfree(intel_connector);
1791 }