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25 #include "../i915_selftest.h"
27 static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
28 unsigned int num_ranges,
34 for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
35 /* Check that the table is watertight */
36 if (is_watertight && (prev + 1) != (s32)ranges->start) {
37 pr_err("%s: entry[%d]:(%x, %x) is not watertight to previous (%x)\n",
38 __func__, i, ranges->start, ranges->end, prev);
42 /* Check that the table never goes backwards */
43 if (prev >= (s32)ranges->start) {
44 pr_err("%s: entry[%d]:(%x, %x) is less than the previous (%x)\n",
45 __func__, i, ranges->start, ranges->end, prev);
49 /* Check that the entry is valid */
50 if (ranges->start >= ranges->end) {
51 pr_err("%s: entry[%d]:(%x, %x) has negative length\n",
52 __func__, i, ranges->start, ranges->end);
62 static int intel_shadow_table_check(void)
65 const i915_reg_t *regs;
68 { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
69 { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
71 const i915_reg_t *reg;
75 for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
76 reg = reg_lists[j].regs;
77 for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
78 u32 offset = i915_mmio_reg_offset(*reg);
80 if (prev >= (s32)offset) {
81 pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
82 __func__, i, offset, prev);
93 int intel_uncore_mock_selftests(void)
96 const struct intel_forcewake_range *ranges;
97 unsigned int num_ranges;
100 { __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
101 { __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
102 { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
103 { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
107 for (i = 0; i < ARRAY_SIZE(fw); i++) {
108 err = intel_fw_table_check(fw[i].ranges,
110 fw[i].is_watertight);
115 err = intel_shadow_table_check();
122 static int live_forcewake_ops(void *arg)
124 static const struct reg {
126 unsigned long platforms;
131 INTEL_GEN_MASK(6, 7),
136 INTEL_GEN_MASK(8, BITS_PER_LONG),
141 struct drm_i915_private *i915 = arg;
142 struct intel_uncore_forcewake_domain *domain;
143 struct intel_uncore *uncore = &i915->uncore;
144 struct intel_engine_cs *engine;
145 enum intel_engine_id id;
146 intel_wakeref_t wakeref;
150 GEM_BUG_ON(i915->gt.awake);
152 /* vlv/chv with their pcu behave differently wrt reads */
153 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
154 pr_debug("PCU fakes forcewake badly; skipping\n");
158 /* We have to pick carefully to get the exact behaviour we need */
159 for (r = registers; r->name; r++)
160 if (r->platforms & INTEL_INFO(i915)->gen_mask)
163 pr_debug("Forcewaked register not known for %s; skipping\n",
164 intel_platform_name(INTEL_INFO(i915)->platform));
168 wakeref = intel_runtime_pm_get(i915);
170 for_each_fw_domain(domain, uncore, tmp) {
171 smp_store_mb(domain->active, false);
172 if (!hrtimer_cancel(&domain->timer))
175 intel_uncore_fw_release_timer(&domain->timer);
178 for_each_engine(engine, i915, id) {
179 i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
180 u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset;
181 enum forcewake_domains fw_domains;
184 if (!engine->default_state)
187 fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio,
192 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
193 if (!domain->wake_count)
196 pr_err("fw_domain %s still active, aborting test!\n",
197 intel_uncore_forcewake_domain_to_str(domain->id));
202 intel_uncore_forcewake_get(uncore, fw_domains);
204 intel_uncore_forcewake_put(uncore, fw_domains);
206 /* Flush the forcewake release (delayed onto a timer) */
207 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
208 smp_store_mb(domain->active, false);
209 if (hrtimer_cancel(&domain->timer))
210 intel_uncore_fw_release_timer(&domain->timer);
213 err = wait_ack_clear(domain, FORCEWAKE_KERNEL);
216 pr_err("Failed to clear fw_domain %s\n",
217 intel_uncore_forcewake_domain_to_str(domain->id));
223 pr_err("%s:%s was zero while fw was held!\n",
224 engine->name, r->name);
229 /* We then expect the read to return 0 outside of the fw */
230 if (wait_for(readl(reg) == 0, 100)) {
231 pr_err("%s:%s=%0x, fw_domains 0x%x still up after 100ms!\n",
232 engine->name, r->name, readl(reg), fw_domains);
239 intel_runtime_pm_put(i915, wakeref);
243 static int live_forcewake_domains(void *arg)
245 #define FW_RANGE 0x40000
246 struct drm_i915_private *dev_priv = arg;
247 struct intel_uncore *uncore = &dev_priv->uncore;
248 unsigned long *valid;
252 if (!HAS_FPGA_DBG_UNCLAIMED(dev_priv) &&
253 !IS_VALLEYVIEW(dev_priv) &&
254 !IS_CHERRYVIEW(dev_priv))
258 * This test may lockup the machine or cause GPU hangs afterwards.
260 if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
263 valid = bitmap_zalloc(FW_RANGE, GFP_KERNEL);
267 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
269 check_for_unclaimed_mmio(uncore);
270 for (offset = 0; offset < FW_RANGE; offset += 4) {
271 i915_reg_t reg = { offset };
273 (void)I915_READ_FW(reg);
274 if (!check_for_unclaimed_mmio(uncore))
275 set_bit(offset, valid);
278 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
281 for_each_set_bit(offset, valid, FW_RANGE) {
282 i915_reg_t reg = { offset };
284 iosf_mbi_punit_acquire();
285 intel_uncore_forcewake_reset(uncore);
286 iosf_mbi_punit_release();
288 check_for_unclaimed_mmio(uncore);
290 (void)I915_READ(reg);
291 if (check_for_unclaimed_mmio(uncore)) {
292 pr_err("Unclaimed mmio read to register 0x%04x\n",
302 int intel_uncore_live_selftests(struct drm_i915_private *i915)
304 static const struct i915_subtest tests[] = {
305 SUBTEST(live_forcewake_ops),
306 SUBTEST(live_forcewake_domains),
311 /* Confirm the table we load is still valid */
312 err = intel_fw_table_check(i915->uncore.fw_domains_table,
313 i915->uncore.fw_domains_table_entries,
314 INTEL_GEN(i915) >= 9);
318 return i915_subtests(tests, i915);