2 * SPDX-License-Identifier: MIT
4 * Copyright © 2017-2018 Intel Corporation
7 #include "intel_wopcm.h"
13 * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
14 * offset registers whose values are calculated and determined by HuC/GuC
15 * firmware size and set of hardware requirements/restrictions as shown below:
19 * +=========> +====================+ <== WOPCM Top
20 * ^ | HW contexts RSVD |
21 * | +===> +====================+ <== GuC WOPCM Top
27 * | Size +--------------------+
28 * WOPCM | | GuC FW RSVD |
29 * | | +--------------------+
30 * | | | GuC Stack RSVD |
31 * | | +------------------- +
32 * | v | GuC WOPCM RSVD |
33 * | +===> +====================+ <== GuC WOPCM base
35 * | +------------------- + <== HuC Firmware Top
37 * +=========> +====================+ <== WOPCM Base
39 * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top.
40 * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6
44 /* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */
45 #define GEN11_WOPCM_SIZE SZ_2M
46 #define GEN9_WOPCM_SIZE SZ_1M
47 /* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
48 #define WOPCM_RESERVED_SIZE SZ_16K
50 /* 16KB reserved at the beginning of GuC WOPCM. */
51 #define GUC_WOPCM_RESERVED SZ_16K
52 /* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
53 #define GUC_WOPCM_STACK_RESERVED SZ_8K
55 /* GuC WOPCM Offset value needs to be aligned to 16KB. */
56 #define GUC_WOPCM_OFFSET_ALIGNMENT (1UL << GUC_WOPCM_OFFSET_SHIFT)
58 /* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
59 #define BXT_WOPCM_RC6_CTX_RESERVED (SZ_16K + SZ_8K)
60 /* 36KB WOPCM reserved at the end of WOPCM on CNL. */
61 #define CNL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K)
63 /* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
64 #define GEN9_GUC_FW_RESERVED SZ_128K
65 #define GEN9_GUC_WOPCM_OFFSET (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)
68 * intel_wopcm_init_early() - Early initialization of the WOPCM.
69 * @wopcm: pointer to intel_wopcm.
71 * Setup the size of WOPCM which will be used by later on WOPCM partitioning.
73 void intel_wopcm_init_early(struct intel_wopcm *wopcm)
75 struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
80 if (INTEL_GEN(i915) >= 11)
81 wopcm->size = GEN11_WOPCM_SIZE;
83 wopcm->size = GEN9_WOPCM_SIZE;
85 DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
88 static inline u32 context_reserved_size(struct drm_i915_private *i915)
91 return BXT_WOPCM_RC6_CTX_RESERVED;
92 else if (INTEL_GEN(i915) >= 10)
93 return CNL_WOPCM_HW_CTX_RESERVED;
98 static inline int gen9_check_dword_gap(u32 guc_wopcm_base, u32 guc_wopcm_size)
103 * GuC WOPCM size shall be at least a dword larger than the offset from
104 * WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET)
105 * due to hardware limitation on Gen9.
107 offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;
108 if (offset > guc_wopcm_size ||
109 (guc_wopcm_size - offset) < sizeof(u32)) {
110 DRM_ERROR("GuC WOPCM size %uKiB is too small. %uKiB needed.\n",
111 guc_wopcm_size / 1024,
112 (u32)(offset + sizeof(u32)) / 1024);
119 static inline int gen9_check_huc_fw_fits(u32 guc_wopcm_size, u32 huc_fw_size)
122 * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
123 * size to be larger than or equal to HuC firmware size. Otherwise,
124 * firmware uploading would fail.
126 if (huc_fw_size > guc_wopcm_size - GUC_WOPCM_RESERVED) {
127 DRM_ERROR("HuC FW (%uKiB) won't fit in GuC WOPCM (%uKiB).\n",
129 (guc_wopcm_size - GUC_WOPCM_RESERVED) / 1024);
136 static inline int check_hw_restriction(struct drm_i915_private *i915,
137 u32 guc_wopcm_base, u32 guc_wopcm_size,
143 err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
146 (IS_GEN(i915, 9) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
147 err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
153 * intel_wopcm_init() - Initialize the WOPCM structure.
154 * @wopcm: pointer to intel_wopcm.
156 * This function will partition WOPCM space based on GuC and HuC firmware sizes
157 * and will allocate max remaining for use by GuC. This function will also
158 * enforce platform dependent hardware restrictions on GuC WOPCM offset and
159 * size. It will fail the WOPCM init if any of these checks were failed, so that
160 * the following GuC firmware uploading would be aborted.
162 * Return: 0 on success, non-zero error code on failure.
164 int intel_wopcm_init(struct intel_wopcm *wopcm)
166 struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
167 u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw);
168 u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw);
169 u32 ctx_rsvd = context_reserved_size(i915);
178 GEM_BUG_ON(!wopcm->size);
180 if (i915_inject_load_failure())
183 if (guc_fw_size >= wopcm->size) {
184 DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
189 if (huc_fw_size >= wopcm->size) {
190 DRM_ERROR("HuC FW (%uKiB) is too big to fit in WOPCM.",
195 guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
196 GUC_WOPCM_OFFSET_ALIGNMENT);
197 if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
198 DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
199 guc_wopcm_base / 1024);
203 guc_wopcm_size = wopcm->size - guc_wopcm_base - ctx_rsvd;
204 guc_wopcm_size &= GUC_WOPCM_SIZE_MASK;
206 DRM_DEBUG_DRIVER("Calculated GuC WOPCM Region: [%uKiB, %uKiB)\n",
207 guc_wopcm_base / 1024, guc_wopcm_size / 1024);
209 guc_wopcm_rsvd = GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
210 if ((guc_fw_size + guc_wopcm_rsvd) > guc_wopcm_size) {
211 DRM_ERROR("Need %uKiB WOPCM for GuC, %uKiB available.\n",
212 (guc_fw_size + guc_wopcm_rsvd) / 1024,
213 guc_wopcm_size / 1024);
217 err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size,
222 wopcm->guc.base = guc_wopcm_base;
223 wopcm->guc.size = guc_wopcm_size;
228 static inline int write_and_verify(struct drm_i915_private *dev_priv,
229 i915_reg_t reg, u32 val, u32 mask,
234 GEM_BUG_ON(val & ~mask);
236 I915_WRITE(reg, val);
238 reg_val = I915_READ(reg);
240 return (reg_val & mask) != (val | locked_bit) ? -EIO : 0;
244 * intel_wopcm_init_hw() - Setup GuC WOPCM registers.
245 * @wopcm: pointer to intel_wopcm.
247 * Setup the GuC WOPCM size and offset registers with the calculated values. It
248 * will verify the register values to make sure the registers are locked with
251 * Return: 0 on success. -EIO if registers were locked with incorrect values.
253 int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
255 struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
260 if (!USES_GUC(dev_priv))
263 GEM_BUG_ON(!HAS_GUC(dev_priv));
264 GEM_BUG_ON(!wopcm->guc.size);
265 GEM_BUG_ON(!wopcm->guc.base);
267 err = write_and_verify(dev_priv, GUC_WOPCM_SIZE, wopcm->guc.size,
268 GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED,
269 GUC_WOPCM_SIZE_LOCKED);
273 huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
274 mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
275 err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
276 wopcm->guc.base | huc_agent, mask,
277 GUC_WOPCM_OFFSET_VALID);
284 DRM_ERROR("Failed to init WOPCM registers:\n");
285 DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
286 I915_READ(DMA_GUC_WOPCM_OFFSET));
287 DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));