drivers/gpu/drm/i915/intel_vdsc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
   6  *         Manasi Navare <manasi.d.navare@intel.com>
   7  */
   8
   9 #include <drm/i915_drm.h>
  10 #include "i915_drv.h"
  11 #include "intel_drv.h"
  12
  13 enum ROW_INDEX_BPP {
  14         ROW_INDEX_6BPP = 0,
  15         ROW_INDEX_8BPP,
  16         ROW_INDEX_10BPP,
  17         ROW_INDEX_12BPP,
  18         ROW_INDEX_15BPP,
  19         MAX_ROW_INDEX
  20 };
  21
  22 enum COLUMN_INDEX_BPC {
  23         COLUMN_INDEX_8BPC = 0,
  24         COLUMN_INDEX_10BPC,
  25         COLUMN_INDEX_12BPC,
  26         COLUMN_INDEX_14BPC,
  27         COLUMN_INDEX_16BPC,
  28         MAX_COLUMN_INDEX
  29 };
  30
  31 #define DSC_SUPPORTED_VERSION_MIN               1
  32
  33 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
  34 static u16 rc_buf_thresh[] = {
  35         896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
  36         7744, 7872, 8000, 8064
  37 };
  38
  39 struct rc_parameters {
  40         u16 initial_xmit_delay;
  41         u8 first_line_bpg_offset;
  42         u16 initial_offset;
  43         u8 flatness_min_qp;
  44         u8 flatness_max_qp;
  45         u8 rc_quant_incr_limit0;
  46         u8 rc_quant_incr_limit1;
  47         struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
  48 };
  49
  50 /*
  51  * Selected Rate Control Related Parameter Recommended Values
  52  * from DSC_v1.11 spec & C Model release: DSC_model_20161212
  53  */
  54 static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = {
  55 {
  56         /* 6BPP/8BPC */
  57         { 768, 15, 6144, 3, 13, 11, 11, {
  58                 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
  59                 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
  60                 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
  61                 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
  62                 }
  63         },
  64         /* 6BPP/10BPC */
  65         { 768, 15, 6144, 7, 17, 15, 15, {
  66                 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
  67                 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
  68                 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
  69                 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
  70                 { 17, 18, -12 }
  71                 }
  72         },
  73         /* 6BPP/12BPC */
  74         { 768, 15, 6144, 11, 21, 19, 19, {
  75                 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
  76                 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
  77                 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
  78                 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
  79                 { 21, 22, -12 }
  80                 }
  81         },
  82         /* 6BPP/14BPC */
  83         { 768, 15, 6144, 15, 25, 23, 27, {
  84                 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
  85                 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
  86                 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
  87                 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
  88                 { 25, 26, -12 }
  89                 }
  90         },
  91         /* 6BPP/16BPC */
  92         { 768, 15, 6144, 19, 29, 27, 27, {
  93                 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
  94                 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
  95                 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
  96                 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
  97                 { 29, 30, -12 }
  98                 }
  99         },
 100 },
 101 {
 102         /* 8BPP/8BPC */
 103         { 512, 12, 6144, 3, 12, 11, 11, {
 104                 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 105                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 106                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
 107                 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 108                 }
 109         },
 110         /* 8BPP/10BPC */
 111         { 512, 12, 6144, 7, 16, 15, 15, {
 112                 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
 113                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 114                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 115                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 116                 }
 117         },
 118         /* 8BPP/12BPC */
 119         { 512, 12, 6144, 11, 20, 19, 19, {
 120                 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
 121                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 122                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 123                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 124                 { 21, 23, -12 }
 125                 }
 126         },
 127         /* 8BPP/14BPC */
 128         { 512, 12, 6144, 15, 24, 23, 23, {
 129                 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
 130                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 131                 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
 132                 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
 133                 { 24, 25, -12 }
 134                 }
 135         },
 136         /* 8BPP/16BPC */
 137         { 512, 12, 6144, 19, 28, 27, 27, {
 138                 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
 139                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 140                 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
 141                 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
 142                 { 28, 29, -12 }
 143                 }
 144         },
 145 },
 146 {
 147         /* 10BPP/8BPC */
 148         { 410, 15, 5632, 3, 12, 11, 11, {
 149                 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
 150                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 151                 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
 152                 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
 153                 }
 154         },
 155         /* 10BPP/10BPC */
 156         { 410, 15, 5632, 7, 16, 15, 15, {
 157                 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
 158                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 159                 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
 160                 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
 161                 }
 162         },
 163         /* 10BPP/12BPC */
 164         { 410, 15, 5632, 11, 20, 19, 19, {
 165                 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
 166                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 167                 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
 168                 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
 169                 { 19, 20, -12 }
 170                 }
 171         },
 172         /* 10BPP/14BPC */
 173         { 410, 15, 5632, 15, 24, 23, 23, {
 174                 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
 175                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 176                 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
 177                 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
 178                 { 23, 24, -12 }
 179                 }
 180         },
 181         /* 10BPP/16BPC */
 182         { 410, 15, 5632, 19, 28, 27, 27, {
 183                 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
 184                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 185                 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
 186                 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
 187                 { 27, 28, -12 }
 188                 }
 189         },
 190 },
 191 {
 192         /* 12BPP/8BPC */
 193         { 341, 15, 2048, 3, 12, 11, 11, {
 194                 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 195                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 196                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
 197                 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 198                 }
 199         },
 200         /* 12BPP/10BPC */
 201         { 341, 15, 2048, 7, 16, 15, 15, {
 202                 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
 203                 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 204                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 205                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 206                 }
 207         },
 208         /* 12BPP/12BPC */
 209         { 341, 15, 2048, 11, 20, 19, 19, {
 210                 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
 211                 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 212                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 213                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 214                 { 21, 23, -12 }
 215                 }
 216         },
 217         /* 12BPP/14BPC */
 218         { 341, 15, 2048, 15, 24, 23, 23, {
 219                 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
 220                 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 221                 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
 222                 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
 223                 { 22, 23, -12 }
 224                 }
 225         },
 226         /* 12BPP/16BPC */
 227         { 341, 15, 2048, 19, 28, 27, 27, {
 228                 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
 229                 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 230                 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
 231                 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
 232                 { 26, 27, -12 }
 233                 }
 234         },
 235 },
 236 {
 237         /* 15BPP/8BPC */
 238         { 273, 15, 2048, 3, 12, 11, 11, {
 239                 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
 240                 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
 241                 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
 242                 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
 243                 }
 244         },
 245         /* 15BPP/10BPC */
 246         { 273, 15, 2048, 7, 16, 15, 15, {
 247                 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
 248                 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
 249                 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
 250                 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
 251                 }
 252         },
 253         /* 15BPP/12BPC */
 254         { 273, 15, 2048, 11, 20, 19, 19, {
 255                 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
 256                 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
 257                 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
 258                 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
 259                 { 16, 17, -12 }
 260                 }
 261         },
 262         /* 15BPP/14BPC */
 263         { 273, 15, 2048, 15, 24, 23, 23, {
 264                 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
 265                 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
 266                 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
 267                 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
 268                 { 20, 21, -12 }
 269                 }
 270         },
 271         /* 15BPP/16BPC */
 272         { 273, 15, 2048, 19, 28, 27, 27, {
 273                 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
 274                 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
 275                 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
 276                 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
 277                 { 24, 25, -12 }
 278                 }
 279         }
 280 }
 281
 282 };
 283
 284 static int get_row_index_for_rc_params(u16 compressed_bpp)
 285 {
 286         switch (compressed_bpp) {
 287         case 6:
 288                 return ROW_INDEX_6BPP;
 289         case 8:
 290                 return ROW_INDEX_8BPP;
 291         case 10:
 292                 return ROW_INDEX_10BPP;
 293         case 12:
 294                 return ROW_INDEX_12BPP;
 295         case 15:
 296                 return ROW_INDEX_15BPP;
 297         default:
 298                 return -EINVAL;
 299         }
 300 }
 301
 302 static int get_column_index_for_rc_params(u8 bits_per_component)
 303 {
 304         switch (bits_per_component) {
 305         case 8:
 306                 return COLUMN_INDEX_8BPC;
 307         case 10:
 308                 return COLUMN_INDEX_10BPC;
 309         case 12:
 310                 return COLUMN_INDEX_12BPC;
 311         case 14:
 312                 return COLUMN_INDEX_14BPC;
 313         case 16:
 314                 return COLUMN_INDEX_16BPC;
 315         default:
 316                 return -EINVAL;
 317         }
 318 }
 319
 320 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 321                                 struct intel_crtc_state *pipe_config)
 322 {
 323         struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
 324         u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;
 325         u8 i = 0;
 326         int row_index = 0;
 327         int column_index = 0;
 328         u8 line_buf_depth = 0;
 329
 330         vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
 331         vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
 332         vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 333                                              pipe_config->dsc_params.slice_count);
 334         /*
 335          * Slice Height of 8 works for all currently available panels. So start
 336          * with that if pic_height is an integral multiple of 8.
 337          * Eventually add logic to try multiple slice heights.
 338          */
 339         if (vdsc_cfg->pic_height % 8 == 0)
 340                 vdsc_cfg->slice_height = 8;
 341         else if (vdsc_cfg->pic_height % 4 == 0)
 342                 vdsc_cfg->slice_height = 4;
 343         else
 344                 vdsc_cfg->slice_height = 2;
 345
 346         /* Values filled from DSC Sink DPCD */
 347         vdsc_cfg->dsc_version_major =
 348                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 349                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
 350         vdsc_cfg->dsc_version_minor =
 351                 min(DSC_SUPPORTED_VERSION_MIN,
 352                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 353                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
 354
 355         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
 356                 DP_DSC_RGB;
 357
 358         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 359         if (!line_buf_depth) {
 360                 DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
 361                 return -EINVAL;
 362         }
 363         if (vdsc_cfg->dsc_version_minor == 2)
 364                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
 365                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
 366         else
 367                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
 368                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
 369
 370         /* Gen 11 does not support YCbCr */
 371         vdsc_cfg->simple_422 = false;
 372         /* Gen 11 does not support VBR */
 373         vdsc_cfg->vbr_enable = false;
 374         vdsc_cfg->block_pred_enable =
 375                         intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
 376                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
 377
 378         /* Gen 11 only supports integral values of bpp */
 379         vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
 380         vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 381
 382         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 383                 /*
 384                  * six 0s are appended to the lsb of each threshold value
 385                  * internally in h/w.
 386                  * Only 8 bits are allowed for programming RcBufThreshold
 387                  */
 388                 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
 389         }
 390
 391         /*
 392          * For 6bpp, RC Buffer threshold 12 and 13 need a different value
 393          * as per C Model
 394          */
 395         if (compressed_bpp == 6) {
 396                 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
 397                 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
 398         }
 399
 400         row_index = get_row_index_for_rc_params(compressed_bpp);
 401         column_index =
 402                 get_column_index_for_rc_params(vdsc_cfg->bits_per_component);
 403
 404         if (row_index < 0 || column_index < 0)
 405                 return -EINVAL;
 406
 407         vdsc_cfg->first_line_bpg_offset =
 408                 rc_params[row_index][column_index].first_line_bpg_offset;
 409         vdsc_cfg->initial_xmit_delay =
 410                 rc_params[row_index][column_index].initial_xmit_delay;
 411         vdsc_cfg->initial_offset =
 412                 rc_params[row_index][column_index].initial_offset;
 413         vdsc_cfg->flatness_min_qp =
 414                 rc_params[row_index][column_index].flatness_min_qp;
 415         vdsc_cfg->flatness_max_qp =
 416                 rc_params[row_index][column_index].flatness_max_qp;
 417         vdsc_cfg->rc_quant_incr_limit0 =
 418                 rc_params[row_index][column_index].rc_quant_incr_limit0;
 419         vdsc_cfg->rc_quant_incr_limit1 =
 420                 rc_params[row_index][column_index].rc_quant_incr_limit1;
 421
 422         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 423                 vdsc_cfg->rc_range_params[i].range_min_qp =
 424                         rc_params[row_index][column_index].rc_range_params[i].range_min_qp;
 425                 vdsc_cfg->rc_range_params[i].range_max_qp =
 426                         rc_params[row_index][column_index].rc_range_params[i].range_max_qp;
 427                 /*
 428                  * Range BPG Offset uses 2's complement and is only a 6 bits. So
 429                  * mask it to get only 6 bits.
 430                  */
 431                 vdsc_cfg->rc_range_params[i].range_bpg_offset =
 432                         rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset &
 433                         DSC_RANGE_BPG_OFFSET_MASK;
 434         }
 435
 436         /*
 437          * BitsPerComponent value determines mux_word_size:
 438          * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
 439          * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
 440          * 48 bits
 441          */
 442         if (vdsc_cfg->bits_per_component == 8 ||
 443             vdsc_cfg->bits_per_component == 10)
 444                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
 445         else if (vdsc_cfg->bits_per_component == 12)
 446                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
 447
 448         /* RC_MODEL_SIZE is a constant across all configurations */
 449         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 450         /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
 451         vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 452                 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 453
 454         return drm_dsc_compute_rc_parameters(vdsc_cfg);
 455 }
 456
 457 enum intel_display_power_domain
 458 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 459 {
 460         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 461
 462         /*
 463          * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
 464          * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
 465          * For any other transcoder, VDSC/joining uses the power well associated
 466          * with the pipe/transcoder in use. Hence another reference on the
 467          * transcoder power domain will suffice.
 468          */
 469         if (cpu_transcoder == TRANSCODER_EDP)
 470                 return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
 471         else
 472                 return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 473 }
 474
 475 static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 476                                                 const struct intel_crtc_state *crtc_state)
 477 {
 478         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 479         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 480         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
 481         enum pipe pipe = crtc->pipe;
 482         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 483         u32 pps_val = 0;
 484         u32 rc_buf_thresh_dword[4];
 485         u32 rc_range_params_dword[8];
 486         u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
 487         int i = 0;
 488
 489         /* Populate PICTURE_PARAMETER_SET_0 registers */
 490         pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
 491                 DSC_VER_MIN_SHIFT |
 492                 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 493                 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
 494         if (vdsc_cfg->block_pred_enable)
 495                 pps_val |= DSC_BLOCK_PREDICTION;
 496         if (vdsc_cfg->convert_rgb)
 497                 pps_val |= DSC_COLOR_SPACE_CONVERSION;
 498         if (vdsc_cfg->simple_422)
 499                 pps_val |= DSC_422_ENABLE;
 500         if (vdsc_cfg->vbr_enable)
 501                 pps_val |= DSC_VBR_ENABLE;
 502         DRM_INFO("PPS0 = 0x%08x\n", pps_val);
 503         if (cpu_transcoder == TRANSCODER_EDP) {
 504                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
 505                 /*
 506                  * If 2 VDSC instances are needed, configure PPS for second
 507                  * VDSC
 508                  */
 509                 if (crtc_state->dsc_params.dsc_split)
 510                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
 511         } else {
 512                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
 513                 if (crtc_state->dsc_params.dsc_split)
 514                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
 515                                    pps_val);
 516         }
 517
 518         /* Populate PICTURE_PARAMETER_SET_1 registers */
 519         pps_val = 0;
 520         pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
 521         DRM_INFO("PPS1 = 0x%08x\n", pps_val);
 522         if (cpu_transcoder == TRANSCODER_EDP) {
 523                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
 524                 /*
 525                  * If 2 VDSC instances are needed, configure PPS for second
 526                  * VDSC
 527                  */
 528                 if (crtc_state->dsc_params.dsc_split)
 529                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
 530         } else {
 531                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
 532                 if (crtc_state->dsc_params.dsc_split)
 533                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
 534                                    pps_val);
 535         }
 536
 537         /* Populate PICTURE_PARAMETER_SET_2 registers */
 538         pps_val = 0;
 539         pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 540                 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 541         DRM_INFO("PPS2 = 0x%08x\n", pps_val);
 542         if (encoder->type == INTEL_OUTPUT_EDP) {
 543                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
 544                 /*
 545                  * If 2 VDSC instances are needed, configure PPS for second
 546                  * VDSC
 547                  */
 548                 if (crtc_state->dsc_params.dsc_split)
 549                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
 550         } else {
 551                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
 552                 if (crtc_state->dsc_params.dsc_split)
 553                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
 554                                    pps_val);
 555         }
 556
 557         /* Populate PICTURE_PARAMETER_SET_3 registers */
 558         pps_val = 0;
 559         pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 560                 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 561         DRM_INFO("PPS3 = 0x%08x\n", pps_val);
 562         if (cpu_transcoder == TRANSCODER_EDP) {
 563                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
 564                 /*
 565                  * If 2 VDSC instances are needed, configure PPS for second
 566                  * VDSC
 567                  */
 568                 if (crtc_state->dsc_params.dsc_split)
 569                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
 570         } else {
 571                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
 572                 if (crtc_state->dsc_params.dsc_split)
 573                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
 574                                    pps_val);
 575         }
 576
 577         /* Populate PICTURE_PARAMETER_SET_4 registers */
 578         pps_val = 0;
 579         pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 580                 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 581         DRM_INFO("PPS4 = 0x%08x\n", pps_val);
 582         if (cpu_transcoder == TRANSCODER_EDP) {
 583                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
 584                 /*
 585                  * If 2 VDSC instances are needed, configure PPS for second
 586                  * VDSC
 587                  */
 588                 if (crtc_state->dsc_params.dsc_split)
 589                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
 590         } else {
 591                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
 592                 if (crtc_state->dsc_params.dsc_split)
 593                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
 594                                    pps_val);
 595         }
 596
 597         /* Populate PICTURE_PARAMETER_SET_5 registers */
 598         pps_val = 0;
 599         pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 600                 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 601         DRM_INFO("PPS5 = 0x%08x\n", pps_val);
 602         if (cpu_transcoder == TRANSCODER_EDP) {
 603                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
 604                 /*
 605                  * If 2 VDSC instances are needed, configure PPS for second
 606                  * VDSC
 607                  */
 608                 if (crtc_state->dsc_params.dsc_split)
 609                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
 610         } else {
 611                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
 612                 if (crtc_state->dsc_params.dsc_split)
 613                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
 614                                    pps_val);
 615         }
 616
 617         /* Populate PICTURE_PARAMETER_SET_6 registers */
 618         pps_val = 0;
 619         pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
 620                 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
 621                 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 622                 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 623         DRM_INFO("PPS6 = 0x%08x\n", pps_val);
 624         if (cpu_transcoder == TRANSCODER_EDP) {
 625                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
 626                 /*
 627                  * If 2 VDSC instances are needed, configure PPS for second
 628                  * VDSC
 629                  */
 630                 if (crtc_state->dsc_params.dsc_split)
 631                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
 632         } else {
 633                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
 634                 if (crtc_state->dsc_params.dsc_split)
 635                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
 636                                    pps_val);
 637         }
 638
 639         /* Populate PICTURE_PARAMETER_SET_7 registers */
 640         pps_val = 0;
 641         pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 642                 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 643         DRM_INFO("PPS7 = 0x%08x\n", pps_val);
 644         if (cpu_transcoder == TRANSCODER_EDP) {
 645                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
 646                 /*
 647                  * If 2 VDSC instances are needed, configure PPS for second
 648                  * VDSC
 649                  */
 650                 if (crtc_state->dsc_params.dsc_split)
 651                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
 652         } else {
 653                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
 654                 if (crtc_state->dsc_params.dsc_split)
 655                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
 656                                    pps_val);
 657         }
 658
 659         /* Populate PICTURE_PARAMETER_SET_8 registers */
 660         pps_val = 0;
 661         pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 662                 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 663         DRM_INFO("PPS8 = 0x%08x\n", pps_val);
 664         if (cpu_transcoder == TRANSCODER_EDP) {
 665                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
 666                 /*
 667                  * If 2 VDSC instances are needed, configure PPS for second
 668                  * VDSC
 669                  */
 670                 if (crtc_state->dsc_params.dsc_split)
 671                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
 672         } else {
 673                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
 674                 if (crtc_state->dsc_params.dsc_split)
 675                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
 676                                    pps_val);
 677         }
 678
 679         /* Populate PICTURE_PARAMETER_SET_9 registers */
 680         pps_val = 0;
 681         pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
 682                 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 683         DRM_INFO("PPS9 = 0x%08x\n", pps_val);
 684         if (cpu_transcoder == TRANSCODER_EDP) {
 685                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
 686                 /*
 687                  * If 2 VDSC instances are needed, configure PPS for second
 688                  * VDSC
 689                  */
 690                 if (crtc_state->dsc_params.dsc_split)
 691                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
 692         } else {
 693                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
 694                 if (crtc_state->dsc_params.dsc_split)
 695                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
 696                                    pps_val);
 697         }
 698
 699         /* Populate PICTURE_PARAMETER_SET_10 registers */
 700         pps_val = 0;
 701         pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
 702                 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
 703                 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 704                 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 705         DRM_INFO("PPS10 = 0x%08x\n", pps_val);
 706         if (cpu_transcoder == TRANSCODER_EDP) {
 707                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
 708                 /*
 709                  * If 2 VDSC instances are needed, configure PPS for second
 710                  * VDSC
 711                  */
 712                 if (crtc_state->dsc_params.dsc_split)
 713                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
 714         } else {
 715                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
 716                 if (crtc_state->dsc_params.dsc_split)
 717                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
 718                                    pps_val);
 719         }
 720
 721         /* Populate Picture parameter set 16 */
 722         pps_val = 0;
 723         pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
 724                 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
 725                                    vdsc_cfg->slice_width) |
 726                 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
 727                                         vdsc_cfg->slice_height);
 728         DRM_INFO("PPS16 = 0x%08x\n", pps_val);
 729         if (cpu_transcoder == TRANSCODER_EDP) {
 730                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
 731                 /*
 732                  * If 2 VDSC instances are needed, configure PPS for second
 733                  * VDSC
 734                  */
 735                 if (crtc_state->dsc_params.dsc_split)
 736                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
 737         } else {
 738                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
 739                 if (crtc_state->dsc_params.dsc_split)
 740                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
 741                                    pps_val);
 742         }
 743
 744         /* Populate the RC_BUF_THRESH registers */
 745         memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 746         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 747                 rc_buf_thresh_dword[i / 4] |=
 748                         (u32)(vdsc_cfg->rc_buf_thresh[i] <<
 749                               BITS_PER_BYTE * (i % 4));
 750                 DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
 751                          rc_buf_thresh_dword[i / 4]);
 752         }
 753         if (cpu_transcoder == TRANSCODER_EDP) {
 754                 I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
 755                 I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
 756                 I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
 757                 I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
 758                 if (crtc_state->dsc_params.dsc_split) {
 759                         I915_WRITE(DSCC_RC_BUF_THRESH_0,
 760                                    rc_buf_thresh_dword[0]);
 761                         I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
 762                                    rc_buf_thresh_dword[1]);
 763                         I915_WRITE(DSCC_RC_BUF_THRESH_1,
 764                                    rc_buf_thresh_dword[2]);
 765                         I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
 766                                    rc_buf_thresh_dword[3]);
 767                 }
 768         } else {
 769                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
 770                            rc_buf_thresh_dword[0]);
 771                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
 772                            rc_buf_thresh_dword[1]);
 773                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
 774                            rc_buf_thresh_dword[2]);
 775                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
 776                            rc_buf_thresh_dword[3]);
 777                 if (crtc_state->dsc_params.dsc_split) {
 778                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
 779                                    rc_buf_thresh_dword[0]);
 780                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
 781                                    rc_buf_thresh_dword[1]);
 782                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
 783                                    rc_buf_thresh_dword[2]);
 784                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
 785                                    rc_buf_thresh_dword[3]);
 786                 }
 787         }
 788
 789         /* Populate the RC_RANGE_PARAMETERS registers */
 790         memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
 791         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 792                 rc_range_params_dword[i / 2] |=
 793                         (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
 794                                 RC_BPG_OFFSET_SHIFT) |
 795                                (vdsc_cfg->rc_range_params[i].range_max_qp <<
 796                                 RC_MAX_QP_SHIFT) |
 797                                (vdsc_cfg->rc_range_params[i].range_min_qp <<
 798                                 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
 799                 DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
 800                          rc_range_params_dword[i / 2]);
 801         }
 802         if (cpu_transcoder == TRANSCODER_EDP) {
 803                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
 804                            rc_range_params_dword[0]);
 805                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
 806                            rc_range_params_dword[1]);
 807                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
 808                            rc_range_params_dword[2]);
 809                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
 810                            rc_range_params_dword[3]);
 811                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
 812                            rc_range_params_dword[4]);
 813                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
 814                            rc_range_params_dword[5]);
 815                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
 816                            rc_range_params_dword[6]);
 817                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
 818                            rc_range_params_dword[7]);
 819                 if (crtc_state->dsc_params.dsc_split) {
 820                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
 821                                    rc_range_params_dword[0]);
 822                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
 823                                    rc_range_params_dword[1]);
 824                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
 825                                    rc_range_params_dword[2]);
 826                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
 827                                    rc_range_params_dword[3]);
 828                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
 829                                    rc_range_params_dword[4]);
 830                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
 831                                    rc_range_params_dword[5]);
 832                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
 833                                    rc_range_params_dword[6]);
 834                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
 835                                    rc_range_params_dword[7]);
 836                 }
 837         } else {
 838                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
 839                            rc_range_params_dword[0]);
 840                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
 841                            rc_range_params_dword[1]);
 842                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
 843                            rc_range_params_dword[2]);
 844                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
 845                            rc_range_params_dword[3]);
 846                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
 847                            rc_range_params_dword[4]);
 848                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
 849                            rc_range_params_dword[5]);
 850                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
 851                            rc_range_params_dword[6]);
 852                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
 853                            rc_range_params_dword[7]);
 854                 if (crtc_state->dsc_params.dsc_split) {
 855                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
 856                                    rc_range_params_dword[0]);
 857                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
 858                                    rc_range_params_dword[1]);
 859                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
 860                                    rc_range_params_dword[2]);
 861                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
 862                                    rc_range_params_dword[3]);
 863                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
 864                                    rc_range_params_dword[4]);
 865                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
 866                                    rc_range_params_dword[5]);
 867                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
 868                                    rc_range_params_dword[6]);
 869                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
 870                                    rc_range_params_dword[7]);
 871                 }
 872         }
 873 }
 874
 875 static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
 876                                        const struct intel_crtc_state *crtc_state)
 877 {
 878         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 879         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 880         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
 881         struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
 882
 883         /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
 884         drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
 885
 886         /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
 887         drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
 888
 889         intel_dig_port->write_infoframe(encoder, crtc_state,
 890                                         DP_SDP_PPS, &dp_dsc_pps_sdp,
 891                                         sizeof(dp_dsc_pps_sdp));
 892 }
 893
 894 void intel_dsc_enable(struct intel_encoder *encoder,
 895                       const struct intel_crtc_state *crtc_state)
 896 {
 897         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 898         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 899         enum pipe pipe = crtc->pipe;
 900         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 901         u32 dss_ctl1_val = 0;
 902         u32 dss_ctl2_val = 0;
 903
 904         if (!crtc_state->dsc_params.compression_enable)
 905                 return;
 906
 907         /* Enable Power wells for VDSC/joining */
 908         intel_display_power_get(dev_priv,
 909                                 intel_dsc_power_domain(crtc_state));
 910
 911         intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
 912
 913         intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
 914
 915         if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
 916                 dss_ctl1_reg = DSS_CTL1;
 917                 dss_ctl2_reg = DSS_CTL2;
 918         } else {
 919                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
 920                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
 921         }
 922         dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
 923         if (crtc_state->dsc_params.dsc_split) {
 924                 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
 925                 dss_ctl1_val |= JOINER_ENABLE;
 926         }
 927         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
 928         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
 929 }
 930
 931 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 932 {
 933         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 934         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 935         enum pipe pipe = crtc->pipe;
 936         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 937         u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
 938
 939         if (!old_crtc_state->dsc_params.compression_enable)
 940                 return;
 941
 942         if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
 943                 dss_ctl1_reg = DSS_CTL1;
 944                 dss_ctl2_reg = DSS_CTL2;
 945         } else {
 946                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
 947                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
 948         }
 949         dss_ctl1_val = I915_READ(dss_ctl1_reg);
 950         if (dss_ctl1_val & JOINER_ENABLE)
 951                 dss_ctl1_val &= ~JOINER_ENABLE;
 952         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
 953
 954         dss_ctl2_val = I915_READ(dss_ctl2_reg);
 955         if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
 956             dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
 957                 dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
 958                                   RIGHT_BRANCH_VDSC_ENABLE);
 959         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
 960
 961         /* Disable Power wells for VDSC/joining */
 962         intel_display_power_put_unchecked(dev_priv,
 963                                           intel_dsc_power_domain(old_crtc_state));
 964 }