2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_UNCORE_H__
26 #define __INTEL_UNCORE_H__
28 #include <linux/spinlock.h>
29 #include <linux/notifier.h>
30 #include <linux/hrtimer.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
35 struct drm_i915_private;
36 struct intel_runtime_pm;
39 struct intel_uncore_mmio_debug {
40 spinlock_t lock; /** lock is also taken in irq contexts. */
41 int unclaimed_mmio_check;
46 enum forcewake_domain_id {
47 FW_DOMAIN_ID_RENDER = 0,
50 FW_DOMAIN_ID_MEDIA_VDBOX0,
51 FW_DOMAIN_ID_MEDIA_VDBOX1,
52 FW_DOMAIN_ID_MEDIA_VDBOX2,
53 FW_DOMAIN_ID_MEDIA_VDBOX3,
54 FW_DOMAIN_ID_MEDIA_VEBOX0,
55 FW_DOMAIN_ID_MEDIA_VEBOX1,
60 enum forcewake_domains {
61 FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
62 FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),
63 FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
64 FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
65 FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
66 FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
67 FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
68 FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
69 FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
71 FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
74 struct intel_uncore_funcs {
75 void (*force_wake_get)(struct intel_uncore *uncore,
76 enum forcewake_domains domains);
77 void (*force_wake_put)(struct intel_uncore *uncore,
78 enum forcewake_domains domains);
80 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
82 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
85 u8 (*mmio_readb)(struct intel_uncore *uncore,
86 i915_reg_t r, bool trace);
87 u16 (*mmio_readw)(struct intel_uncore *uncore,
88 i915_reg_t r, bool trace);
89 u32 (*mmio_readl)(struct intel_uncore *uncore,
90 i915_reg_t r, bool trace);
91 u64 (*mmio_readq)(struct intel_uncore *uncore,
92 i915_reg_t r, bool trace);
94 void (*mmio_writeb)(struct intel_uncore *uncore,
95 i915_reg_t r, u8 val, bool trace);
96 void (*mmio_writew)(struct intel_uncore *uncore,
97 i915_reg_t r, u16 val, bool trace);
98 void (*mmio_writel)(struct intel_uncore *uncore,
99 i915_reg_t r, u32 val, bool trace);
102 struct intel_forcewake_range {
106 enum forcewake_domains domains;
109 struct intel_uncore {
112 struct drm_i915_private *i915;
113 struct intel_runtime_pm *rpm;
115 spinlock_t lock; /** lock is also taken in irq contexts. */
118 #define UNCORE_HAS_FORCEWAKE BIT(0)
119 #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
120 #define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
121 #define UNCORE_HAS_FIFO BIT(3)
123 const struct intel_forcewake_range *fw_domains_table;
124 unsigned int fw_domains_table_entries;
126 struct notifier_block pmic_bus_access_nb;
127 struct intel_uncore_funcs funcs;
129 unsigned int fifo_count;
131 enum forcewake_domains fw_domains;
132 enum forcewake_domains fw_domains_active;
133 enum forcewake_domains fw_domains_timer;
134 enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
136 struct intel_uncore_forcewake_domain {
137 struct intel_uncore *uncore;
138 enum forcewake_domain_id id;
139 enum forcewake_domains mask;
140 unsigned int wake_count;
142 struct hrtimer timer;
143 u32 __iomem *reg_set;
144 u32 __iomem *reg_ack;
145 } *fw_domain[FW_DOMAIN_ID_COUNT];
147 unsigned int user_forcewake_count;
149 struct intel_uncore_mmio_debug *debug;
152 /* Iterate over initialised fw domains */
153 #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
154 for (tmp__ = (mask__); tmp__ ;) \
155 for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)])
157 #define for_each_fw_domain(domain__, uncore__, tmp__) \
158 for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
161 intel_uncore_has_forcewake(const struct intel_uncore *uncore)
163 return uncore->flags & UNCORE_HAS_FORCEWAKE;
167 intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
169 return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
173 intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
175 return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
179 intel_uncore_has_fifo(const struct intel_uncore *uncore)
181 return uncore->flags & UNCORE_HAS_FIFO;
185 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
186 void intel_uncore_init_early(struct intel_uncore *uncore,
187 struct drm_i915_private *i915);
188 int intel_uncore_init_mmio(struct intel_uncore *uncore);
189 void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore);
190 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
191 bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
192 void intel_uncore_fini_mmio(struct intel_uncore *uncore);
193 void intel_uncore_suspend(struct intel_uncore *uncore);
194 void intel_uncore_resume_early(struct intel_uncore *uncore);
195 void intel_uncore_runtime_resume(struct intel_uncore *uncore);
197 void assert_forcewakes_inactive(struct intel_uncore *uncore);
198 void assert_forcewakes_active(struct intel_uncore *uncore,
199 enum forcewake_domains fw_domains);
200 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
202 enum forcewake_domains
203 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
204 i915_reg_t reg, unsigned int op);
205 #define FW_REG_READ (1)
206 #define FW_REG_WRITE (2)
208 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
209 enum forcewake_domains domains);
210 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
211 enum forcewake_domains domains);
212 void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
213 enum forcewake_domains fw_domains);
216 * Like above but the caller must manage the uncore.lock itself.
217 * Must be used with I915_READ_FW and friends.
219 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
220 enum forcewake_domains domains);
221 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
222 enum forcewake_domains domains);
224 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
225 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
227 int __intel_wait_for_register(struct intel_uncore *uncore,
231 unsigned int fast_timeout_us,
232 unsigned int slow_timeout_ms,
235 intel_wait_for_register(struct intel_uncore *uncore,
239 unsigned int timeout_ms)
241 return __intel_wait_for_register(uncore, reg, mask, value, 2,
245 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
249 unsigned int fast_timeout_us,
250 unsigned int slow_timeout_ms,
253 intel_wait_for_register_fw(struct intel_uncore *uncore,
257 unsigned int timeout_ms)
259 return __intel_wait_for_register_fw(uncore, reg, mask, value,
260 2, timeout_ms, NULL);
263 /* register access functions */
264 #define __raw_read(x__, s__) \
265 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
268 return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
271 #define __raw_write(x__, s__) \
272 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
273 i915_reg_t reg, u##x__ val) \
275 write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
290 #define __uncore_read(name__, x__, s__, trace__) \
291 static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
294 return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
297 #define __uncore_write(name__, x__, s__, trace__) \
298 static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
299 i915_reg_t reg, u##x__ val) \
301 uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
304 __uncore_read(read8, 8, b, true)
305 __uncore_read(read16, 16, w, true)
306 __uncore_read(read, 32, l, true)
307 __uncore_read(read16_notrace, 16, w, false)
308 __uncore_read(read_notrace, 32, l, false)
310 __uncore_write(write8, 8, b, true)
311 __uncore_write(write16, 16, w, true)
312 __uncore_write(write, 32, l, true)
313 __uncore_write(write_notrace, 32, l, false)
315 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
316 * will be implemented using 2 32-bit writes in an arbitrary order with
317 * an arbitrary delay between them. This can cause the hardware to
318 * act upon the intermediate value, possibly leading to corruption and
319 * machine death. For this reason we do not support I915_WRITE64, or
320 * uncore->funcs.mmio_writeq.
322 * When reading a 64-bit value as two 32-bit values, the delay may cause
323 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
324 * occasionally a 64-bit register does not actually support a full readq
325 * and must be read using two 32-bit reads.
327 * You have been warned.
329 __uncore_read(read64, 64, q, true)
332 intel_uncore_read64_2x32(struct intel_uncore *uncore,
333 i915_reg_t lower_reg, i915_reg_t upper_reg)
335 u32 upper, lower, old_upper, loop = 0;
336 upper = intel_uncore_read(uncore, upper_reg);
339 lower = intel_uncore_read(uncore, lower_reg);
340 upper = intel_uncore_read(uncore, upper_reg);
341 } while (upper != old_upper && loop++ < 2);
342 return (u64)upper << 32 | lower;
345 #define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
346 #define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
349 #undef __uncore_write
351 /* These are untraced mmio-accessors that are only valid to be used inside
352 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
355 * Think twice, and think again, before using these.
357 * As an example, these accessors can possibly be used between:
359 * spin_lock_irq(&uncore->lock);
360 * intel_uncore_forcewake_get__locked();
364 * intel_uncore_forcewake_put__locked();
365 * spin_unlock_irq(&uncore->lock);
368 * Note: some registers may not need forcewake held, so
369 * intel_uncore_forcewake_{get,put} can be omitted, see
370 * intel_uncore_forcewake_for_reg().
372 * Certain architectures will die if the same cacheline is concurrently accessed
373 * by different clients (e.g. on Ivybridge). Access to registers should
374 * therefore generally be serialised, by either the dev_priv->uncore.lock or
375 * a more localised lock guarding all access to that bank of registers.
377 #define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
378 #define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
379 #define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
380 #define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
382 static inline void intel_uncore_rmw(struct intel_uncore *uncore,
383 i915_reg_t reg, u32 clear, u32 set)
387 old = intel_uncore_read(uncore, reg);
388 val = (old & ~clear) | set;
390 intel_uncore_write(uncore, reg, val);
393 static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
394 i915_reg_t reg, u32 clear, u32 set)
398 old = intel_uncore_read_fw(uncore, reg);
399 val = (old & ~clear) | set;
401 intel_uncore_write_fw(uncore, reg, val);
404 static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
405 i915_reg_t reg, u32 val,
406 u32 mask, u32 expected_val)
410 intel_uncore_write(uncore, reg, val);
411 reg_val = intel_uncore_read(uncore, reg);
413 return (reg_val & mask) != expected_val ? -EINVAL : 0;
416 #define raw_reg_read(base, reg) \
417 readl(base + i915_mmio_reg_offset(reg))
418 #define raw_reg_write(base, reg, value) \
419 writel(value, base + i915_mmio_reg_offset(reg))
421 #endif /* !__INTEL_UNCORE_H__ */