drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26 #include "i915_vgpu.h"
  27
  28 #include <asm/iosf_mbi.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  32 #define GT_FIFO_TIMEOUT_MS       10
  33
  34 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
  35
  36 static const char * const forcewake_domain_names[] = {
  37         "render",
  38         "blitter",
  39         "media",
  40         "vdbox0",
  41         "vdbox1",
  42         "vdbox2",
  43         "vdbox3",
  44         "vebox0",
  45         "vebox1",
  46 };
  47
  48 const char *
  49 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  50 {
  51         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  52
  53         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  54                 return forcewake_domain_names[id];
  55
  56         WARN_ON(id);
  57
  58         return "unknown";
  59 }
  60
  61 #define fw_ack(d) readl((d)->reg_ack)
  62 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
  63 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
  64
  65 static inline void
  66 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  67 {
  68         /*
  69          * We don't really know if the powerwell for the forcewake domain we are
  70          * trying to reset here does exist at this point (engines could be fused
  71          * off in ICL+), so no waiting for acks
  72          */
  73         /* WaRsClearFWBitsAtReset:bdw,skl */
  74         fw_clear(d, 0xffff);
  75 }
  76
  77 static inline void
  78 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  79 {
  80         d->wake_count++;
  81         hrtimer_start_range_ns(&d->timer,
  82                                NSEC_PER_MSEC,
  83                                NSEC_PER_MSEC,
  84                                HRTIMER_MODE_REL);
  85 }
  86
  87 static inline int
  88 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
  89                const u32 ack,
  90                const u32 value)
  91 {
  92         return wait_for_atomic((fw_ack(d) & ack) == value,
  93                                FORCEWAKE_ACK_TIMEOUT_MS);
  94 }
  95
  96 static inline int
  97 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
  98                const u32 ack)
  99 {
 100         return __wait_for_ack(d, ack, 0);
 101 }
 102
 103 static inline int
 104 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
 105              const u32 ack)
 106 {
 107         return __wait_for_ack(d, ack, ack);
 108 }
 109
 110 static inline void
 111 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
 112 {
 113         if (wait_ack_clear(d, FORCEWAKE_KERNEL))
 114                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
 115                           intel_uncore_forcewake_domain_to_str(d->id));
 116 }
 117
 118 enum ack_type {
 119         ACK_CLEAR = 0,
 120         ACK_SET
 121 };
 122
 123 static int
 124 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
 125                                  const enum ack_type type)
 126 {
 127         const u32 ack_bit = FORCEWAKE_KERNEL;
 128         const u32 value = type == ACK_SET ? ack_bit : 0;
 129         unsigned int pass;
 130         bool ack_detected;
 131
 132         /*
 133          * There is a possibility of driver's wake request colliding
 134          * with hardware's own wake requests and that can cause
 135          * hardware to not deliver the driver's ack message.
 136          *
 137          * Use a fallback bit toggle to kick the gpu state machine
 138          * in the hope that the original ack will be delivered along with
 139          * the fallback ack.
 140          *
 141          * This workaround is described in HSDES #1604254524 and it's known as:
 142          * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
 143          * although the name is a bit misleading.
 144          */
 145
 146         pass = 1;
 147         do {
 148                 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 149
 150                 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
 151                 /* Give gt some time to relax before the polling frenzy */
 152                 udelay(10 * pass);
 153                 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
 154
 155                 ack_detected = (fw_ack(d) & ack_bit) == value;
 156
 157                 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 158         } while (!ack_detected && pass++ < 10);
 159
 160         DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
 161                          intel_uncore_forcewake_domain_to_str(d->id),
 162                          type == ACK_SET ? "set" : "clear",
 163                          fw_ack(d),
 164                          pass);
 165
 166         return ack_detected ? 0 : -ETIMEDOUT;
 167 }
 168
 169 static inline void
 170 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
 171 {
 172         if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
 173                 return;
 174
 175         if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
 176                 fw_domain_wait_ack_clear(d);
 177 }
 178
 179 static inline void
 180 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
 181 {
 182         fw_set(d, FORCEWAKE_KERNEL);
 183 }
 184
 185 static inline void
 186 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
 187 {
 188         if (wait_ack_set(d, FORCEWAKE_KERNEL))
 189                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 190                           intel_uncore_forcewake_domain_to_str(d->id));
 191 }
 192
 193 static inline void
 194 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
 195 {
 196         if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
 197                 return;
 198
 199         if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
 200                 fw_domain_wait_ack_set(d);
 201 }
 202
 203 static inline void
 204 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 205 {
 206         fw_clear(d, FORCEWAKE_KERNEL);
 207 }
 208
 209 static void
 210 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 211 {
 212         struct intel_uncore_forcewake_domain *d;
 213         unsigned int tmp;
 214
 215         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 216
 217         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 218                 fw_domain_wait_ack_clear(d);
 219                 fw_domain_get(d);
 220         }
 221
 222         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 223                 fw_domain_wait_ack_set(d);
 224
 225         uncore->fw_domains_active |= fw_domains;
 226 }
 227
 228 static void
 229 fw_domains_get_with_fallback(struct intel_uncore *uncore,
 230                              enum forcewake_domains fw_domains)
 231 {
 232         struct intel_uncore_forcewake_domain *d;
 233         unsigned int tmp;
 234
 235         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 236
 237         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 238                 fw_domain_wait_ack_clear_fallback(d);
 239                 fw_domain_get(d);
 240         }
 241
 242         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 243                 fw_domain_wait_ack_set_fallback(d);
 244
 245         uncore->fw_domains_active |= fw_domains;
 246 }
 247
 248 static void
 249 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 250 {
 251         struct intel_uncore_forcewake_domain *d;
 252         unsigned int tmp;
 253
 254         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 255
 256         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 257                 fw_domain_put(d);
 258
 259         uncore->fw_domains_active &= ~fw_domains;
 260 }
 261
 262 static void
 263 fw_domains_reset(struct intel_uncore *uncore,
 264                  enum forcewake_domains fw_domains)
 265 {
 266         struct intel_uncore_forcewake_domain *d;
 267         unsigned int tmp;
 268
 269         if (!fw_domains)
 270                 return;
 271
 272         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 273
 274         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 275                 fw_domain_reset(d);
 276 }
 277
 278 static inline u32 gt_thread_status(struct intel_uncore *uncore)
 279 {
 280         u32 val;
 281
 282         val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
 283         val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
 284
 285         return val;
 286 }
 287
 288 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
 289 {
 290         /*
 291          * w/a for a sporadic read returning 0 by waiting for the GT
 292          * thread to wake up.
 293          */
 294         WARN_ONCE(wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
 295                   "GT thread status wait timed out\n");
 296 }
 297
 298 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
 299                                               enum forcewake_domains fw_domains)
 300 {
 301         fw_domains_get(uncore, fw_domains);
 302
 303         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 304         __gen6_gt_wait_for_thread_c0(uncore);
 305 }
 306
 307 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
 308 {
 309         u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
 310
 311         return count & GT_FIFO_FREE_ENTRIES_MASK;
 312 }
 313
 314 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
 315 {
 316         u32 n;
 317
 318         /* On VLV, FIFO will be shared by both SW and HW.
 319          * So, we need to read the FREE_ENTRIES everytime */
 320         if (IS_VALLEYVIEW(uncore_to_i915(uncore)))
 321                 n = fifo_free_entries(uncore);
 322         else
 323                 n = uncore->fifo_count;
 324
 325         if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
 326                 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
 327                                     GT_FIFO_NUM_RESERVED_ENTRIES,
 328                                     GT_FIFO_TIMEOUT_MS)) {
 329                         DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n);
 330                         return;
 331                 }
 332         }
 333
 334         uncore->fifo_count = n - 1;
 335 }
 336
 337 static enum hrtimer_restart
 338 intel_uncore_fw_release_timer(struct hrtimer *timer)
 339 {
 340         struct intel_uncore_forcewake_domain *domain =
 341                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 342         struct intel_uncore *uncore = forcewake_domain_to_uncore(domain);
 343         unsigned long irqflags;
 344
 345         assert_rpm_device_not_suspended(uncore->rpm);
 346
 347         if (xchg(&domain->active, false))
 348                 return HRTIMER_RESTART;
 349
 350         spin_lock_irqsave(&uncore->lock, irqflags);
 351         if (WARN_ON(domain->wake_count == 0))
 352                 domain->wake_count++;
 353
 354         if (--domain->wake_count == 0)
 355                 uncore->funcs.force_wake_put(uncore, domain->mask);
 356
 357         spin_unlock_irqrestore(&uncore->lock, irqflags);
 358
 359         return HRTIMER_NORESTART;
 360 }
 361
 362 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
 363 static unsigned int
 364 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
 365 {
 366         unsigned long irqflags;
 367         struct intel_uncore_forcewake_domain *domain;
 368         int retry_count = 100;
 369         enum forcewake_domains fw, active_domains;
 370
 371         iosf_mbi_assert_punit_acquired();
 372
 373         /* Hold uncore.lock across reset to prevent any register access
 374          * with forcewake not set correctly. Wait until all pending
 375          * timers are run before holding.
 376          */
 377         while (1) {
 378                 unsigned int tmp;
 379
 380                 active_domains = 0;
 381
 382                 for_each_fw_domain(domain, uncore, tmp) {
 383                         smp_store_mb(domain->active, false);
 384                         if (hrtimer_cancel(&domain->timer) == 0)
 385                                 continue;
 386
 387                         intel_uncore_fw_release_timer(&domain->timer);
 388                 }
 389
 390                 spin_lock_irqsave(&uncore->lock, irqflags);
 391
 392                 for_each_fw_domain(domain, uncore, tmp) {
 393                         if (hrtimer_active(&domain->timer))
 394                                 active_domains |= domain->mask;
 395                 }
 396
 397                 if (active_domains == 0)
 398                         break;
 399
 400                 if (--retry_count == 0) {
 401                         DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
 402                         break;
 403                 }
 404
 405                 spin_unlock_irqrestore(&uncore->lock, irqflags);
 406                 cond_resched();
 407         }
 408
 409         WARN_ON(active_domains);
 410
 411         fw = uncore->fw_domains_active;
 412         if (fw)
 413                 uncore->funcs.force_wake_put(uncore, fw);
 414
 415         fw_domains_reset(uncore, uncore->fw_domains);
 416         assert_forcewakes_inactive(uncore);
 417
 418         spin_unlock_irqrestore(&uncore->lock, irqflags);
 419
 420         return fw; /* track the lost user forcewake domains */
 421 }
 422
 423 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
 424 {
 425         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
 426         const unsigned int sets[4] = { 1, 1, 2, 2 };
 427         const u32 cap = dev_priv->edram_cap;
 428
 429         return EDRAM_NUM_BANKS(cap) *
 430                 ways[EDRAM_WAYS_IDX(cap)] *
 431                 sets[EDRAM_SETS_IDX(cap)] *
 432                 1024 * 1024;
 433 }
 434
 435 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
 436 {
 437         if (!HAS_EDRAM(dev_priv))
 438                 return 0;
 439
 440         /* The needed capability bits for size calculation
 441          * are not there with pre gen9 so return 128MB always.
 442          */
 443         if (INTEL_GEN(dev_priv) < 9)
 444                 return 128 * 1024 * 1024;
 445
 446         return gen9_edram_size(dev_priv);
 447 }
 448
 449 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 450 {
 451         if (IS_HASWELL(dev_priv) ||
 452             IS_BROADWELL(dev_priv) ||
 453             INTEL_GEN(dev_priv) >= 9) {
 454                 dev_priv->edram_cap = __raw_uncore_read32(&dev_priv->uncore,
 455                                                           HSW_EDRAM_CAP);
 456
 457                 /* NB: We can't write IDICR yet because we do not have gt funcs
 458                  * set up */
 459         } else {
 460                 dev_priv->edram_cap = 0;
 461         }
 462
 463         if (HAS_EDRAM(dev_priv))
 464                 DRM_INFO("Found %lluMB of eDRAM\n",
 465                          intel_uncore_edram_size(dev_priv) / (1024 * 1024));
 466 }
 467
 468 static bool
 469 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 470 {
 471         u32 dbg;
 472
 473         dbg = __raw_uncore_read32(uncore, FPGA_DBG);
 474         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 475                 return false;
 476
 477         __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 478
 479         return true;
 480 }
 481
 482 static bool
 483 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 484 {
 485         u32 cer;
 486
 487         cer = __raw_uncore_read32(uncore, CLAIM_ER);
 488         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 489                 return false;
 490
 491         __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
 492
 493         return true;
 494 }
 495
 496 static bool
 497 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
 498 {
 499         u32 fifodbg;
 500
 501         fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
 502
 503         if (unlikely(fifodbg)) {
 504                 DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
 505                 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
 506         }
 507
 508         return fifodbg;
 509 }
 510
 511 static bool
 512 check_for_unclaimed_mmio(struct intel_uncore *uncore)
 513 {
 514         bool ret = false;
 515
 516         if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
 517                 ret |= fpga_check_for_unclaimed_mmio(uncore);
 518
 519         if (intel_uncore_has_dbg_unclaimed(uncore))
 520                 ret |= vlv_check_for_unclaimed_mmio(uncore);
 521
 522         if (intel_uncore_has_fifo(uncore))
 523                 ret |= gen6_check_for_fifo_debug(uncore);
 524
 525         return ret;
 526 }
 527
 528 static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
 529                                           unsigned int restore_forcewake)
 530 {
 531         /* clear out unclaimed reg detection bit */
 532         if (check_for_unclaimed_mmio(uncore))
 533                 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
 534
 535         /* WaDisableShadowRegForCpd:chv */
 536         if (IS_CHERRYVIEW(uncore_to_i915(uncore))) {
 537                 __raw_uncore_write32(uncore, GTFIFOCTL,
 538                                      __raw_uncore_read32(uncore, GTFIFOCTL) |
 539                                      GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 540                                      GT_FIFO_CTL_RC6_POLICY_STALL);
 541         }
 542
 543         iosf_mbi_punit_acquire();
 544         intel_uncore_forcewake_reset(uncore);
 545         if (restore_forcewake) {
 546                 spin_lock_irq(&uncore->lock);
 547                 uncore->funcs.force_wake_get(uncore, restore_forcewake);
 548
 549                 if (intel_uncore_has_fifo(uncore))
 550                         uncore->fifo_count = fifo_free_entries(uncore);
 551                 spin_unlock_irq(&uncore->lock);
 552         }
 553         iosf_mbi_punit_release();
 554 }
 555
 556 void intel_uncore_suspend(struct intel_uncore *uncore)
 557 {
 558         iosf_mbi_punit_acquire();
 559         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
 560                 &uncore->pmic_bus_access_nb);
 561         uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
 562         iosf_mbi_punit_release();
 563 }
 564
 565 void intel_uncore_resume_early(struct intel_uncore *uncore)
 566 {
 567         unsigned int restore_forcewake;
 568
 569         restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
 570         __intel_uncore_early_sanitize(uncore, restore_forcewake);
 571
 572         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 573 }
 574
 575 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
 576 {
 577         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 578 }
 579
 580 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 581 {
 582         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 583         intel_sanitize_gt_powersave(dev_priv);
 584 }
 585
 586 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
 587                                          enum forcewake_domains fw_domains)
 588 {
 589         struct intel_uncore_forcewake_domain *domain;
 590         unsigned int tmp;
 591
 592         fw_domains &= uncore->fw_domains;
 593
 594         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 595                 if (domain->wake_count++) {
 596                         fw_domains &= ~domain->mask;
 597                         domain->active = true;
 598                 }
 599         }
 600
 601         if (fw_domains)
 602                 uncore->funcs.force_wake_get(uncore, fw_domains);
 603 }
 604
 605 /**
 606  * intel_uncore_forcewake_get - grab forcewake domain references
 607  * @uncore: the intel_uncore structure
 608  * @fw_domains: forcewake domains to get reference on
 609  *
 610  * This function can be used get GT's forcewake domain references.
 611  * Normal register access will handle the forcewake domains automatically.
 612  * However if some sequence requires the GT to not power down a particular
 613  * forcewake domains this function should be called at the beginning of the
 614  * sequence. And subsequently the reference should be dropped by symmetric
 615  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 616  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 617  */
 618 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 619                                 enum forcewake_domains fw_domains)
 620 {
 621         unsigned long irqflags;
 622
 623         if (!uncore->funcs.force_wake_get)
 624                 return;
 625
 626         __assert_rpm_wakelock_held(uncore->rpm);
 627
 628         spin_lock_irqsave(&uncore->lock, irqflags);
 629         __intel_uncore_forcewake_get(uncore, fw_domains);
 630         spin_unlock_irqrestore(&uncore->lock, irqflags);
 631 }
 632
 633 /**
 634  * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
 635  * @uncore: the intel_uncore structure
 636  *
 637  * This function is a wrapper around intel_uncore_forcewake_get() to acquire
 638  * the GT powerwell and in the process disable our debugging for the
 639  * duration of userspace's bypass.
 640  */
 641 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
 642 {
 643         spin_lock_irq(&uncore->lock);
 644         if (!uncore->user_forcewake.count++) {
 645                 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
 646
 647                 /* Save and disable mmio debugging for the user bypass */
 648                 uncore->user_forcewake.saved_mmio_check =
 649                         uncore->unclaimed_mmio_check;
 650                 uncore->user_forcewake.saved_mmio_debug =
 651                         i915_modparams.mmio_debug;
 652
 653                 uncore->unclaimed_mmio_check = 0;
 654                 i915_modparams.mmio_debug = 0;
 655         }
 656         spin_unlock_irq(&uncore->lock);
 657 }
 658
 659 /**
 660  * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
 661  * @uncore: the intel_uncore structure
 662  *
 663  * This function complements intel_uncore_forcewake_user_get() and releases
 664  * the GT powerwell taken on behalf of the userspace bypass.
 665  */
 666 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
 667 {
 668         spin_lock_irq(&uncore->lock);
 669         if (!--uncore->user_forcewake.count) {
 670                 if (intel_uncore_unclaimed_mmio(uncore))
 671                         dev_info(uncore_to_i915(uncore)->drm.dev,
 672                                  "Invalid mmio detected during user access\n");
 673
 674                 uncore->unclaimed_mmio_check =
 675                         uncore->user_forcewake.saved_mmio_check;
 676                 i915_modparams.mmio_debug =
 677                         uncore->user_forcewake.saved_mmio_debug;
 678
 679                 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
 680         }
 681         spin_unlock_irq(&uncore->lock);
 682 }
 683
 684 /**
 685  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 686  * @uncore: the intel_uncore structure
 687  * @fw_domains: forcewake domains to get reference on
 688  *
 689  * See intel_uncore_forcewake_get(). This variant places the onus
 690  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 691  */
 692 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 693                                         enum forcewake_domains fw_domains)
 694 {
 695         lockdep_assert_held(&uncore->lock);
 696
 697         if (!uncore->funcs.force_wake_get)
 698                 return;
 699
 700         __intel_uncore_forcewake_get(uncore, fw_domains);
 701 }
 702
 703 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
 704                                          enum forcewake_domains fw_domains)
 705 {
 706         struct intel_uncore_forcewake_domain *domain;
 707         unsigned int tmp;
 708
 709         fw_domains &= uncore->fw_domains;
 710
 711         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 712                 if (WARN_ON(domain->wake_count == 0))
 713                         continue;
 714
 715                 if (--domain->wake_count) {
 716                         domain->active = true;
 717                         continue;
 718                 }
 719
 720                 fw_domain_arm_timer(domain);
 721         }
 722 }
 723
 724 /**
 725  * intel_uncore_forcewake_put - release a forcewake domain reference
 726  * @uncore: the intel_uncore structure
 727  * @fw_domains: forcewake domains to put references
 728  *
 729  * This function drops the device-level forcewakes for specified
 730  * domains obtained by intel_uncore_forcewake_get().
 731  */
 732 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 733                                 enum forcewake_domains fw_domains)
 734 {
 735         unsigned long irqflags;
 736
 737         if (!uncore->funcs.force_wake_put)
 738                 return;
 739
 740         spin_lock_irqsave(&uncore->lock, irqflags);
 741         __intel_uncore_forcewake_put(uncore, fw_domains);
 742         spin_unlock_irqrestore(&uncore->lock, irqflags);
 743 }
 744
 745 /**
 746  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 747  * @uncore: the intel_uncore structure
 748  * @fw_domains: forcewake domains to get reference on
 749  *
 750  * See intel_uncore_forcewake_put(). This variant places the onus
 751  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 752  */
 753 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 754                                         enum forcewake_domains fw_domains)
 755 {
 756         lockdep_assert_held(&uncore->lock);
 757
 758         if (!uncore->funcs.force_wake_put)
 759                 return;
 760
 761         __intel_uncore_forcewake_put(uncore, fw_domains);
 762 }
 763
 764 void assert_forcewakes_inactive(struct intel_uncore *uncore)
 765 {
 766         if (!uncore->funcs.force_wake_get)
 767                 return;
 768
 769         WARN(uncore->fw_domains_active,
 770              "Expected all fw_domains to be inactive, but %08x are still on\n",
 771              uncore->fw_domains_active);
 772 }
 773
 774 void assert_forcewakes_active(struct intel_uncore *uncore,
 775                               enum forcewake_domains fw_domains)
 776 {
 777         if (!uncore->funcs.force_wake_get)
 778                 return;
 779
 780         __assert_rpm_wakelock_held(uncore->rpm);
 781
 782         fw_domains &= uncore->fw_domains;
 783         WARN(fw_domains & ~uncore->fw_domains_active,
 784              "Expected %08x fw_domains to be active, but %08x are off\n",
 785              fw_domains, fw_domains & ~uncore->fw_domains_active);
 786 }
 787
 788 /* We give fast paths for the really cool registers */
 789 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 790
 791 #define GEN11_NEEDS_FORCE_WAKE(reg) \
 792         ((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000))
 793
 794 #define __gen6_reg_read_fw_domains(uncore, offset) \
 795 ({ \
 796         enum forcewake_domains __fwd; \
 797         if (NEEDS_FORCE_WAKE(offset)) \
 798                 __fwd = FORCEWAKE_RENDER; \
 799         else \
 800                 __fwd = 0; \
 801         __fwd; \
 802 })
 803
 804 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 805 {
 806         if (offset < entry->start)
 807                 return -1;
 808         else if (offset > entry->end)
 809                 return 1;
 810         else
 811                 return 0;
 812 }
 813
 814 /* Copied and "macroized" from lib/bsearch.c */
 815 #define BSEARCH(key, base, num, cmp) ({                                 \
 816         unsigned int start__ = 0, end__ = (num);                        \
 817         typeof(base) result__ = NULL;                                   \
 818         while (start__ < end__) {                                       \
 819                 unsigned int mid__ = start__ + (end__ - start__) / 2;   \
 820                 int ret__ = (cmp)((key), (base) + mid__);               \
 821                 if (ret__ < 0) {                                        \
 822                         end__ = mid__;                                  \
 823                 } else if (ret__ > 0) {                                 \
 824                         start__ = mid__ + 1;                            \
 825                 } else {                                                \
 826                         result__ = (base) + mid__;                      \
 827                         break;                                          \
 828                 }                                                       \
 829         }                                                               \
 830         result__;                                                       \
 831 })
 832
 833 static enum forcewake_domains
 834 find_fw_domain(struct intel_uncore *uncore, u32 offset)
 835 {
 836         const struct intel_forcewake_range *entry;
 837
 838         entry = BSEARCH(offset,
 839                         uncore->fw_domains_table,
 840                         uncore->fw_domains_table_entries,
 841                         fw_range_cmp);
 842
 843         if (!entry)
 844                 return 0;
 845
 846         /*
 847          * The list of FW domains depends on the SKU in gen11+ so we
 848          * can't determine it statically. We use FORCEWAKE_ALL and
 849          * translate it here to the list of available domains.
 850          */
 851         if (entry->domains == FORCEWAKE_ALL)
 852                 return uncore->fw_domains;
 853
 854         WARN(entry->domains & ~uncore->fw_domains,
 855              "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 856              entry->domains & ~uncore->fw_domains, offset);
 857
 858         return entry->domains;
 859 }
 860
 861 #define GEN_FW_RANGE(s, e, d) \
 862         { .start = (s), .end = (e), .domains = (d) }
 863
 864 #define HAS_FWTABLE(dev_priv) \
 865         (INTEL_GEN(dev_priv) >= 9 || \
 866          IS_CHERRYVIEW(dev_priv) || \
 867          IS_VALLEYVIEW(dev_priv))
 868
 869 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 870 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 871         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 872         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
 873         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
 874         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 875         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
 876         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
 877         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 878 };
 879
 880 #define __fwtable_reg_read_fw_domains(uncore, offset) \
 881 ({ \
 882         enum forcewake_domains __fwd = 0; \
 883         if (NEEDS_FORCE_WAKE((offset))) \
 884                 __fwd = find_fw_domain(uncore, offset); \
 885         __fwd; \
 886 })
 887
 888 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
 889 ({ \
 890         enum forcewake_domains __fwd = 0; \
 891         if (GEN11_NEEDS_FORCE_WAKE((offset))) \
 892                 __fwd = find_fw_domain(uncore, offset); \
 893         __fwd; \
 894 })
 895
 896 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 897 static const i915_reg_t gen8_shadowed_regs[] = {
 898         RING_TAIL(RENDER_RING_BASE),    /* 0x2000 (base) */
 899         GEN6_RPNSWREQ,                  /* 0xA008 */
 900         GEN6_RC_VIDEO_FREQ,             /* 0xA00C */
 901         RING_TAIL(GEN6_BSD_RING_BASE),  /* 0x12000 (base) */
 902         RING_TAIL(VEBOX_RING_BASE),     /* 0x1a000 (base) */
 903         RING_TAIL(BLT_RING_BASE),       /* 0x22000 (base) */
 904         /* TODO: Other registers are not yet used */
 905 };
 906
 907 static const i915_reg_t gen11_shadowed_regs[] = {
 908         RING_TAIL(RENDER_RING_BASE),            /* 0x2000 (base) */
 909         GEN6_RPNSWREQ,                          /* 0xA008 */
 910         GEN6_RC_VIDEO_FREQ,                     /* 0xA00C */
 911         RING_TAIL(BLT_RING_BASE),               /* 0x22000 (base) */
 912         RING_TAIL(GEN11_BSD_RING_BASE),         /* 0x1C0000 (base) */
 913         RING_TAIL(GEN11_BSD2_RING_BASE),        /* 0x1C4000 (base) */
 914         RING_TAIL(GEN11_VEBOX_RING_BASE),       /* 0x1C8000 (base) */
 915         RING_TAIL(GEN11_BSD3_RING_BASE),        /* 0x1D0000 (base) */
 916         RING_TAIL(GEN11_BSD4_RING_BASE),        /* 0x1D4000 (base) */
 917         RING_TAIL(GEN11_VEBOX2_RING_BASE),      /* 0x1D8000 (base) */
 918         /* TODO: Other registers are not yet used */
 919 };
 920
 921 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 922 {
 923         u32 offset = i915_mmio_reg_offset(*reg);
 924
 925         if (key < offset)
 926                 return -1;
 927         else if (key > offset)
 928                 return 1;
 929         else
 930                 return 0;
 931 }
 932
 933 #define __is_genX_shadowed(x) \
 934 static bool is_gen##x##_shadowed(u32 offset) \
 935 { \
 936         const i915_reg_t *regs = gen##x##_shadowed_regs; \
 937         return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
 938                        mmio_reg_cmp); \
 939 }
 940
 941 __is_genX_shadowed(8)
 942 __is_genX_shadowed(11)
 943
 944 #define __gen8_reg_write_fw_domains(uncore, offset) \
 945 ({ \
 946         enum forcewake_domains __fwd; \
 947         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 948                 __fwd = FORCEWAKE_RENDER; \
 949         else \
 950                 __fwd = 0; \
 951         __fwd; \
 952 })
 953
 954 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 955 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 956         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 957         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 958         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 959         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 960         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 961         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 962         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
 963         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 964         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
 965         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
 966         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
 967         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 968         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 969         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
 970         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
 971         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
 972 };
 973
 974 #define __fwtable_reg_write_fw_domains(uncore, offset) \
 975 ({ \
 976         enum forcewake_domains __fwd = 0; \
 977         if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
 978                 __fwd = find_fw_domain(uncore, offset); \
 979         __fwd; \
 980 })
 981
 982 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
 983 ({ \
 984         enum forcewake_domains __fwd = 0; \
 985         if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
 986                 __fwd = find_fw_domain(uncore, offset); \
 987         __fwd; \
 988 })
 989
 990 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 991 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 992         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
 993         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
 994         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
 995         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
 996         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
 997         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
 998         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 999         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
1000         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1001         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1002         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1003         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1004         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
1005         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1006         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
1007         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1008         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1009         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1010         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1011         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1012         GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
1013         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1014         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
1015         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1016         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
1017         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1018         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
1019         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1020         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
1021         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1022         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
1023         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1024 };
1025
1026 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1027 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1028         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1029         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1030         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1031         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1032         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1033         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1034         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1035         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1036         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1037         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1038         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1039         GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
1040         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1041         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1042         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
1043         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1044         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1045         GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
1046         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1047         GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER),
1048         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1049         GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1050         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1051         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1052         GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1053         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1054         GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1055         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1056         GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1057         GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1058 };
1059
1060 static void
1061 ilk_dummy_write(struct intel_uncore *uncore)
1062 {
1063         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1064          * the chip from rc6 before touching it for real. MI_MODE is masked,
1065          * hence harmless to write 0 into. */
1066         __raw_uncore_write32(uncore, MI_MODE, 0);
1067 }
1068
1069 static void
1070 __unclaimed_reg_debug(struct intel_uncore *uncore,
1071                       const i915_reg_t reg,
1072                       const bool read,
1073                       const bool before)
1074 {
1075         if (WARN(check_for_unclaimed_mmio(uncore) && !before,
1076                  "Unclaimed %s register 0x%x\n",
1077                  read ? "read from" : "write to",
1078                  i915_mmio_reg_offset(reg)))
1079                 /* Only report the first N failures */
1080                 i915_modparams.mmio_debug--;
1081 }
1082
1083 static inline void
1084 unclaimed_reg_debug(struct intel_uncore *uncore,
1085                     const i915_reg_t reg,
1086                     const bool read,
1087                     const bool before)
1088 {
1089         if (likely(!i915_modparams.mmio_debug))
1090                 return;
1091
1092         __unclaimed_reg_debug(uncore, reg, read, before);
1093 }
1094
1095 #define GEN2_READ_HEADER(x) \
1096         u##x val = 0; \
1097         __assert_rpm_wakelock_held(uncore->rpm);
1098
1099 #define GEN2_READ_FOOTER \
1100         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1101         return val
1102
1103 #define __gen2_read(x) \
1104 static u##x \
1105 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1106         GEN2_READ_HEADER(x); \
1107         val = __raw_uncore_read##x(uncore, reg); \
1108         GEN2_READ_FOOTER; \
1109 }
1110
1111 #define __gen5_read(x) \
1112 static u##x \
1113 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1114         GEN2_READ_HEADER(x); \
1115         ilk_dummy_write(uncore); \
1116         val = __raw_uncore_read##x(uncore, reg); \
1117         GEN2_READ_FOOTER; \
1118 }
1119
1120 __gen5_read(8)
1121 __gen5_read(16)
1122 __gen5_read(32)
1123 __gen5_read(64)
1124 __gen2_read(8)
1125 __gen2_read(16)
1126 __gen2_read(32)
1127 __gen2_read(64)
1128
1129 #undef __gen5_read
1130 #undef __gen2_read
1131
1132 #undef GEN2_READ_FOOTER
1133 #undef GEN2_READ_HEADER
1134
1135 #define GEN6_READ_HEADER(x) \
1136         u32 offset = i915_mmio_reg_offset(reg); \
1137         unsigned long irqflags; \
1138         u##x val = 0; \
1139         __assert_rpm_wakelock_held(uncore->rpm); \
1140         spin_lock_irqsave(&uncore->lock, irqflags); \
1141         unclaimed_reg_debug(uncore, reg, true, true)
1142
1143 #define GEN6_READ_FOOTER \
1144         unclaimed_reg_debug(uncore, reg, true, false); \
1145         spin_unlock_irqrestore(&uncore->lock, irqflags); \
1146         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1147         return val
1148
1149 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1150                                         enum forcewake_domains fw_domains)
1151 {
1152         struct intel_uncore_forcewake_domain *domain;
1153         unsigned int tmp;
1154
1155         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1156
1157         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1158                 fw_domain_arm_timer(domain);
1159
1160         uncore->funcs.force_wake_get(uncore, fw_domains);
1161 }
1162
1163 static inline void __force_wake_auto(struct intel_uncore *uncore,
1164                                      enum forcewake_domains fw_domains)
1165 {
1166         if (WARN_ON(!fw_domains))
1167                 return;
1168
1169         /* Turn on all requested but inactive supported forcewake domains. */
1170         fw_domains &= uncore->fw_domains;
1171         fw_domains &= ~uncore->fw_domains_active;
1172
1173         if (fw_domains)
1174                 ___force_wake_auto(uncore, fw_domains);
1175 }
1176
1177 #define __gen_read(func, x) \
1178 static u##x \
1179 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1180         enum forcewake_domains fw_engine; \
1181         GEN6_READ_HEADER(x); \
1182         fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
1183         if (fw_engine) \
1184                 __force_wake_auto(uncore, fw_engine); \
1185         val = __raw_uncore_read##x(uncore, reg); \
1186         GEN6_READ_FOOTER; \
1187 }
1188 #define __gen6_read(x) __gen_read(gen6, x)
1189 #define __fwtable_read(x) __gen_read(fwtable, x)
1190 #define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x)
1191
1192 __gen11_fwtable_read(8)
1193 __gen11_fwtable_read(16)
1194 __gen11_fwtable_read(32)
1195 __gen11_fwtable_read(64)
1196 __fwtable_read(8)
1197 __fwtable_read(16)
1198 __fwtable_read(32)
1199 __fwtable_read(64)
1200 __gen6_read(8)
1201 __gen6_read(16)
1202 __gen6_read(32)
1203 __gen6_read(64)
1204
1205 #undef __gen11_fwtable_read
1206 #undef __fwtable_read
1207 #undef __gen6_read
1208 #undef GEN6_READ_FOOTER
1209 #undef GEN6_READ_HEADER
1210
1211 #define GEN2_WRITE_HEADER \
1212         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1213         __assert_rpm_wakelock_held(uncore->rpm); \
1214
1215 #define GEN2_WRITE_FOOTER
1216
1217 #define __gen2_write(x) \
1218 static void \
1219 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1220         GEN2_WRITE_HEADER; \
1221         __raw_uncore_write##x(uncore, reg, val); \
1222         GEN2_WRITE_FOOTER; \
1223 }
1224
1225 #define __gen5_write(x) \
1226 static void \
1227 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1228         GEN2_WRITE_HEADER; \
1229         ilk_dummy_write(uncore); \
1230         __raw_uncore_write##x(uncore, reg, val); \
1231         GEN2_WRITE_FOOTER; \
1232 }
1233
1234 __gen5_write(8)
1235 __gen5_write(16)
1236 __gen5_write(32)
1237 __gen2_write(8)
1238 __gen2_write(16)
1239 __gen2_write(32)
1240
1241 #undef __gen5_write
1242 #undef __gen2_write
1243
1244 #undef GEN2_WRITE_FOOTER
1245 #undef GEN2_WRITE_HEADER
1246
1247 #define GEN6_WRITE_HEADER \
1248         u32 offset = i915_mmio_reg_offset(reg); \
1249         unsigned long irqflags; \
1250         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1251         __assert_rpm_wakelock_held(uncore->rpm); \
1252         spin_lock_irqsave(&uncore->lock, irqflags); \
1253         unclaimed_reg_debug(uncore, reg, false, true)
1254
1255 #define GEN6_WRITE_FOOTER \
1256         unclaimed_reg_debug(uncore, reg, false, false); \
1257         spin_unlock_irqrestore(&uncore->lock, irqflags)
1258
1259 #define __gen6_write(x) \
1260 static void \
1261 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1262         GEN6_WRITE_HEADER; \
1263         if (NEEDS_FORCE_WAKE(offset)) \
1264                 __gen6_gt_wait_for_fifo(uncore); \
1265         __raw_uncore_write##x(uncore, reg, val); \
1266         GEN6_WRITE_FOOTER; \
1267 }
1268
1269 #define __gen_write(func, x) \
1270 static void \
1271 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1272         enum forcewake_domains fw_engine; \
1273         GEN6_WRITE_HEADER; \
1274         fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
1275         if (fw_engine) \
1276                 __force_wake_auto(uncore, fw_engine); \
1277         __raw_uncore_write##x(uncore, reg, val); \
1278         GEN6_WRITE_FOOTER; \
1279 }
1280 #define __gen8_write(x) __gen_write(gen8, x)
1281 #define __fwtable_write(x) __gen_write(fwtable, x)
1282 #define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x)
1283
1284 __gen11_fwtable_write(8)
1285 __gen11_fwtable_write(16)
1286 __gen11_fwtable_write(32)
1287 __fwtable_write(8)
1288 __fwtable_write(16)
1289 __fwtable_write(32)
1290 __gen8_write(8)
1291 __gen8_write(16)
1292 __gen8_write(32)
1293 __gen6_write(8)
1294 __gen6_write(16)
1295 __gen6_write(32)
1296
1297 #undef __gen11_fwtable_write
1298 #undef __fwtable_write
1299 #undef __gen8_write
1300 #undef __gen6_write
1301 #undef GEN6_WRITE_FOOTER
1302 #undef GEN6_WRITE_HEADER
1303
1304 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1305 do { \
1306         (uncore)->funcs.mmio_writeb = x##_write8; \
1307         (uncore)->funcs.mmio_writew = x##_write16; \
1308         (uncore)->funcs.mmio_writel = x##_write32; \
1309 } while (0)
1310
1311 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1312 do { \
1313         (uncore)->funcs.mmio_readb = x##_read8; \
1314         (uncore)->funcs.mmio_readw = x##_read16; \
1315         (uncore)->funcs.mmio_readl = x##_read32; \
1316         (uncore)->funcs.mmio_readq = x##_read64; \
1317 } while (0)
1318
1319
1320 static void fw_domain_init(struct intel_uncore *uncore,
1321                            enum forcewake_domain_id domain_id,
1322                            i915_reg_t reg_set,
1323                            i915_reg_t reg_ack)
1324 {
1325         struct intel_uncore_forcewake_domain *d;
1326
1327         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1328                 return;
1329
1330         d = &uncore->fw_domain[domain_id];
1331
1332         WARN_ON(d->wake_count);
1333
1334         WARN_ON(!i915_mmio_reg_valid(reg_set));
1335         WARN_ON(!i915_mmio_reg_valid(reg_ack));
1336
1337         d->wake_count = 0;
1338         d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1339         d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
1340
1341         d->id = domain_id;
1342
1343         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1344         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1345         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1346         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1347         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1348         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1349         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1350         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1351         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1352
1353
1354         d->mask = BIT(domain_id);
1355
1356         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1357         d->timer.function = intel_uncore_fw_release_timer;
1358
1359         uncore->fw_domains |= BIT(domain_id);
1360
1361         fw_domain_reset(d);
1362 }
1363
1364 static void fw_domain_fini(struct intel_uncore *uncore,
1365                            enum forcewake_domain_id domain_id)
1366 {
1367         struct intel_uncore_forcewake_domain *d;
1368
1369         if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1370                 return;
1371
1372         d = &uncore->fw_domain[domain_id];
1373
1374         WARN_ON(d->wake_count);
1375         WARN_ON(hrtimer_cancel(&d->timer));
1376         memset(d, 0, sizeof(*d));
1377
1378         uncore->fw_domains &= ~BIT(domain_id);
1379 }
1380
1381 static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
1382 {
1383         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1384
1385         if (!intel_uncore_has_forcewake(uncore))
1386                 return;
1387
1388         if (INTEL_GEN(i915) >= 11) {
1389                 int i;
1390
1391                 uncore->funcs.force_wake_get =
1392                         fw_domains_get_with_fallback;
1393                 uncore->funcs.force_wake_put = fw_domains_put;
1394                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1395                                FORCEWAKE_RENDER_GEN9,
1396                                FORCEWAKE_ACK_RENDER_GEN9);
1397                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1398                                FORCEWAKE_BLITTER_GEN9,
1399                                FORCEWAKE_ACK_BLITTER_GEN9);
1400                 for (i = 0; i < I915_MAX_VCS; i++) {
1401                         if (!HAS_ENGINE(i915, _VCS(i)))
1402                                 continue;
1403
1404                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1405                                        FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1406                                        FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1407                 }
1408                 for (i = 0; i < I915_MAX_VECS; i++) {
1409                         if (!HAS_ENGINE(i915, _VECS(i)))
1410                                 continue;
1411
1412                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1413                                        FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1414                                        FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1415                 }
1416         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1417                 uncore->funcs.force_wake_get =
1418                         fw_domains_get_with_fallback;
1419                 uncore->funcs.force_wake_put = fw_domains_put;
1420                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1421                                FORCEWAKE_RENDER_GEN9,
1422                                FORCEWAKE_ACK_RENDER_GEN9);
1423                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1424                                FORCEWAKE_BLITTER_GEN9,
1425                                FORCEWAKE_ACK_BLITTER_GEN9);
1426                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1427                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1428         } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1429                 uncore->funcs.force_wake_get = fw_domains_get;
1430                 uncore->funcs.force_wake_put = fw_domains_put;
1431                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1432                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1433                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1434                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1435         } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1436                 uncore->funcs.force_wake_get =
1437                         fw_domains_get_with_thread_status;
1438                 uncore->funcs.force_wake_put = fw_domains_put;
1439                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1440                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1441         } else if (IS_IVYBRIDGE(i915)) {
1442                 u32 ecobus;
1443
1444                 /* IVB configs may use multi-threaded forcewake */
1445
1446                 /* A small trick here - if the bios hasn't configured
1447                  * MT forcewake, and if the device is in RC6, then
1448                  * force_wake_mt_get will not wake the device and the
1449                  * ECOBUS read will return zero. Which will be
1450                  * (correctly) interpreted by the test below as MT
1451                  * forcewake being disabled.
1452                  */
1453                 uncore->funcs.force_wake_get =
1454                         fw_domains_get_with_thread_status;
1455                 uncore->funcs.force_wake_put = fw_domains_put;
1456
1457                 /* We need to init first for ECOBUS access and then
1458                  * determine later if we want to reinit, in case of MT access is
1459                  * not working. In this stage we don't know which flavour this
1460                  * ivb is, so it is better to reset also the gen6 fw registers
1461                  * before the ecobus check.
1462                  */
1463
1464                 __raw_uncore_write32(uncore, FORCEWAKE, 0);
1465                 __raw_posting_read(uncore, ECOBUS);
1466
1467                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1468                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1469
1470                 spin_lock_irq(&uncore->lock);
1471                 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
1472                 ecobus = __raw_uncore_read32(uncore, ECOBUS);
1473                 fw_domains_put(uncore, FORCEWAKE_RENDER);
1474                 spin_unlock_irq(&uncore->lock);
1475
1476                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1477                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1478                         DRM_INFO("when using vblank-synced partial screen updates.\n");
1479                         fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1480                                        FORCEWAKE, FORCEWAKE_ACK);
1481                 }
1482         } else if (IS_GEN(i915, 6)) {
1483                 uncore->funcs.force_wake_get =
1484                         fw_domains_get_with_thread_status;
1485                 uncore->funcs.force_wake_put = fw_domains_put;
1486                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1487                                FORCEWAKE, FORCEWAKE_ACK);
1488         }
1489
1490         /* All future platforms are expected to require complex power gating */
1491         WARN_ON(uncore->fw_domains == 0);
1492 }
1493
1494 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
1495 { \
1496         (uncore)->fw_domains_table = \
1497                         (struct intel_forcewake_range *)(d); \
1498         (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
1499 }
1500
1501 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1502                                          unsigned long action, void *data)
1503 {
1504         struct drm_i915_private *dev_priv = container_of(nb,
1505                         struct drm_i915_private, uncore.pmic_bus_access_nb);
1506
1507         switch (action) {
1508         case MBI_PMIC_BUS_ACCESS_BEGIN:
1509                 /*
1510                  * forcewake all now to make sure that we don't need to do a
1511                  * forcewake later which on systems where this notifier gets
1512                  * called requires the punit to access to the shared pmic i2c
1513                  * bus, which will be busy after this notification, leading to:
1514                  * "render: timed out waiting for forcewake ack request."
1515                  * errors.
1516                  *
1517                  * The notifier is unregistered during intel_runtime_suspend(),
1518                  * so it's ok to access the HW here without holding a RPM
1519                  * wake reference -> disable wakeref asserts for the time of
1520                  * the access.
1521                  */
1522                 disable_rpm_wakeref_asserts(dev_priv);
1523                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
1524                 enable_rpm_wakeref_asserts(dev_priv);
1525                 break;
1526         case MBI_PMIC_BUS_ACCESS_END:
1527                 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1528                 break;
1529         }
1530
1531         return NOTIFY_OK;
1532 }
1533
1534 static int uncore_mmio_setup(struct intel_uncore *uncore)
1535 {
1536         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1537         struct pci_dev *pdev = i915->drm.pdev;
1538         int mmio_bar;
1539         int mmio_size;
1540
1541         mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
1542         /*
1543          * Before gen4, the registers and the GTT are behind different BARs.
1544          * However, from gen4 onwards, the registers and the GTT are shared
1545          * in the same BAR, so we want to restrict this ioremap from
1546          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1547          * the register BAR remains the same size for all the earlier
1548          * generations up to Ironlake.
1549          */
1550         if (INTEL_GEN(i915) < 5)
1551                 mmio_size = 512 * 1024;
1552         else
1553                 mmio_size = 2 * 1024 * 1024;
1554         uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
1555         if (uncore->regs == NULL) {
1556                 DRM_ERROR("failed to map registers\n");
1557
1558                 return -EIO;
1559         }
1560
1561         return 0;
1562 }
1563
1564 static void uncore_mmio_cleanup(struct intel_uncore *uncore)
1565 {
1566         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1567         struct pci_dev *pdev = i915->drm.pdev;
1568
1569         pci_iounmap(pdev, uncore->regs);
1570 }
1571
1572
1573 int intel_uncore_init(struct intel_uncore *uncore)
1574 {
1575         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1576         int ret;
1577
1578         ret = uncore_mmio_setup(uncore);
1579         if (ret)
1580                 return ret;
1581
1582         i915_check_vgpu(i915);
1583
1584         if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
1585                 uncore->flags |= UNCORE_HAS_FORCEWAKE;
1586
1587         intel_uncore_edram_detect(i915);
1588         intel_uncore_fw_domains_init(uncore);
1589         __intel_uncore_early_sanitize(uncore, 0);
1590
1591         uncore->unclaimed_mmio_check = 1;
1592         uncore->pmic_bus_access_nb.notifier_call =
1593                 i915_pmic_bus_access_notifier;
1594
1595         uncore->rpm = &i915->runtime_pm;
1596
1597         if (!intel_uncore_has_forcewake(uncore)) {
1598                 if (IS_GEN(i915, 5)) {
1599                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
1600                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
1601                 } else {
1602                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
1603                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
1604                 }
1605         } else if (IS_GEN_RANGE(i915, 6, 7)) {
1606                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
1607
1608                 if (IS_VALLEYVIEW(i915)) {
1609                         ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
1610                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1611                 } else {
1612                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1613                 }
1614         } else if (IS_GEN(i915, 8)) {
1615                 if (IS_CHERRYVIEW(i915)) {
1616                         ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
1617                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1618                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1619
1620                 } else {
1621                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
1622                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1623                 }
1624         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1625                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
1626                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1627                 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1628         } else {
1629                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
1630                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
1631                 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
1632         }
1633
1634         if (HAS_FPGA_DBG_UNCLAIMED(i915))
1635                 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
1636
1637         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1638                 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
1639
1640         if (IS_GEN_RANGE(i915, 6, 7))
1641                 uncore->flags |= UNCORE_HAS_FIFO;
1642
1643         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
1644
1645         return 0;
1646 }
1647
1648 /*
1649  * We might have detected that some engines are fused off after we initialized
1650  * the forcewake domains. Prune them, to make sure they only reference existing
1651  * engines.
1652  */
1653 void intel_uncore_prune(struct intel_uncore *uncore)
1654 {
1655         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1656
1657         if (INTEL_GEN(i915) >= 11) {
1658                 enum forcewake_domains fw_domains = uncore->fw_domains;
1659                 enum forcewake_domain_id domain_id;
1660                 int i;
1661
1662                 for (i = 0; i < I915_MAX_VCS; i++) {
1663                         domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1664
1665                         if (HAS_ENGINE(i915, _VCS(i)))
1666                                 continue;
1667
1668                         if (fw_domains & BIT(domain_id))
1669                                 fw_domain_fini(uncore, domain_id);
1670                 }
1671
1672                 for (i = 0; i < I915_MAX_VECS; i++) {
1673                         domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1674
1675                         if (HAS_ENGINE(i915, _VECS(i)))
1676                                 continue;
1677
1678                         if (fw_domains & BIT(domain_id))
1679                                 fw_domain_fini(uncore, domain_id);
1680                 }
1681         }
1682 }
1683
1684 void intel_uncore_fini(struct intel_uncore *uncore)
1685 {
1686         /* Paranoia: make sure we have disabled everything before we exit. */
1687         intel_uncore_sanitize(uncore_to_i915(uncore));
1688
1689         iosf_mbi_punit_acquire();
1690         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
1691                 &uncore->pmic_bus_access_nb);
1692         intel_uncore_forcewake_reset(uncore);
1693         iosf_mbi_punit_release();
1694         uncore_mmio_cleanup(uncore);
1695 }
1696
1697 static const struct reg_whitelist {
1698         i915_reg_t offset_ldw;
1699         i915_reg_t offset_udw;
1700         u16 gen_mask;
1701         u8 size;
1702 } reg_read_whitelist[] = { {
1703         .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1704         .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1705         .gen_mask = INTEL_GEN_MASK(4, 11),
1706         .size = 8
1707 } };
1708
1709 int i915_reg_read_ioctl(struct drm_device *dev,
1710                         void *data, struct drm_file *file)
1711 {
1712         struct drm_i915_private *dev_priv = to_i915(dev);
1713         struct drm_i915_reg_read *reg = data;
1714         struct reg_whitelist const *entry;
1715         intel_wakeref_t wakeref;
1716         unsigned int flags;
1717         int remain;
1718         int ret = 0;
1719
1720         entry = reg_read_whitelist;
1721         remain = ARRAY_SIZE(reg_read_whitelist);
1722         while (remain) {
1723                 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
1724
1725                 GEM_BUG_ON(!is_power_of_2(entry->size));
1726                 GEM_BUG_ON(entry->size > 8);
1727                 GEM_BUG_ON(entry_offset & (entry->size - 1));
1728
1729                 if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
1730                     entry_offset == (reg->offset & -entry->size))
1731                         break;
1732                 entry++;
1733                 remain--;
1734         }
1735
1736         if (!remain)
1737                 return -EINVAL;
1738
1739         flags = reg->offset & (entry->size - 1);
1740
1741         with_intel_runtime_pm(dev_priv, wakeref) {
1742                 if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
1743                         reg->val = I915_READ64_2x32(entry->offset_ldw,
1744                                                     entry->offset_udw);
1745                 else if (entry->size == 8 && flags == 0)
1746                         reg->val = I915_READ64(entry->offset_ldw);
1747                 else if (entry->size == 4 && flags == 0)
1748                         reg->val = I915_READ(entry->offset_ldw);
1749                 else if (entry->size == 2 && flags == 0)
1750                         reg->val = I915_READ16(entry->offset_ldw);
1751                 else if (entry->size == 1 && flags == 0)
1752                         reg->val = I915_READ8(entry->offset_ldw);
1753                 else
1754                         ret = -EINVAL;
1755         }
1756
1757         return ret;
1758 }
1759
1760 /**
1761  * __intel_wait_for_register_fw - wait until register matches expected state
1762  * @dev_priv: the i915 device
1763  * @reg: the register to read
1764  * @mask: mask to apply to register value
1765  * @value: expected value
1766  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1767  * @slow_timeout_ms: slow timeout in millisecond
1768  * @out_value: optional placeholder to hold registry value
1769  *
1770  * This routine waits until the target register @reg contains the expected
1771  * @value after applying the @mask, i.e. it waits until ::
1772  *
1773  *     (I915_READ_FW(reg) & mask) == value
1774  *
1775  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
1776  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
1777  * must be not larger than 20,0000 microseconds.
1778  *
1779  * Note that this routine assumes the caller holds forcewake asserted, it is
1780  * not suitable for very long waits. See intel_wait_for_register() if you
1781  * wish to wait without holding forcewake for the duration (i.e. you expect
1782  * the wait to be slow).
1783  *
1784  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1785  */
1786 int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
1787                                  i915_reg_t reg,
1788                                  u32 mask,
1789                                  u32 value,
1790                                  unsigned int fast_timeout_us,
1791                                  unsigned int slow_timeout_ms,
1792                                  u32 *out_value)
1793 {
1794         u32 uninitialized_var(reg_value);
1795 #define done (((reg_value = I915_READ_FW(reg)) & mask) == value)
1796         int ret;
1797
1798         /* Catch any overuse of this function */
1799         might_sleep_if(slow_timeout_ms);
1800         GEM_BUG_ON(fast_timeout_us > 20000);
1801
1802         ret = -ETIMEDOUT;
1803         if (fast_timeout_us && fast_timeout_us <= 20000)
1804                 ret = _wait_for_atomic(done, fast_timeout_us, 0);
1805         if (ret && slow_timeout_ms)
1806                 ret = wait_for(done, slow_timeout_ms);
1807
1808         if (out_value)
1809                 *out_value = reg_value;
1810
1811         return ret;
1812 #undef done
1813 }
1814
1815 /**
1816  * __intel_wait_for_register - wait until register matches expected state
1817  * @dev_priv: the i915 device
1818  * @reg: the register to read
1819  * @mask: mask to apply to register value
1820  * @value: expected value
1821  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1822  * @slow_timeout_ms: slow timeout in millisecond
1823  * @out_value: optional placeholder to hold registry value
1824  *
1825  * This routine waits until the target register @reg contains the expected
1826  * @value after applying the @mask, i.e. it waits until ::
1827  *
1828  *     (I915_READ(reg) & mask) == value
1829  *
1830  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1831  *
1832  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1833  */
1834 int __intel_wait_for_register(struct drm_i915_private *dev_priv,
1835                             i915_reg_t reg,
1836                             u32 mask,
1837                             u32 value,
1838                             unsigned int fast_timeout_us,
1839                             unsigned int slow_timeout_ms,
1840                             u32 *out_value)
1841 {
1842         struct intel_uncore *uncore = &dev_priv->uncore;
1843         unsigned fw =
1844                 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
1845         u32 reg_value;
1846         int ret;
1847
1848         might_sleep_if(slow_timeout_ms);
1849
1850         spin_lock_irq(&uncore->lock);
1851         intel_uncore_forcewake_get__locked(uncore, fw);
1852
1853         ret = __intel_wait_for_register_fw(dev_priv,
1854                                            reg, mask, value,
1855                                            fast_timeout_us, 0, &reg_value);
1856
1857         intel_uncore_forcewake_put__locked(uncore, fw);
1858         spin_unlock_irq(&uncore->lock);
1859
1860         if (ret && slow_timeout_ms)
1861                 ret = __wait_for(reg_value = I915_READ_NOTRACE(reg),
1862                                  (reg_value & mask) == value,
1863                                  slow_timeout_ms * 1000, 10, 1000);
1864
1865         /* just trace the final value */
1866         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
1867
1868         if (out_value)
1869                 *out_value = reg_value;
1870
1871         return ret;
1872 }
1873
1874 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
1875 {
1876         return check_for_unclaimed_mmio(uncore);
1877 }
1878
1879 bool
1880 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
1881 {
1882         bool ret = false;
1883
1884         spin_lock_irq(&uncore->lock);
1885
1886         if (unlikely(uncore->unclaimed_mmio_check <= 0))
1887                 goto out;
1888
1889         if (unlikely(intel_uncore_unclaimed_mmio(uncore))) {
1890                 if (!i915_modparams.mmio_debug) {
1891                         DRM_DEBUG("Unclaimed register detected, "
1892                                   "enabling oneshot unclaimed register reporting. "
1893                                   "Please use i915.mmio_debug=N for more information.\n");
1894                         i915_modparams.mmio_debug++;
1895                 }
1896                 uncore->unclaimed_mmio_check--;
1897                 ret = true;
1898         }
1899
1900 out:
1901         spin_unlock_irq(&uncore->lock);
1902
1903         return ret;
1904 }
1905
1906 static enum forcewake_domains
1907 intel_uncore_forcewake_for_read(struct intel_uncore *uncore,
1908                                 i915_reg_t reg)
1909 {
1910         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1911         u32 offset = i915_mmio_reg_offset(reg);
1912         enum forcewake_domains fw_domains;
1913
1914         if (INTEL_GEN(i915) >= 11) {
1915                 fw_domains = __gen11_fwtable_reg_read_fw_domains(uncore, offset);
1916         } else if (HAS_FWTABLE(i915)) {
1917                 fw_domains = __fwtable_reg_read_fw_domains(uncore, offset);
1918         } else if (INTEL_GEN(i915) >= 6) {
1919                 fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
1920         } else {
1921                 /* on devices with FW we expect to hit one of the above cases */
1922                 if (intel_uncore_has_forcewake(uncore))
1923                         MISSING_CASE(INTEL_GEN(i915));
1924
1925                 fw_domains = 0;
1926         }
1927
1928         WARN_ON(fw_domains & ~uncore->fw_domains);
1929
1930         return fw_domains;
1931 }
1932
1933 static enum forcewake_domains
1934 intel_uncore_forcewake_for_write(struct intel_uncore *uncore,
1935                                  i915_reg_t reg)
1936 {
1937         struct drm_i915_private *i915 = uncore_to_i915(uncore);
1938         u32 offset = i915_mmio_reg_offset(reg);
1939         enum forcewake_domains fw_domains;
1940
1941         if (INTEL_GEN(i915) >= 11) {
1942                 fw_domains = __gen11_fwtable_reg_write_fw_domains(uncore, offset);
1943         } else if (HAS_FWTABLE(i915) && !IS_VALLEYVIEW(i915)) {
1944                 fw_domains = __fwtable_reg_write_fw_domains(uncore, offset);
1945         } else if (IS_GEN(i915, 8)) {
1946                 fw_domains = __gen8_reg_write_fw_domains(uncore, offset);
1947         } else if (IS_GEN_RANGE(i915, 6, 7)) {
1948                 fw_domains = FORCEWAKE_RENDER;
1949         } else {
1950                 /* on devices with FW we expect to hit one of the above cases */
1951                 if (intel_uncore_has_forcewake(uncore))
1952                         MISSING_CASE(INTEL_GEN(i915));
1953
1954                 fw_domains = 0;
1955         }
1956
1957         WARN_ON(fw_domains & ~uncore->fw_domains);
1958
1959         return fw_domains;
1960 }
1961
1962 /**
1963  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1964  *                                  a register
1965  * @uncore: pointer to struct intel_uncore
1966  * @reg: register in question
1967  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1968  *
1969  * Returns a set of forcewake domains required to be taken with for example
1970  * intel_uncore_forcewake_get for the specified register to be accessible in the
1971  * specified mode (read, write or read/write) with raw mmio accessors.
1972  *
1973  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1974  * callers to do FIFO management on their own or risk losing writes.
1975  */
1976 enum forcewake_domains
1977 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
1978                                i915_reg_t reg, unsigned int op)
1979 {
1980         enum forcewake_domains fw_domains = 0;
1981
1982         WARN_ON(!op);
1983
1984         if (!intel_uncore_has_forcewake(uncore))
1985                 return 0;
1986
1987         if (op & FW_REG_READ)
1988                 fw_domains = intel_uncore_forcewake_for_read(uncore, reg);
1989
1990         if (op & FW_REG_WRITE)
1991                 fw_domains |= intel_uncore_forcewake_for_write(uncore, reg);
1992
1993         return fw_domains;
1994 }
1995
1996 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1997 #include "selftests/mock_uncore.c"
1998 #include "selftests/intel_uncore.c"
1999 #endif