drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <drm/drm_managed.h>
  25 #include <linux/pm_runtime.h>
  26
  27 #include "gt/intel_engine_regs.h"
  28 #include "gt/intel_gt_regs.h"
  29
  30 #include "i915_drv.h"
  31 #include "i915_iosf_mbi.h"
  32 #include "i915_trace.h"
  33 #include "i915_vgpu.h"
  34 #include "intel_pm.h"
  35
  36 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  37 #define GT_FIFO_TIMEOUT_MS       10
  38
  39 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
  40
  41 static void
  42 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
  43 {
  44         uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
  45 }
  46
  47 void
  48 intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
  49 {
  50         spin_lock_init(&i915->mmio_debug.lock);
  51         i915->mmio_debug.unclaimed_mmio_check = 1;
  52
  53         i915->uncore.debug = &i915->mmio_debug;
  54 }
  55
  56 static void mmio_debug_suspend(struct intel_uncore *uncore)
  57 {
  58         if (!uncore->debug)
  59                 return;
  60
  61         spin_lock(&uncore->debug->lock);
  62
  63         /* Save and disable mmio debugging for the user bypass */
  64         if (!uncore->debug->suspend_count++) {
  65                 uncore->debug->saved_mmio_check = uncore->debug->unclaimed_mmio_check;
  66                 uncore->debug->unclaimed_mmio_check = 0;
  67         }
  68
  69         spin_unlock(&uncore->debug->lock);
  70 }
  71
  72 static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);
  73
  74 static void mmio_debug_resume(struct intel_uncore *uncore)
  75 {
  76         if (!uncore->debug)
  77                 return;
  78
  79         spin_lock(&uncore->debug->lock);
  80
  81         if (!--uncore->debug->suspend_count)
  82                 uncore->debug->unclaimed_mmio_check = uncore->debug->saved_mmio_check;
  83
  84         if (check_for_unclaimed_mmio(uncore))
  85                 drm_info(&uncore->i915->drm,
  86                          "Invalid mmio detected during user access\n");
  87
  88         spin_unlock(&uncore->debug->lock);
  89 }
  90
  91 static const char * const forcewake_domain_names[] = {
  92         "render",
  93         "gt",
  94         "media",
  95         "vdbox0",
  96         "vdbox1",
  97         "vdbox2",
  98         "vdbox3",
  99         "vdbox4",
 100         "vdbox5",
 101         "vdbox6",
 102         "vdbox7",
 103         "vebox0",
 104         "vebox1",
 105         "vebox2",
 106         "vebox3",
 107 };
 108
 109 const char *
 110 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
 111 {
 112         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
 113
 114         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
 115                 return forcewake_domain_names[id];
 116
 117         WARN_ON(id);
 118
 119         return "unknown";
 120 }
 121
 122 #define fw_ack(d) readl((d)->reg_ack)
 123 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
 124 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
 125
 126 static inline void
 127 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
 128 {
 129         /*
 130          * We don't really know if the powerwell for the forcewake domain we are
 131          * trying to reset here does exist at this point (engines could be fused
 132          * off in ICL+), so no waiting for acks
 133          */
 134         /* WaRsClearFWBitsAtReset */
 135         if (GRAPHICS_VER(d->uncore->i915) >= 12)
 136                 fw_clear(d, 0xefff);
 137         else
 138                 fw_clear(d, 0xffff);
 139 }
 140
 141 static inline void
 142 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
 143 {
 144         GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);
 145         d->uncore->fw_domains_timer |= d->mask;
 146         d->wake_count++;
 147         hrtimer_start_range_ns(&d->timer,
 148                                NSEC_PER_MSEC,
 149                                NSEC_PER_MSEC,
 150                                HRTIMER_MODE_REL);
 151 }
 152
 153 static inline int
 154 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
 155                const u32 ack,
 156                const u32 value)
 157 {
 158         return wait_for_atomic((fw_ack(d) & ack) == value,
 159                                FORCEWAKE_ACK_TIMEOUT_MS);
 160 }
 161
 162 static inline int
 163 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
 164                const u32 ack)
 165 {
 166         return __wait_for_ack(d, ack, 0);
 167 }
 168
 169 static inline int
 170 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
 171              const u32 ack)
 172 {
 173         return __wait_for_ack(d, ack, ack);
 174 }
 175
 176 static inline void
 177 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
 178 {
 179         if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
 180                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
 181                           intel_uncore_forcewake_domain_to_str(d->id));
 182                 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
 183         }
 184 }
 185
 186 enum ack_type {
 187         ACK_CLEAR = 0,
 188         ACK_SET
 189 };
 190
 191 static int
 192 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
 193                                  const enum ack_type type)
 194 {
 195         const u32 ack_bit = FORCEWAKE_KERNEL;
 196         const u32 value = type == ACK_SET ? ack_bit : 0;
 197         unsigned int pass;
 198         bool ack_detected;
 199
 200         /*
 201          * There is a possibility of driver's wake request colliding
 202          * with hardware's own wake requests and that can cause
 203          * hardware to not deliver the driver's ack message.
 204          *
 205          * Use a fallback bit toggle to kick the gpu state machine
 206          * in the hope that the original ack will be delivered along with
 207          * the fallback ack.
 208          *
 209          * This workaround is described in HSDES #1604254524 and it's known as:
 210          * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
 211          * although the name is a bit misleading.
 212          */
 213
 214         pass = 1;
 215         do {
 216                 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 217
 218                 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
 219                 /* Give gt some time to relax before the polling frenzy */
 220                 udelay(10 * pass);
 221                 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
 222
 223                 ack_detected = (fw_ack(d) & ack_bit) == value;
 224
 225                 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 226         } while (!ack_detected && pass++ < 10);
 227
 228         DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
 229                          intel_uncore_forcewake_domain_to_str(d->id),
 230                          type == ACK_SET ? "set" : "clear",
 231                          fw_ack(d),
 232                          pass);
 233
 234         return ack_detected ? 0 : -ETIMEDOUT;
 235 }
 236
 237 static inline void
 238 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
 239 {
 240         if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
 241                 return;
 242
 243         if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
 244                 fw_domain_wait_ack_clear(d);
 245 }
 246
 247 static inline void
 248 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
 249 {
 250         fw_set(d, FORCEWAKE_KERNEL);
 251 }
 252
 253 static inline void
 254 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
 255 {
 256         if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
 257                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 258                           intel_uncore_forcewake_domain_to_str(d->id));
 259                 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
 260         }
 261 }
 262
 263 static inline void
 264 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
 265 {
 266         if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
 267                 return;
 268
 269         if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
 270                 fw_domain_wait_ack_set(d);
 271 }
 272
 273 static inline void
 274 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 275 {
 276         fw_clear(d, FORCEWAKE_KERNEL);
 277 }
 278
 279 static void
 280 fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 281 {
 282         struct intel_uncore_forcewake_domain *d;
 283         unsigned int tmp;
 284
 285         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 286
 287         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 288                 fw_domain_wait_ack_clear(d);
 289                 fw_domain_get(d);
 290         }
 291
 292         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 293                 fw_domain_wait_ack_set(d);
 294
 295         uncore->fw_domains_active |= fw_domains;
 296 }
 297
 298 static void
 299 fw_domains_get_with_fallback(struct intel_uncore *uncore,
 300                              enum forcewake_domains fw_domains)
 301 {
 302         struct intel_uncore_forcewake_domain *d;
 303         unsigned int tmp;
 304
 305         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 306
 307         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 308                 fw_domain_wait_ack_clear_fallback(d);
 309                 fw_domain_get(d);
 310         }
 311
 312         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 313                 fw_domain_wait_ack_set_fallback(d);
 314
 315         uncore->fw_domains_active |= fw_domains;
 316 }
 317
 318 static void
 319 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 320 {
 321         struct intel_uncore_forcewake_domain *d;
 322         unsigned int tmp;
 323
 324         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 325
 326         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 327                 fw_domain_put(d);
 328
 329         uncore->fw_domains_active &= ~fw_domains;
 330 }
 331
 332 static void
 333 fw_domains_reset(struct intel_uncore *uncore,
 334                  enum forcewake_domains fw_domains)
 335 {
 336         struct intel_uncore_forcewake_domain *d;
 337         unsigned int tmp;
 338
 339         if (!fw_domains)
 340                 return;
 341
 342         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 343
 344         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 345                 fw_domain_reset(d);
 346 }
 347
 348 static inline u32 gt_thread_status(struct intel_uncore *uncore)
 349 {
 350         u32 val;
 351
 352         val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
 353         val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
 354
 355         return val;
 356 }
 357
 358 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
 359 {
 360         /*
 361          * w/a for a sporadic read returning 0 by waiting for the GT
 362          * thread to wake up.
 363          */
 364         drm_WARN_ONCE(&uncore->i915->drm,
 365                       wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
 366                       "GT thread status wait timed out\n");
 367 }
 368
 369 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
 370                                               enum forcewake_domains fw_domains)
 371 {
 372         fw_domains_get_normal(uncore, fw_domains);
 373
 374         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 375         __gen6_gt_wait_for_thread_c0(uncore);
 376 }
 377
 378 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
 379 {
 380         u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
 381
 382         return count & GT_FIFO_FREE_ENTRIES_MASK;
 383 }
 384
 385 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
 386 {
 387         u32 n;
 388
 389         /* On VLV, FIFO will be shared by both SW and HW.
 390          * So, we need to read the FREE_ENTRIES everytime */
 391         if (IS_VALLEYVIEW(uncore->i915))
 392                 n = fifo_free_entries(uncore);
 393         else
 394                 n = uncore->fifo_count;
 395
 396         if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
 397                 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
 398                                     GT_FIFO_NUM_RESERVED_ENTRIES,
 399                                     GT_FIFO_TIMEOUT_MS)) {
 400                         drm_dbg(&uncore->i915->drm,
 401                                 "GT_FIFO timeout, entries: %u\n", n);
 402                         return;
 403                 }
 404         }
 405
 406         uncore->fifo_count = n - 1;
 407 }
 408
 409 static enum hrtimer_restart
 410 intel_uncore_fw_release_timer(struct hrtimer *timer)
 411 {
 412         struct intel_uncore_forcewake_domain *domain =
 413                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 414         struct intel_uncore *uncore = domain->uncore;
 415         unsigned long irqflags;
 416
 417         assert_rpm_device_not_suspended(uncore->rpm);
 418
 419         if (xchg(&domain->active, false))
 420                 return HRTIMER_RESTART;
 421
 422         spin_lock_irqsave(&uncore->lock, irqflags);
 423
 424         uncore->fw_domains_timer &= ~domain->mask;
 425
 426         GEM_BUG_ON(!domain->wake_count);
 427         if (--domain->wake_count == 0)
 428                 fw_domains_put(uncore, domain->mask);
 429
 430         spin_unlock_irqrestore(&uncore->lock, irqflags);
 431
 432         return HRTIMER_NORESTART;
 433 }
 434
 435 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
 436 static unsigned int
 437 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
 438 {
 439         unsigned long irqflags;
 440         struct intel_uncore_forcewake_domain *domain;
 441         int retry_count = 100;
 442         enum forcewake_domains fw, active_domains;
 443
 444         iosf_mbi_assert_punit_acquired();
 445
 446         /* Hold uncore.lock across reset to prevent any register access
 447          * with forcewake not set correctly. Wait until all pending
 448          * timers are run before holding.
 449          */
 450         while (1) {
 451                 unsigned int tmp;
 452
 453                 active_domains = 0;
 454
 455                 for_each_fw_domain(domain, uncore, tmp) {
 456                         smp_store_mb(domain->active, false);
 457                         if (hrtimer_cancel(&domain->timer) == 0)
 458                                 continue;
 459
 460                         intel_uncore_fw_release_timer(&domain->timer);
 461                 }
 462
 463                 spin_lock_irqsave(&uncore->lock, irqflags);
 464
 465                 for_each_fw_domain(domain, uncore, tmp) {
 466                         if (hrtimer_active(&domain->timer))
 467                                 active_domains |= domain->mask;
 468                 }
 469
 470                 if (active_domains == 0)
 471                         break;
 472
 473                 if (--retry_count == 0) {
 474                         drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n");
 475                         break;
 476                 }
 477
 478                 spin_unlock_irqrestore(&uncore->lock, irqflags);
 479                 cond_resched();
 480         }
 481
 482         drm_WARN_ON(&uncore->i915->drm, active_domains);
 483
 484         fw = uncore->fw_domains_active;
 485         if (fw)
 486                 fw_domains_put(uncore, fw);
 487
 488         fw_domains_reset(uncore, uncore->fw_domains);
 489         assert_forcewakes_inactive(uncore);
 490
 491         spin_unlock_irqrestore(&uncore->lock, irqflags);
 492
 493         return fw; /* track the lost user forcewake domains */
 494 }
 495
 496 static bool
 497 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 498 {
 499         u32 dbg;
 500
 501         dbg = __raw_uncore_read32(uncore, FPGA_DBG);
 502         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 503                 return false;
 504
 505         /*
 506          * Bugs in PCI programming (or failing hardware) can occasionally cause
 507          * us to lose access to the MMIO BAR.  When this happens, register
 508          * reads will come back with 0xFFFFFFFF for every register and things
 509          * go bad very quickly.  Let's try to detect that special case and at
 510          * least try to print a more informative message about what has
 511          * happened.
 512          *
 513          * During normal operation the FPGA_DBG register has several unused
 514          * bits that will always read back as 0's so we can use them as canaries
 515          * to recognize when MMIO accesses are just busted.
 516          */
 517         if (unlikely(dbg == ~0))
 518                 drm_err(&uncore->i915->drm,
 519                         "Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n");
 520
 521         __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 522
 523         return true;
 524 }
 525
 526 static bool
 527 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 528 {
 529         u32 cer;
 530
 531         cer = __raw_uncore_read32(uncore, CLAIM_ER);
 532         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 533                 return false;
 534
 535         __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
 536
 537         return true;
 538 }
 539
 540 static bool
 541 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
 542 {
 543         u32 fifodbg;
 544
 545         fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
 546
 547         if (unlikely(fifodbg)) {
 548                 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
 549                 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
 550         }
 551
 552         return fifodbg;
 553 }
 554
 555 static bool
 556 check_for_unclaimed_mmio(struct intel_uncore *uncore)
 557 {
 558         bool ret = false;
 559
 560         lockdep_assert_held(&uncore->debug->lock);
 561
 562         if (uncore->debug->suspend_count)
 563                 return false;
 564
 565         if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
 566                 ret |= fpga_check_for_unclaimed_mmio(uncore);
 567
 568         if (intel_uncore_has_dbg_unclaimed(uncore))
 569                 ret |= vlv_check_for_unclaimed_mmio(uncore);
 570
 571         if (intel_uncore_has_fifo(uncore))
 572                 ret |= gen6_check_for_fifo_debug(uncore);
 573
 574         return ret;
 575 }
 576
 577 static void forcewake_early_sanitize(struct intel_uncore *uncore,
 578                                      unsigned int restore_forcewake)
 579 {
 580         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
 581
 582         /* WaDisableShadowRegForCpd:chv */
 583         if (IS_CHERRYVIEW(uncore->i915)) {
 584                 __raw_uncore_write32(uncore, GTFIFOCTL,
 585                                      __raw_uncore_read32(uncore, GTFIFOCTL) |
 586                                      GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 587                                      GT_FIFO_CTL_RC6_POLICY_STALL);
 588         }
 589
 590         iosf_mbi_punit_acquire();
 591         intel_uncore_forcewake_reset(uncore);
 592         if (restore_forcewake) {
 593                 spin_lock_irq(&uncore->lock);
 594                 fw_domains_get(uncore, restore_forcewake);
 595
 596                 if (intel_uncore_has_fifo(uncore))
 597                         uncore->fifo_count = fifo_free_entries(uncore);
 598                 spin_unlock_irq(&uncore->lock);
 599         }
 600         iosf_mbi_punit_release();
 601 }
 602
 603 void intel_uncore_suspend(struct intel_uncore *uncore)
 604 {
 605         if (!intel_uncore_has_forcewake(uncore))
 606                 return;
 607
 608         iosf_mbi_punit_acquire();
 609         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
 610                 &uncore->pmic_bus_access_nb);
 611         uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
 612         iosf_mbi_punit_release();
 613 }
 614
 615 void intel_uncore_resume_early(struct intel_uncore *uncore)
 616 {
 617         unsigned int restore_forcewake;
 618
 619         if (intel_uncore_unclaimed_mmio(uncore))
 620                 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
 621
 622         if (!intel_uncore_has_forcewake(uncore))
 623                 return;
 624
 625         restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
 626         forcewake_early_sanitize(uncore, restore_forcewake);
 627
 628         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 629 }
 630
 631 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
 632 {
 633         if (!intel_uncore_has_forcewake(uncore))
 634                 return;
 635
 636         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 637 }
 638
 639 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
 640                                          enum forcewake_domains fw_domains)
 641 {
 642         struct intel_uncore_forcewake_domain *domain;
 643         unsigned int tmp;
 644
 645         fw_domains &= uncore->fw_domains;
 646
 647         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 648                 if (domain->wake_count++) {
 649                         fw_domains &= ~domain->mask;
 650                         domain->active = true;
 651                 }
 652         }
 653
 654         if (fw_domains)
 655                 fw_domains_get(uncore, fw_domains);
 656 }
 657
 658 /**
 659  * intel_uncore_forcewake_get - grab forcewake domain references
 660  * @uncore: the intel_uncore structure
 661  * @fw_domains: forcewake domains to get reference on
 662  *
 663  * This function can be used get GT's forcewake domain references.
 664  * Normal register access will handle the forcewake domains automatically.
 665  * However if some sequence requires the GT to not power down a particular
 666  * forcewake domains this function should be called at the beginning of the
 667  * sequence. And subsequently the reference should be dropped by symmetric
 668  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 669  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 670  */
 671 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 672                                 enum forcewake_domains fw_domains)
 673 {
 674         unsigned long irqflags;
 675
 676         if (!uncore->fw_get_funcs)
 677                 return;
 678
 679         assert_rpm_wakelock_held(uncore->rpm);
 680
 681         spin_lock_irqsave(&uncore->lock, irqflags);
 682         __intel_uncore_forcewake_get(uncore, fw_domains);
 683         spin_unlock_irqrestore(&uncore->lock, irqflags);
 684 }
 685
 686 /**
 687  * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
 688  * @uncore: the intel_uncore structure
 689  *
 690  * This function is a wrapper around intel_uncore_forcewake_get() to acquire
 691  * the GT powerwell and in the process disable our debugging for the
 692  * duration of userspace's bypass.
 693  */
 694 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
 695 {
 696         spin_lock_irq(&uncore->lock);
 697         if (!uncore->user_forcewake_count++) {
 698                 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
 699                 mmio_debug_suspend(uncore);
 700         }
 701         spin_unlock_irq(&uncore->lock);
 702 }
 703
 704 /**
 705  * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
 706  * @uncore: the intel_uncore structure
 707  *
 708  * This function complements intel_uncore_forcewake_user_get() and releases
 709  * the GT powerwell taken on behalf of the userspace bypass.
 710  */
 711 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
 712 {
 713         spin_lock_irq(&uncore->lock);
 714         if (!--uncore->user_forcewake_count) {
 715                 mmio_debug_resume(uncore);
 716                 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
 717         }
 718         spin_unlock_irq(&uncore->lock);
 719 }
 720
 721 /**
 722  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 723  * @uncore: the intel_uncore structure
 724  * @fw_domains: forcewake domains to get reference on
 725  *
 726  * See intel_uncore_forcewake_get(). This variant places the onus
 727  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 728  */
 729 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 730                                         enum forcewake_domains fw_domains)
 731 {
 732         lockdep_assert_held(&uncore->lock);
 733
 734         if (!uncore->fw_get_funcs)
 735                 return;
 736
 737         __intel_uncore_forcewake_get(uncore, fw_domains);
 738 }
 739
 740 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
 741                                          enum forcewake_domains fw_domains,
 742                                          bool delayed)
 743 {
 744         struct intel_uncore_forcewake_domain *domain;
 745         unsigned int tmp;
 746
 747         fw_domains &= uncore->fw_domains;
 748
 749         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 750                 GEM_BUG_ON(!domain->wake_count);
 751
 752                 if (--domain->wake_count) {
 753                         domain->active = true;
 754                         continue;
 755                 }
 756
 757                 if (delayed &&
 758                     !(domain->uncore->fw_domains_timer & domain->mask))
 759                         fw_domain_arm_timer(domain);
 760                 else
 761                         fw_domains_put(uncore, domain->mask);
 762         }
 763 }
 764
 765 /**
 766  * intel_uncore_forcewake_put - release a forcewake domain reference
 767  * @uncore: the intel_uncore structure
 768  * @fw_domains: forcewake domains to put references
 769  *
 770  * This function drops the device-level forcewakes for specified
 771  * domains obtained by intel_uncore_forcewake_get().
 772  */
 773 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 774                                 enum forcewake_domains fw_domains)
 775 {
 776         unsigned long irqflags;
 777
 778         if (!uncore->fw_get_funcs)
 779                 return;
 780
 781         spin_lock_irqsave(&uncore->lock, irqflags);
 782         __intel_uncore_forcewake_put(uncore, fw_domains, false);
 783         spin_unlock_irqrestore(&uncore->lock, irqflags);
 784 }
 785
 786 void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
 787                                         enum forcewake_domains fw_domains)
 788 {
 789         unsigned long irqflags;
 790
 791         if (!uncore->fw_get_funcs)
 792                 return;
 793
 794         spin_lock_irqsave(&uncore->lock, irqflags);
 795         __intel_uncore_forcewake_put(uncore, fw_domains, true);
 796         spin_unlock_irqrestore(&uncore->lock, irqflags);
 797 }
 798
 799 /**
 800  * intel_uncore_forcewake_flush - flush the delayed release
 801  * @uncore: the intel_uncore structure
 802  * @fw_domains: forcewake domains to flush
 803  */
 804 void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
 805                                   enum forcewake_domains fw_domains)
 806 {
 807         struct intel_uncore_forcewake_domain *domain;
 808         unsigned int tmp;
 809
 810         if (!uncore->fw_get_funcs)
 811                 return;
 812
 813         fw_domains &= uncore->fw_domains;
 814         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 815                 WRITE_ONCE(domain->active, false);
 816                 if (hrtimer_cancel(&domain->timer))
 817                         intel_uncore_fw_release_timer(&domain->timer);
 818         }
 819 }
 820
 821 /**
 822  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 823  * @uncore: the intel_uncore structure
 824  * @fw_domains: forcewake domains to get reference on
 825  *
 826  * See intel_uncore_forcewake_put(). This variant places the onus
 827  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 828  */
 829 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 830                                         enum forcewake_domains fw_domains)
 831 {
 832         lockdep_assert_held(&uncore->lock);
 833
 834         if (!uncore->fw_get_funcs)
 835                 return;
 836
 837         __intel_uncore_forcewake_put(uncore, fw_domains, false);
 838 }
 839
 840 void assert_forcewakes_inactive(struct intel_uncore *uncore)
 841 {
 842         if (!uncore->fw_get_funcs)
 843                 return;
 844
 845         drm_WARN(&uncore->i915->drm, uncore->fw_domains_active,
 846                  "Expected all fw_domains to be inactive, but %08x are still on\n",
 847                  uncore->fw_domains_active);
 848 }
 849
 850 void assert_forcewakes_active(struct intel_uncore *uncore,
 851                               enum forcewake_domains fw_domains)
 852 {
 853         struct intel_uncore_forcewake_domain *domain;
 854         unsigned int tmp;
 855
 856         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 857                 return;
 858
 859         if (!uncore->fw_get_funcs)
 860                 return;
 861
 862         spin_lock_irq(&uncore->lock);
 863
 864         assert_rpm_wakelock_held(uncore->rpm);
 865
 866         fw_domains &= uncore->fw_domains;
 867         drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active,
 868                  "Expected %08x fw_domains to be active, but %08x are off\n",
 869                  fw_domains, fw_domains & ~uncore->fw_domains_active);
 870
 871         /*
 872          * Check that the caller has an explicit wakeref and we don't mistake
 873          * it for the auto wakeref.
 874          */
 875         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 876                 unsigned int actual = READ_ONCE(domain->wake_count);
 877                 unsigned int expect = 1;
 878
 879                 if (uncore->fw_domains_timer & domain->mask)
 880                         expect++; /* pending automatic release */
 881
 882                 if (drm_WARN(&uncore->i915->drm, actual < expect,
 883                              "Expected domain %d to be held awake by caller, count=%d\n",
 884                              domain->id, actual))
 885                         break;
 886         }
 887
 888         spin_unlock_irq(&uncore->lock);
 889 }
 890
 891 /* We give fast paths for the really cool registers */
 892 #define NEEDS_FORCE_WAKE(reg) ({ \
 893         u32 __reg = (reg); \
 894         __reg < 0x40000 || __reg >= GEN11_BSD_RING_BASE; \
 895 })
 896
 897 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 898 {
 899         if (offset < entry->start)
 900                 return -1;
 901         else if (offset > entry->end)
 902                 return 1;
 903         else
 904                 return 0;
 905 }
 906
 907 /* Copied and "macroized" from lib/bsearch.c */
 908 #define BSEARCH(key, base, num, cmp) ({                                 \
 909         unsigned int start__ = 0, end__ = (num);                        \
 910         typeof(base) result__ = NULL;                                   \
 911         while (start__ < end__) {                                       \
 912                 unsigned int mid__ = start__ + (end__ - start__) / 2;   \
 913                 int ret__ = (cmp)((key), (base) + mid__);               \
 914                 if (ret__ < 0) {                                        \
 915                         end__ = mid__;                                  \
 916                 } else if (ret__ > 0) {                                 \
 917                         start__ = mid__ + 1;                            \
 918                 } else {                                                \
 919                         result__ = (base) + mid__;                      \
 920                         break;                                          \
 921                 }                                                       \
 922         }                                                               \
 923         result__;                                                       \
 924 })
 925
 926 static enum forcewake_domains
 927 find_fw_domain(struct intel_uncore *uncore, u32 offset)
 928 {
 929         const struct intel_forcewake_range *entry;
 930
 931         if (IS_GSI_REG(offset))
 932                 offset += uncore->gsi_offset;
 933
 934         entry = BSEARCH(offset,
 935                         uncore->fw_domains_table,
 936                         uncore->fw_domains_table_entries,
 937                         fw_range_cmp);
 938
 939         if (!entry)
 940                 return 0;
 941
 942         /*
 943          * The list of FW domains depends on the SKU in gen11+ so we
 944          * can't determine it statically. We use FORCEWAKE_ALL and
 945          * translate it here to the list of available domains.
 946          */
 947         if (entry->domains == FORCEWAKE_ALL)
 948                 return uncore->fw_domains;
 949
 950         drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains,
 951                  "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 952                  entry->domains & ~uncore->fw_domains, offset);
 953
 954         return entry->domains;
 955 }
 956
 957 /*
 958  * Shadowed register tables describe special register ranges that i915 is
 959  * allowed to write to without acquiring forcewake.  If these registers' power
 960  * wells are down, the hardware will save values written by i915 to a shadow
 961  * copy and automatically transfer them into the real register the next time
 962  * the power well is woken up.  Shadowing only applies to writes; forcewake
 963  * must still be acquired when reading from registers in these ranges.
 964  *
 965  * The documentation for shadowed registers is somewhat spotty on older
 966  * platforms.  However missing registers from these lists is non-fatal; it just
 967  * means we'll wake up the hardware for some register accesses where we didn't
 968  * really need to.
 969  *
 970  * The ranges listed in these tables must be sorted by offset.
 971  *
 972  * When adding new tables here, please also add them to
 973  * intel_shadow_table_check() in selftests/intel_uncore.c so that they will be
 974  * scanned for obvious mistakes or typos by the selftests.
 975  */
 976
 977 static const struct i915_range gen8_shadowed_regs[] = {
 978         { .start =  0x2030, .end =  0x2030 },
 979         { .start =  0xA008, .end =  0xA00C },
 980         { .start = 0x12030, .end = 0x12030 },
 981         { .start = 0x1a030, .end = 0x1a030 },
 982         { .start = 0x22030, .end = 0x22030 },
 983 };
 984
 985 static const struct i915_range gen11_shadowed_regs[] = {
 986         { .start =   0x2030, .end =   0x2030 },
 987         { .start =   0x2550, .end =   0x2550 },
 988         { .start =   0xA008, .end =   0xA00C },
 989         { .start =  0x22030, .end =  0x22030 },
 990         { .start =  0x22230, .end =  0x22230 },
 991         { .start =  0x22510, .end =  0x22550 },
 992         { .start = 0x1C0030, .end = 0x1C0030 },
 993         { .start = 0x1C0230, .end = 0x1C0230 },
 994         { .start = 0x1C0510, .end = 0x1C0550 },
 995         { .start = 0x1C4030, .end = 0x1C4030 },
 996         { .start = 0x1C4230, .end = 0x1C4230 },
 997         { .start = 0x1C4510, .end = 0x1C4550 },
 998         { .start = 0x1C8030, .end = 0x1C8030 },
 999         { .start = 0x1C8230, .end = 0x1C8230 },
1000         { .start = 0x1C8510, .end = 0x1C8550 },
1001         { .start = 0x1D0030, .end = 0x1D0030 },
1002         { .start = 0x1D0230, .end = 0x1D0230 },
1003         { .start = 0x1D0510, .end = 0x1D0550 },
1004         { .start = 0x1D4030, .end = 0x1D4030 },
1005         { .start = 0x1D4230, .end = 0x1D4230 },
1006         { .start = 0x1D4510, .end = 0x1D4550 },
1007         { .start = 0x1D8030, .end = 0x1D8030 },
1008         { .start = 0x1D8230, .end = 0x1D8230 },
1009         { .start = 0x1D8510, .end = 0x1D8550 },
1010 };
1011
1012 static const struct i915_range gen12_shadowed_regs[] = {
1013         { .start =   0x2030, .end =   0x2030 },
1014         { .start =   0x2510, .end =   0x2550 },
1015         { .start =   0xA008, .end =   0xA00C },
1016         { .start =   0xA188, .end =   0xA188 },
1017         { .start =   0xA278, .end =   0xA278 },
1018         { .start =   0xA540, .end =   0xA56C },
1019         { .start =   0xC4C8, .end =   0xC4C8 },
1020         { .start =   0xC4D4, .end =   0xC4D4 },
1021         { .start =   0xC600, .end =   0xC600 },
1022         { .start =  0x22030, .end =  0x22030 },
1023         { .start =  0x22510, .end =  0x22550 },
1024         { .start = 0x1C0030, .end = 0x1C0030 },
1025         { .start = 0x1C0510, .end = 0x1C0550 },
1026         { .start = 0x1C4030, .end = 0x1C4030 },
1027         { .start = 0x1C4510, .end = 0x1C4550 },
1028         { .start = 0x1C8030, .end = 0x1C8030 },
1029         { .start = 0x1C8510, .end = 0x1C8550 },
1030         { .start = 0x1D0030, .end = 0x1D0030 },
1031         { .start = 0x1D0510, .end = 0x1D0550 },
1032         { .start = 0x1D4030, .end = 0x1D4030 },
1033         { .start = 0x1D4510, .end = 0x1D4550 },
1034         { .start = 0x1D8030, .end = 0x1D8030 },
1035         { .start = 0x1D8510, .end = 0x1D8550 },
1036
1037         /*
1038          * The rest of these ranges are specific to Xe_HP and beyond, but
1039          * are reserved/unused ranges on earlier gen12 platforms, so they can
1040          * be safely added to the gen12 table.
1041          */
1042         { .start = 0x1E0030, .end = 0x1E0030 },
1043         { .start = 0x1E0510, .end = 0x1E0550 },
1044         { .start = 0x1E4030, .end = 0x1E4030 },
1045         { .start = 0x1E4510, .end = 0x1E4550 },
1046         { .start = 0x1E8030, .end = 0x1E8030 },
1047         { .start = 0x1E8510, .end = 0x1E8550 },
1048         { .start = 0x1F0030, .end = 0x1F0030 },
1049         { .start = 0x1F0510, .end = 0x1F0550 },
1050         { .start = 0x1F4030, .end = 0x1F4030 },
1051         { .start = 0x1F4510, .end = 0x1F4550 },
1052         { .start = 0x1F8030, .end = 0x1F8030 },
1053         { .start = 0x1F8510, .end = 0x1F8550 },
1054 };
1055
1056 static const struct i915_range dg2_shadowed_regs[] = {
1057         { .start =   0x2030, .end =   0x2030 },
1058         { .start =   0x2510, .end =   0x2550 },
1059         { .start =   0xA008, .end =   0xA00C },
1060         { .start =   0xA188, .end =   0xA188 },
1061         { .start =   0xA278, .end =   0xA278 },
1062         { .start =   0xA540, .end =   0xA56C },
1063         { .start =   0xC4C8, .end =   0xC4C8 },
1064         { .start =   0xC4E0, .end =   0xC4E0 },
1065         { .start =   0xC600, .end =   0xC600 },
1066         { .start =   0xC658, .end =   0xC658 },
1067         { .start =  0x22030, .end =  0x22030 },
1068         { .start =  0x22510, .end =  0x22550 },
1069         { .start = 0x1C0030, .end = 0x1C0030 },
1070         { .start = 0x1C0510, .end = 0x1C0550 },
1071         { .start = 0x1C4030, .end = 0x1C4030 },
1072         { .start = 0x1C4510, .end = 0x1C4550 },
1073         { .start = 0x1C8030, .end = 0x1C8030 },
1074         { .start = 0x1C8510, .end = 0x1C8550 },
1075         { .start = 0x1D0030, .end = 0x1D0030 },
1076         { .start = 0x1D0510, .end = 0x1D0550 },
1077         { .start = 0x1D4030, .end = 0x1D4030 },
1078         { .start = 0x1D4510, .end = 0x1D4550 },
1079         { .start = 0x1D8030, .end = 0x1D8030 },
1080         { .start = 0x1D8510, .end = 0x1D8550 },
1081         { .start = 0x1E0030, .end = 0x1E0030 },
1082         { .start = 0x1E0510, .end = 0x1E0550 },
1083         { .start = 0x1E4030, .end = 0x1E4030 },
1084         { .start = 0x1E4510, .end = 0x1E4550 },
1085         { .start = 0x1E8030, .end = 0x1E8030 },
1086         { .start = 0x1E8510, .end = 0x1E8550 },
1087         { .start = 0x1F0030, .end = 0x1F0030 },
1088         { .start = 0x1F0510, .end = 0x1F0550 },
1089         { .start = 0x1F4030, .end = 0x1F4030 },
1090         { .start = 0x1F4510, .end = 0x1F4550 },
1091         { .start = 0x1F8030, .end = 0x1F8030 },
1092         { .start = 0x1F8510, .end = 0x1F8550 },
1093 };
1094
1095 static const struct i915_range pvc_shadowed_regs[] = {
1096         { .start =   0x2030, .end =   0x2030 },
1097         { .start =   0x2510, .end =   0x2550 },
1098         { .start =   0xA008, .end =   0xA00C },
1099         { .start =   0xA188, .end =   0xA188 },
1100         { .start =   0xA278, .end =   0xA278 },
1101         { .start =   0xA540, .end =   0xA56C },
1102         { .start =   0xC4C8, .end =   0xC4C8 },
1103         { .start =   0xC4E0, .end =   0xC4E0 },
1104         { .start =   0xC600, .end =   0xC600 },
1105         { .start =   0xC658, .end =   0xC658 },
1106         { .start =  0x22030, .end =  0x22030 },
1107         { .start =  0x22510, .end =  0x22550 },
1108         { .start = 0x1C0030, .end = 0x1C0030 },
1109         { .start = 0x1C0510, .end = 0x1C0550 },
1110         { .start = 0x1C4030, .end = 0x1C4030 },
1111         { .start = 0x1C4510, .end = 0x1C4550 },
1112         { .start = 0x1C8030, .end = 0x1C8030 },
1113         { .start = 0x1C8510, .end = 0x1C8550 },
1114         { .start = 0x1D0030, .end = 0x1D0030 },
1115         { .start = 0x1D0510, .end = 0x1D0550 },
1116         { .start = 0x1D4030, .end = 0x1D4030 },
1117         { .start = 0x1D4510, .end = 0x1D4550 },
1118         { .start = 0x1D8030, .end = 0x1D8030 },
1119         { .start = 0x1D8510, .end = 0x1D8550 },
1120         { .start = 0x1E0030, .end = 0x1E0030 },
1121         { .start = 0x1E0510, .end = 0x1E0550 },
1122         { .start = 0x1E4030, .end = 0x1E4030 },
1123         { .start = 0x1E4510, .end = 0x1E4550 },
1124         { .start = 0x1E8030, .end = 0x1E8030 },
1125         { .start = 0x1E8510, .end = 0x1E8550 },
1126         { .start = 0x1F0030, .end = 0x1F0030 },
1127         { .start = 0x1F0510, .end = 0x1F0550 },
1128         { .start = 0x1F4030, .end = 0x1F4030 },
1129         { .start = 0x1F4510, .end = 0x1F4550 },
1130         { .start = 0x1F8030, .end = 0x1F8030 },
1131         { .start = 0x1F8510, .end = 0x1F8550 },
1132 };
1133
1134 static int mmio_range_cmp(u32 key, const struct i915_range *range)
1135 {
1136         if (key < range->start)
1137                 return -1;
1138         else if (key > range->end)
1139                 return 1;
1140         else
1141                 return 0;
1142 }
1143
1144 static bool is_shadowed(struct intel_uncore *uncore, u32 offset)
1145 {
1146         if (drm_WARN_ON(&uncore->i915->drm, !uncore->shadowed_reg_table))
1147                 return false;
1148
1149         if (IS_GSI_REG(offset))
1150                 offset += uncore->gsi_offset;
1151
1152         return BSEARCH(offset,
1153                        uncore->shadowed_reg_table,
1154                        uncore->shadowed_reg_table_entries,
1155                        mmio_range_cmp);
1156 }
1157
1158 static enum forcewake_domains
1159 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
1160 {
1161         return FORCEWAKE_RENDER;
1162 }
1163
1164 #define __fwtable_reg_read_fw_domains(uncore, offset) \
1165 ({ \
1166         enum forcewake_domains __fwd = 0; \
1167         if (NEEDS_FORCE_WAKE((offset))) \
1168                 __fwd = find_fw_domain(uncore, offset); \
1169         __fwd; \
1170 })
1171
1172 #define __fwtable_reg_write_fw_domains(uncore, offset) \
1173 ({ \
1174         enum forcewake_domains __fwd = 0; \
1175         const u32 __offset = (offset); \
1176         if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
1177                 __fwd = find_fw_domain(uncore, __offset); \
1178         __fwd; \
1179 })
1180
1181 #define GEN_FW_RANGE(s, e, d) \
1182         { .start = (s), .end = (e), .domains = (d) }
1183
1184 /*
1185  * All platforms' forcewake tables below must be sorted by offset ranges.
1186  * Furthermore, new forcewake tables added should be "watertight" and have
1187  * no gaps between ranges.
1188  *
1189  * When there are multiple consecutive ranges listed in the bspec with
1190  * the same forcewake domain, it is customary to combine them into a single
1191  * row in the tables below to keep the tables small and lookups fast.
1192  * Likewise, reserved/unused ranges may be combined with the preceding and/or
1193  * following ranges since the driver will never be making MMIO accesses in
1194  * those ranges.
1195  *
1196  * For example, if the bspec were to list:
1197  *
1198  *    ...
1199  *    0x1000 - 0x1fff:  GT
1200  *    0x2000 - 0x2cff:  GT
1201  *    0x2d00 - 0x2fff:  unused/reserved
1202  *    0x3000 - 0xffff:  GT
1203  *    ...
1204  *
1205  * these could all be represented by a single line in the code:
1206  *
1207  *   GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT)
1208  *
1209  * When adding new forcewake tables here, please also add them to
1210  * intel_uncore_mock_selftests in selftests/intel_uncore.c so that they will be
1211  * scanned for obvious mistakes or typos by the selftests.
1212  */
1213
1214 static const struct intel_forcewake_range __gen6_fw_ranges[] = {
1215         GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER),
1216 };
1217
1218 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
1219         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1220         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
1221         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
1222         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1223         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
1224         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
1225         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1226 };
1227
1228 static const struct intel_forcewake_range __chv_fw_ranges[] = {
1229         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1230         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1231         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1232         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1233         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1234         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1235         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
1236         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1237         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1238         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1239         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
1240         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1241         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1242         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
1243         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
1244         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
1245 };
1246
1247 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
1248         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
1249         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1250         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1251         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1252         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1253         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1254         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1255         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT),
1256         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1257         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1258         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1259         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1260         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1261         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1262         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT),
1263         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1264         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
1265         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1266         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1267         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1268         GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT),
1269         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1270         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT),
1271         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1272         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT),
1273         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1274         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT),
1275         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1276         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT),
1277         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1278         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT),
1279         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1280 };
1281
1282 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1283         GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
1284         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1285         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1286         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1287         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1288         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1289         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1290         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1291         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1292         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1293         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1294         GEN_FW_RANGE(0x8800, 0x8bff, 0),
1295         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1296         GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT),
1297         GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1298         GEN_FW_RANGE(0x9560, 0x95ff, 0),
1299         GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT),
1300         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1301         GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT),
1302         GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
1303         GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT),
1304         GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
1305         GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT),
1306         GEN_FW_RANGE(0x24000, 0x2407f, 0),
1307         GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT),
1308         GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
1309         GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT),
1310         GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
1311         GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT),
1312         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1313         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1314         GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1315         GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0),
1316         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1317         GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
1318 };
1319
1320 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
1321         GEN_FW_RANGE(0x0, 0x1fff, 0), /*
1322                 0x0   -  0xaff: reserved
1323                 0xb00 - 0x1fff: always on */
1324         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1325         GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT),
1326         GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER),
1327         GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT),
1328         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1329         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /*
1330                 0x4000 - 0x48ff: gt
1331                 0x4900 - 0x51ff: reserved */
1332         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /*
1333                 0x5200 - 0x53ff: render
1334                 0x5400 - 0x54ff: reserved
1335                 0x5500 - 0x7fff: render */
1336         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1337         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1338         GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
1339                 0x8160 - 0x817f: reserved
1340                 0x8180 - 0x81ff: always on */
1341         GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
1342         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1343         GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
1344                 0x8500 - 0x87ff: gt
1345                 0x8800 - 0x8fff: reserved
1346                 0x9000 - 0x947f: gt
1347                 0x9480 - 0x94cf: reserved */
1348         GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1349         GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
1350                 0x9560 - 0x95ff: always on
1351                 0x9600 - 0x97ff: reserved */
1352         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1353         GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER),
1354         GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /*
1355                 0xb400 - 0xbf7f: gt
1356                 0xb480 - 0xbfff: reserved
1357                 0xc000 - 0xcfff: gt */
1358         GEN_FW_RANGE(0xd000, 0xd7ff, 0),
1359         GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER),
1360         GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT),
1361         GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /*
1362                 0xdc00 - 0xddff: render
1363                 0xde00 - 0xde7f: reserved
1364                 0xde80 - 0xe8ff: render
1365                 0xe900 - 0xefff: reserved */
1366         GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /*
1367                  0xf000 - 0xffff: gt
1368                 0x10000 - 0x147ff: reserved */
1369         GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /*
1370                 0x14800 - 0x14fff: render
1371                 0x15000 - 0x16dff: reserved
1372                 0x16e00 - 0x1bfff: render
1373                 0x1c000 - 0x1ffff: reserved */
1374         GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0),
1375         GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2),
1376         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1377         GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
1378                 0x24000 - 0x2407f: always on
1379                 0x24080 - 0x2417f: reserved */
1380         GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
1381                 0x24180 - 0x241ff: gt
1382                 0x24200 - 0x249ff: reserved */
1383         GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
1384                 0x24a00 - 0x24a7f: render
1385                 0x24a80 - 0x251ff: reserved */
1386         GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /*
1387                 0x25200 - 0x252ff: gt
1388                 0x25300 - 0x255ff: reserved */
1389         GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0),
1390         GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /*
1391                 0x25680 - 0x256ff: VD2
1392                 0x25700 - 0x259ff: reserved */
1393         GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0),
1394         GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /*
1395                 0x25a80 - 0x25aff: VD2
1396                 0x25b00 - 0x2ffff: reserved */
1397         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
1398         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1399         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
1400                 0x1c0000 - 0x1c2bff: VD0
1401                 0x1c2c00 - 0x1c2cff: reserved
1402                 0x1c2d00 - 0x1c2dff: VD0
1403                 0x1c2e00 - 0x1c3eff: reserved
1404                 0x1c3f00 - 0x1c3fff: VD0 */
1405         GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1406         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
1407                 0x1c8000 - 0x1ca0ff: VE0
1408                 0x1ca100 - 0x1cbeff: reserved
1409                 0x1cbf00 - 0x1cbfff: VE0 */
1410         GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /*
1411                 0x1cc000 - 0x1ccfff: VD0
1412                 0x1cd000 - 0x1cffff: reserved */
1413         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
1414                 0x1d0000 - 0x1d2bff: VD2
1415                 0x1d2c00 - 0x1d2cff: reserved
1416                 0x1d2d00 - 0x1d2dff: VD2
1417                 0x1d2e00 - 0x1d3eff: reserved
1418                 0x1d3f00 - 0x1d3fff: VD2 */
1419 };
1420
1421 /*
1422  * Graphics IP version 12.55 brings a slight change to the 0xd800 range,
1423  * switching it from the GT domain to the render domain.
1424  */
1425 #define XEHP_FWRANGES(FW_RANGE_D800)                                    \
1426         GEN_FW_RANGE(0x0, 0x1fff, 0), /*                                        \
1427                   0x0 -  0xaff: reserved                                        \
1428                 0xb00 - 0x1fff: always on */                                    \
1429         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),                         \
1430         GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT),                             \
1431         GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*                                     \
1432                 0x4b00 - 0x4fff: reserved                                       \
1433                 0x5000 - 0x51ff: always on */                                   \
1434         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),                         \
1435         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),                             \
1436         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),                         \
1437         GEN_FW_RANGE(0x8160, 0x81ff, 0), /*                                     \
1438                 0x8160 - 0x817f: reserved                                       \
1439                 0x8180 - 0x81ff: always on */                                   \
1440         GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),                             \
1441         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),                         \
1442         GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /*                          \
1443                 0x8500 - 0x87ff: gt                                             \
1444                 0x8800 - 0x8c7f: reserved                                       \
1445                 0x8c80 - 0x8cff: gt (DG2 only) */                               \
1446         GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /*                      \
1447                 0x8d00 - 0x8dff: render (DG2 only)                              \
1448                 0x8e00 - 0x8fff: reserved */                                    \
1449         GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /*                          \
1450                 0x9000 - 0x947f: gt                                             \
1451                 0x9480 - 0x94cf: reserved */                                    \
1452         GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),                         \
1453         GEN_FW_RANGE(0x9560, 0x967f, 0), /*                                     \
1454                 0x9560 - 0x95ff: always on                                      \
1455                 0x9600 - 0x967f: reserved */                                    \
1456         GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*                      \
1457                 0x9680 - 0x96ff: render (DG2 only)                              \
1458                 0x9700 - 0x97ff: reserved */                                    \
1459         GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*                          \
1460                 0x9800 - 0xb4ff: gt                                             \
1461                 0xb500 - 0xbfff: reserved                                       \
1462                 0xc000 - 0xcfff: gt */                                          \
1463         GEN_FW_RANGE(0xd000, 0xd7ff, 0),                                        \
1464         GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800),                    \
1465         GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT),                             \
1466         GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),                         \
1467         GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*                          \
1468                 0xdd00 - 0xddff: gt                                             \
1469                 0xde00 - 0xde7f: reserved */                                    \
1470         GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*                      \
1471                 0xde80 - 0xdfff: render                                         \
1472                 0xe000 - 0xe0ff: reserved                                       \
1473                 0xe100 - 0xe8ff: render */                                      \
1474         GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /*                          \
1475                 0xe900 - 0xe9ff: gt                                             \
1476                 0xea00 - 0xefff: reserved                                       \
1477                 0xf000 - 0xffff: gt */                                          \
1478         GEN_FW_RANGE(0x10000, 0x12fff, 0), /*                                   \
1479                 0x10000 - 0x11fff: reserved                                     \
1480                 0x12000 - 0x127ff: always on                                    \
1481                 0x12800 - 0x12fff: reserved */                                  \
1482         GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */  \
1483         GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /*              \
1484                 0x13200 - 0x133ff: VD2 (DG2 only)                               \
1485                 0x13400 - 0x13fff: reserved */                                  \
1486         GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */      \
1487         GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */      \
1488         GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */      \
1489         GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */      \
1490         GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),                       \
1491         GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*                        \
1492                 0x15000 - 0x15fff: gt (DG2 only)                                \
1493                 0x16000 - 0x16dff: reserved */                                  \
1494         GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER),                       \
1495         GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*              \
1496                 0x20000 - 0x20fff: VD0 (XEHPSDV only)                           \
1497                 0x21000 - 0x21fff: reserved */                                  \
1498         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),                           \
1499         GEN_FW_RANGE(0x24000, 0x2417f, 0), /*                                   \
1500                 0x24000 - 0x2407f: always on                                    \
1501                 0x24080 - 0x2417f: reserved */                                  \
1502         GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*                        \
1503                 0x24180 - 0x241ff: gt                                           \
1504                 0x24200 - 0x249ff: reserved */                                  \
1505         GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*                    \
1506                 0x24a00 - 0x24a7f: render                                       \
1507                 0x24a80 - 0x251ff: reserved */                                  \
1508         GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /*                        \
1509                 0x25200 - 0x252ff: gt                                           \
1510                 0x25300 - 0x25fff: reserved */                                  \
1511         GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*                    \
1512                 0x26000 - 0x27fff: render                                       \
1513                 0x28000 - 0x29fff: reserved                                     \
1514                 0x2a000 - 0x2ffff: undocumented */                              \
1515         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),                           \
1516         GEN_FW_RANGE(0x40000, 0x1bffff, 0),                                     \
1517         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*            \
1518                 0x1c0000 - 0x1c2bff: VD0                                        \
1519                 0x1c2c00 - 0x1c2cff: reserved                                   \
1520                 0x1c2d00 - 0x1c2dff: VD0                                        \
1521                 0x1c2e00 - 0x1c3eff: VD0 (DG2 only)                             \
1522                 0x1c3f00 - 0x1c3fff: VD0 */                                     \
1523         GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /*            \
1524                 0x1c4000 - 0x1c6bff: VD1                                        \
1525                 0x1c6c00 - 0x1c6cff: reserved                                   \
1526                 0x1c6d00 - 0x1c6dff: VD1                                        \
1527                 0x1c6e00 - 0x1c7fff: reserved */                                \
1528         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*            \
1529                 0x1c8000 - 0x1ca0ff: VE0                                        \
1530                 0x1ca100 - 0x1cbfff: reserved */                                \
1531         GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0),               \
1532         GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2),               \
1533         GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4),               \
1534         GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6),               \
1535         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*            \
1536                 0x1d0000 - 0x1d2bff: VD2                                        \
1537                 0x1d2c00 - 0x1d2cff: reserved                                   \
1538                 0x1d2d00 - 0x1d2dff: VD2                                        \
1539                 0x1d2e00 - 0x1d3dff: VD2 (DG2 only)                             \
1540                 0x1d3e00 - 0x1d3eff: reserved                                   \
1541                 0x1d3f00 - 0x1d3fff: VD2 */                                     \
1542         GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /*            \
1543                 0x1d4000 - 0x1d6bff: VD3                                        \
1544                 0x1d6c00 - 0x1d6cff: reserved                                   \
1545                 0x1d6d00 - 0x1d6dff: VD3                                        \
1546                 0x1d6e00 - 0x1d7fff: reserved */                                \
1547         GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /*            \
1548                 0x1d8000 - 0x1da0ff: VE1                                        \
1549                 0x1da100 - 0x1dffff: reserved */                                \
1550         GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /*            \
1551                 0x1e0000 - 0x1e2bff: VD4                                        \
1552                 0x1e2c00 - 0x1e2cff: reserved                                   \
1553                 0x1e2d00 - 0x1e2dff: VD4                                        \
1554                 0x1e2e00 - 0x1e3eff: reserved                                   \
1555                 0x1e3f00 - 0x1e3fff: VD4 */                                     \
1556         GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /*            \
1557                 0x1e4000 - 0x1e6bff: VD5                                        \
1558                 0x1e6c00 - 0x1e6cff: reserved                                   \
1559                 0x1e6d00 - 0x1e6dff: VD5                                        \
1560                 0x1e6e00 - 0x1e7fff: reserved */                                \
1561         GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /*            \
1562                 0x1e8000 - 0x1ea0ff: VE2                                        \
1563                 0x1ea100 - 0x1effff: reserved */                                \
1564         GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /*            \
1565                 0x1f0000 - 0x1f2bff: VD6                                        \
1566                 0x1f2c00 - 0x1f2cff: reserved                                   \
1567                 0x1f2d00 - 0x1f2dff: VD6                                        \
1568                 0x1f2e00 - 0x1f3eff: reserved                                   \
1569                 0x1f3f00 - 0x1f3fff: VD6 */                                     \
1570         GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /*            \
1571                 0x1f4000 - 0x1f6bff: VD7                                        \
1572                 0x1f6c00 - 0x1f6cff: reserved                                   \
1573                 0x1f6d00 - 0x1f6dff: VD7                                        \
1574                 0x1f6e00 - 0x1f7fff: reserved */                                \
1575         GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
1576
1577 static const struct intel_forcewake_range __xehp_fw_ranges[] = {
1578         XEHP_FWRANGES(FORCEWAKE_GT)
1579 };
1580
1581 static const struct intel_forcewake_range __dg2_fw_ranges[] = {
1582         XEHP_FWRANGES(FORCEWAKE_RENDER)
1583 };
1584
1585 static const struct intel_forcewake_range __pvc_fw_ranges[] = {
1586         GEN_FW_RANGE(0x0, 0xaff, 0),
1587         GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
1588         GEN_FW_RANGE(0xc00, 0xfff, 0),
1589         GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
1590         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1591         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1592         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1593         GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
1594                 0x4000 - 0x4aff: gt
1595                 0x4b00 - 0x4fff: reserved
1596                 0x5000 - 0x51ff: gt
1597                 0x5200 - 0x52ff: reserved
1598                 0x5300 - 0x53ff: gt
1599                 0x5400 - 0x7fff: reserved
1600                 0x8000 - 0x813f: gt */
1601         GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER),
1602         GEN_FW_RANGE(0x8180, 0x81ff, 0),
1603         GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
1604                 0x8200 - 0x82ff: gt
1605                 0x8300 - 0x84ff: reserved
1606                 0x8500 - 0x887f: gt
1607                 0x8880 - 0x8a7f: reserved
1608                 0x8a80 - 0x8aff: gt
1609                 0x8b00 - 0x8fff: reserved
1610                 0x9000 - 0x947f: gt
1611                 0x9480 - 0x94cf: reserved */
1612         GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1613         GEN_FW_RANGE(0x9560, 0x967f, 0), /*
1614                 0x9560 - 0x95ff: always on
1615                 0x9600 - 0x967f: reserved */
1616         GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
1617                 0x9680 - 0x96ff: render
1618                 0x9700 - 0x97ff: reserved */
1619         GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
1620                 0x9800 - 0xb4ff: gt
1621                 0xb500 - 0xbfff: reserved
1622                 0xc000 - 0xcfff: gt */
1623         GEN_FW_RANGE(0xd000, 0xd3ff, 0),
1624         GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT),
1625         GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
1626         GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
1627                 0xdd00 - 0xddff: gt
1628                 0xde00 - 0xde7f: reserved */
1629         GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
1630                 0xde80 - 0xdeff: render
1631                 0xdf00 - 0xe1ff: reserved
1632                 0xe200 - 0xe7ff: render
1633                 0xe800 - 0xe8ff: reserved */
1634         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
1635                  0xe900 -  0xe9ff: gt
1636                  0xea00 -  0xebff: reserved
1637                  0xec00 -  0xffff: gt
1638                 0x10000 - 0x11fff: reserved */
1639         GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
1640                 0x12000 - 0x127ff: always on
1641                 0x12800 - 0x12fff: reserved */
1642         GEN_FW_RANGE(0x13000, 0x23fff, FORCEWAKE_GT), /*
1643                 0x13000 - 0x135ff: gt
1644                 0x13600 - 0x147ff: reserved
1645                 0x14800 - 0x153ff: gt
1646                 0x15400 - 0x19fff: reserved
1647                 0x1a000 - 0x1ffff: gt
1648                 0x20000 - 0x21fff: reserved
1649                 0x22000 - 0x23fff: gt */
1650         GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
1651                 24000 - 0x2407f: always on
1652                 24080 - 0x2417f: reserved */
1653         GEN_FW_RANGE(0x24180, 0x3ffff, FORCEWAKE_GT), /*
1654                 0x24180 - 0x241ff: gt
1655                 0x24200 - 0x251ff: reserved
1656                 0x25200 - 0x252ff: gt
1657                 0x25300 - 0x25fff: reserved
1658                 0x26000 - 0x27fff: gt
1659                 0x28000 - 0x2ffff: reserved
1660                 0x30000 - 0x3ffff: gt */
1661         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1662         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
1663                 0x1c0000 - 0x1c2bff: VD0
1664                 0x1c2c00 - 0x1c2cff: reserved
1665                 0x1c2d00 - 0x1c2dff: VD0
1666                 0x1c2e00 - 0x1c3eff: reserved
1667                 0x1c3f00 - 0x1c3fff: VD0 */
1668         GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
1669                 0x1c4000 - 0x1c6aff: VD1
1670                 0x1c6b00 - 0x1c7eff: reserved
1671                 0x1c7f00 - 0x1c7fff: VD1
1672                 0x1c8000 - 0x1cffff: reserved */
1673         GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
1674                 0x1d0000 - 0x1d2aff: VD2
1675                 0x1d2b00 - 0x1d3eff: reserved
1676                 0x1d3f00 - 0x1d3fff: VD2
1677                 0x1d4000 - 0x23ffff: reserved */
1678         GEN_FW_RANGE(0x240000, 0x3dffff, 0),
1679         GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT),
1680 };
1681
1682 static void
1683 ilk_dummy_write(struct intel_uncore *uncore)
1684 {
1685         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1686          * the chip from rc6 before touching it for real. MI_MODE is masked,
1687          * hence harmless to write 0 into. */
1688         __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);
1689 }
1690
1691 static void
1692 __unclaimed_reg_debug(struct intel_uncore *uncore,
1693                       const i915_reg_t reg,
1694                       const bool read)
1695 {
1696         if (drm_WARN(&uncore->i915->drm,
1697                      check_for_unclaimed_mmio(uncore),
1698                      "Unclaimed %s register 0x%x\n",
1699                      read ? "read from" : "write to",
1700                      i915_mmio_reg_offset(reg)))
1701                 /* Only report the first N failures */
1702                 uncore->i915->params.mmio_debug--;
1703 }
1704
1705 static void
1706 __unclaimed_previous_reg_debug(struct intel_uncore *uncore,
1707                                const i915_reg_t reg,
1708                                const bool read)
1709 {
1710         if (check_for_unclaimed_mmio(uncore))
1711                 drm_dbg(&uncore->i915->drm,
1712                         "Unclaimed access detected before %s register 0x%x\n",
1713                         read ? "read from" : "write to",
1714                         i915_mmio_reg_offset(reg));
1715 }
1716
1717 static inline void
1718 unclaimed_reg_debug(struct intel_uncore *uncore,
1719                     const i915_reg_t reg,
1720                     const bool read,
1721                     const bool before)
1722 {
1723         if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug)
1724                 return;
1725
1726         /* interrupts are disabled and re-enabled around uncore->lock usage */
1727         lockdep_assert_held(&uncore->lock);
1728
1729         if (before) {
1730                 spin_lock(&uncore->debug->lock);
1731                 __unclaimed_previous_reg_debug(uncore, reg, read);
1732         } else {
1733                 __unclaimed_reg_debug(uncore, reg, read);
1734                 spin_unlock(&uncore->debug->lock);
1735         }
1736 }
1737
1738 #define __vgpu_read(x) \
1739 static u##x \
1740 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1741         u##x val = __raw_uncore_read##x(uncore, reg); \
1742         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1743         return val; \
1744 }
1745 __vgpu_read(8)
1746 __vgpu_read(16)
1747 __vgpu_read(32)
1748 __vgpu_read(64)
1749
1750 #define GEN2_READ_HEADER(x) \
1751         u##x val = 0; \
1752         assert_rpm_wakelock_held(uncore->rpm);
1753
1754 #define GEN2_READ_FOOTER \
1755         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1756         return val
1757
1758 #define __gen2_read(x) \
1759 static u##x \
1760 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1761         GEN2_READ_HEADER(x); \
1762         val = __raw_uncore_read##x(uncore, reg); \
1763         GEN2_READ_FOOTER; \
1764 }
1765
1766 #define __gen5_read(x) \
1767 static u##x \
1768 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1769         GEN2_READ_HEADER(x); \
1770         ilk_dummy_write(uncore); \
1771         val = __raw_uncore_read##x(uncore, reg); \
1772         GEN2_READ_FOOTER; \
1773 }
1774
1775 __gen5_read(8)
1776 __gen5_read(16)
1777 __gen5_read(32)
1778 __gen5_read(64)
1779 __gen2_read(8)
1780 __gen2_read(16)
1781 __gen2_read(32)
1782 __gen2_read(64)
1783
1784 #undef __gen5_read
1785 #undef __gen2_read
1786
1787 #undef GEN2_READ_FOOTER
1788 #undef GEN2_READ_HEADER
1789
1790 #define GEN6_READ_HEADER(x) \
1791         u32 offset = i915_mmio_reg_offset(reg); \
1792         unsigned long irqflags; \
1793         u##x val = 0; \
1794         assert_rpm_wakelock_held(uncore->rpm); \
1795         spin_lock_irqsave(&uncore->lock, irqflags); \
1796         unclaimed_reg_debug(uncore, reg, true, true)
1797
1798 #define GEN6_READ_FOOTER \
1799         unclaimed_reg_debug(uncore, reg, true, false); \
1800         spin_unlock_irqrestore(&uncore->lock, irqflags); \
1801         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1802         return val
1803
1804 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1805                                         enum forcewake_domains fw_domains)
1806 {
1807         struct intel_uncore_forcewake_domain *domain;
1808         unsigned int tmp;
1809
1810         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1811
1812         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1813                 fw_domain_arm_timer(domain);
1814
1815         fw_domains_get(uncore, fw_domains);
1816 }
1817
1818 static inline void __force_wake_auto(struct intel_uncore *uncore,
1819                                      enum forcewake_domains fw_domains)
1820 {
1821         GEM_BUG_ON(!fw_domains);
1822
1823         /* Turn on all requested but inactive supported forcewake domains. */
1824         fw_domains &= uncore->fw_domains;
1825         fw_domains &= ~uncore->fw_domains_active;
1826
1827         if (fw_domains)
1828                 ___force_wake_auto(uncore, fw_domains);
1829 }
1830
1831 #define __gen_fwtable_read(x) \
1832 static u##x \
1833 fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
1834 { \
1835         enum forcewake_domains fw_engine; \
1836         GEN6_READ_HEADER(x); \
1837         fw_engine = __fwtable_reg_read_fw_domains(uncore, offset); \
1838         if (fw_engine) \
1839                 __force_wake_auto(uncore, fw_engine); \
1840         val = __raw_uncore_read##x(uncore, reg); \
1841         GEN6_READ_FOOTER; \
1842 }
1843
1844 static enum forcewake_domains
1845 fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) {
1846         return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));
1847 }
1848
1849 __gen_fwtable_read(8)
1850 __gen_fwtable_read(16)
1851 __gen_fwtable_read(32)
1852 __gen_fwtable_read(64)
1853
1854 #undef __gen_fwtable_read
1855 #undef GEN6_READ_FOOTER
1856 #undef GEN6_READ_HEADER
1857
1858 #define GEN2_WRITE_HEADER \
1859         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1860         assert_rpm_wakelock_held(uncore->rpm); \
1861
1862 #define GEN2_WRITE_FOOTER
1863
1864 #define __gen2_write(x) \
1865 static void \
1866 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1867         GEN2_WRITE_HEADER; \
1868         __raw_uncore_write##x(uncore, reg, val); \
1869         GEN2_WRITE_FOOTER; \
1870 }
1871
1872 #define __gen5_write(x) \
1873 static void \
1874 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1875         GEN2_WRITE_HEADER; \
1876         ilk_dummy_write(uncore); \
1877         __raw_uncore_write##x(uncore, reg, val); \
1878         GEN2_WRITE_FOOTER; \
1879 }
1880
1881 __gen5_write(8)
1882 __gen5_write(16)
1883 __gen5_write(32)
1884 __gen2_write(8)
1885 __gen2_write(16)
1886 __gen2_write(32)
1887
1888 #undef __gen5_write
1889 #undef __gen2_write
1890
1891 #undef GEN2_WRITE_FOOTER
1892 #undef GEN2_WRITE_HEADER
1893
1894 #define GEN6_WRITE_HEADER \
1895         u32 offset = i915_mmio_reg_offset(reg); \
1896         unsigned long irqflags; \
1897         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1898         assert_rpm_wakelock_held(uncore->rpm); \
1899         spin_lock_irqsave(&uncore->lock, irqflags); \
1900         unclaimed_reg_debug(uncore, reg, false, true)
1901
1902 #define GEN6_WRITE_FOOTER \
1903         unclaimed_reg_debug(uncore, reg, false, false); \
1904         spin_unlock_irqrestore(&uncore->lock, irqflags)
1905
1906 #define __gen6_write(x) \
1907 static void \
1908 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1909         GEN6_WRITE_HEADER; \
1910         if (NEEDS_FORCE_WAKE(offset)) \
1911                 __gen6_gt_wait_for_fifo(uncore); \
1912         __raw_uncore_write##x(uncore, reg, val); \
1913         GEN6_WRITE_FOOTER; \
1914 }
1915 __gen6_write(8)
1916 __gen6_write(16)
1917 __gen6_write(32)
1918
1919 #define __gen_fwtable_write(x) \
1920 static void \
1921 fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1922         enum forcewake_domains fw_engine; \
1923         GEN6_WRITE_HEADER; \
1924         fw_engine = __fwtable_reg_write_fw_domains(uncore, offset); \
1925         if (fw_engine) \
1926                 __force_wake_auto(uncore, fw_engine); \
1927         __raw_uncore_write##x(uncore, reg, val); \
1928         GEN6_WRITE_FOOTER; \
1929 }
1930
1931 static enum forcewake_domains
1932 fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
1933 {
1934         return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg));
1935 }
1936
1937 __gen_fwtable_write(8)
1938 __gen_fwtable_write(16)
1939 __gen_fwtable_write(32)
1940
1941 #undef __gen_fwtable_write
1942 #undef GEN6_WRITE_FOOTER
1943 #undef GEN6_WRITE_HEADER
1944
1945 #define __vgpu_write(x) \
1946 static void \
1947 vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1948         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1949         __raw_uncore_write##x(uncore, reg, val); \
1950 }
1951 __vgpu_write(8)
1952 __vgpu_write(16)
1953 __vgpu_write(32)
1954
1955 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
1956 do { \
1957         (uncore)->funcs.mmio_writeb = x##_write8; \
1958         (uncore)->funcs.mmio_writew = x##_write16; \
1959         (uncore)->funcs.mmio_writel = x##_write32; \
1960 } while (0)
1961
1962 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
1963 do { \
1964         (uncore)->funcs.mmio_readb = x##_read8; \
1965         (uncore)->funcs.mmio_readw = x##_read16; \
1966         (uncore)->funcs.mmio_readl = x##_read32; \
1967         (uncore)->funcs.mmio_readq = x##_read64; \
1968 } while (0)
1969
1970 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1971 do { \
1972         ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
1973         (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
1974 } while (0)
1975
1976 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1977 do { \
1978         ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
1979         (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
1980 } while (0)
1981
1982 static int __fw_domain_init(struct intel_uncore *uncore,
1983                             enum forcewake_domain_id domain_id,
1984                             i915_reg_t reg_set,
1985                             i915_reg_t reg_ack)
1986 {
1987         struct intel_uncore_forcewake_domain *d;
1988
1989         GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1990         GEM_BUG_ON(uncore->fw_domain[domain_id]);
1991
1992         if (i915_inject_probe_failure(uncore->i915))
1993                 return -ENOMEM;
1994
1995         d = kzalloc(sizeof(*d), GFP_KERNEL);
1996         if (!d)
1997                 return -ENOMEM;
1998
1999         drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set));
2000         drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack));
2001
2002         d->uncore = uncore;
2003         d->wake_count = 0;
2004         d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset;
2005         d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) + uncore->gsi_offset;
2006
2007         d->id = domain_id;
2008
2009         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
2010         BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT));
2011         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
2012         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
2013         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
2014         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
2015         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
2016         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4));
2017         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5));
2018         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6));
2019         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7));
2020         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
2021         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
2022         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2));
2023         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3));
2024
2025         d->mask = BIT(domain_id);
2026
2027         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2028         d->timer.function = intel_uncore_fw_release_timer;
2029
2030         uncore->fw_domains |= BIT(domain_id);
2031
2032         fw_domain_reset(d);
2033
2034         uncore->fw_domain[domain_id] = d;
2035
2036         return 0;
2037 }
2038
2039 static void fw_domain_fini(struct intel_uncore *uncore,
2040                            enum forcewake_domain_id domain_id)
2041 {
2042         struct intel_uncore_forcewake_domain *d;
2043
2044         GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
2045
2046         d = fetch_and_zero(&uncore->fw_domain[domain_id]);
2047         if (!d)
2048                 return;
2049
2050         uncore->fw_domains &= ~BIT(domain_id);
2051         drm_WARN_ON(&uncore->i915->drm, d->wake_count);
2052         drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer));
2053         kfree(d);
2054 }
2055
2056 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
2057 {
2058         struct intel_uncore_forcewake_domain *d;
2059         int tmp;
2060
2061         for_each_fw_domain(d, uncore, tmp)
2062                 fw_domain_fini(uncore, d->id);
2063 }
2064
2065 static const struct intel_uncore_fw_get uncore_get_fallback = {
2066         .force_wake_get = fw_domains_get_with_fallback
2067 };
2068
2069 static const struct intel_uncore_fw_get uncore_get_normal = {
2070         .force_wake_get = fw_domains_get_normal,
2071 };
2072
2073 static const struct intel_uncore_fw_get uncore_get_thread_status = {
2074         .force_wake_get = fw_domains_get_with_thread_status
2075 };
2076
2077 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
2078 {
2079         struct drm_i915_private *i915 = uncore->i915;
2080         int ret = 0;
2081
2082         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
2083
2084 #define fw_domain_init(uncore__, id__, set__, ack__) \
2085         (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
2086
2087         if (GRAPHICS_VER(i915) >= 11) {
2088                 /* we'll prune the domains of missing engines later */
2089                 intel_engine_mask_t emask = RUNTIME_INFO(i915)->platform_engine_mask;
2090                 int i;
2091
2092                 uncore->fw_get_funcs = &uncore_get_fallback;
2093                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2094                                FORCEWAKE_RENDER_GEN9,
2095                                FORCEWAKE_ACK_RENDER_GEN9);
2096                 fw_domain_init(uncore, FW_DOMAIN_ID_GT,
2097                                FORCEWAKE_GT_GEN9,
2098                                FORCEWAKE_ACK_GT_GEN9);
2099
2100                 for (i = 0; i < I915_MAX_VCS; i++) {
2101                         if (!__HAS_ENGINE(emask, _VCS(i)))
2102                                 continue;
2103
2104                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
2105                                        FORCEWAKE_MEDIA_VDBOX_GEN11(i),
2106                                        FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
2107                 }
2108                 for (i = 0; i < I915_MAX_VECS; i++) {
2109                         if (!__HAS_ENGINE(emask, _VECS(i)))
2110                                 continue;
2111
2112                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
2113                                        FORCEWAKE_MEDIA_VEBOX_GEN11(i),
2114                                        FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
2115                 }
2116         } else if (IS_GRAPHICS_VER(i915, 9, 10)) {
2117                 uncore->fw_get_funcs = &uncore_get_fallback;
2118                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2119                                FORCEWAKE_RENDER_GEN9,
2120                                FORCEWAKE_ACK_RENDER_GEN9);
2121                 fw_domain_init(uncore, FW_DOMAIN_ID_GT,
2122                                FORCEWAKE_GT_GEN9,
2123                                FORCEWAKE_ACK_GT_GEN9);
2124                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
2125                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
2126         } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
2127                 uncore->fw_get_funcs = &uncore_get_normal;
2128                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2129                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
2130                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
2131                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
2132         } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
2133                 uncore->fw_get_funcs = &uncore_get_thread_status;
2134                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2135                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
2136         } else if (IS_IVYBRIDGE(i915)) {
2137                 u32 ecobus;
2138
2139                 /* IVB configs may use multi-threaded forcewake */
2140
2141                 /* A small trick here - if the bios hasn't configured
2142                  * MT forcewake, and if the device is in RC6, then
2143                  * force_wake_mt_get will not wake the device and the
2144                  * ECOBUS read will return zero. Which will be
2145                  * (correctly) interpreted by the test below as MT
2146                  * forcewake being disabled.
2147                  */
2148                 uncore->fw_get_funcs = &uncore_get_thread_status;
2149
2150                 /* We need to init first for ECOBUS access and then
2151                  * determine later if we want to reinit, in case of MT access is
2152                  * not working. In this stage we don't know which flavour this
2153                  * ivb is, so it is better to reset also the gen6 fw registers
2154                  * before the ecobus check.
2155                  */
2156
2157                 __raw_uncore_write32(uncore, FORCEWAKE, 0);
2158                 __raw_posting_read(uncore, ECOBUS);
2159
2160                 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2161                                        FORCEWAKE_MT, FORCEWAKE_MT_ACK);
2162                 if (ret)
2163                         goto out;
2164
2165                 spin_lock_irq(&uncore->lock);
2166                 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
2167                 ecobus = __raw_uncore_read32(uncore, ECOBUS);
2168                 fw_domains_put(uncore, FORCEWAKE_RENDER);
2169                 spin_unlock_irq(&uncore->lock);
2170
2171                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
2172                         drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n");
2173                         drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n");
2174                         fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER);
2175                         fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2176                                        FORCEWAKE, FORCEWAKE_ACK);
2177                 }
2178         } else if (GRAPHICS_VER(i915) == 6) {
2179                 uncore->fw_get_funcs = &uncore_get_thread_status;
2180                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
2181                                FORCEWAKE, FORCEWAKE_ACK);
2182         }
2183
2184 #undef fw_domain_init
2185
2186         /* All future platforms are expected to require complex power gating */
2187         drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0);
2188
2189 out:
2190         if (ret)
2191                 intel_uncore_fw_domains_fini(uncore);
2192
2193         return ret;
2194 }
2195
2196 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
2197 { \
2198         (uncore)->fw_domains_table = \
2199                         (struct intel_forcewake_range *)(d); \
2200         (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
2201 }
2202
2203 #define ASSIGN_SHADOW_TABLE(uncore, d) \
2204 { \
2205         (uncore)->shadowed_reg_table = d; \
2206         (uncore)->shadowed_reg_table_entries = ARRAY_SIZE((d)); \
2207 }
2208
2209 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
2210                                          unsigned long action, void *data)
2211 {
2212         struct intel_uncore *uncore = container_of(nb,
2213                         struct intel_uncore, pmic_bus_access_nb);
2214
2215         switch (action) {
2216         case MBI_PMIC_BUS_ACCESS_BEGIN:
2217                 /*
2218                  * forcewake all now to make sure that we don't need to do a
2219                  * forcewake later which on systems where this notifier gets
2220                  * called requires the punit to access to the shared pmic i2c
2221                  * bus, which will be busy after this notification, leading to:
2222                  * "render: timed out waiting for forcewake ack request."
2223                  * errors.
2224                  *
2225                  * The notifier is unregistered during intel_runtime_suspend(),
2226                  * so it's ok to access the HW here without holding a RPM
2227                  * wake reference -> disable wakeref asserts for the time of
2228                  * the access.
2229                  */
2230                 disable_rpm_wakeref_asserts(uncore->rpm);
2231                 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
2232                 enable_rpm_wakeref_asserts(uncore->rpm);
2233                 break;
2234         case MBI_PMIC_BUS_ACCESS_END:
2235                 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
2236                 break;
2237         }
2238
2239         return NOTIFY_OK;
2240 }
2241
2242 static void uncore_unmap_mmio(struct drm_device *drm, void *regs)
2243 {
2244         iounmap(regs);
2245 }
2246
2247 int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
2248 {
2249         struct drm_i915_private *i915 = uncore->i915;
2250         int mmio_size;
2251
2252         /*
2253          * Before gen4, the registers and the GTT are behind different BARs.
2254          * However, from gen4 onwards, the registers and the GTT are shared
2255          * in the same BAR, so we want to restrict this ioremap from
2256          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
2257          * the register BAR remains the same size for all the earlier
2258          * generations up to Ironlake.
2259          * For dgfx chips register range is expanded to 4MB, and this larger
2260          * range is also used for integrated gpus beginning with Meteor Lake.
2261          */
2262         if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
2263                 mmio_size = 4 * 1024 * 1024;
2264         else if (GRAPHICS_VER(i915) >= 5)
2265                 mmio_size = 2 * 1024 * 1024;
2266         else
2267                 mmio_size = 512 * 1024;
2268
2269         uncore->regs = ioremap(phys_addr, mmio_size);
2270         if (uncore->regs == NULL) {
2271                 drm_err(&i915->drm, "failed to map registers\n");
2272                 return -EIO;
2273         }
2274
2275         return drmm_add_action_or_reset(&i915->drm, uncore_unmap_mmio, uncore->regs);
2276 }
2277
2278 void intel_uncore_init_early(struct intel_uncore *uncore,
2279                              struct intel_gt *gt)
2280 {
2281         spin_lock_init(&uncore->lock);
2282         uncore->i915 = gt->i915;
2283         uncore->gt = gt;
2284         uncore->rpm = &gt->i915->runtime_pm;
2285 }
2286
2287 static void uncore_raw_init(struct intel_uncore *uncore)
2288 {
2289         GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
2290
2291         if (intel_vgpu_active(uncore->i915)) {
2292                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
2293                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
2294         } else if (GRAPHICS_VER(uncore->i915) == 5) {
2295                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
2296                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
2297         } else {
2298                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
2299                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
2300         }
2301 }
2302
2303 static int uncore_forcewake_init(struct intel_uncore *uncore)
2304 {
2305         struct drm_i915_private *i915 = uncore->i915;
2306         int ret;
2307
2308         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
2309
2310         ret = intel_uncore_fw_domains_init(uncore);
2311         if (ret)
2312                 return ret;
2313         forcewake_early_sanitize(uncore, 0);
2314
2315         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
2316
2317         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) {
2318                 ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges);
2319                 ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs);
2320                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2321         } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
2322                 ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
2323                 ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
2324                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2325         } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
2326                 ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
2327                 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
2328                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2329         } else if (GRAPHICS_VER(i915) >= 12) {
2330                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
2331                 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
2332                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2333         } else if (GRAPHICS_VER(i915) == 11) {
2334                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
2335                 ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs);
2336                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2337         } else if (IS_GRAPHICS_VER(i915, 9, 10)) {
2338                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
2339                 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
2340                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2341         } else if (IS_CHERRYVIEW(i915)) {
2342                 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
2343                 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
2344                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2345         } else if (GRAPHICS_VER(i915) == 8) {
2346                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
2347                 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
2348                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
2349         } else if (IS_VALLEYVIEW(i915)) {
2350                 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
2351                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
2352         } else if (IS_GRAPHICS_VER(i915, 6, 7)) {
2353                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
2354                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
2355         }
2356
2357         uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
2358         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
2359
2360         return 0;
2361 }
2362
2363 int intel_uncore_init_mmio(struct intel_uncore *uncore)
2364 {
2365         struct drm_i915_private *i915 = uncore->i915;
2366         int ret;
2367
2368         /*
2369          * The boot firmware initializes local memory and assesses its health.
2370          * If memory training fails, the punit will have been instructed to
2371          * keep the GT powered down; we won't be able to communicate with it
2372          * and we should not continue with driver initialization.
2373          */
2374         if (IS_DGFX(i915) &&
2375             !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) {
2376                 drm_err(&i915->drm, "LMEM not initialized by firmware\n");
2377                 return -ENODEV;
2378         }
2379
2380         if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915))
2381                 uncore->flags |= UNCORE_HAS_FORCEWAKE;
2382
2383         if (!intel_uncore_has_forcewake(uncore)) {
2384                 uncore_raw_init(uncore);
2385         } else {
2386                 ret = uncore_forcewake_init(uncore);
2387                 if (ret)
2388                         return ret;
2389         }
2390
2391         /* make sure fw funcs are set if and only if we have fw*/
2392         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->fw_get_funcs);
2393         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
2394         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
2395
2396         if (HAS_FPGA_DBG_UNCLAIMED(i915))
2397                 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
2398
2399         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
2400                 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
2401
2402         if (IS_GRAPHICS_VER(i915, 6, 7))
2403                 uncore->flags |= UNCORE_HAS_FIFO;
2404
2405         /* clear out unclaimed reg detection bit */
2406         if (intel_uncore_unclaimed_mmio(uncore))
2407                 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
2408
2409         return 0;
2410 }
2411
2412 /*
2413  * We might have detected that some engines are fused off after we initialized
2414  * the forcewake domains. Prune them, to make sure they only reference existing
2415  * engines.
2416  */
2417 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
2418                                           struct intel_gt *gt)
2419 {
2420         enum forcewake_domains fw_domains = uncore->fw_domains;
2421         enum forcewake_domain_id domain_id;
2422         int i;
2423
2424         if (!intel_uncore_has_forcewake(uncore) || GRAPHICS_VER(uncore->i915) < 11)
2425                 return;
2426
2427         for (i = 0; i < I915_MAX_VCS; i++) {
2428                 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
2429
2430                 if (HAS_ENGINE(gt, _VCS(i)))
2431                         continue;
2432
2433                 /*
2434                  * Starting with XeHP, the power well for an even-numbered
2435                  * VDBOX is also used for shared units within the
2436                  * media slice such as SFC.  So even if the engine
2437                  * itself is fused off, we still need to initialize
2438                  * the forcewake domain if any of the other engines
2439                  * in the same media slice are present.
2440                  */
2441                 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) {
2442                         if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1)))
2443                                 continue;
2444
2445                         if (HAS_ENGINE(gt, _VECS(i / 2)))
2446                                 continue;
2447                 }
2448
2449                 if (fw_domains & BIT(domain_id))
2450                         fw_domain_fini(uncore, domain_id);
2451         }
2452
2453         for (i = 0; i < I915_MAX_VECS; i++) {
2454                 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
2455
2456                 if (HAS_ENGINE(gt, _VECS(i)))
2457                         continue;
2458
2459                 if (fw_domains & BIT(domain_id))
2460                         fw_domain_fini(uncore, domain_id);
2461         }
2462 }
2463
2464 /* Called via drm-managed action */
2465 void intel_uncore_fini_mmio(struct drm_device *dev, void *data)
2466 {
2467         struct intel_uncore *uncore = data;
2468
2469         if (intel_uncore_has_forcewake(uncore)) {
2470                 iosf_mbi_punit_acquire();
2471                 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
2472                         &uncore->pmic_bus_access_nb);
2473                 intel_uncore_forcewake_reset(uncore);
2474                 intel_uncore_fw_domains_fini(uncore);
2475                 iosf_mbi_punit_release();
2476         }
2477 }
2478
2479 /**
2480  * __intel_wait_for_register_fw - wait until register matches expected state
2481  * @uncore: the struct intel_uncore
2482  * @reg: the register to read
2483  * @mask: mask to apply to register value
2484  * @value: expected value
2485  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2486  * @slow_timeout_ms: slow timeout in millisecond
2487  * @out_value: optional placeholder to hold registry value
2488  *
2489  * This routine waits until the target register @reg contains the expected
2490  * @value after applying the @mask, i.e. it waits until ::
2491  *
2492  *     (intel_uncore_read_fw(uncore, reg) & mask) == value
2493  *
2494  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
2495  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
2496  * must be not larger than 20,0000 microseconds.
2497  *
2498  * Note that this routine assumes the caller holds forcewake asserted, it is
2499  * not suitable for very long waits. See intel_wait_for_register() if you
2500  * wish to wait without holding forcewake for the duration (i.e. you expect
2501  * the wait to be slow).
2502  *
2503  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2504  */
2505 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
2506                                  i915_reg_t reg,
2507                                  u32 mask,
2508                                  u32 value,
2509                                  unsigned int fast_timeout_us,
2510                                  unsigned int slow_timeout_ms,
2511                                  u32 *out_value)
2512 {
2513         u32 reg_value = 0;
2514 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
2515         int ret;
2516
2517         /* Catch any overuse of this function */
2518         might_sleep_if(slow_timeout_ms);
2519         GEM_BUG_ON(fast_timeout_us > 20000);
2520         GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
2521
2522         ret = -ETIMEDOUT;
2523         if (fast_timeout_us && fast_timeout_us <= 20000)
2524                 ret = _wait_for_atomic(done, fast_timeout_us, 0);
2525         if (ret && slow_timeout_ms)
2526                 ret = wait_for(done, slow_timeout_ms);
2527
2528         if (out_value)
2529                 *out_value = reg_value;
2530
2531         return ret;
2532 #undef done
2533 }
2534
2535 /**
2536  * __intel_wait_for_register - wait until register matches expected state
2537  * @uncore: the struct intel_uncore
2538  * @reg: the register to read
2539  * @mask: mask to apply to register value
2540  * @value: expected value
2541  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2542  * @slow_timeout_ms: slow timeout in millisecond
2543  * @out_value: optional placeholder to hold registry value
2544  *
2545  * This routine waits until the target register @reg contains the expected
2546  * @value after applying the @mask, i.e. it waits until ::
2547  *
2548  *     (intel_uncore_read(uncore, reg) & mask) == value
2549  *
2550  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
2551  *
2552  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2553  */
2554 int __intel_wait_for_register(struct intel_uncore *uncore,
2555                               i915_reg_t reg,
2556                               u32 mask,
2557                               u32 value,
2558                               unsigned int fast_timeout_us,
2559                               unsigned int slow_timeout_ms,
2560                               u32 *out_value)
2561 {
2562         unsigned fw =
2563                 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
2564         u32 reg_value;
2565         int ret;
2566
2567         might_sleep_if(slow_timeout_ms);
2568
2569         spin_lock_irq(&uncore->lock);
2570         intel_uncore_forcewake_get__locked(uncore, fw);
2571
2572         ret = __intel_wait_for_register_fw(uncore,
2573                                            reg, mask, value,
2574                                            fast_timeout_us, 0, &reg_value);
2575
2576         intel_uncore_forcewake_put__locked(uncore, fw);
2577         spin_unlock_irq(&uncore->lock);
2578
2579         if (ret && slow_timeout_ms)
2580                 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
2581                                                                        reg),
2582                                  (reg_value & mask) == value,
2583                                  slow_timeout_ms * 1000, 10, 1000);
2584
2585         /* just trace the final value */
2586         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2587
2588         if (out_value)
2589                 *out_value = reg_value;
2590
2591         return ret;
2592 }
2593
2594 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
2595 {
2596         bool ret;
2597
2598         if (!uncore->debug)
2599                 return false;
2600
2601         spin_lock_irq(&uncore->debug->lock);
2602         ret = check_for_unclaimed_mmio(uncore);
2603         spin_unlock_irq(&uncore->debug->lock);
2604
2605         return ret;
2606 }
2607
2608 bool
2609 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
2610 {
2611         bool ret = false;
2612
2613         if (drm_WARN_ON(&uncore->i915->drm, !uncore->debug))
2614                 return false;
2615
2616         spin_lock_irq(&uncore->debug->lock);
2617
2618         if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
2619                 goto out;
2620
2621         if (unlikely(check_for_unclaimed_mmio(uncore))) {
2622                 if (!uncore->i915->params.mmio_debug) {
2623                         drm_dbg(&uncore->i915->drm,
2624                                 "Unclaimed register detected, "
2625                                 "enabling oneshot unclaimed register reporting. "
2626                                 "Please use i915.mmio_debug=N for more information.\n");
2627                         uncore->i915->params.mmio_debug++;
2628                 }
2629                 uncore->debug->unclaimed_mmio_check--;
2630                 ret = true;
2631         }
2632
2633 out:
2634         spin_unlock_irq(&uncore->debug->lock);
2635
2636         return ret;
2637 }
2638
2639 /**
2640  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
2641  *                                  a register
2642  * @uncore: pointer to struct intel_uncore
2643  * @reg: register in question
2644  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
2645  *
2646  * Returns a set of forcewake domains required to be taken with for example
2647  * intel_uncore_forcewake_get for the specified register to be accessible in the
2648  * specified mode (read, write or read/write) with raw mmio accessors.
2649  *
2650  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
2651  * callers to do FIFO management on their own or risk losing writes.
2652  */
2653 enum forcewake_domains
2654 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
2655                                i915_reg_t reg, unsigned int op)
2656 {
2657         enum forcewake_domains fw_domains = 0;
2658
2659         drm_WARN_ON(&uncore->i915->drm, !op);
2660
2661         if (!intel_uncore_has_forcewake(uncore))
2662                 return 0;
2663
2664         if (op & FW_REG_READ)
2665                 fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
2666
2667         if (op & FW_REG_WRITE)
2668                 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
2669
2670         drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains);
2671
2672         return fw_domains;
2673 }
2674
2675 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2676 #include "selftests/mock_uncore.c"
2677 #include "selftests/intel_uncore.c"
2678 #endif