drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/pm_runtime.h>
  25 #include <asm/iosf_mbi.h>
  26
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "i915_vgpu.h"
  30 #include "intel_pm.h"
  31
  32 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  33 #define GT_FIFO_TIMEOUT_MS       10
  34
  35 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
  36
  37 void
  38 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
  39 {
  40         spin_lock_init(&mmio_debug->lock);
  41         mmio_debug->unclaimed_mmio_check = 1;
  42 }
  43
  44 static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug)
  45 {
  46         lockdep_assert_held(&mmio_debug->lock);
  47
  48         /* Save and disable mmio debugging for the user bypass */
  49         if (!mmio_debug->suspend_count++) {
  50                 mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check;
  51                 mmio_debug->unclaimed_mmio_check = 0;
  52         }
  53 }
  54
  55 static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
  56 {
  57         lockdep_assert_held(&mmio_debug->lock);
  58
  59         if (!--mmio_debug->suspend_count)
  60                 mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check;
  61 }
  62
  63 static const char * const forcewake_domain_names[] = {
  64         "render",
  65         "blitter",
  66         "media",
  67         "vdbox0",
  68         "vdbox1",
  69         "vdbox2",
  70         "vdbox3",
  71         "vebox0",
  72         "vebox1",
  73 };
  74
  75 const char *
  76 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  77 {
  78         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  79
  80         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  81                 return forcewake_domain_names[id];
  82
  83         WARN_ON(id);
  84
  85         return "unknown";
  86 }
  87
  88 #define fw_ack(d) readl((d)->reg_ack)
  89 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
  90 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
  91
  92 static inline void
  93 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  94 {
  95         /*
  96          * We don't really know if the powerwell for the forcewake domain we are
  97          * trying to reset here does exist at this point (engines could be fused
  98          * off in ICL+), so no waiting for acks
  99          */
 100         /* WaRsClearFWBitsAtReset:bdw,skl */
 101         fw_clear(d, 0xffff);
 102 }
 103
 104 static inline void
 105 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
 106 {
 107         GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);
 108         d->uncore->fw_domains_timer |= d->mask;
 109         d->wake_count++;
 110         hrtimer_start_range_ns(&d->timer,
 111                                NSEC_PER_MSEC,
 112                                NSEC_PER_MSEC,
 113                                HRTIMER_MODE_REL);
 114 }
 115
 116 static inline int
 117 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
 118                const u32 ack,
 119                const u32 value)
 120 {
 121         return wait_for_atomic((fw_ack(d) & ack) == value,
 122                                FORCEWAKE_ACK_TIMEOUT_MS);
 123 }
 124
 125 static inline int
 126 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
 127                const u32 ack)
 128 {
 129         return __wait_for_ack(d, ack, 0);
 130 }
 131
 132 static inline int
 133 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
 134              const u32 ack)
 135 {
 136         return __wait_for_ack(d, ack, ack);
 137 }
 138
 139 static inline void
 140 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
 141 {
 142         if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
 143                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
 144                           intel_uncore_forcewake_domain_to_str(d->id));
 145                 add_taint_for_CI(TAINT_WARN); /* CI now unreliable */
 146         }
 147 }
 148
 149 enum ack_type {
 150         ACK_CLEAR = 0,
 151         ACK_SET
 152 };
 153
 154 static int
 155 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
 156                                  const enum ack_type type)
 157 {
 158         const u32 ack_bit = FORCEWAKE_KERNEL;
 159         const u32 value = type == ACK_SET ? ack_bit : 0;
 160         unsigned int pass;
 161         bool ack_detected;
 162
 163         /*
 164          * There is a possibility of driver's wake request colliding
 165          * with hardware's own wake requests and that can cause
 166          * hardware to not deliver the driver's ack message.
 167          *
 168          * Use a fallback bit toggle to kick the gpu state machine
 169          * in the hope that the original ack will be delivered along with
 170          * the fallback ack.
 171          *
 172          * This workaround is described in HSDES #1604254524 and it's known as:
 173          * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
 174          * although the name is a bit misleading.
 175          */
 176
 177         pass = 1;
 178         do {
 179                 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 180
 181                 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
 182                 /* Give gt some time to relax before the polling frenzy */
 183                 udelay(10 * pass);
 184                 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
 185
 186                 ack_detected = (fw_ack(d) & ack_bit) == value;
 187
 188                 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 189         } while (!ack_detected && pass++ < 10);
 190
 191         DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
 192                          intel_uncore_forcewake_domain_to_str(d->id),
 193                          type == ACK_SET ? "set" : "clear",
 194                          fw_ack(d),
 195                          pass);
 196
 197         return ack_detected ? 0 : -ETIMEDOUT;
 198 }
 199
 200 static inline void
 201 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
 202 {
 203         if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
 204                 return;
 205
 206         if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
 207                 fw_domain_wait_ack_clear(d);
 208 }
 209
 210 static inline void
 211 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
 212 {
 213         fw_set(d, FORCEWAKE_KERNEL);
 214 }
 215
 216 static inline void
 217 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
 218 {
 219         if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
 220                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 221                           intel_uncore_forcewake_domain_to_str(d->id));
 222                 add_taint_for_CI(TAINT_WARN); /* CI now unreliable */
 223         }
 224 }
 225
 226 static inline void
 227 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
 228 {
 229         if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
 230                 return;
 231
 232         if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
 233                 fw_domain_wait_ack_set(d);
 234 }
 235
 236 static inline void
 237 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 238 {
 239         fw_clear(d, FORCEWAKE_KERNEL);
 240 }
 241
 242 static void
 243 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 244 {
 245         struct intel_uncore_forcewake_domain *d;
 246         unsigned int tmp;
 247
 248         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 249
 250         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 251                 fw_domain_wait_ack_clear(d);
 252                 fw_domain_get(d);
 253         }
 254
 255         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 256                 fw_domain_wait_ack_set(d);
 257
 258         uncore->fw_domains_active |= fw_domains;
 259 }
 260
 261 static void
 262 fw_domains_get_with_fallback(struct intel_uncore *uncore,
 263                              enum forcewake_domains fw_domains)
 264 {
 265         struct intel_uncore_forcewake_domain *d;
 266         unsigned int tmp;
 267
 268         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 269
 270         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 271                 fw_domain_wait_ack_clear_fallback(d);
 272                 fw_domain_get(d);
 273         }
 274
 275         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 276                 fw_domain_wait_ack_set_fallback(d);
 277
 278         uncore->fw_domains_active |= fw_domains;
 279 }
 280
 281 static void
 282 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 283 {
 284         struct intel_uncore_forcewake_domain *d;
 285         unsigned int tmp;
 286
 287         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 288
 289         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 290                 fw_domain_put(d);
 291
 292         uncore->fw_domains_active &= ~fw_domains;
 293 }
 294
 295 static void
 296 fw_domains_reset(struct intel_uncore *uncore,
 297                  enum forcewake_domains fw_domains)
 298 {
 299         struct intel_uncore_forcewake_domain *d;
 300         unsigned int tmp;
 301
 302         if (!fw_domains)
 303                 return;
 304
 305         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 306
 307         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 308                 fw_domain_reset(d);
 309 }
 310
 311 static inline u32 gt_thread_status(struct intel_uncore *uncore)
 312 {
 313         u32 val;
 314
 315         val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
 316         val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
 317
 318         return val;
 319 }
 320
 321 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
 322 {
 323         /*
 324          * w/a for a sporadic read returning 0 by waiting for the GT
 325          * thread to wake up.
 326          */
 327         drm_WARN_ONCE(&uncore->i915->drm,
 328                       wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
 329                       "GT thread status wait timed out\n");
 330 }
 331
 332 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
 333                                               enum forcewake_domains fw_domains)
 334 {
 335         fw_domains_get(uncore, fw_domains);
 336
 337         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 338         __gen6_gt_wait_for_thread_c0(uncore);
 339 }
 340
 341 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
 342 {
 343         u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
 344
 345         return count & GT_FIFO_FREE_ENTRIES_MASK;
 346 }
 347
 348 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
 349 {
 350         u32 n;
 351
 352         /* On VLV, FIFO will be shared by both SW and HW.
 353          * So, we need to read the FREE_ENTRIES everytime */
 354         if (IS_VALLEYVIEW(uncore->i915))
 355                 n = fifo_free_entries(uncore);
 356         else
 357                 n = uncore->fifo_count;
 358
 359         if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
 360                 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
 361                                     GT_FIFO_NUM_RESERVED_ENTRIES,
 362                                     GT_FIFO_TIMEOUT_MS)) {
 363                         drm_dbg(&uncore->i915->drm,
 364                                 "GT_FIFO timeout, entries: %u\n", n);
 365                         return;
 366                 }
 367         }
 368
 369         uncore->fifo_count = n - 1;
 370 }
 371
 372 static enum hrtimer_restart
 373 intel_uncore_fw_release_timer(struct hrtimer *timer)
 374 {
 375         struct intel_uncore_forcewake_domain *domain =
 376                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 377         struct intel_uncore *uncore = domain->uncore;
 378         unsigned long irqflags;
 379
 380         assert_rpm_device_not_suspended(uncore->rpm);
 381
 382         if (xchg(&domain->active, false))
 383                 return HRTIMER_RESTART;
 384
 385         spin_lock_irqsave(&uncore->lock, irqflags);
 386
 387         uncore->fw_domains_timer &= ~domain->mask;
 388
 389         GEM_BUG_ON(!domain->wake_count);
 390         if (--domain->wake_count == 0)
 391                 uncore->funcs.force_wake_put(uncore, domain->mask);
 392
 393         spin_unlock_irqrestore(&uncore->lock, irqflags);
 394
 395         return HRTIMER_NORESTART;
 396 }
 397
 398 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
 399 static unsigned int
 400 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
 401 {
 402         unsigned long irqflags;
 403         struct intel_uncore_forcewake_domain *domain;
 404         int retry_count = 100;
 405         enum forcewake_domains fw, active_domains;
 406
 407         iosf_mbi_assert_punit_acquired();
 408
 409         /* Hold uncore.lock across reset to prevent any register access
 410          * with forcewake not set correctly. Wait until all pending
 411          * timers are run before holding.
 412          */
 413         while (1) {
 414                 unsigned int tmp;
 415
 416                 active_domains = 0;
 417
 418                 for_each_fw_domain(domain, uncore, tmp) {
 419                         smp_store_mb(domain->active, false);
 420                         if (hrtimer_cancel(&domain->timer) == 0)
 421                                 continue;
 422
 423                         intel_uncore_fw_release_timer(&domain->timer);
 424                 }
 425
 426                 spin_lock_irqsave(&uncore->lock, irqflags);
 427
 428                 for_each_fw_domain(domain, uncore, tmp) {
 429                         if (hrtimer_active(&domain->timer))
 430                                 active_domains |= domain->mask;
 431                 }
 432
 433                 if (active_domains == 0)
 434                         break;
 435
 436                 if (--retry_count == 0) {
 437                         drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n");
 438                         break;
 439                 }
 440
 441                 spin_unlock_irqrestore(&uncore->lock, irqflags);
 442                 cond_resched();
 443         }
 444
 445         drm_WARN_ON(&uncore->i915->drm, active_domains);
 446
 447         fw = uncore->fw_domains_active;
 448         if (fw)
 449                 uncore->funcs.force_wake_put(uncore, fw);
 450
 451         fw_domains_reset(uncore, uncore->fw_domains);
 452         assert_forcewakes_inactive(uncore);
 453
 454         spin_unlock_irqrestore(&uncore->lock, irqflags);
 455
 456         return fw; /* track the lost user forcewake domains */
 457 }
 458
 459 static bool
 460 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 461 {
 462         u32 dbg;
 463
 464         dbg = __raw_uncore_read32(uncore, FPGA_DBG);
 465         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 466                 return false;
 467
 468         __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 469
 470         return true;
 471 }
 472
 473 static bool
 474 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 475 {
 476         u32 cer;
 477
 478         cer = __raw_uncore_read32(uncore, CLAIM_ER);
 479         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 480                 return false;
 481
 482         __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
 483
 484         return true;
 485 }
 486
 487 static bool
 488 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
 489 {
 490         u32 fifodbg;
 491
 492         fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
 493
 494         if (unlikely(fifodbg)) {
 495                 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
 496                 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
 497         }
 498
 499         return fifodbg;
 500 }
 501
 502 static bool
 503 check_for_unclaimed_mmio(struct intel_uncore *uncore)
 504 {
 505         bool ret = false;
 506
 507         lockdep_assert_held(&uncore->debug->lock);
 508
 509         if (uncore->debug->suspend_count)
 510                 return false;
 511
 512         if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
 513                 ret |= fpga_check_for_unclaimed_mmio(uncore);
 514
 515         if (intel_uncore_has_dbg_unclaimed(uncore))
 516                 ret |= vlv_check_for_unclaimed_mmio(uncore);
 517
 518         if (intel_uncore_has_fifo(uncore))
 519                 ret |= gen6_check_for_fifo_debug(uncore);
 520
 521         return ret;
 522 }
 523
 524 static void forcewake_early_sanitize(struct intel_uncore *uncore,
 525                                      unsigned int restore_forcewake)
 526 {
 527         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
 528
 529         /* WaDisableShadowRegForCpd:chv */
 530         if (IS_CHERRYVIEW(uncore->i915)) {
 531                 __raw_uncore_write32(uncore, GTFIFOCTL,
 532                                      __raw_uncore_read32(uncore, GTFIFOCTL) |
 533                                      GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 534                                      GT_FIFO_CTL_RC6_POLICY_STALL);
 535         }
 536
 537         iosf_mbi_punit_acquire();
 538         intel_uncore_forcewake_reset(uncore);
 539         if (restore_forcewake) {
 540                 spin_lock_irq(&uncore->lock);
 541                 uncore->funcs.force_wake_get(uncore, restore_forcewake);
 542
 543                 if (intel_uncore_has_fifo(uncore))
 544                         uncore->fifo_count = fifo_free_entries(uncore);
 545                 spin_unlock_irq(&uncore->lock);
 546         }
 547         iosf_mbi_punit_release();
 548 }
 549
 550 void intel_uncore_suspend(struct intel_uncore *uncore)
 551 {
 552         if (!intel_uncore_has_forcewake(uncore))
 553                 return;
 554
 555         iosf_mbi_punit_acquire();
 556         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
 557                 &uncore->pmic_bus_access_nb);
 558         uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
 559         iosf_mbi_punit_release();
 560 }
 561
 562 void intel_uncore_resume_early(struct intel_uncore *uncore)
 563 {
 564         unsigned int restore_forcewake;
 565
 566         if (intel_uncore_unclaimed_mmio(uncore))
 567                 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
 568
 569         if (!intel_uncore_has_forcewake(uncore))
 570                 return;
 571
 572         restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
 573         forcewake_early_sanitize(uncore, restore_forcewake);
 574
 575         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 576 }
 577
 578 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
 579 {
 580         if (!intel_uncore_has_forcewake(uncore))
 581                 return;
 582
 583         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 584 }
 585
 586 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
 587                                          enum forcewake_domains fw_domains)
 588 {
 589         struct intel_uncore_forcewake_domain *domain;
 590         unsigned int tmp;
 591
 592         fw_domains &= uncore->fw_domains;
 593
 594         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 595                 if (domain->wake_count++) {
 596                         fw_domains &= ~domain->mask;
 597                         domain->active = true;
 598                 }
 599         }
 600
 601         if (fw_domains)
 602                 uncore->funcs.force_wake_get(uncore, fw_domains);
 603 }
 604
 605 /**
 606  * intel_uncore_forcewake_get - grab forcewake domain references
 607  * @uncore: the intel_uncore structure
 608  * @fw_domains: forcewake domains to get reference on
 609  *
 610  * This function can be used get GT's forcewake domain references.
 611  * Normal register access will handle the forcewake domains automatically.
 612  * However if some sequence requires the GT to not power down a particular
 613  * forcewake domains this function should be called at the beginning of the
 614  * sequence. And subsequently the reference should be dropped by symmetric
 615  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 616  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 617  */
 618 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 619                                 enum forcewake_domains fw_domains)
 620 {
 621         unsigned long irqflags;
 622
 623         if (!uncore->funcs.force_wake_get)
 624                 return;
 625
 626         assert_rpm_wakelock_held(uncore->rpm);
 627
 628         spin_lock_irqsave(&uncore->lock, irqflags);
 629         __intel_uncore_forcewake_get(uncore, fw_domains);
 630         spin_unlock_irqrestore(&uncore->lock, irqflags);
 631 }
 632
 633 /**
 634  * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
 635  * @uncore: the intel_uncore structure
 636  *
 637  * This function is a wrapper around intel_uncore_forcewake_get() to acquire
 638  * the GT powerwell and in the process disable our debugging for the
 639  * duration of userspace's bypass.
 640  */
 641 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
 642 {
 643         spin_lock_irq(&uncore->lock);
 644         if (!uncore->user_forcewake_count++) {
 645                 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
 646                 spin_lock(&uncore->debug->lock);
 647                 mmio_debug_suspend(uncore->debug);
 648                 spin_unlock(&uncore->debug->lock);
 649         }
 650         spin_unlock_irq(&uncore->lock);
 651 }
 652
 653 /**
 654  * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
 655  * @uncore: the intel_uncore structure
 656  *
 657  * This function complements intel_uncore_forcewake_user_get() and releases
 658  * the GT powerwell taken on behalf of the userspace bypass.
 659  */
 660 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
 661 {
 662         spin_lock_irq(&uncore->lock);
 663         if (!--uncore->user_forcewake_count) {
 664                 spin_lock(&uncore->debug->lock);
 665                 mmio_debug_resume(uncore->debug);
 666
 667                 if (check_for_unclaimed_mmio(uncore))
 668                         drm_info(&uncore->i915->drm,
 669                                  "Invalid mmio detected during user access\n");
 670                 spin_unlock(&uncore->debug->lock);
 671
 672                 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
 673         }
 674         spin_unlock_irq(&uncore->lock);
 675 }
 676
 677 /**
 678  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 679  * @uncore: the intel_uncore structure
 680  * @fw_domains: forcewake domains to get reference on
 681  *
 682  * See intel_uncore_forcewake_get(). This variant places the onus
 683  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 684  */
 685 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 686                                         enum forcewake_domains fw_domains)
 687 {
 688         lockdep_assert_held(&uncore->lock);
 689
 690         if (!uncore->funcs.force_wake_get)
 691                 return;
 692
 693         __intel_uncore_forcewake_get(uncore, fw_domains);
 694 }
 695
 696 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
 697                                          enum forcewake_domains fw_domains)
 698 {
 699         struct intel_uncore_forcewake_domain *domain;
 700         unsigned int tmp;
 701
 702         fw_domains &= uncore->fw_domains;
 703
 704         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 705                 GEM_BUG_ON(!domain->wake_count);
 706
 707                 if (--domain->wake_count) {
 708                         domain->active = true;
 709                         continue;
 710                 }
 711
 712                 fw_domain_arm_timer(domain);
 713         }
 714 }
 715
 716 /**
 717  * intel_uncore_forcewake_put - release a forcewake domain reference
 718  * @uncore: the intel_uncore structure
 719  * @fw_domains: forcewake domains to put references
 720  *
 721  * This function drops the device-level forcewakes for specified
 722  * domains obtained by intel_uncore_forcewake_get().
 723  */
 724 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 725                                 enum forcewake_domains fw_domains)
 726 {
 727         unsigned long irqflags;
 728
 729         if (!uncore->funcs.force_wake_put)
 730                 return;
 731
 732         spin_lock_irqsave(&uncore->lock, irqflags);
 733         __intel_uncore_forcewake_put(uncore, fw_domains);
 734         spin_unlock_irqrestore(&uncore->lock, irqflags);
 735 }
 736
 737 /**
 738  * intel_uncore_forcewake_flush - flush the delayed release
 739  * @uncore: the intel_uncore structure
 740  * @fw_domains: forcewake domains to flush
 741  */
 742 void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
 743                                   enum forcewake_domains fw_domains)
 744 {
 745         struct intel_uncore_forcewake_domain *domain;
 746         unsigned int tmp;
 747
 748         if (!uncore->funcs.force_wake_put)
 749                 return;
 750
 751         fw_domains &= uncore->fw_domains;
 752         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 753                 WRITE_ONCE(domain->active, false);
 754                 if (hrtimer_cancel(&domain->timer))
 755                         intel_uncore_fw_release_timer(&domain->timer);
 756         }
 757 }
 758
 759 /**
 760  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 761  * @uncore: the intel_uncore structure
 762  * @fw_domains: forcewake domains to get reference on
 763  *
 764  * See intel_uncore_forcewake_put(). This variant places the onus
 765  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 766  */
 767 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 768                                         enum forcewake_domains fw_domains)
 769 {
 770         lockdep_assert_held(&uncore->lock);
 771
 772         if (!uncore->funcs.force_wake_put)
 773                 return;
 774
 775         __intel_uncore_forcewake_put(uncore, fw_domains);
 776 }
 777
 778 void assert_forcewakes_inactive(struct intel_uncore *uncore)
 779 {
 780         if (!uncore->funcs.force_wake_get)
 781                 return;
 782
 783         drm_WARN(&uncore->i915->drm, uncore->fw_domains_active,
 784                  "Expected all fw_domains to be inactive, but %08x are still on\n",
 785                  uncore->fw_domains_active);
 786 }
 787
 788 void assert_forcewakes_active(struct intel_uncore *uncore,
 789                               enum forcewake_domains fw_domains)
 790 {
 791         struct intel_uncore_forcewake_domain *domain;
 792         unsigned int tmp;
 793
 794         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 795                 return;
 796
 797         if (!uncore->funcs.force_wake_get)
 798                 return;
 799
 800         spin_lock_irq(&uncore->lock);
 801
 802         assert_rpm_wakelock_held(uncore->rpm);
 803
 804         fw_domains &= uncore->fw_domains;
 805         drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active,
 806                  "Expected %08x fw_domains to be active, but %08x are off\n",
 807                  fw_domains, fw_domains & ~uncore->fw_domains_active);
 808
 809         /*
 810          * Check that the caller has an explicit wakeref and we don't mistake
 811          * it for the auto wakeref.
 812          */
 813         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 814                 unsigned int actual = READ_ONCE(domain->wake_count);
 815                 unsigned int expect = 1;
 816
 817                 if (uncore->fw_domains_timer & domain->mask)
 818                         expect++; /* pending automatic release */
 819
 820                 if (drm_WARN(&uncore->i915->drm, actual < expect,
 821                              "Expected domain %d to be held awake by caller, count=%d\n",
 822                              domain->id, actual))
 823                         break;
 824         }
 825
 826         spin_unlock_irq(&uncore->lock);
 827 }
 828
 829 /* We give fast paths for the really cool registers */
 830 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 831
 832 #define __gen6_reg_read_fw_domains(uncore, offset) \
 833 ({ \
 834         enum forcewake_domains __fwd; \
 835         if (NEEDS_FORCE_WAKE(offset)) \
 836                 __fwd = FORCEWAKE_RENDER; \
 837         else \
 838                 __fwd = 0; \
 839         __fwd; \
 840 })
 841
 842 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 843 {
 844         if (offset < entry->start)
 845                 return -1;
 846         else if (offset > entry->end)
 847                 return 1;
 848         else
 849                 return 0;
 850 }
 851
 852 /* Copied and "macroized" from lib/bsearch.c */
 853 #define BSEARCH(key, base, num, cmp) ({                                 \
 854         unsigned int start__ = 0, end__ = (num);                        \
 855         typeof(base) result__ = NULL;                                   \
 856         while (start__ < end__) {                                       \
 857                 unsigned int mid__ = start__ + (end__ - start__) / 2;   \
 858                 int ret__ = (cmp)((key), (base) + mid__);               \
 859                 if (ret__ < 0) {                                        \
 860                         end__ = mid__;                                  \
 861                 } else if (ret__ > 0) {                                 \
 862                         start__ = mid__ + 1;                            \
 863                 } else {                                                \
 864                         result__ = (base) + mid__;                      \
 865                         break;                                          \
 866                 }                                                       \
 867         }                                                               \
 868         result__;                                                       \
 869 })
 870
 871 static enum forcewake_domains
 872 find_fw_domain(struct intel_uncore *uncore, u32 offset)
 873 {
 874         const struct intel_forcewake_range *entry;
 875
 876         entry = BSEARCH(offset,
 877                         uncore->fw_domains_table,
 878                         uncore->fw_domains_table_entries,
 879                         fw_range_cmp);
 880
 881         if (!entry)
 882                 return 0;
 883
 884         /*
 885          * The list of FW domains depends on the SKU in gen11+ so we
 886          * can't determine it statically. We use FORCEWAKE_ALL and
 887          * translate it here to the list of available domains.
 888          */
 889         if (entry->domains == FORCEWAKE_ALL)
 890                 return uncore->fw_domains;
 891
 892         drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains,
 893                  "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 894                  entry->domains & ~uncore->fw_domains, offset);
 895
 896         return entry->domains;
 897 }
 898
 899 #define GEN_FW_RANGE(s, e, d) \
 900         { .start = (s), .end = (e), .domains = (d) }
 901
 902 #define HAS_FWTABLE(dev_priv) \
 903         (INTEL_GEN(dev_priv) >= 9 || \
 904          IS_CHERRYVIEW(dev_priv) || \
 905          IS_VALLEYVIEW(dev_priv))
 906
 907 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 908 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 909         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 910         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
 911         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
 912         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 913         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
 914         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
 915         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 916 };
 917
 918 #define __fwtable_reg_read_fw_domains(uncore, offset) \
 919 ({ \
 920         enum forcewake_domains __fwd = 0; \
 921         if (NEEDS_FORCE_WAKE((offset))) \
 922                 __fwd = find_fw_domain(uncore, offset); \
 923         __fwd; \
 924 })
 925
 926 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
 927         find_fw_domain(uncore, offset)
 928
 929 #define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
 930         find_fw_domain(uncore, offset)
 931
 932 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 933 static const i915_reg_t gen8_shadowed_regs[] = {
 934         RING_TAIL(RENDER_RING_BASE),    /* 0x2000 (base) */
 935         GEN6_RPNSWREQ,                  /* 0xA008 */
 936         GEN6_RC_VIDEO_FREQ,             /* 0xA00C */
 937         RING_TAIL(GEN6_BSD_RING_BASE),  /* 0x12000 (base) */
 938         RING_TAIL(VEBOX_RING_BASE),     /* 0x1a000 (base) */
 939         RING_TAIL(BLT_RING_BASE),       /* 0x22000 (base) */
 940         /* TODO: Other registers are not yet used */
 941 };
 942
 943 static const i915_reg_t gen11_shadowed_regs[] = {
 944         RING_TAIL(RENDER_RING_BASE),            /* 0x2000 (base) */
 945         GEN6_RPNSWREQ,                          /* 0xA008 */
 946         GEN6_RC_VIDEO_FREQ,                     /* 0xA00C */
 947         RING_TAIL(BLT_RING_BASE),               /* 0x22000 (base) */
 948         RING_TAIL(GEN11_BSD_RING_BASE),         /* 0x1C0000 (base) */
 949         RING_TAIL(GEN11_BSD2_RING_BASE),        /* 0x1C4000 (base) */
 950         RING_TAIL(GEN11_VEBOX_RING_BASE),       /* 0x1C8000 (base) */
 951         RING_TAIL(GEN11_BSD3_RING_BASE),        /* 0x1D0000 (base) */
 952         RING_TAIL(GEN11_BSD4_RING_BASE),        /* 0x1D4000 (base) */
 953         RING_TAIL(GEN11_VEBOX2_RING_BASE),      /* 0x1D8000 (base) */
 954         /* TODO: Other registers are not yet used */
 955 };
 956
 957 static const i915_reg_t gen12_shadowed_regs[] = {
 958         RING_TAIL(RENDER_RING_BASE),            /* 0x2000 (base) */
 959         GEN6_RPNSWREQ,                          /* 0xA008 */
 960         GEN6_RC_VIDEO_FREQ,                     /* 0xA00C */
 961         RING_TAIL(BLT_RING_BASE),               /* 0x22000 (base) */
 962         RING_TAIL(GEN11_BSD_RING_BASE),         /* 0x1C0000 (base) */
 963         RING_TAIL(GEN11_BSD2_RING_BASE),        /* 0x1C4000 (base) */
 964         RING_TAIL(GEN11_VEBOX_RING_BASE),       /* 0x1C8000 (base) */
 965         RING_TAIL(GEN11_BSD3_RING_BASE),        /* 0x1D0000 (base) */
 966         RING_TAIL(GEN11_BSD4_RING_BASE),        /* 0x1D4000 (base) */
 967         RING_TAIL(GEN11_VEBOX2_RING_BASE),      /* 0x1D8000 (base) */
 968         /* TODO: Other registers are not yet used */
 969 };
 970
 971 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 972 {
 973         u32 offset = i915_mmio_reg_offset(*reg);
 974
 975         if (key < offset)
 976                 return -1;
 977         else if (key > offset)
 978                 return 1;
 979         else
 980                 return 0;
 981 }
 982
 983 #define __is_genX_shadowed(x) \
 984 static bool is_gen##x##_shadowed(u32 offset) \
 985 { \
 986         const i915_reg_t *regs = gen##x##_shadowed_regs; \
 987         return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
 988                        mmio_reg_cmp); \
 989 }
 990
 991 __is_genX_shadowed(8)
 992 __is_genX_shadowed(11)
 993 __is_genX_shadowed(12)
 994
 995 static enum forcewake_domains
 996 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
 997 {
 998         return FORCEWAKE_RENDER;
 999 }
1000
1001 #define __gen8_reg_write_fw_domains(uncore, offset) \
1002 ({ \
1003         enum forcewake_domains __fwd; \
1004         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
1005                 __fwd = FORCEWAKE_RENDER; \
1006         else \
1007                 __fwd = 0; \
1008         __fwd; \
1009 })
1010
1011 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1012 static const struct intel_forcewake_range __chv_fw_ranges[] = {
1013         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1014         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1015         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1016         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1017         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1018         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1019         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
1020         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1021         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1022         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1023         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
1024         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1025         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1026         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
1027         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
1028         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
1029 };
1030
1031 #define __fwtable_reg_write_fw_domains(uncore, offset) \
1032 ({ \
1033         enum forcewake_domains __fwd = 0; \
1034         if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
1035                 __fwd = find_fw_domain(uncore, offset); \
1036         __fwd; \
1037 })
1038
1039 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
1040 ({ \
1041         enum forcewake_domains __fwd = 0; \
1042         const u32 __offset = (offset); \
1043         if (!is_gen11_shadowed(__offset)) \
1044                 __fwd = find_fw_domain(uncore, __offset); \
1045         __fwd; \
1046 })
1047
1048 #define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
1049 ({ \
1050         enum forcewake_domains __fwd = 0; \
1051         const u32 __offset = (offset); \
1052         if (!is_gen12_shadowed(__offset)) \
1053                 __fwd = find_fw_domain(uncore, __offset); \
1054         __fwd; \
1055 })
1056
1057 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1058 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
1059         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1060         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1061         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1062         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1063         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1064         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1065         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1066         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
1067         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1068         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1069         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1070         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1071         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
1072         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1073         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
1074         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1075         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1076         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1077         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1078         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1079         GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
1080         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1081         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
1082         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1083         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
1084         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1085         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
1086         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1087         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
1088         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1089         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
1090         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1091 };
1092
1093 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1094 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1095         GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
1096         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1097         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1098         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1099         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1100         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1101         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1102         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1103         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1104         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1105         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
1106         GEN_FW_RANGE(0x8800, 0x8bff, 0),
1107         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1108         GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER),
1109         GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1110         GEN_FW_RANGE(0x9560, 0x95ff, 0),
1111         GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER),
1112         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1113         GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
1114         GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
1115         GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
1116         GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
1117         GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER),
1118         GEN_FW_RANGE(0x24000, 0x2407f, 0),
1119         GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER),
1120         GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
1121         GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER),
1122         GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
1123         GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_BLITTER),
1124         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1125         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1126         GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1127         GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0),
1128         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1129         GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
1130 };
1131
1132 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1133 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
1134         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1135         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1136         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1137         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1138         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1139         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1140         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1141         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1142         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1143         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1144         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1145         GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
1146         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1147         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1148         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
1149         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1150         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1151         GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
1152         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1153         GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
1154         GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
1155         GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
1156         GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
1157         GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
1158         GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
1159         GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
1160         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1161         GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1162         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1163         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1164         GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1165         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1166         GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1167         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1168         GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1169         GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1170 };
1171
1172 static void
1173 ilk_dummy_write(struct intel_uncore *uncore)
1174 {
1175         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1176          * the chip from rc6 before touching it for real. MI_MODE is masked,
1177          * hence harmless to write 0 into. */
1178         __raw_uncore_write32(uncore, MI_MODE, 0);
1179 }
1180
1181 static void
1182 __unclaimed_reg_debug(struct intel_uncore *uncore,
1183                       const i915_reg_t reg,
1184                       const bool read,
1185                       const bool before)
1186 {
1187         if (drm_WARN(&uncore->i915->drm,
1188                      check_for_unclaimed_mmio(uncore) && !before,
1189                      "Unclaimed %s register 0x%x\n",
1190                      read ? "read from" : "write to",
1191                      i915_mmio_reg_offset(reg)))
1192                 /* Only report the first N failures */
1193                 i915_modparams.mmio_debug--;
1194 }
1195
1196 static inline void
1197 unclaimed_reg_debug(struct intel_uncore *uncore,
1198                     const i915_reg_t reg,
1199                     const bool read,
1200                     const bool before)
1201 {
1202         if (likely(!i915_modparams.mmio_debug))
1203                 return;
1204
1205         /* interrupts are disabled and re-enabled around uncore->lock usage */
1206         lockdep_assert_held(&uncore->lock);
1207
1208         if (before)
1209                 spin_lock(&uncore->debug->lock);
1210
1211         __unclaimed_reg_debug(uncore, reg, read, before);
1212
1213         if (!before)
1214                 spin_unlock(&uncore->debug->lock);
1215 }
1216
1217 #define GEN2_READ_HEADER(x) \
1218         u##x val = 0; \
1219         assert_rpm_wakelock_held(uncore->rpm);
1220
1221 #define GEN2_READ_FOOTER \
1222         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1223         return val
1224
1225 #define __gen2_read(x) \
1226 static u##x \
1227 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1228         GEN2_READ_HEADER(x); \
1229         val = __raw_uncore_read##x(uncore, reg); \
1230         GEN2_READ_FOOTER; \
1231 }
1232
1233 #define __gen5_read(x) \
1234 static u##x \
1235 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1236         GEN2_READ_HEADER(x); \
1237         ilk_dummy_write(uncore); \
1238         val = __raw_uncore_read##x(uncore, reg); \
1239         GEN2_READ_FOOTER; \
1240 }
1241
1242 __gen5_read(8)
1243 __gen5_read(16)
1244 __gen5_read(32)
1245 __gen5_read(64)
1246 __gen2_read(8)
1247 __gen2_read(16)
1248 __gen2_read(32)
1249 __gen2_read(64)
1250
1251 #undef __gen5_read
1252 #undef __gen2_read
1253
1254 #undef GEN2_READ_FOOTER
1255 #undef GEN2_READ_HEADER
1256
1257 #define GEN6_READ_HEADER(x) \
1258         u32 offset = i915_mmio_reg_offset(reg); \
1259         unsigned long irqflags; \
1260         u##x val = 0; \
1261         assert_rpm_wakelock_held(uncore->rpm); \
1262         spin_lock_irqsave(&uncore->lock, irqflags); \
1263         unclaimed_reg_debug(uncore, reg, true, true)
1264
1265 #define GEN6_READ_FOOTER \
1266         unclaimed_reg_debug(uncore, reg, true, false); \
1267         spin_unlock_irqrestore(&uncore->lock, irqflags); \
1268         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1269         return val
1270
1271 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1272                                         enum forcewake_domains fw_domains)
1273 {
1274         struct intel_uncore_forcewake_domain *domain;
1275         unsigned int tmp;
1276
1277         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1278
1279         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1280                 fw_domain_arm_timer(domain);
1281
1282         uncore->funcs.force_wake_get(uncore, fw_domains);
1283 }
1284
1285 static inline void __force_wake_auto(struct intel_uncore *uncore,
1286                                      enum forcewake_domains fw_domains)
1287 {
1288         GEM_BUG_ON(!fw_domains);
1289
1290         /* Turn on all requested but inactive supported forcewake domains. */
1291         fw_domains &= uncore->fw_domains;
1292         fw_domains &= ~uncore->fw_domains_active;
1293
1294         if (fw_domains)
1295                 ___force_wake_auto(uncore, fw_domains);
1296 }
1297
1298 #define __gen_read(func, x) \
1299 static u##x \
1300 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1301         enum forcewake_domains fw_engine; \
1302         GEN6_READ_HEADER(x); \
1303         fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
1304         if (fw_engine) \
1305                 __force_wake_auto(uncore, fw_engine); \
1306         val = __raw_uncore_read##x(uncore, reg); \
1307         GEN6_READ_FOOTER; \
1308 }
1309
1310 #define __gen_reg_read_funcs(func) \
1311 static enum forcewake_domains \
1312 func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1313         return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1314 } \
1315 \
1316 __gen_read(func, 8) \
1317 __gen_read(func, 16) \
1318 __gen_read(func, 32) \
1319 __gen_read(func, 64)
1320
1321 __gen_reg_read_funcs(gen12_fwtable);
1322 __gen_reg_read_funcs(gen11_fwtable);
1323 __gen_reg_read_funcs(fwtable);
1324 __gen_reg_read_funcs(gen6);
1325
1326 #undef __gen_reg_read_funcs
1327 #undef GEN6_READ_FOOTER
1328 #undef GEN6_READ_HEADER
1329
1330 #define GEN2_WRITE_HEADER \
1331         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1332         assert_rpm_wakelock_held(uncore->rpm); \
1333
1334 #define GEN2_WRITE_FOOTER
1335
1336 #define __gen2_write(x) \
1337 static void \
1338 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1339         GEN2_WRITE_HEADER; \
1340         __raw_uncore_write##x(uncore, reg, val); \
1341         GEN2_WRITE_FOOTER; \
1342 }
1343
1344 #define __gen5_write(x) \
1345 static void \
1346 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1347         GEN2_WRITE_HEADER; \
1348         ilk_dummy_write(uncore); \
1349         __raw_uncore_write##x(uncore, reg, val); \
1350         GEN2_WRITE_FOOTER; \
1351 }
1352
1353 __gen5_write(8)
1354 __gen5_write(16)
1355 __gen5_write(32)
1356 __gen2_write(8)
1357 __gen2_write(16)
1358 __gen2_write(32)
1359
1360 #undef __gen5_write
1361 #undef __gen2_write
1362
1363 #undef GEN2_WRITE_FOOTER
1364 #undef GEN2_WRITE_HEADER
1365
1366 #define GEN6_WRITE_HEADER \
1367         u32 offset = i915_mmio_reg_offset(reg); \
1368         unsigned long irqflags; \
1369         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1370         assert_rpm_wakelock_held(uncore->rpm); \
1371         spin_lock_irqsave(&uncore->lock, irqflags); \
1372         unclaimed_reg_debug(uncore, reg, false, true)
1373
1374 #define GEN6_WRITE_FOOTER \
1375         unclaimed_reg_debug(uncore, reg, false, false); \
1376         spin_unlock_irqrestore(&uncore->lock, irqflags)
1377
1378 #define __gen6_write(x) \
1379 static void \
1380 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1381         GEN6_WRITE_HEADER; \
1382         if (NEEDS_FORCE_WAKE(offset)) \
1383                 __gen6_gt_wait_for_fifo(uncore); \
1384         __raw_uncore_write##x(uncore, reg, val); \
1385         GEN6_WRITE_FOOTER; \
1386 }
1387 __gen6_write(8)
1388 __gen6_write(16)
1389 __gen6_write(32)
1390
1391 #define __gen_write(func, x) \
1392 static void \
1393 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1394         enum forcewake_domains fw_engine; \
1395         GEN6_WRITE_HEADER; \
1396         fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
1397         if (fw_engine) \
1398                 __force_wake_auto(uncore, fw_engine); \
1399         __raw_uncore_write##x(uncore, reg, val); \
1400         GEN6_WRITE_FOOTER; \
1401 }
1402
1403 #define __gen_reg_write_funcs(func) \
1404 static enum forcewake_domains \
1405 func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1406         return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1407 } \
1408 \
1409 __gen_write(func, 8) \
1410 __gen_write(func, 16) \
1411 __gen_write(func, 32)
1412
1413 __gen_reg_write_funcs(gen12_fwtable);
1414 __gen_reg_write_funcs(gen11_fwtable);
1415 __gen_reg_write_funcs(fwtable);
1416 __gen_reg_write_funcs(gen8);
1417
1418 #undef __gen_reg_write_funcs
1419 #undef GEN6_WRITE_FOOTER
1420 #undef GEN6_WRITE_HEADER
1421
1422 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
1423 do { \
1424         (uncore)->funcs.mmio_writeb = x##_write8; \
1425         (uncore)->funcs.mmio_writew = x##_write16; \
1426         (uncore)->funcs.mmio_writel = x##_write32; \
1427 } while (0)
1428
1429 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
1430 do { \
1431         (uncore)->funcs.mmio_readb = x##_read8; \
1432         (uncore)->funcs.mmio_readw = x##_read16; \
1433         (uncore)->funcs.mmio_readl = x##_read32; \
1434         (uncore)->funcs.mmio_readq = x##_read64; \
1435 } while (0)
1436
1437 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1438 do { \
1439         ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
1440         (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
1441 } while (0)
1442
1443 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1444 do { \
1445         ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
1446         (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
1447 } while (0)
1448
1449 static int __fw_domain_init(struct intel_uncore *uncore,
1450                             enum forcewake_domain_id domain_id,
1451                             i915_reg_t reg_set,
1452                             i915_reg_t reg_ack)
1453 {
1454         struct intel_uncore_forcewake_domain *d;
1455
1456         GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1457         GEM_BUG_ON(uncore->fw_domain[domain_id]);
1458
1459         if (i915_inject_probe_failure(uncore->i915))
1460                 return -ENOMEM;
1461
1462         d = kzalloc(sizeof(*d), GFP_KERNEL);
1463         if (!d)
1464                 return -ENOMEM;
1465
1466         drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set));
1467         drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack));
1468
1469         d->uncore = uncore;
1470         d->wake_count = 0;
1471         d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1472         d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
1473
1474         d->id = domain_id;
1475
1476         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1477         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1478         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1479         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1480         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1481         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1482         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1483         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1484         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1485
1486         d->mask = BIT(domain_id);
1487
1488         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1489         d->timer.function = intel_uncore_fw_release_timer;
1490
1491         uncore->fw_domains |= BIT(domain_id);
1492
1493         fw_domain_reset(d);
1494
1495         uncore->fw_domain[domain_id] = d;
1496
1497         return 0;
1498 }
1499
1500 static void fw_domain_fini(struct intel_uncore *uncore,
1501                            enum forcewake_domain_id domain_id)
1502 {
1503         struct intel_uncore_forcewake_domain *d;
1504
1505         GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1506
1507         d = fetch_and_zero(&uncore->fw_domain[domain_id]);
1508         if (!d)
1509                 return;
1510
1511         uncore->fw_domains &= ~BIT(domain_id);
1512         drm_WARN_ON(&uncore->i915->drm, d->wake_count);
1513         drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer));
1514         kfree(d);
1515 }
1516
1517 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
1518 {
1519         struct intel_uncore_forcewake_domain *d;
1520         int tmp;
1521
1522         for_each_fw_domain(d, uncore, tmp)
1523                 fw_domain_fini(uncore, d->id);
1524 }
1525
1526 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
1527 {
1528         struct drm_i915_private *i915 = uncore->i915;
1529         int ret = 0;
1530
1531         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1532
1533 #define fw_domain_init(uncore__, id__, set__, ack__) \
1534         (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
1535
1536         if (INTEL_GEN(i915) >= 11) {
1537                 int i;
1538
1539                 uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1540                 uncore->funcs.force_wake_put = fw_domains_put;
1541                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1542                                FORCEWAKE_RENDER_GEN9,
1543                                FORCEWAKE_ACK_RENDER_GEN9);
1544                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1545                                FORCEWAKE_BLITTER_GEN9,
1546                                FORCEWAKE_ACK_BLITTER_GEN9);
1547
1548                 for (i = 0; i < I915_MAX_VCS; i++) {
1549                         if (!HAS_ENGINE(i915, _VCS(i)))
1550                                 continue;
1551
1552                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1553                                        FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1554                                        FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1555                 }
1556                 for (i = 0; i < I915_MAX_VECS; i++) {
1557                         if (!HAS_ENGINE(i915, _VECS(i)))
1558                                 continue;
1559
1560                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1561                                        FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1562                                        FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1563                 }
1564         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1565                 uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1566                 uncore->funcs.force_wake_put = fw_domains_put;
1567                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1568                                FORCEWAKE_RENDER_GEN9,
1569                                FORCEWAKE_ACK_RENDER_GEN9);
1570                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1571                                FORCEWAKE_BLITTER_GEN9,
1572                                FORCEWAKE_ACK_BLITTER_GEN9);
1573                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1574                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1575         } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1576                 uncore->funcs.force_wake_get = fw_domains_get;
1577                 uncore->funcs.force_wake_put = fw_domains_put;
1578                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1579                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1580                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1581                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1582         } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1583                 uncore->funcs.force_wake_get =
1584                         fw_domains_get_with_thread_status;
1585                 uncore->funcs.force_wake_put = fw_domains_put;
1586                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1587                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1588         } else if (IS_IVYBRIDGE(i915)) {
1589                 u32 ecobus;
1590
1591                 /* IVB configs may use multi-threaded forcewake */
1592
1593                 /* A small trick here - if the bios hasn't configured
1594                  * MT forcewake, and if the device is in RC6, then
1595                  * force_wake_mt_get will not wake the device and the
1596                  * ECOBUS read will return zero. Which will be
1597                  * (correctly) interpreted by the test below as MT
1598                  * forcewake being disabled.
1599                  */
1600                 uncore->funcs.force_wake_get =
1601                         fw_domains_get_with_thread_status;
1602                 uncore->funcs.force_wake_put = fw_domains_put;
1603
1604                 /* We need to init first for ECOBUS access and then
1605                  * determine later if we want to reinit, in case of MT access is
1606                  * not working. In this stage we don't know which flavour this
1607                  * ivb is, so it is better to reset also the gen6 fw registers
1608                  * before the ecobus check.
1609                  */
1610
1611                 __raw_uncore_write32(uncore, FORCEWAKE, 0);
1612                 __raw_posting_read(uncore, ECOBUS);
1613
1614                 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1615                                        FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1616                 if (ret)
1617                         goto out;
1618
1619                 spin_lock_irq(&uncore->lock);
1620                 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
1621                 ecobus = __raw_uncore_read32(uncore, ECOBUS);
1622                 fw_domains_put(uncore, FORCEWAKE_RENDER);
1623                 spin_unlock_irq(&uncore->lock);
1624
1625                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1626                         drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n");
1627                         drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n");
1628                         fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER);
1629                         fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1630                                        FORCEWAKE, FORCEWAKE_ACK);
1631                 }
1632         } else if (IS_GEN(i915, 6)) {
1633                 uncore->funcs.force_wake_get =
1634                         fw_domains_get_with_thread_status;
1635                 uncore->funcs.force_wake_put = fw_domains_put;
1636                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1637                                FORCEWAKE, FORCEWAKE_ACK);
1638         }
1639
1640 #undef fw_domain_init
1641
1642         /* All future platforms are expected to require complex power gating */
1643         drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0);
1644
1645 out:
1646         if (ret)
1647                 intel_uncore_fw_domains_fini(uncore);
1648
1649         return ret;
1650 }
1651
1652 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
1653 { \
1654         (uncore)->fw_domains_table = \
1655                         (struct intel_forcewake_range *)(d); \
1656         (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
1657 }
1658
1659 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1660                                          unsigned long action, void *data)
1661 {
1662         struct intel_uncore *uncore = container_of(nb,
1663                         struct intel_uncore, pmic_bus_access_nb);
1664
1665         switch (action) {
1666         case MBI_PMIC_BUS_ACCESS_BEGIN:
1667                 /*
1668                  * forcewake all now to make sure that we don't need to do a
1669                  * forcewake later which on systems where this notifier gets
1670                  * called requires the punit to access to the shared pmic i2c
1671                  * bus, which will be busy after this notification, leading to:
1672                  * "render: timed out waiting for forcewake ack request."
1673                  * errors.
1674                  *
1675                  * The notifier is unregistered during intel_runtime_suspend(),
1676                  * so it's ok to access the HW here without holding a RPM
1677                  * wake reference -> disable wakeref asserts for the time of
1678                  * the access.
1679                  */
1680                 disable_rpm_wakeref_asserts(uncore->rpm);
1681                 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1682                 enable_rpm_wakeref_asserts(uncore->rpm);
1683                 break;
1684         case MBI_PMIC_BUS_ACCESS_END:
1685                 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1686                 break;
1687         }
1688
1689         return NOTIFY_OK;
1690 }
1691
1692 static int uncore_mmio_setup(struct intel_uncore *uncore)
1693 {
1694         struct drm_i915_private *i915 = uncore->i915;
1695         struct pci_dev *pdev = i915->drm.pdev;
1696         int mmio_bar;
1697         int mmio_size;
1698
1699         mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
1700         /*
1701          * Before gen4, the registers and the GTT are behind different BARs.
1702          * However, from gen4 onwards, the registers and the GTT are shared
1703          * in the same BAR, so we want to restrict this ioremap from
1704          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1705          * the register BAR remains the same size for all the earlier
1706          * generations up to Ironlake.
1707          */
1708         if (INTEL_GEN(i915) < 5)
1709                 mmio_size = 512 * 1024;
1710         else
1711                 mmio_size = 2 * 1024 * 1024;
1712         uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
1713         if (uncore->regs == NULL) {
1714                 drm_err(&i915->drm, "failed to map registers\n");
1715                 return -EIO;
1716         }
1717
1718         return 0;
1719 }
1720
1721 static void uncore_mmio_cleanup(struct intel_uncore *uncore)
1722 {
1723         struct pci_dev *pdev = uncore->i915->drm.pdev;
1724
1725         pci_iounmap(pdev, uncore->regs);
1726 }
1727
1728 void intel_uncore_init_early(struct intel_uncore *uncore,
1729                              struct drm_i915_private *i915)
1730 {
1731         spin_lock_init(&uncore->lock);
1732         uncore->i915 = i915;
1733         uncore->rpm = &i915->runtime_pm;
1734         uncore->debug = &i915->mmio_debug;
1735 }
1736
1737 static void uncore_raw_init(struct intel_uncore *uncore)
1738 {
1739         GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
1740
1741         if (IS_GEN(uncore->i915, 5)) {
1742                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
1743                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
1744         } else {
1745                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
1746                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
1747         }
1748 }
1749
1750 static int uncore_forcewake_init(struct intel_uncore *uncore)
1751 {
1752         struct drm_i915_private *i915 = uncore->i915;
1753         int ret;
1754
1755         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1756
1757         ret = intel_uncore_fw_domains_init(uncore);
1758         if (ret)
1759                 return ret;
1760         forcewake_early_sanitize(uncore, 0);
1761
1762         if (IS_GEN_RANGE(i915, 6, 7)) {
1763                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
1764
1765                 if (IS_VALLEYVIEW(i915)) {
1766                         ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
1767                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1768                 } else {
1769                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1770                 }
1771         } else if (IS_GEN(i915, 8)) {
1772                 if (IS_CHERRYVIEW(i915)) {
1773                         ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
1774                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1775                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1776                 } else {
1777                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
1778                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1779                 }
1780         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1781                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
1782                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1783                 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1784         } else if (IS_GEN(i915, 11)) {
1785                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
1786                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
1787                 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
1788         } else {
1789                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
1790                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
1791                 ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
1792         }
1793
1794         uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
1795         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
1796
1797         return 0;
1798 }
1799
1800 int intel_uncore_init_mmio(struct intel_uncore *uncore)
1801 {
1802         struct drm_i915_private *i915 = uncore->i915;
1803         int ret;
1804
1805         ret = uncore_mmio_setup(uncore);
1806         if (ret)
1807                 return ret;
1808
1809         if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
1810                 uncore->flags |= UNCORE_HAS_FORCEWAKE;
1811
1812         if (!intel_uncore_has_forcewake(uncore)) {
1813                 uncore_raw_init(uncore);
1814         } else {
1815                 ret = uncore_forcewake_init(uncore);
1816                 if (ret)
1817                         goto out_mmio_cleanup;
1818         }
1819
1820         /* make sure fw funcs are set if and only if we have fw*/
1821         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get);
1822         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put);
1823         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
1824         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
1825
1826         if (HAS_FPGA_DBG_UNCLAIMED(i915))
1827                 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
1828
1829         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1830                 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
1831
1832         if (IS_GEN_RANGE(i915, 6, 7))
1833                 uncore->flags |= UNCORE_HAS_FIFO;
1834
1835         /* clear out unclaimed reg detection bit */
1836         if (intel_uncore_unclaimed_mmio(uncore))
1837                 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
1838
1839         return 0;
1840
1841 out_mmio_cleanup:
1842         uncore_mmio_cleanup(uncore);
1843
1844         return ret;
1845 }
1846
1847 /*
1848  * We might have detected that some engines are fused off after we initialized
1849  * the forcewake domains. Prune them, to make sure they only reference existing
1850  * engines.
1851  */
1852 void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
1853 {
1854         struct drm_i915_private *i915 = uncore->i915;
1855         enum forcewake_domains fw_domains = uncore->fw_domains;
1856         enum forcewake_domain_id domain_id;
1857         int i;
1858
1859         if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11)
1860                 return;
1861
1862         for (i = 0; i < I915_MAX_VCS; i++) {
1863                 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1864
1865                 if (HAS_ENGINE(i915, _VCS(i)))
1866                         continue;
1867
1868                 if (fw_domains & BIT(domain_id))
1869                         fw_domain_fini(uncore, domain_id);
1870         }
1871
1872         for (i = 0; i < I915_MAX_VECS; i++) {
1873                 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1874
1875                 if (HAS_ENGINE(i915, _VECS(i)))
1876                         continue;
1877
1878                 if (fw_domains & BIT(domain_id))
1879                         fw_domain_fini(uncore, domain_id);
1880         }
1881 }
1882
1883 void intel_uncore_fini_mmio(struct intel_uncore *uncore)
1884 {
1885         if (intel_uncore_has_forcewake(uncore)) {
1886                 iosf_mbi_punit_acquire();
1887                 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
1888                         &uncore->pmic_bus_access_nb);
1889                 intel_uncore_forcewake_reset(uncore);
1890                 intel_uncore_fw_domains_fini(uncore);
1891                 iosf_mbi_punit_release();
1892         }
1893
1894         uncore_mmio_cleanup(uncore);
1895 }
1896
1897 static const struct reg_whitelist {
1898         i915_reg_t offset_ldw;
1899         i915_reg_t offset_udw;
1900         u16 gen_mask;
1901         u8 size;
1902 } reg_read_whitelist[] = { {
1903         .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1904         .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1905         .gen_mask = INTEL_GEN_MASK(4, 12),
1906         .size = 8
1907 } };
1908
1909 int i915_reg_read_ioctl(struct drm_device *dev,
1910                         void *data, struct drm_file *file)
1911 {
1912         struct drm_i915_private *i915 = to_i915(dev);
1913         struct intel_uncore *uncore = &i915->uncore;
1914         struct drm_i915_reg_read *reg = data;
1915         struct reg_whitelist const *entry;
1916         intel_wakeref_t wakeref;
1917         unsigned int flags;
1918         int remain;
1919         int ret = 0;
1920
1921         entry = reg_read_whitelist;
1922         remain = ARRAY_SIZE(reg_read_whitelist);
1923         while (remain) {
1924                 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
1925
1926                 GEM_BUG_ON(!is_power_of_2(entry->size));
1927                 GEM_BUG_ON(entry->size > 8);
1928                 GEM_BUG_ON(entry_offset & (entry->size - 1));
1929
1930                 if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
1931                     entry_offset == (reg->offset & -entry->size))
1932                         break;
1933                 entry++;
1934                 remain--;
1935         }
1936
1937         if (!remain)
1938                 return -EINVAL;
1939
1940         flags = reg->offset & (entry->size - 1);
1941
1942         with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
1943                 if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
1944                         reg->val = intel_uncore_read64_2x32(uncore,
1945                                                             entry->offset_ldw,
1946                                                             entry->offset_udw);
1947                 else if (entry->size == 8 && flags == 0)
1948                         reg->val = intel_uncore_read64(uncore,
1949                                                        entry->offset_ldw);
1950                 else if (entry->size == 4 && flags == 0)
1951                         reg->val = intel_uncore_read(uncore, entry->offset_ldw);
1952                 else if (entry->size == 2 && flags == 0)
1953                         reg->val = intel_uncore_read16(uncore,
1954                                                        entry->offset_ldw);
1955                 else if (entry->size == 1 && flags == 0)
1956                         reg->val = intel_uncore_read8(uncore,
1957                                                       entry->offset_ldw);
1958                 else
1959                         ret = -EINVAL;
1960         }
1961
1962         return ret;
1963 }
1964
1965 /**
1966  * __intel_wait_for_register_fw - wait until register matches expected state
1967  * @uncore: the struct intel_uncore
1968  * @reg: the register to read
1969  * @mask: mask to apply to register value
1970  * @value: expected value
1971  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1972  * @slow_timeout_ms: slow timeout in millisecond
1973  * @out_value: optional placeholder to hold registry value
1974  *
1975  * This routine waits until the target register @reg contains the expected
1976  * @value after applying the @mask, i.e. it waits until ::
1977  *
1978  *     (I915_READ_FW(reg) & mask) == value
1979  *
1980  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
1981  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
1982  * must be not larger than 20,0000 microseconds.
1983  *
1984  * Note that this routine assumes the caller holds forcewake asserted, it is
1985  * not suitable for very long waits. See intel_wait_for_register() if you
1986  * wish to wait without holding forcewake for the duration (i.e. you expect
1987  * the wait to be slow).
1988  *
1989  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
1990  */
1991 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
1992                                  i915_reg_t reg,
1993                                  u32 mask,
1994                                  u32 value,
1995                                  unsigned int fast_timeout_us,
1996                                  unsigned int slow_timeout_ms,
1997                                  u32 *out_value)
1998 {
1999         u32 uninitialized_var(reg_value);
2000 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
2001         int ret;
2002
2003         /* Catch any overuse of this function */
2004         might_sleep_if(slow_timeout_ms);
2005         GEM_BUG_ON(fast_timeout_us > 20000);
2006
2007         ret = -ETIMEDOUT;
2008         if (fast_timeout_us && fast_timeout_us <= 20000)
2009                 ret = _wait_for_atomic(done, fast_timeout_us, 0);
2010         if (ret && slow_timeout_ms)
2011                 ret = wait_for(done, slow_timeout_ms);
2012
2013         if (out_value)
2014                 *out_value = reg_value;
2015
2016         return ret;
2017 #undef done
2018 }
2019
2020 /**
2021  * __intel_wait_for_register - wait until register matches expected state
2022  * @uncore: the struct intel_uncore
2023  * @reg: the register to read
2024  * @mask: mask to apply to register value
2025  * @value: expected value
2026  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2027  * @slow_timeout_ms: slow timeout in millisecond
2028  * @out_value: optional placeholder to hold registry value
2029  *
2030  * This routine waits until the target register @reg contains the expected
2031  * @value after applying the @mask, i.e. it waits until ::
2032  *
2033  *     (I915_READ(reg) & mask) == value
2034  *
2035  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
2036  *
2037  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2038  */
2039 int __intel_wait_for_register(struct intel_uncore *uncore,
2040                               i915_reg_t reg,
2041                               u32 mask,
2042                               u32 value,
2043                               unsigned int fast_timeout_us,
2044                               unsigned int slow_timeout_ms,
2045                               u32 *out_value)
2046 {
2047         unsigned fw =
2048                 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
2049         u32 reg_value;
2050         int ret;
2051
2052         might_sleep_if(slow_timeout_ms);
2053
2054         spin_lock_irq(&uncore->lock);
2055         intel_uncore_forcewake_get__locked(uncore, fw);
2056
2057         ret = __intel_wait_for_register_fw(uncore,
2058                                            reg, mask, value,
2059                                            fast_timeout_us, 0, &reg_value);
2060
2061         intel_uncore_forcewake_put__locked(uncore, fw);
2062         spin_unlock_irq(&uncore->lock);
2063
2064         if (ret && slow_timeout_ms)
2065                 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
2066                                                                        reg),
2067                                  (reg_value & mask) == value,
2068                                  slow_timeout_ms * 1000, 10, 1000);
2069
2070         /* just trace the final value */
2071         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2072
2073         if (out_value)
2074                 *out_value = reg_value;
2075
2076         return ret;
2077 }
2078
2079 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
2080 {
2081         bool ret;
2082
2083         spin_lock_irq(&uncore->debug->lock);
2084         ret = check_for_unclaimed_mmio(uncore);
2085         spin_unlock_irq(&uncore->debug->lock);
2086
2087         return ret;
2088 }
2089
2090 bool
2091 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
2092 {
2093         bool ret = false;
2094
2095         spin_lock_irq(&uncore->debug->lock);
2096
2097         if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
2098                 goto out;
2099
2100         if (unlikely(check_for_unclaimed_mmio(uncore))) {
2101                 if (!i915_modparams.mmio_debug) {
2102                         drm_dbg(&uncore->i915->drm,
2103                                 "Unclaimed register detected, "
2104                                 "enabling oneshot unclaimed register reporting. "
2105                                 "Please use i915.mmio_debug=N for more information.\n");
2106                         i915_modparams.mmio_debug++;
2107                 }
2108                 uncore->debug->unclaimed_mmio_check--;
2109                 ret = true;
2110         }
2111
2112 out:
2113         spin_unlock_irq(&uncore->debug->lock);
2114
2115         return ret;
2116 }
2117
2118 /**
2119  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
2120  *                                  a register
2121  * @uncore: pointer to struct intel_uncore
2122  * @reg: register in question
2123  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
2124  *
2125  * Returns a set of forcewake domains required to be taken with for example
2126  * intel_uncore_forcewake_get for the specified register to be accessible in the
2127  * specified mode (read, write or read/write) with raw mmio accessors.
2128  *
2129  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
2130  * callers to do FIFO management on their own or risk losing writes.
2131  */
2132 enum forcewake_domains
2133 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
2134                                i915_reg_t reg, unsigned int op)
2135 {
2136         enum forcewake_domains fw_domains = 0;
2137
2138         drm_WARN_ON(&uncore->i915->drm, !op);
2139
2140         if (!intel_uncore_has_forcewake(uncore))
2141                 return 0;
2142
2143         if (op & FW_REG_READ)
2144                 fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
2145
2146         if (op & FW_REG_WRITE)
2147                 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
2148
2149         drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains);
2150
2151         return fw_domains;
2152 }
2153
2154 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2155 #include "selftests/mock_uncore.c"
2156 #include "selftests/intel_uncore.c"
2157 #endif