drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_rect.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 static bool
  45 format_is_yuv(uint32_t format)
  46 {
  47         switch (format) {
  48         case DRM_FORMAT_YUYV:
  49         case DRM_FORMAT_UYVY:
  50         case DRM_FORMAT_VYUY:
  51         case DRM_FORMAT_YVYU:
  52                 return true;
  53         default:
  54                 return false;
  55         }
  56 }
  57
  58 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  59                              int usecs)
  60 {
  61         /* paranoia */
  62         if (!adjusted_mode->crtc_htotal)
  63                 return 1;
  64
  65         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  66                             1000 * adjusted_mode->crtc_htotal);
  67 }
  68
  69 /* FIXME: We should instead only take spinlocks once for the entire update
  70  * instead of once per mmio. */
  71 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  72 #define VBLANK_EVASION_TIME_US 250
  73 #else
  74 #define VBLANK_EVASION_TIME_US 100
  75 #endif
  76
  77 /**
  78  * intel_pipe_update_start() - start update of a set of display registers
  79  * @new_crtc_state: the new crtc state
  80  *
  81  * Mark the start of an update to pipe registers that should be updated
  82  * atomically regarding vblank. If the next vblank will happens within
  83  * the next 100 us, this function waits until the vblank passes.
  84  *
  85  * After a successful call to this function, interrupts will be disabled
  86  * until a subsequent call to intel_pipe_update_end(). That is done to
  87  * avoid random delays.
  88  */
  89 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  90 {
  91         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
  92         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  93         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
  94         long timeout = msecs_to_jiffies_timeout(1);
  95         int scanline, min, max, vblank_start;
  96         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  97         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  98                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  99         DEFINE_WAIT(wait);
 100
 101         vblank_start = adjusted_mode->crtc_vblank_start;
 102         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 103                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
 104
 105         /* FIXME needs to be calibrated sensibly */
 106         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
 107                                                       VBLANK_EVASION_TIME_US);
 108         max = vblank_start - 1;
 109
 110         local_irq_disable();
 111
 112         if (min <= 0 || max <= 0)
 113                 return;
 114
 115         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 116                 return;
 117
 118         crtc->debug.min_vbl = min;
 119         crtc->debug.max_vbl = max;
 120         trace_i915_pipe_update_start(crtc);
 121
 122         for (;;) {
 123                 /*
 124                  * prepare_to_wait() has a memory barrier, which guarantees
 125                  * other CPUs can see the task state update by the time we
 126                  * read the scanline.
 127                  */
 128                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 129
 130                 scanline = intel_get_crtc_scanline(crtc);
 131                 if (scanline < min || scanline > max)
 132                         break;
 133
 134                 if (timeout <= 0) {
 135                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 136                                   pipe_name(crtc->pipe));
 137                         break;
 138                 }
 139
 140                 local_irq_enable();
 141
 142                 timeout = schedule_timeout(timeout);
 143
 144                 local_irq_disable();
 145         }
 146
 147         finish_wait(wq, &wait);
 148
 149         drm_crtc_vblank_put(&crtc->base);
 150
 151         /*
 152          * On VLV/CHV DSI the scanline counter would appear to
 153          * increment approx. 1/3 of a scanline before start of vblank.
 154          * The registers still get latched at start of vblank however.
 155          * This means we must not write any registers on the first
 156          * line of vblank (since not the whole line is actually in
 157          * vblank). And unfortunately we can't use the interrupt to
 158          * wait here since it will fire too soon. We could use the
 159          * frame start interrupt instead since it will fire after the
 160          * critical scanline, but that would require more changes
 161          * in the interrupt code. So for now we'll just do the nasty
 162          * thing and poll for the bad scanline to pass us by.
 163          *
 164          * FIXME figure out if BXT+ DSI suffers from this as well
 165          */
 166         while (need_vlv_dsi_wa && scanline == vblank_start)
 167                 scanline = intel_get_crtc_scanline(crtc);
 168
 169         crtc->debug.scanline_start = scanline;
 170         crtc->debug.start_vbl_time = ktime_get();
 171         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 172
 173         trace_i915_pipe_update_vblank_evaded(crtc);
 174 }
 175
 176 /**
 177  * intel_pipe_update_end() - end update of a set of display registers
 178  * @new_crtc_state: the new crtc state
 179  *
 180  * Mark the end of an update started with intel_pipe_update_start(). This
 181  * re-enables interrupts and verifies the update was actually completed
 182  * before a vblank.
 183  */
 184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 185 {
 186         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 187         enum pipe pipe = crtc->pipe;
 188         int scanline_end = intel_get_crtc_scanline(crtc);
 189         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 190         ktime_t end_vbl_time = ktime_get();
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192
 193         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 194
 195         /* We're still in the vblank-evade critical section, this can't race.
 196          * Would be slightly nice to just grab the vblank count and arm the
 197          * event outside of the critical section - the spinlock might spin for a
 198          * while ... */
 199         if (new_crtc_state->base.event) {
 200                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 201
 202                 spin_lock(&crtc->base.dev->event_lock);
 203                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
 204                 spin_unlock(&crtc->base.dev->event_lock);
 205
 206                 new_crtc_state->base.event = NULL;
 207         }
 208
 209         local_irq_enable();
 210
 211         if (intel_vgpu_active(dev_priv))
 212                 return;
 213
 214         if (crtc->debug.start_vbl_count &&
 215             crtc->debug.start_vbl_count != end_vbl_count) {
 216                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 217                           pipe_name(pipe), crtc->debug.start_vbl_count,
 218                           end_vbl_count,
 219                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 220                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 221                           crtc->debug.scanline_start, scanline_end);
 222         }
 223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 224         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 225                  VBLANK_EVASION_TIME_US)
 226                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 227                          pipe_name(pipe),
 228                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 229                          VBLANK_EVASION_TIME_US);
 230 #endif
 231 }
 232
 233 void
 234 skl_update_plane(struct intel_plane *plane,
 235                  const struct intel_crtc_state *crtc_state,
 236                  const struct intel_plane_state *plane_state)
 237 {
 238         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 239         const struct drm_framebuffer *fb = plane_state->base.fb;
 240         enum plane_id plane_id = plane->id;
 241         enum pipe pipe = plane->pipe;
 242         u32 plane_ctl = plane_state->ctl;
 243         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 244         u32 surf_addr = plane_state->main.offset;
 245         unsigned int rotation = plane_state->base.rotation;
 246         u32 stride = skl_plane_stride(fb, 0, rotation);
 247         u32 aux_stride = skl_plane_stride(fb, 1, rotation);
 248         int crtc_x = plane_state->base.dst.x1;
 249         int crtc_y = plane_state->base.dst.y1;
 250         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 251         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 252         uint32_t x = plane_state->main.x;
 253         uint32_t y = plane_state->main.y;
 254         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 255         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 256         unsigned long irqflags;
 257
 258         /* Sizes are 0 based */
 259         src_w--;
 260         src_h--;
 261         crtc_w--;
 262         crtc_h--;
 263
 264         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 265
 266         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 267                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 268                               plane_state->color_ctl);
 269         if (key->flags) {
 270                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 271                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 272                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 273         }
 274
 275         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 276         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 277         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 278         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 279                       (plane_state->aux.offset - surf_addr) | aux_stride);
 280         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 281                       (plane_state->aux.y << 16) | plane_state->aux.x);
 282
 283         /* program plane scaler */
 284         if (plane_state->scaler_id >= 0) {
 285                 int scaler_id = plane_state->scaler_id;
 286                 const struct intel_scaler *scaler;
 287
 288                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 289
 290                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 291                               PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 292                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 293                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 294                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 295                               ((crtc_w + 1) << 16)|(crtc_h + 1));
 296
 297                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 298         } else {
 299                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 300         }
 301
 302         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 303         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 304                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 305         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 306
 307         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 308 }
 309
 310 void
 311 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 312 {
 313         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 314         enum plane_id plane_id = plane->id;
 315         enum pipe pipe = plane->pipe;
 316         unsigned long irqflags;
 317
 318         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 319
 320         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 321
 322         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 323         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 324
 325         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 326 }
 327
 328 bool
 329 skl_plane_get_hw_state(struct intel_plane *plane)
 330 {
 331         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 332         enum intel_display_power_domain power_domain;
 333         enum plane_id plane_id = plane->id;
 334         enum pipe pipe = plane->pipe;
 335         bool ret;
 336
 337         power_domain = POWER_DOMAIN_PIPE(pipe);
 338         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 339                 return false;
 340
 341         ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
 342
 343         intel_display_power_put(dev_priv, power_domain);
 344
 345         return ret;
 346 }
 347
 348 static void
 349 chv_update_csc(struct intel_plane *plane, uint32_t format)
 350 {
 351         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 352         enum plane_id plane_id = plane->id;
 353
 354         /* Seems RGB data bypasses the CSC always */
 355         if (!format_is_yuv(format))
 356                 return;
 357
 358         /*
 359          * BT.601 limited range YCbCr -> full range RGB
 360          *
 361          * |r|   | 6537 4769     0|   |cr  |
 362          * |g| = |-3330 4769 -1605| x |y-64|
 363          * |b|   |    0 4769  8263|   |cb  |
 364          *
 365          * Cb and Cr apparently come in as signed already, so no
 366          * need for any offset. For Y we need to remove the offset.
 367          */
 368         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 369         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 370         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 371
 372         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
 373         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
 374         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
 375         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
 376         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
 377
 378         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 379         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 380         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 381
 382         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 383         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 384         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 385 }
 386
 387 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 388                           const struct intel_plane_state *plane_state)
 389 {
 390         const struct drm_framebuffer *fb = plane_state->base.fb;
 391         unsigned int rotation = plane_state->base.rotation;
 392         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 393         u32 sprctl;
 394
 395         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 396
 397         switch (fb->format->format) {
 398         case DRM_FORMAT_YUYV:
 399                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 400                 break;
 401         case DRM_FORMAT_YVYU:
 402                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 403                 break;
 404         case DRM_FORMAT_UYVY:
 405                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 406                 break;
 407         case DRM_FORMAT_VYUY:
 408                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 409                 break;
 410         case DRM_FORMAT_RGB565:
 411                 sprctl |= SP_FORMAT_BGR565;
 412                 break;
 413         case DRM_FORMAT_XRGB8888:
 414                 sprctl |= SP_FORMAT_BGRX8888;
 415                 break;
 416         case DRM_FORMAT_ARGB8888:
 417                 sprctl |= SP_FORMAT_BGRA8888;
 418                 break;
 419         case DRM_FORMAT_XBGR2101010:
 420                 sprctl |= SP_FORMAT_RGBX1010102;
 421                 break;
 422         case DRM_FORMAT_ABGR2101010:
 423                 sprctl |= SP_FORMAT_RGBA1010102;
 424                 break;
 425         case DRM_FORMAT_XBGR8888:
 426                 sprctl |= SP_FORMAT_RGBX8888;
 427                 break;
 428         case DRM_FORMAT_ABGR8888:
 429                 sprctl |= SP_FORMAT_RGBA8888;
 430                 break;
 431         default:
 432                 MISSING_CASE(fb->format->format);
 433                 return 0;
 434         }
 435
 436         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 437                 sprctl |= SP_TILED;
 438
 439         if (rotation & DRM_MODE_ROTATE_180)
 440                 sprctl |= SP_ROTATE_180;
 441
 442         if (rotation & DRM_MODE_REFLECT_X)
 443                 sprctl |= SP_MIRROR;
 444
 445         if (key->flags & I915_SET_COLORKEY_SOURCE)
 446                 sprctl |= SP_SOURCE_KEY;
 447
 448         return sprctl;
 449 }
 450
 451 static void
 452 vlv_update_plane(struct intel_plane *plane,
 453                  const struct intel_crtc_state *crtc_state,
 454                  const struct intel_plane_state *plane_state)
 455 {
 456         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 457         const struct drm_framebuffer *fb = plane_state->base.fb;
 458         enum pipe pipe = plane->pipe;
 459         enum plane_id plane_id = plane->id;
 460         u32 sprctl = plane_state->ctl;
 461         u32 sprsurf_offset = plane_state->main.offset;
 462         u32 linear_offset;
 463         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 464         int crtc_x = plane_state->base.dst.x1;
 465         int crtc_y = plane_state->base.dst.y1;
 466         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 467         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 468         uint32_t x = plane_state->main.x;
 469         uint32_t y = plane_state->main.y;
 470         unsigned long irqflags;
 471
 472         /* Sizes are 0 based */
 473         crtc_w--;
 474         crtc_h--;
 475
 476         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 477
 478         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 479
 480         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 481                 chv_update_csc(plane, fb->format->format);
 482
 483         if (key->flags) {
 484                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 485                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 486                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 487         }
 488         I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 489         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 490
 491         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 492                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 493         else
 494                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 495
 496         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 497
 498         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 499         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 500         I915_WRITE_FW(SPSURF(pipe, plane_id),
 501                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 502         POSTING_READ_FW(SPSURF(pipe, plane_id));
 503
 504         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 505 }
 506
 507 static void
 508 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 509 {
 510         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 511         enum pipe pipe = plane->pipe;
 512         enum plane_id plane_id = plane->id;
 513         unsigned long irqflags;
 514
 515         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 516
 517         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 518
 519         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 520         POSTING_READ_FW(SPSURF(pipe, plane_id));
 521
 522         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 523 }
 524
 525 static bool
 526 vlv_plane_get_hw_state(struct intel_plane *plane)
 527 {
 528         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 529         enum intel_display_power_domain power_domain;
 530         enum plane_id plane_id = plane->id;
 531         enum pipe pipe = plane->pipe;
 532         bool ret;
 533
 534         power_domain = POWER_DOMAIN_PIPE(pipe);
 535         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 536                 return false;
 537
 538         ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
 539
 540         intel_display_power_put(dev_priv, power_domain);
 541
 542         return ret;
 543 }
 544
 545 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 546                           const struct intel_plane_state *plane_state)
 547 {
 548         struct drm_i915_private *dev_priv =
 549                 to_i915(plane_state->base.plane->dev);
 550         const struct drm_framebuffer *fb = plane_state->base.fb;
 551         unsigned int rotation = plane_state->base.rotation;
 552         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 553         u32 sprctl;
 554
 555         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 556
 557         if (IS_IVYBRIDGE(dev_priv))
 558                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 559
 560         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 561                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 562
 563         switch (fb->format->format) {
 564         case DRM_FORMAT_XBGR8888:
 565                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 566                 break;
 567         case DRM_FORMAT_XRGB8888:
 568                 sprctl |= SPRITE_FORMAT_RGBX888;
 569                 break;
 570         case DRM_FORMAT_YUYV:
 571                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 572                 break;
 573         case DRM_FORMAT_YVYU:
 574                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 575                 break;
 576         case DRM_FORMAT_UYVY:
 577                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 578                 break;
 579         case DRM_FORMAT_VYUY:
 580                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 581                 break;
 582         default:
 583                 MISSING_CASE(fb->format->format);
 584                 return 0;
 585         }
 586
 587         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 588                 sprctl |= SPRITE_TILED;
 589
 590         if (rotation & DRM_MODE_ROTATE_180)
 591                 sprctl |= SPRITE_ROTATE_180;
 592
 593         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 594                 sprctl |= SPRITE_DEST_KEY;
 595         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 596                 sprctl |= SPRITE_SOURCE_KEY;
 597
 598         return sprctl;
 599 }
 600
 601 static void
 602 ivb_update_plane(struct intel_plane *plane,
 603                  const struct intel_crtc_state *crtc_state,
 604                  const struct intel_plane_state *plane_state)
 605 {
 606         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 607         const struct drm_framebuffer *fb = plane_state->base.fb;
 608         enum pipe pipe = plane->pipe;
 609         u32 sprctl = plane_state->ctl, sprscale = 0;
 610         u32 sprsurf_offset = plane_state->main.offset;
 611         u32 linear_offset;
 612         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 613         int crtc_x = plane_state->base.dst.x1;
 614         int crtc_y = plane_state->base.dst.y1;
 615         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 616         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 617         uint32_t x = plane_state->main.x;
 618         uint32_t y = plane_state->main.y;
 619         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 620         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 621         unsigned long irqflags;
 622
 623         /* Sizes are 0 based */
 624         src_w--;
 625         src_h--;
 626         crtc_w--;
 627         crtc_h--;
 628
 629         if (crtc_w != src_w || crtc_h != src_h)
 630                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 631
 632         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 633
 634         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 635
 636         if (key->flags) {
 637                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 638                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 639                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 640         }
 641
 642         I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
 643         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 644
 645         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 646          * register */
 647         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 648                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 649         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 650                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 651         else
 652                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 653
 654         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 655         if (plane->can_scale)
 656                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 657         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 658         I915_WRITE_FW(SPRSURF(pipe),
 659                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 660         POSTING_READ_FW(SPRSURF(pipe));
 661
 662         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 663 }
 664
 665 static void
 666 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 667 {
 668         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 669         enum pipe pipe = plane->pipe;
 670         unsigned long irqflags;
 671
 672         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 673
 674         I915_WRITE_FW(SPRCTL(pipe), 0);
 675         /* Can't leave the scaler enabled... */
 676         if (plane->can_scale)
 677                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 678
 679         I915_WRITE_FW(SPRSURF(pipe), 0);
 680         POSTING_READ_FW(SPRSURF(pipe));
 681
 682         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 683 }
 684
 685 static bool
 686 ivb_plane_get_hw_state(struct intel_plane *plane)
 687 {
 688         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 689         enum intel_display_power_domain power_domain;
 690         enum pipe pipe = plane->pipe;
 691         bool ret;
 692
 693         power_domain = POWER_DOMAIN_PIPE(pipe);
 694         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 695                 return false;
 696
 697         ret =  I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
 698
 699         intel_display_power_put(dev_priv, power_domain);
 700
 701         return ret;
 702 }
 703
 704 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 705                           const struct intel_plane_state *plane_state)
 706 {
 707         struct drm_i915_private *dev_priv =
 708                 to_i915(plane_state->base.plane->dev);
 709         const struct drm_framebuffer *fb = plane_state->base.fb;
 710         unsigned int rotation = plane_state->base.rotation;
 711         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 712         u32 dvscntr;
 713
 714         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 715
 716         if (IS_GEN6(dev_priv))
 717                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 718
 719         switch (fb->format->format) {
 720         case DRM_FORMAT_XBGR8888:
 721                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 722                 break;
 723         case DRM_FORMAT_XRGB8888:
 724                 dvscntr |= DVS_FORMAT_RGBX888;
 725                 break;
 726         case DRM_FORMAT_YUYV:
 727                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 728                 break;
 729         case DRM_FORMAT_YVYU:
 730                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 731                 break;
 732         case DRM_FORMAT_UYVY:
 733                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 734                 break;
 735         case DRM_FORMAT_VYUY:
 736                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 737                 break;
 738         default:
 739                 MISSING_CASE(fb->format->format);
 740                 return 0;
 741         }
 742
 743         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 744                 dvscntr |= DVS_TILED;
 745
 746         if (rotation & DRM_MODE_ROTATE_180)
 747                 dvscntr |= DVS_ROTATE_180;
 748
 749         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 750                 dvscntr |= DVS_DEST_KEY;
 751         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 752                 dvscntr |= DVS_SOURCE_KEY;
 753
 754         return dvscntr;
 755 }
 756
 757 static void
 758 g4x_update_plane(struct intel_plane *plane,
 759                  const struct intel_crtc_state *crtc_state,
 760                  const struct intel_plane_state *plane_state)
 761 {
 762         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 763         const struct drm_framebuffer *fb = plane_state->base.fb;
 764         enum pipe pipe = plane->pipe;
 765         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 766         u32 dvssurf_offset = plane_state->main.offset;
 767         u32 linear_offset;
 768         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 769         int crtc_x = plane_state->base.dst.x1;
 770         int crtc_y = plane_state->base.dst.y1;
 771         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 772         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 773         uint32_t x = plane_state->main.x;
 774         uint32_t y = plane_state->main.y;
 775         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 776         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 777         unsigned long irqflags;
 778
 779         /* Sizes are 0 based */
 780         src_w--;
 781         src_h--;
 782         crtc_w--;
 783         crtc_h--;
 784
 785         if (crtc_w != src_w || crtc_h != src_h)
 786                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 787
 788         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 789
 790         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 791
 792         if (key->flags) {
 793                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 794                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 795                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 796         }
 797
 798         I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
 799         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 800
 801         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 802                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
 803         else
 804                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
 805
 806         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 807         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
 808         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
 809         I915_WRITE_FW(DVSSURF(pipe),
 810                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 811         POSTING_READ_FW(DVSSURF(pipe));
 812
 813         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 814 }
 815
 816 static void
 817 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 818 {
 819         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 820         enum pipe pipe = plane->pipe;
 821         unsigned long irqflags;
 822
 823         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 824
 825         I915_WRITE_FW(DVSCNTR(pipe), 0);
 826         /* Disable the scaler */
 827         I915_WRITE_FW(DVSSCALE(pipe), 0);
 828
 829         I915_WRITE_FW(DVSSURF(pipe), 0);
 830         POSTING_READ_FW(DVSSURF(pipe));
 831
 832         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 833 }
 834
 835 static bool
 836 g4x_plane_get_hw_state(struct intel_plane *plane)
 837 {
 838         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 839         enum intel_display_power_domain power_domain;
 840         enum pipe pipe = plane->pipe;
 841         bool ret;
 842
 843         power_domain = POWER_DOMAIN_PIPE(pipe);
 844         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 845                 return false;
 846
 847         ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
 848
 849         intel_display_power_put(dev_priv, power_domain);
 850
 851         return ret;
 852 }
 853
 854 static int
 855 intel_check_sprite_plane(struct intel_plane *plane,
 856                          struct intel_crtc_state *crtc_state,
 857                          struct intel_plane_state *state)
 858 {
 859         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 860         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 861         struct drm_framebuffer *fb = state->base.fb;
 862         int crtc_x, crtc_y;
 863         unsigned int crtc_w, crtc_h;
 864         uint32_t src_x, src_y, src_w, src_h;
 865         struct drm_rect *src = &state->base.src;
 866         struct drm_rect *dst = &state->base.dst;
 867         struct drm_rect clip = {};
 868         int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
 869         int hscale, vscale;
 870         int max_scale, min_scale;
 871         bool can_scale;
 872         int ret;
 873
 874         *src = drm_plane_state_src(&state->base);
 875         *dst = drm_plane_state_dest(&state->base);
 876
 877         if (!fb) {
 878                 state->base.visible = false;
 879                 return 0;
 880         }
 881
 882         /* Don't modify another pipe's plane */
 883         if (plane->pipe != crtc->pipe) {
 884                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 885                 return -EINVAL;
 886         }
 887
 888         /* FIXME check all gen limits */
 889         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > max_stride) {
 890                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 891                 return -EINVAL;
 892         }
 893
 894         /* setup can_scale, min_scale, max_scale */
 895         if (INTEL_GEN(dev_priv) >= 9) {
 896                 /* use scaler when colorkey is not required */
 897                 if (!state->ckey.flags) {
 898                         can_scale = 1;
 899                         min_scale = 1;
 900                         max_scale = skl_max_scale(crtc, crtc_state);
 901                 } else {
 902                         can_scale = 0;
 903                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 904                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 905                 }
 906         } else {
 907                 can_scale = plane->can_scale;
 908                 max_scale = plane->max_downscale << 16;
 909                 min_scale = plane->can_scale ? 1 : (1 << 16);
 910         }
 911
 912         /*
 913          * FIXME the following code does a bunch of fuzzy adjustments to the
 914          * coordinates and sizes. We probably need some way to decide whether
 915          * more strict checking should be done instead.
 916          */
 917         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 918                         state->base.rotation);
 919
 920         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 921         BUG_ON(hscale < 0);
 922
 923         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 924         BUG_ON(vscale < 0);
 925
 926         if (crtc_state->base.enable)
 927                 drm_mode_get_hv_timing(&crtc_state->base.mode,
 928                                        &clip.x2, &clip.y2);
 929
 930         state->base.visible = drm_rect_clip_scaled(src, dst, &clip, hscale, vscale);
 931
 932         crtc_x = dst->x1;
 933         crtc_y = dst->y1;
 934         crtc_w = drm_rect_width(dst);
 935         crtc_h = drm_rect_height(dst);
 936
 937         if (state->base.visible) {
 938                 /* check again in case clipping clamped the results */
 939                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 940                 if (hscale < 0) {
 941                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 942                         drm_rect_debug_print("src: ", src, true);
 943                         drm_rect_debug_print("dst: ", dst, false);
 944
 945                         return hscale;
 946                 }
 947
 948                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 949                 if (vscale < 0) {
 950                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 951                         drm_rect_debug_print("src: ", src, true);
 952                         drm_rect_debug_print("dst: ", dst, false);
 953
 954                         return vscale;
 955                 }
 956
 957                 /* Make the source viewport size an exact multiple of the scaling factors. */
 958                 drm_rect_adjust_size(src,
 959                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 960                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 961
 962                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 963                                     state->base.rotation);
 964
 965                 /* sanity check to make sure the src viewport wasn't enlarged */
 966                 WARN_ON(src->x1 < (int) state->base.src_x ||
 967                         src->y1 < (int) state->base.src_y ||
 968                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 969                         src->y2 > (int) state->base.src_y + state->base.src_h);
 970
 971                 /*
 972                  * Hardware doesn't handle subpixel coordinates.
 973                  * Adjust to (macro)pixel boundary, but be careful not to
 974                  * increase the source viewport size, because that could
 975                  * push the downscaling factor out of bounds.
 976                  */
 977                 src_x = src->x1 >> 16;
 978                 src_w = drm_rect_width(src) >> 16;
 979                 src_y = src->y1 >> 16;
 980                 src_h = drm_rect_height(src) >> 16;
 981
 982                 if (format_is_yuv(fb->format->format)) {
 983                         src_x &= ~1;
 984                         src_w &= ~1;
 985
 986                         /*
 987                          * Must keep src and dst the
 988                          * same if we can't scale.
 989                          */
 990                         if (!can_scale)
 991                                 crtc_w &= ~1;
 992
 993                         if (crtc_w == 0)
 994                                 state->base.visible = false;
 995                 }
 996         }
 997
 998         /* Check size restrictions when scaling */
 999         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
1000                 unsigned int width_bytes;
1001                 int cpp = fb->format->cpp[0];
1002
1003                 WARN_ON(!can_scale);
1004
1005                 /* FIXME interlacing min height is 6 */
1006
1007                 if (crtc_w < 3 || crtc_h < 3)
1008                         state->base.visible = false;
1009
1010                 if (src_w < 3 || src_h < 3)
1011                         state->base.visible = false;
1012
1013                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1014
1015                 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
1016                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
1017                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1018                         return -EINVAL;
1019                 }
1020         }
1021
1022         if (state->base.visible) {
1023                 src->x1 = src_x << 16;
1024                 src->x2 = (src_x + src_w) << 16;
1025                 src->y1 = src_y << 16;
1026                 src->y2 = (src_y + src_h) << 16;
1027         }
1028
1029         dst->x1 = crtc_x;
1030         dst->x2 = crtc_x + crtc_w;
1031         dst->y1 = crtc_y;
1032         dst->y2 = crtc_y + crtc_h;
1033
1034         if (INTEL_GEN(dev_priv) >= 9) {
1035                 ret = skl_check_plane_surface(crtc_state, state);
1036                 if (ret)
1037                         return ret;
1038
1039                 state->ctl = skl_plane_ctl(crtc_state, state);
1040         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1041                 ret = i9xx_check_plane_surface(state);
1042                 if (ret)
1043                         return ret;
1044
1045                 state->ctl = vlv_sprite_ctl(crtc_state, state);
1046         } else if (INTEL_GEN(dev_priv) >= 7) {
1047                 ret = i9xx_check_plane_surface(state);
1048                 if (ret)
1049                         return ret;
1050
1051                 state->ctl = ivb_sprite_ctl(crtc_state, state);
1052         } else {
1053                 ret = i9xx_check_plane_surface(state);
1054                 if (ret)
1055                         return ret;
1056
1057                 state->ctl = g4x_sprite_ctl(crtc_state, state);
1058         }
1059
1060         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1061                 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
1062
1063         return 0;
1064 }
1065
1066 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1067                                     struct drm_file *file_priv)
1068 {
1069         struct drm_i915_private *dev_priv = to_i915(dev);
1070         struct drm_intel_sprite_colorkey *set = data;
1071         struct drm_plane *plane;
1072         struct drm_plane_state *plane_state;
1073         struct drm_atomic_state *state;
1074         struct drm_modeset_acquire_ctx ctx;
1075         int ret = 0;
1076
1077         /* ignore the pointless "none" flag */
1078         set->flags &= ~I915_SET_COLORKEY_NONE;
1079
1080         if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1081                 return -EINVAL;
1082
1083         /* Make sure we don't try to enable both src & dest simultaneously */
1084         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1085                 return -EINVAL;
1086
1087         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1088             set->flags & I915_SET_COLORKEY_DESTINATION)
1089                 return -EINVAL;
1090
1091         plane = drm_plane_find(dev, file_priv, set->plane_id);
1092         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1093                 return -ENOENT;
1094
1095         drm_modeset_acquire_init(&ctx, 0);
1096
1097         state = drm_atomic_state_alloc(plane->dev);
1098         if (!state) {
1099                 ret = -ENOMEM;
1100                 goto out;
1101         }
1102         state->acquire_ctx = &ctx;
1103
1104         while (1) {
1105                 plane_state = drm_atomic_get_plane_state(state, plane);
1106                 ret = PTR_ERR_OR_ZERO(plane_state);
1107                 if (!ret) {
1108                         to_intel_plane_state(plane_state)->ckey = *set;
1109                         ret = drm_atomic_commit(state);
1110                 }
1111
1112                 if (ret != -EDEADLK)
1113                         break;
1114
1115                 drm_atomic_state_clear(state);
1116                 drm_modeset_backoff(&ctx);
1117         }
1118
1119         drm_atomic_state_put(state);
1120 out:
1121         drm_modeset_drop_locks(&ctx);
1122         drm_modeset_acquire_fini(&ctx);
1123         return ret;
1124 }
1125
1126 static const uint32_t g4x_plane_formats[] = {
1127         DRM_FORMAT_XRGB8888,
1128         DRM_FORMAT_YUYV,
1129         DRM_FORMAT_YVYU,
1130         DRM_FORMAT_UYVY,
1131         DRM_FORMAT_VYUY,
1132 };
1133
1134 static const uint64_t i9xx_plane_format_modifiers[] = {
1135         I915_FORMAT_MOD_X_TILED,
1136         DRM_FORMAT_MOD_LINEAR,
1137         DRM_FORMAT_MOD_INVALID
1138 };
1139
1140 static const uint32_t snb_plane_formats[] = {
1141         DRM_FORMAT_XBGR8888,
1142         DRM_FORMAT_XRGB8888,
1143         DRM_FORMAT_YUYV,
1144         DRM_FORMAT_YVYU,
1145         DRM_FORMAT_UYVY,
1146         DRM_FORMAT_VYUY,
1147 };
1148
1149 static const uint32_t vlv_plane_formats[] = {
1150         DRM_FORMAT_RGB565,
1151         DRM_FORMAT_ABGR8888,
1152         DRM_FORMAT_ARGB8888,
1153         DRM_FORMAT_XBGR8888,
1154         DRM_FORMAT_XRGB8888,
1155         DRM_FORMAT_XBGR2101010,
1156         DRM_FORMAT_ABGR2101010,
1157         DRM_FORMAT_YUYV,
1158         DRM_FORMAT_YVYU,
1159         DRM_FORMAT_UYVY,
1160         DRM_FORMAT_VYUY,
1161 };
1162
1163 static uint32_t skl_plane_formats[] = {
1164         DRM_FORMAT_RGB565,
1165         DRM_FORMAT_ABGR8888,
1166         DRM_FORMAT_ARGB8888,
1167         DRM_FORMAT_XBGR8888,
1168         DRM_FORMAT_XRGB8888,
1169         DRM_FORMAT_YUYV,
1170         DRM_FORMAT_YVYU,
1171         DRM_FORMAT_UYVY,
1172         DRM_FORMAT_VYUY,
1173 };
1174
1175 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1176         I915_FORMAT_MOD_Yf_TILED,
1177         I915_FORMAT_MOD_Y_TILED,
1178         I915_FORMAT_MOD_X_TILED,
1179         DRM_FORMAT_MOD_LINEAR,
1180         DRM_FORMAT_MOD_INVALID
1181 };
1182
1183 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1184         I915_FORMAT_MOD_Yf_TILED_CCS,
1185         I915_FORMAT_MOD_Y_TILED_CCS,
1186         I915_FORMAT_MOD_Yf_TILED,
1187         I915_FORMAT_MOD_Y_TILED,
1188         I915_FORMAT_MOD_X_TILED,
1189         DRM_FORMAT_MOD_LINEAR,
1190         DRM_FORMAT_MOD_INVALID
1191 };
1192
1193 static bool g4x_mod_supported(uint32_t format, uint64_t modifier)
1194 {
1195         switch (format) {
1196         case DRM_FORMAT_XRGB8888:
1197         case DRM_FORMAT_YUYV:
1198         case DRM_FORMAT_YVYU:
1199         case DRM_FORMAT_UYVY:
1200         case DRM_FORMAT_VYUY:
1201                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1202                     modifier == I915_FORMAT_MOD_X_TILED)
1203                         return true;
1204                 /* fall through */
1205         default:
1206                 return false;
1207         }
1208 }
1209
1210 static bool snb_mod_supported(uint32_t format, uint64_t modifier)
1211 {
1212         switch (format) {
1213         case DRM_FORMAT_XRGB8888:
1214         case DRM_FORMAT_XBGR8888:
1215         case DRM_FORMAT_YUYV:
1216         case DRM_FORMAT_YVYU:
1217         case DRM_FORMAT_UYVY:
1218         case DRM_FORMAT_VYUY:
1219                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1220                     modifier == I915_FORMAT_MOD_X_TILED)
1221                         return true;
1222                 /* fall through */
1223         default:
1224                 return false;
1225         }
1226 }
1227
1228 static bool vlv_mod_supported(uint32_t format, uint64_t modifier)
1229 {
1230         switch (format) {
1231         case DRM_FORMAT_RGB565:
1232         case DRM_FORMAT_ABGR8888:
1233         case DRM_FORMAT_ARGB8888:
1234         case DRM_FORMAT_XBGR8888:
1235         case DRM_FORMAT_XRGB8888:
1236         case DRM_FORMAT_XBGR2101010:
1237         case DRM_FORMAT_ABGR2101010:
1238         case DRM_FORMAT_YUYV:
1239         case DRM_FORMAT_YVYU:
1240         case DRM_FORMAT_UYVY:
1241         case DRM_FORMAT_VYUY:
1242                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1243                     modifier == I915_FORMAT_MOD_X_TILED)
1244                         return true;
1245                 /* fall through */
1246         default:
1247                 return false;
1248         }
1249 }
1250
1251 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
1252 {
1253         switch (format) {
1254         case DRM_FORMAT_XRGB8888:
1255         case DRM_FORMAT_XBGR8888:
1256         case DRM_FORMAT_ARGB8888:
1257         case DRM_FORMAT_ABGR8888:
1258                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
1259                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
1260                         return true;
1261                 /* fall through */
1262         case DRM_FORMAT_RGB565:
1263         case DRM_FORMAT_XRGB2101010:
1264         case DRM_FORMAT_XBGR2101010:
1265         case DRM_FORMAT_YUYV:
1266         case DRM_FORMAT_YVYU:
1267         case DRM_FORMAT_UYVY:
1268         case DRM_FORMAT_VYUY:
1269                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1270                         return true;
1271                 /* fall through */
1272         case DRM_FORMAT_C8:
1273                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1274                     modifier == I915_FORMAT_MOD_X_TILED ||
1275                     modifier == I915_FORMAT_MOD_Y_TILED)
1276                         return true;
1277                 /* fall through */
1278         default:
1279                 return false;
1280         }
1281 }
1282
1283 static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1284                                                     uint32_t format,
1285                                                     uint64_t modifier)
1286 {
1287         struct drm_i915_private *dev_priv = to_i915(plane->dev);
1288
1289         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1290                 return false;
1291
1292         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1293             modifier != DRM_FORMAT_MOD_LINEAR)
1294                 return false;
1295
1296         if (INTEL_GEN(dev_priv) >= 9)
1297                 return skl_mod_supported(format, modifier);
1298         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1299                 return vlv_mod_supported(format, modifier);
1300         else if (INTEL_GEN(dev_priv) >= 6)
1301                 return snb_mod_supported(format, modifier);
1302         else
1303                 return g4x_mod_supported(format, modifier);
1304 }
1305
1306 static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1307         .update_plane = drm_atomic_helper_update_plane,
1308         .disable_plane = drm_atomic_helper_disable_plane,
1309         .destroy = intel_plane_destroy,
1310         .atomic_get_property = intel_plane_atomic_get_property,
1311         .atomic_set_property = intel_plane_atomic_set_property,
1312         .atomic_duplicate_state = intel_plane_duplicate_state,
1313         .atomic_destroy_state = intel_plane_destroy_state,
1314         .format_mod_supported = intel_sprite_plane_format_mod_supported,
1315 };
1316
1317 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1318                        enum pipe pipe, enum plane_id plane_id)
1319 {
1320         if (plane_id == PLANE_CURSOR)
1321                 return false;
1322
1323         if (INTEL_GEN(dev_priv) >= 10)
1324                 return true;
1325
1326         if (IS_GEMINILAKE(dev_priv))
1327                 return pipe != PIPE_C;
1328
1329         return pipe != PIPE_C &&
1330                 (plane_id == PLANE_PRIMARY ||
1331                  plane_id == PLANE_SPRITE0);
1332 }
1333
1334 struct intel_plane *
1335 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1336                           enum pipe pipe, int plane)
1337 {
1338         struct intel_plane *intel_plane = NULL;
1339         struct intel_plane_state *state = NULL;
1340         unsigned long possible_crtcs;
1341         const uint32_t *plane_formats;
1342         const uint64_t *modifiers;
1343         unsigned int supported_rotations;
1344         int num_plane_formats;
1345         int ret;
1346
1347         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1348         if (!intel_plane) {
1349                 ret = -ENOMEM;
1350                 goto fail;
1351         }
1352
1353         state = intel_create_plane_state(&intel_plane->base);
1354         if (!state) {
1355                 ret = -ENOMEM;
1356                 goto fail;
1357         }
1358         intel_plane->base.state = &state->base;
1359
1360         if (INTEL_GEN(dev_priv) >= 9) {
1361                 intel_plane->can_scale = true;
1362                 state->scaler_id = -1;
1363
1364                 intel_plane->update_plane = skl_update_plane;
1365                 intel_plane->disable_plane = skl_disable_plane;
1366                 intel_plane->get_hw_state = skl_plane_get_hw_state;
1367
1368                 plane_formats = skl_plane_formats;
1369                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1370
1371                 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
1372                         modifiers = skl_plane_format_modifiers_ccs;
1373                 else
1374                         modifiers = skl_plane_format_modifiers_noccs;
1375         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1376                 intel_plane->can_scale = false;
1377                 intel_plane->max_downscale = 1;
1378
1379                 intel_plane->update_plane = vlv_update_plane;
1380                 intel_plane->disable_plane = vlv_disable_plane;
1381                 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1382
1383                 plane_formats = vlv_plane_formats;
1384                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1385                 modifiers = i9xx_plane_format_modifiers;
1386         } else if (INTEL_GEN(dev_priv) >= 7) {
1387                 if (IS_IVYBRIDGE(dev_priv)) {
1388                         intel_plane->can_scale = true;
1389                         intel_plane->max_downscale = 2;
1390                 } else {
1391                         intel_plane->can_scale = false;
1392                         intel_plane->max_downscale = 1;
1393                 }
1394
1395                 intel_plane->update_plane = ivb_update_plane;
1396                 intel_plane->disable_plane = ivb_disable_plane;
1397                 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1398
1399                 plane_formats = snb_plane_formats;
1400                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1401                 modifiers = i9xx_plane_format_modifiers;
1402         } else {
1403                 intel_plane->can_scale = true;
1404                 intel_plane->max_downscale = 16;
1405
1406                 intel_plane->update_plane = g4x_update_plane;
1407                 intel_plane->disable_plane = g4x_disable_plane;
1408                 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1409
1410                 modifiers = i9xx_plane_format_modifiers;
1411                 if (IS_GEN6(dev_priv)) {
1412                         plane_formats = snb_plane_formats;
1413                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1414                 } else {
1415                         plane_formats = g4x_plane_formats;
1416                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1417                 }
1418         }
1419
1420         if (INTEL_GEN(dev_priv) >= 9) {
1421                 supported_rotations =
1422                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1423                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1424         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1425                 supported_rotations =
1426                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1427                         DRM_MODE_REFLECT_X;
1428         } else {
1429                 supported_rotations =
1430                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1431         }
1432
1433         intel_plane->pipe = pipe;
1434         intel_plane->i9xx_plane = plane;
1435         intel_plane->id = PLANE_SPRITE0 + plane;
1436         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
1437         intel_plane->check_plane = intel_check_sprite_plane;
1438
1439         possible_crtcs = (1 << pipe);
1440
1441         if (INTEL_GEN(dev_priv) >= 9)
1442                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1443                                                possible_crtcs, &intel_sprite_plane_funcs,
1444                                                plane_formats, num_plane_formats,
1445                                                modifiers,
1446                                                DRM_PLANE_TYPE_OVERLAY,
1447                                                "plane %d%c", plane + 2, pipe_name(pipe));
1448         else
1449                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1450                                                possible_crtcs, &intel_sprite_plane_funcs,
1451                                                plane_formats, num_plane_formats,
1452                                                modifiers,
1453                                                DRM_PLANE_TYPE_OVERLAY,
1454                                                "sprite %c", sprite_name(pipe, plane));
1455         if (ret)
1456                 goto fail;
1457
1458         drm_plane_create_rotation_property(&intel_plane->base,
1459                                            DRM_MODE_ROTATE_0,
1460                                            supported_rotations);
1461
1462         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1463
1464         return intel_plane;
1465
1466 fail:
1467         kfree(state);
1468         kfree(intel_plane);
1469
1470         return ERR_PTR(ret);
1471 }