2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <asm/iosf_mbi.h>
28 #include "intel_sideband.h"
31 * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
32 * VLV_VLV2_PUNIT_HAS_0.8.docx
35 /* Standard MMIO read, non-posted */
36 #define SB_MRD_NP 0x00
37 /* Standard MMIO write, non-posted */
38 #define SB_MWR_NP 0x01
39 /* Private register read, double-word addressing, non-posted */
40 #define SB_CRRDDA_NP 0x06
41 /* Private register write, double-word addressing, non-posted */
42 #define SB_CRWRDA_NP 0x07
44 static void ping(void *info)
48 static void __vlv_punit_get(struct drm_i915_private *i915)
50 iosf_mbi_punit_acquire();
53 * Prevent the cpu from sleeping while we use this sideband, otherwise
54 * the punit may cause a machine hang. The issue appears to be isolated
55 * with changing the power state of the CPU package while changing
56 * the power state via the punit, and we have only observed it
57 * reliably on 4-core Baytail systems suggesting the issue is in the
58 * power delivery mechanism and likely to be be board/function
59 * specific. Hence we presume the workaround needs only be applied
60 * to the Valleyview P-unit and not all sideband communications.
62 if (IS_VALLEYVIEW(i915)) {
63 pm_qos_update_request(&i915->sb_qos, 0);
64 on_each_cpu(ping, NULL, 1);
68 static void __vlv_punit_put(struct drm_i915_private *i915)
70 if (IS_VALLEYVIEW(i915))
71 pm_qos_update_request(&i915->sb_qos, PM_QOS_DEFAULT_VALUE);
73 iosf_mbi_punit_release();
76 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
78 if (ports & BIT(VLV_IOSF_SB_PUNIT))
79 __vlv_punit_get(i915);
81 mutex_lock(&i915->sb_lock);
84 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
86 mutex_unlock(&i915->sb_lock);
88 if (ports & BIT(VLV_IOSF_SB_PUNIT))
89 __vlv_punit_put(i915);
92 static int vlv_sideband_rw(struct drm_i915_private *i915,
93 u32 devfn, u32 port, u32 opcode,
96 struct intel_uncore *uncore = &i915->uncore;
97 const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
100 lockdep_assert_held(&i915->sb_lock);
101 if (port == IOSF_PORT_PUNIT)
102 iosf_mbi_assert_punit_acquired();
104 /* Flush the previous comms, just in case it failed last time. */
105 if (intel_wait_for_register(uncore,
106 VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
108 DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
109 is_read ? "read" : "write");
115 intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr);
116 intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
117 intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ,
118 (devfn << IOSF_DEVFN_SHIFT) |
119 (opcode << IOSF_OPCODE_SHIFT) |
120 (port << IOSF_PORT_SHIFT) |
121 (0xf << IOSF_BYTE_ENABLES_SHIFT) |
122 (0 << IOSF_BAR_SHIFT) |
125 if (__intel_wait_for_register_fw(uncore,
126 VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
127 10000, 0, NULL) == 0) {
129 *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
132 DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
133 is_read ? "read" : "write");
142 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
146 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
147 SB_CRRDDA_NP, addr, &val);
152 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
154 return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
155 SB_CRWRDA_NP, addr, &val);
158 u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
162 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
163 SB_CRRDDA_NP, reg, &val);
168 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
170 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
171 SB_CRWRDA_NP, reg, &val);
174 u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
178 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
179 SB_CRRDDA_NP, addr, &val);
184 u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
188 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
189 SB_CRRDDA_NP, reg, &val);
194 void vlv_iosf_sb_write(struct drm_i915_private *i915,
195 u8 port, u32 reg, u32 val)
197 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
198 SB_CRWRDA_NP, reg, &val);
201 u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
205 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
206 SB_CRRDDA_NP, reg, &val);
211 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
213 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
214 SB_CRWRDA_NP, reg, &val);
217 u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
221 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
222 SB_CRRDDA_NP, reg, &val);
227 void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
229 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
230 SB_CRWRDA_NP, reg, &val);
233 u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
235 int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
238 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
241 * FIXME: There might be some registers where all 1's is a valid value,
242 * so ideally we should check the register offset instead...
244 WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
245 pipe_name(pipe), reg, val);
250 void vlv_dpio_write(struct drm_i915_private *i915,
251 enum pipe pipe, int reg, u32 val)
253 int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
255 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
258 u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
262 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
267 void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
269 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
274 static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
275 enum intel_sbi_destination destination,
276 u32 *val, bool is_read)
278 struct intel_uncore *uncore = &i915->uncore;
281 lockdep_assert_held(&i915->sb_lock);
283 if (intel_wait_for_register_fw(uncore,
284 SBI_CTL_STAT, SBI_BUSY, 0,
286 DRM_ERROR("timeout waiting for SBI to become ready\n");
290 intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
291 intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
293 if (destination == SBI_ICLK)
294 cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
296 cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
299 intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
301 if (__intel_wait_for_register_fw(uncore,
302 SBI_CTL_STAT, SBI_BUSY, 0,
304 DRM_ERROR("timeout waiting for SBI to complete read\n");
308 if (cmd & SBI_RESPONSE_FAIL) {
309 DRM_ERROR("error during SBI read of reg %x\n", reg);
314 *val = intel_uncore_read_fw(uncore, SBI_DATA);
319 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
320 enum intel_sbi_destination destination)
324 intel_sbi_rw(i915, reg, destination, &result, true);
329 void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
330 enum intel_sbi_destination destination)
332 intel_sbi_rw(i915, reg, destination, &value, false);
335 static inline int gen6_check_mailbox_status(u32 mbox)
337 switch (mbox & GEN6_PCODE_ERROR_MASK) {
338 case GEN6_PCODE_SUCCESS:
340 case GEN6_PCODE_UNIMPLEMENTED_CMD:
342 case GEN6_PCODE_ILLEGAL_CMD:
344 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
345 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
347 case GEN6_PCODE_TIMEOUT:
350 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
355 static inline int gen7_check_mailbox_status(u32 mbox)
357 switch (mbox & GEN6_PCODE_ERROR_MASK) {
358 case GEN6_PCODE_SUCCESS:
360 case GEN6_PCODE_ILLEGAL_CMD:
362 case GEN7_PCODE_TIMEOUT:
364 case GEN7_PCODE_ILLEGAL_DATA:
366 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
369 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
374 static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
375 u32 mbox, u32 *val, u32 *val1,
380 struct intel_uncore *uncore = &i915->uncore;
382 lockdep_assert_held(&i915->sb_lock);
385 * GEN6_PCODE_* are outside of the forcewake domain, we can
386 * use te fw I915_READ variants to reduce the amount of work
387 * required when reading/writing.
390 if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
393 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
394 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
395 intel_uncore_write_fw(uncore,
396 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
398 if (__intel_wait_for_register_fw(uncore,
407 *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
409 *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
411 if (INTEL_GEN(i915) > 6)
412 return gen7_check_mailbox_status(mbox);
414 return gen6_check_mailbox_status(mbox);
417 int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
422 mutex_lock(&i915->sb_lock);
423 err = __sandybridge_pcode_rw(i915, mbox, val, val1,
426 mutex_unlock(&i915->sb_lock);
429 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
430 mbox, __builtin_return_address(0), err);
436 int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
443 mutex_lock(&i915->sb_lock);
444 err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
445 fast_timeout_us, slow_timeout_ms,
447 mutex_unlock(&i915->sb_lock);
450 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
451 val, mbox, __builtin_return_address(0), err);
457 static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
458 u32 request, u32 reply_mask, u32 reply,
461 *status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
465 return *status || ((request & reply_mask) == reply);
469 * skl_pcode_request - send PCODE request until acknowledgment
470 * @i915: device private
471 * @mbox: PCODE mailbox ID the request is targeted for
472 * @request: request ID
473 * @reply_mask: mask used to check for request acknowledgment
474 * @reply: value used to check for request acknowledgment
475 * @timeout_base_ms: timeout for polling with preemption enabled
477 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
478 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
479 * The request is acknowledged once the PCODE reply dword equals @reply after
480 * applying @reply_mask. Polling is first attempted with preemption enabled
481 * for @timeout_base_ms and if this times out for another 50 ms with
482 * preemption disabled.
484 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
485 * other error as reported by PCODE.
487 int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
488 u32 reply_mask, u32 reply, int timeout_base_ms)
493 mutex_lock(&i915->sb_lock);
496 skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
499 * Prime the PCODE by doing a request first. Normally it guarantees
500 * that a subsequent request, at most @timeout_base_ms later, succeeds.
501 * _wait_for() doesn't guarantee when its passed condition is evaluated
502 * first, so send the first request explicitly.
508 ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
513 * The above can time out if the number of requests was low (2 in the
514 * worst case) _and_ PCODE was busy for some reason even after a
515 * (queued) request and @timeout_base_ms delay. As a workaround retry
516 * the poll with preemption disabled to maximize the number of
517 * requests. Increase the timeout from @timeout_base_ms to 50ms to
518 * account for interrupts that could reduce the number of these
519 * requests, and for any quirks of the PCODE firmware that delays
520 * the request completion.
522 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
523 WARN_ON_ONCE(timeout_base_ms > 3);
525 ret = wait_for_atomic(COND, 50);
529 mutex_unlock(&i915->sb_lock);
530 return ret ? ret : status;