1 /* SPDX-License-Identifier: MIT */
2 #ifndef _INTEL_RINGBUFFER_H_
3 #define _INTEL_RINGBUFFER_H_
5 #include <drm/drm_util.h>
7 #include <linux/hashtable.h>
8 #include <linux/irq_work.h>
9 #include <linux/random.h>
10 #include <linux/seqlock.h>
12 #include "i915_gem_batch_pool.h"
16 #include "i915_request.h"
17 #include "i915_selftest.h"
18 #include "i915_timeline.h"
19 #include "intel_gpu_commands.h"
20 #include "intel_workarounds.h"
23 struct i915_sched_attr;
25 #define I915_CMD_HASH_ORDER 9
27 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
28 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
29 * to give some inclination as to some of the magic values used in the various
32 #define CACHELINE_BYTES 64
33 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
35 struct intel_hw_status_page {
40 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
41 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
43 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
44 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
46 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
47 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
49 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
50 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
52 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
53 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
55 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
56 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
58 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
59 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
61 enum intel_engine_hangcheck_action {
66 ENGINE_ACTIVE_SUBUNITS,
71 static inline const char *
72 hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
79 case ENGINE_ACTIVE_SEQNO:
80 return "active seqno";
81 case ENGINE_ACTIVE_HEAD:
83 case ENGINE_ACTIVE_SUBUNITS:
84 return "active subunits";
85 case ENGINE_WAIT_KICK:
94 #define I915_MAX_SLICES 3
95 #define I915_MAX_SUBSLICES 8
97 #define instdone_slice_mask(dev_priv__) \
98 (IS_GEN(dev_priv__, 7) ? \
99 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
101 #define instdone_subslice_mask(dev_priv__) \
102 (IS_GEN(dev_priv__, 7) ? \
103 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
105 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
106 for ((slice__) = 0, (subslice__) = 0; \
107 (slice__) < I915_MAX_SLICES; \
108 (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
109 (slice__) += ((subslice__) == 0)) \
110 for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
111 (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
113 struct intel_instdone {
115 /* The following exist only in the RCS engine */
117 u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
118 u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
121 struct intel_engine_hangcheck {
125 unsigned long action_timestamp;
126 struct intel_instdone instdone;
130 struct i915_vma *vma;
133 struct i915_timeline *timeline;
134 struct list_head request_list;
135 struct list_head active_link;
146 struct i915_gem_context;
147 struct drm_i915_reg_table;
150 * we use a single page to load ctx workarounds so all of these
151 * values are referred in terms of dwords
153 * struct i915_wa_ctx_bb:
154 * offset: specifies batch starting position, also helpful in case
155 * if we want to have multiple batches at different offsets based on
156 * some criteria. It is not a requirement at the moment but provides
157 * an option for future use.
158 * size: size of the batch in DWORDS
160 struct i915_ctx_workarounds {
161 struct i915_wa_ctx_bb {
164 } indirect_ctx, per_ctx;
165 struct i915_vma *vma;
170 #define I915_MAX_VCS 4
171 #define I915_MAX_VECS 2
174 * Engine IDs definitions.
175 * Keep instances of the same type engine together.
177 enum intel_engine_id {
184 #define _VCS(n) (VCS + (n))
187 #define _VECS(n) (VECS + (n))
190 struct i915_priolist {
191 struct list_head requests[I915_PRIORITY_COUNT];
197 #define priolist_for_each_request(it, plist, idx) \
198 for (idx = 0; idx < ARRAY_SIZE((plist)->requests); idx++) \
199 list_for_each_entry(it, &(plist)->requests[idx], sched.link)
201 #define priolist_for_each_request_consume(it, n, plist, idx) \
202 for (; (idx = ffs((plist)->used)); (plist)->used &= ~BIT(idx - 1)) \
203 list_for_each_entry_safe(it, n, \
204 &(plist)->requests[idx - 1], \
207 struct st_preempt_hang {
208 struct completion completion;
214 * struct intel_engine_execlists - execlist submission queue and port state
216 * The struct intel_engine_execlists represents the combined logical state of
217 * driver and the hardware state for execlist mode of submission.
219 struct intel_engine_execlists {
221 * @tasklet: softirq tasklet for bottom handler
223 struct tasklet_struct tasklet;
226 * @default_priolist: priority list for I915_PRIORITY_NORMAL
228 struct i915_priolist default_priolist;
231 * @no_priolist: priority lists disabled
236 * @submit_reg: gen-specific execlist submission register
237 * set to the ExecList Submission Port (elsp) register pre-Gen11 and to
238 * the ExecList Submission Queue Contents register array for Gen11+
240 u32 __iomem *submit_reg;
243 * @ctrl_reg: the enhanced execlists control register, used to load the
244 * submit queue on the HW and to request preemptions to idle
246 u32 __iomem *ctrl_reg;
249 * @port: execlist port states
251 * For each hardware ELSP (ExecList Submission Port) we keep
252 * track of the last request and the number of times we submitted
253 * that port to hw. We then count the number of times the hw reports
254 * a context completion or preemption. As only one context can
255 * be active on hw, we limit resubmission of context to port[0]. This
256 * is called Lite Restore, of the context.
258 struct execlist_port {
260 * @request_count: combined request and submission count
262 struct i915_request *request_count;
263 #define EXECLIST_COUNT_BITS 2
264 #define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
265 #define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
266 #define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
267 #define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
268 #define port_set(p, packed) ((p)->request_count = (packed))
269 #define port_isset(p) ((p)->request_count)
270 #define port_index(p, execlists) ((p) - (execlists)->port)
273 * @context_id: context ID for port
275 GEM_DEBUG_DECL(u32 context_id);
277 #define EXECLIST_MAX_PORTS 2
278 } port[EXECLIST_MAX_PORTS];
281 * @active: is the HW active? We consider the HW as active after
282 * submitting any context for execution and until we have seen the
283 * last context completion event. After that, we do not expect any
284 * more events until we submit, and so can park the HW.
286 * As we have a small number of different sources from which we feed
287 * the HW, we track the state of each inside a single bitfield.
290 #define EXECLISTS_ACTIVE_USER 0
291 #define EXECLISTS_ACTIVE_PREEMPT 1
292 #define EXECLISTS_ACTIVE_HWACK 2
295 * @port_mask: number of execlist ports - 1
297 unsigned int port_mask;
300 * @queue_priority_hint: Highest pending priority.
302 * When we add requests into the queue, or adjust the priority of
303 * executing requests, we compute the maximum priority of those
304 * pending requests. We can then use this value to determine if
305 * we need to preempt the executing requests to service the queue.
306 * However, since the we may have recorded the priority of an inflight
307 * request we wanted to preempt but since completed, at the time of
308 * dequeuing the priority hint may no longer may match the highest
309 * available request priority.
311 int queue_priority_hint;
314 * @queue: queue of requests, in priority lists
316 struct rb_root_cached queue;
319 * @csb_write: control register for Context Switch buffer
321 * Note this register may be either mmio or HWSP shadow.
326 * @csb_status: status array for Context Switch buffer
328 * Note these register may be either mmio or HWSP shadow.
333 * @preempt_complete_status: expected CSB upon completing preemption
335 u32 preempt_complete_status;
338 * @csb_head: context status buffer head
342 I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;)
345 #define INTEL_ENGINE_CS_MAX_NAME 8
347 struct intel_engine_cs {
348 struct drm_i915_private *i915;
349 char name[INTEL_ENGINE_CS_MAX_NAME];
351 enum intel_engine_id id;
363 struct intel_ring *buffer;
365 struct i915_timeline timeline;
367 struct drm_i915_gem_object *default_state;
368 void *pinned_default_state;
370 /* Rather than have every client wait upon all user interrupts,
371 * with the herd waking after every interrupt and each doing the
372 * heavyweight seqno dance, we delegate the task (of being the
373 * bottom-half of the user interrupt) to the first client. After
374 * every interrupt, we wake up one client, who does the heavyweight
375 * coherent seqno read and either goes back to sleep (if incomplete),
376 * or wakes up all the completed clients in parallel, before then
377 * transferring the bottom-half status to the next client in the queue.
379 * Compared to walking the entire list of waiters in a single dedicated
380 * bottom-half, we reduce the latency of the first waiter by avoiding
381 * a context switch, but incur additional coherent seqno reads when
382 * following the chain of request breadcrumbs. Since it is most likely
383 * that we have a single client waiting on each seqno, then reducing
384 * the overhead of waking that client is much preferred.
386 struct intel_breadcrumbs {
388 struct list_head signalers;
390 struct irq_work irq_work; /* for use from inside irq_lock */
392 unsigned int irq_enabled;
397 struct intel_engine_pmu {
399 * @enable: Bitmask of enable sample events on this engine.
401 * Bits correspond to sample event types, for instance
402 * I915_SAMPLE_QUEUED is bit 0 etc.
406 * @enable_count: Reference count for the enabled samplers.
408 * Index number corresponds to @enum drm_i915_pmu_engine_sample.
410 unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT];
412 * @sample: Counter values for sampling events.
414 * Our internal timer stores the current counters in this field.
416 * Index number corresponds to @enum drm_i915_pmu_engine_sample.
418 struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_COUNT];
422 * A pool of objects to use as shadow copies of client batch buffers
423 * when the command parser is enabled. Prevents the client from
424 * modifying the batch contents after software parsing.
426 struct i915_gem_batch_pool batch_pool;
428 struct intel_hw_status_page status_page;
429 struct i915_ctx_workarounds wa_ctx;
430 struct i915_wa_list ctx_wa_list;
431 struct i915_wa_list wa_list;
432 struct i915_wa_list whitelist;
434 u32 irq_keep_mask; /* always keep these interrupts */
435 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
436 void (*irq_enable)(struct intel_engine_cs *engine);
437 void (*irq_disable)(struct intel_engine_cs *engine);
439 int (*init_hw)(struct intel_engine_cs *engine);
442 void (*prepare)(struct intel_engine_cs *engine);
443 void (*reset)(struct intel_engine_cs *engine, bool stalled);
444 void (*finish)(struct intel_engine_cs *engine);
447 void (*park)(struct intel_engine_cs *engine);
448 void (*unpark)(struct intel_engine_cs *engine);
450 void (*set_default_submission)(struct intel_engine_cs *engine);
452 struct intel_context *(*context_pin)(struct intel_engine_cs *engine,
453 struct i915_gem_context *ctx);
455 int (*request_alloc)(struct i915_request *rq);
456 int (*init_context)(struct i915_request *rq);
458 int (*emit_flush)(struct i915_request *request, u32 mode);
459 #define EMIT_INVALIDATE BIT(0)
460 #define EMIT_FLUSH BIT(1)
461 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
462 int (*emit_bb_start)(struct i915_request *rq,
463 u64 offset, u32 length,
464 unsigned int dispatch_flags);
465 #define I915_DISPATCH_SECURE BIT(0)
466 #define I915_DISPATCH_PINNED BIT(1)
467 int (*emit_init_breadcrumb)(struct i915_request *rq);
468 u32 *(*emit_fini_breadcrumb)(struct i915_request *rq,
470 unsigned int emit_fini_breadcrumb_dw;
472 /* Pass the request to the hardware queue (e.g. directly into
473 * the legacy ringbuffer or to the end of an execlist).
475 * This is called from an atomic context with irqs disabled; must
478 void (*submit_request)(struct i915_request *rq);
481 * Call when the priority on a request has changed and it and its
482 * dependencies may need rescheduling. Note the request itself may
483 * not be ready to run!
485 void (*schedule)(struct i915_request *request,
486 const struct i915_sched_attr *attr);
489 * Cancel all requests on the hardware, or queued for execution.
490 * This should only cancel the ready requests that have been
491 * submitted to the engine (via the engine->submit_request callback).
492 * This is called when marking the device as wedged.
494 void (*cancel_requests)(struct intel_engine_cs *engine);
496 void (*cleanup)(struct intel_engine_cs *engine);
498 struct intel_engine_execlists execlists;
500 /* Contexts are pinned whilst they are active on the GPU. The last
501 * context executed remains active whilst the GPU is idle - the
502 * switch away and write to the context object only occurs on the
503 * next execution. Contexts are only unpinned on retirement of the
504 * following request ensuring that we can always write to the object
505 * on the context switch even after idling. Across suspend, we switch
506 * to the kernel context and trash it as the save may not happen
507 * before the hardware is powered down.
509 struct intel_context *last_retired_context;
511 /* status_notifier: list of callbacks for context-switch changes */
512 struct atomic_notifier_head context_status_notifier;
514 struct intel_engine_hangcheck hangcheck;
516 #define I915_ENGINE_NEEDS_CMD_PARSER BIT(0)
517 #define I915_ENGINE_SUPPORTS_STATS BIT(1)
518 #define I915_ENGINE_HAS_PREEMPTION BIT(2)
522 * Table of commands the command parser needs to know about
525 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
528 * Table of registers allowed in commands that read/write registers.
530 const struct drm_i915_reg_table *reg_tables;
534 * Returns the bitmask for the length field of the specified command.
535 * Return 0 for an unrecognized/invalid command.
537 * If the command parser finds an entry for a command in the engine's
538 * cmd_tables, it gets the command's length based on the table entry.
539 * If not, it calls this function to determine the per-engine length
540 * field encoding for the command (i.e. different opcode ranges use
541 * certain bits to encode the command length in the header).
543 u32 (*get_cmd_length_mask)(u32 cmd_header);
547 * @lock: Lock protecting the below fields.
551 * @enabled: Reference count indicating number of listeners.
553 unsigned int enabled;
555 * @active: Number of contexts currently scheduled in.
559 * @enabled_at: Timestamp when busy stats were enabled.
563 * @start: Timestamp of the last idle to active transition.
565 * Idle is defined as active == 0, active is active > 0.
569 * @total: Total time this engine was busy.
571 * Accumulated time not counting the most recent block in cases
572 * where engine is currently busy (active > 0).
579 intel_engine_needs_cmd_parser(const struct intel_engine_cs *engine)
581 return engine->flags & I915_ENGINE_NEEDS_CMD_PARSER;
585 intel_engine_supports_stats(const struct intel_engine_cs *engine)
587 return engine->flags & I915_ENGINE_SUPPORTS_STATS;
591 intel_engine_has_preemption(const struct intel_engine_cs *engine)
593 return engine->flags & I915_ENGINE_HAS_PREEMPTION;
596 static inline bool __execlists_need_preempt(int prio, int last)
599 * Allow preemption of low -> normal -> high, but we do
600 * not allow low priority tasks to preempt other low priority
601 * tasks under the impression that latency for low priority
602 * tasks does not matter (as much as background throughput),
605 * More naturally we would write
606 * prio >= max(0, last);
607 * except that we wish to prevent triggering preemption at the same
608 * priority level: the task that is running should remain running
609 * to preserve FIFO ordering of dependencies.
611 return prio > max(I915_PRIORITY_NORMAL - 1, last);
615 execlists_set_active(struct intel_engine_execlists *execlists,
618 __set_bit(bit, (unsigned long *)&execlists->active);
622 execlists_set_active_once(struct intel_engine_execlists *execlists,
625 return !__test_and_set_bit(bit, (unsigned long *)&execlists->active);
629 execlists_clear_active(struct intel_engine_execlists *execlists,
632 __clear_bit(bit, (unsigned long *)&execlists->active);
636 execlists_clear_all_active(struct intel_engine_execlists *execlists)
638 execlists->active = 0;
642 execlists_is_active(const struct intel_engine_execlists *execlists,
645 return test_bit(bit, (unsigned long *)&execlists->active);
648 void execlists_user_begin(struct intel_engine_execlists *execlists,
649 const struct execlist_port *port);
650 void execlists_user_end(struct intel_engine_execlists *execlists);
653 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists);
656 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
658 static inline unsigned int
659 execlists_num_ports(const struct intel_engine_execlists * const execlists)
661 return execlists->port_mask + 1;
664 static inline struct execlist_port *
665 execlists_port_complete(struct intel_engine_execlists * const execlists,
666 struct execlist_port * const port)
668 const unsigned int m = execlists->port_mask;
670 GEM_BUG_ON(port_index(port, execlists) != 0);
671 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
673 memmove(port, port + 1, m * sizeof(struct execlist_port));
674 memset(port + m, 0, sizeof(struct execlist_port));
679 static inline unsigned int
680 intel_engine_flag(const struct intel_engine_cs *engine)
682 return BIT(engine->id);
686 intel_read_status_page(const struct intel_engine_cs *engine, int reg)
688 /* Ensure that the compiler doesn't optimize away the load. */
689 return READ_ONCE(engine->status_page.addr[reg]);
693 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
695 /* Writing into the status page should be done sparingly. Since
696 * we do when we are uncertain of the device state, we take a bit
697 * of extra paranoia to try and ensure that the HWS takes the value
698 * we give and that it doesn't end up trapped inside the CPU!
700 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
702 clflush(&engine->status_page.addr[reg]);
703 engine->status_page.addr[reg] = value;
704 clflush(&engine->status_page.addr[reg]);
707 WRITE_ONCE(engine->status_page.addr[reg], value);
712 * Reads a dword out of the status page, which is written to from the command
713 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
716 * The following dwords have a reserved meaning:
717 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
718 * 0x04: ring 0 head pointer
719 * 0x05: ring 1 head pointer (915-class)
720 * 0x06: ring 2 head pointer (915-class)
721 * 0x10-0x1b: Context status DWords (GM45)
722 * 0x1f: Last written status offset. (GM45)
723 * 0x20-0x2f: Reserved (Gen6+)
725 * The area from dword 0x30 to 0x3ff is available for driver usage.
727 #define I915_GEM_HWS_PREEMPT 0x32
728 #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
729 #define I915_GEM_HWS_HANGCHECK 0x34
730 #define I915_GEM_HWS_HANGCHECK_ADDR (I915_GEM_HWS_HANGCHECK * sizeof(u32))
731 #define I915_GEM_HWS_SEQNO 0x40
732 #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
733 #define I915_GEM_HWS_SCRATCH 0x80
734 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32))
736 #define I915_HWS_CSB_BUF0_INDEX 0x10
737 #define I915_HWS_CSB_WRITE_INDEX 0x1f
738 #define CNL_HWS_CSB_WRITE_INDEX 0x2f
741 intel_engine_create_ring(struct intel_engine_cs *engine,
742 struct i915_timeline *timeline,
744 int intel_ring_pin(struct intel_ring *ring);
745 void intel_ring_reset(struct intel_ring *ring, u32 tail);
746 unsigned int intel_ring_update_space(struct intel_ring *ring);
747 void intel_ring_unpin(struct intel_ring *ring);
748 void intel_ring_free(struct intel_ring *ring);
750 void intel_engine_stop(struct intel_engine_cs *engine);
751 void intel_engine_cleanup(struct intel_engine_cs *engine);
753 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);
755 int __must_check intel_ring_cacheline_align(struct i915_request *rq);
757 u32 __must_check *intel_ring_begin(struct i915_request *rq, unsigned int n);
759 static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)
763 * This serves as a placeholder in the code so that the reader
764 * can compare against the preceding intel_ring_begin() and
765 * check that the number of dwords emitted matches the space
766 * reserved for the command packet (i.e. the value passed to
767 * intel_ring_begin()).
769 GEM_BUG_ON((rq->ring->vaddr + rq->ring->emit) != cs);
772 static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
774 return pos & (ring->size - 1);
778 intel_ring_offset_valid(const struct intel_ring *ring,
781 if (pos & -ring->size) /* must be strictly within the ring */
784 if (!IS_ALIGNED(pos, 8)) /* must be qword aligned */
790 static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)
792 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
793 u32 offset = addr - rq->ring->vaddr;
794 GEM_BUG_ON(offset > rq->ring->size);
795 return intel_ring_wrap(rq->ring, offset);
799 assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
801 GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
805 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6
806 * Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5
807 * Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5
808 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
809 * same cacheline, the Head Pointer must not be greater than the Tail
812 * We use ring->head as the last known location of the actual RING_HEAD,
813 * it may have advanced but in the worst case it is equally the same
814 * as ring->head and so we should never program RING_TAIL to advance
815 * into the same cacheline as ring->head.
817 #define cacheline(a) round_down(a, CACHELINE_BYTES)
818 GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) &&
823 static inline unsigned int
824 intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
826 /* Whilst writes to the tail are strictly order, there is no
827 * serialisation between readers and the writers. The tail may be
828 * read by i915_request_retire() just as it is being updated
829 * by execlists, as although the breadcrumb is complete, the context
830 * switch hasn't been seen.
832 assert_ring_tail_valid(ring, tail);
837 static inline unsigned int
838 __intel_ring_space(unsigned int head, unsigned int tail, unsigned int size)
841 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
842 * same cacheline, the Head Pointer must not be greater than the Tail
845 GEM_BUG_ON(!is_power_of_2(size));
846 return (head - tail - CACHELINE_BYTES) & (size - 1);
849 int intel_engine_setup_common(struct intel_engine_cs *engine);
850 int intel_engine_init_common(struct intel_engine_cs *engine);
851 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
853 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
854 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
855 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
856 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
858 int intel_engine_stop_cs(struct intel_engine_cs *engine);
859 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
861 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
863 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
864 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
866 void intel_engine_get_instdone(struct intel_engine_cs *engine,
867 struct intel_instdone *instdone);
869 void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
870 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
872 void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine);
873 void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine);
875 bool intel_engine_signal_breadcrumbs(struct intel_engine_cs *engine);
876 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
879 intel_engine_queue_breadcrumbs(struct intel_engine_cs *engine)
881 irq_work_queue(&engine->breadcrumbs.irq_work);
884 bool intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine);
886 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
887 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
889 void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
890 struct drm_printer *p);
892 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
894 memset(batch, 0, 6 * sizeof(u32));
896 batch[0] = GFX_OP_PIPE_CONTROL(6);
904 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
906 /* We're using qword write, offset should be aligned to 8 bytes. */
907 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
909 /* w/a for post sync ops following a GPGPU operation we
910 * need a prior CS_STALL, which is emitted by the flush
911 * following the batch.
913 *cs++ = GFX_OP_PIPE_CONTROL(6);
914 *cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
918 /* We're thrashing one dword of HWS. */
925 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset)
927 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
928 GEM_BUG_ON(gtt_offset & (1 << 5));
929 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
930 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
932 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
933 *cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
940 static inline void intel_engine_reset(struct intel_engine_cs *engine,
943 if (engine->reset.reset)
944 engine->reset.reset(engine, stalled);
947 void intel_engines_sanitize(struct drm_i915_private *i915, bool force);
949 bool intel_engine_is_idle(struct intel_engine_cs *engine);
950 bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
952 bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine);
953 void intel_engine_lost_context(struct intel_engine_cs *engine);
955 void intel_engines_park(struct drm_i915_private *i915);
956 void intel_engines_unpark(struct drm_i915_private *i915);
958 void intel_engines_reset_default_submission(struct drm_i915_private *i915);
959 unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915);
961 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
964 void intel_engine_dump(struct intel_engine_cs *engine,
965 struct drm_printer *m,
966 const char *header, ...);
968 struct intel_engine_cs *
969 intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance);
971 static inline void intel_engine_context_in(struct intel_engine_cs *engine)
975 if (READ_ONCE(engine->stats.enabled) == 0)
978 write_seqlock_irqsave(&engine->stats.lock, flags);
980 if (engine->stats.enabled > 0) {
981 if (engine->stats.active++ == 0)
982 engine->stats.start = ktime_get();
983 GEM_BUG_ON(engine->stats.active == 0);
986 write_sequnlock_irqrestore(&engine->stats.lock, flags);
989 static inline void intel_engine_context_out(struct intel_engine_cs *engine)
993 if (READ_ONCE(engine->stats.enabled) == 0)
996 write_seqlock_irqsave(&engine->stats.lock, flags);
998 if (engine->stats.enabled > 0) {
1001 if (engine->stats.active && --engine->stats.active == 0) {
1003 * Decrement the active context count and in case GPU
1004 * is now idle add up to the running total.
1006 last = ktime_sub(ktime_get(), engine->stats.start);
1008 engine->stats.total = ktime_add(engine->stats.total,
1010 } else if (engine->stats.active == 0) {
1012 * After turning on engine stats, context out might be
1013 * the first event in which case we account from the
1014 * time stats gathering was turned on.
1016 last = ktime_sub(ktime_get(), engine->stats.enabled_at);
1018 engine->stats.total = ktime_add(engine->stats.total,
1023 write_sequnlock_irqrestore(&engine->stats.lock, flags);
1026 int intel_enable_engine_stats(struct intel_engine_cs *engine);
1027 void intel_disable_engine_stats(struct intel_engine_cs *engine);
1029 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
1031 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1033 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
1035 if (!execlists->preempt_hang.inject_hang)
1038 complete(&execlists->preempt_hang.completion);
1044 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
1052 intel_engine_next_hangcheck_seqno(struct intel_engine_cs *engine)
1054 return engine->hangcheck.next_seqno =
1055 next_pseudo_random32(engine->hangcheck.next_seqno);
1059 intel_engine_get_hangcheck_seqno(struct intel_engine_cs *engine)
1061 return intel_read_status_page(engine, I915_GEM_HWS_HANGCHECK);
1064 #endif /* _INTEL_RINGBUFFER_H_ */