1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2019 Intel Corporation
9 #include <linux/types.h>
13 struct drm_atomic_state;
15 struct drm_i915_private;
18 struct intel_crtc_state;
20 struct skl_ddb_allocation;
25 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
26 void intel_suspend_hw(struct drm_i915_private *dev_priv);
27 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
28 void intel_update_watermarks(struct intel_crtc *crtc);
29 void intel_init_pm(struct drm_i915_private *dev_priv);
30 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
31 void intel_pm_setup(struct drm_i915_private *dev_priv);
32 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
33 void intel_gpu_ips_teardown(void);
34 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
35 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
36 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
37 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
38 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
39 void gen6_rps_busy(struct drm_i915_private *dev_priv);
40 void gen6_rps_idle(struct drm_i915_private *dev_priv);
41 void gen6_rps_boost(struct i915_request *rq);
42 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
43 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
44 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
45 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
46 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
47 struct skl_ddb_entry *ddb_y,
48 struct skl_ddb_entry *ddb_uv);
49 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
50 struct skl_ddb_allocation *ddb /* out */);
51 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
52 struct skl_pipe_wm *out);
53 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
54 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
55 bool intel_can_enable_sagv(struct drm_atomic_state *state);
56 int intel_enable_sagv(struct drm_i915_private *dev_priv);
57 int intel_disable_sagv(struct drm_i915_private *dev_priv);
58 bool skl_wm_level_equals(const struct skl_wm_level *l1,
59 const struct skl_wm_level *l2);
60 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
61 const struct skl_ddb_entry *entries,
62 int num_entries, int ignore_idx);
63 void skl_write_plane_wm(struct intel_plane *plane,
64 const struct intel_crtc_state *crtc_state);
65 void skl_write_cursor_wm(struct intel_plane *plane,
66 const struct intel_crtc_state *crtc_state);
67 bool ilk_disable_lp_wm(struct drm_device *dev);
68 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
69 struct intel_crtc_state *cstate);
70 void intel_init_ipc(struct drm_i915_private *dev_priv);
71 void intel_enable_ipc(struct drm_i915_private *dev_priv);
73 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
74 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
75 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
76 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
78 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
80 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
81 unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
82 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
83 void i915_update_gfx_val(struct drm_i915_private *dev_priv);
85 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
86 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
87 void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive);
88 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
90 #endif /* __INTEL_PM_H__ */