drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         I915_WRITE(GEN8_CONFIG0,
  66                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  67
  68         /* WaEnableChickenDCPR:skl,bxt,kbl */
  69         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  70                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  71
  72         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  73         /* WaFbcWakeMemOn:skl,bxt,kbl */
  74         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  75                    DISP_FBC_WM_DIS |
  76                    DISP_FBC_MEMORY_WAKE);
  77
  78         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  79         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  80                    ILK_DPFC_DISABLE_DUMMY0);
  81 }
  82
  83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
  84 {
  85         gen9_init_clock_gating(dev_priv);
  86
  87         /* WaDisableSDEUnitClockGating:bxt */
  88         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  89                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  90
  91         /*
  92          * FIXME:
  93          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  94          */
  95         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  96                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  97
  98         /*
  99          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 100          * to stay fully on.
 101          */
 102         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 103                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 104                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 105 }
 106
 107 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 108 {
 109         u32 tmp;
 110
 111         tmp = I915_READ(CLKCFG);
 112
 113         switch (tmp & CLKCFG_FSB_MASK) {
 114         case CLKCFG_FSB_533:
 115                 dev_priv->fsb_freq = 533; /* 133*4 */
 116                 break;
 117         case CLKCFG_FSB_800:
 118                 dev_priv->fsb_freq = 800; /* 200*4 */
 119                 break;
 120         case CLKCFG_FSB_667:
 121                 dev_priv->fsb_freq =  667; /* 167*4 */
 122                 break;
 123         case CLKCFG_FSB_400:
 124                 dev_priv->fsb_freq = 400; /* 100*4 */
 125                 break;
 126         }
 127
 128         switch (tmp & CLKCFG_MEM_MASK) {
 129         case CLKCFG_MEM_533:
 130                 dev_priv->mem_freq = 533;
 131                 break;
 132         case CLKCFG_MEM_667:
 133                 dev_priv->mem_freq = 667;
 134                 break;
 135         case CLKCFG_MEM_800:
 136                 dev_priv->mem_freq = 800;
 137                 break;
 138         }
 139
 140         /* detect pineview DDR3 setting */
 141         tmp = I915_READ(CSHRDDR3CTL);
 142         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 143 }
 144
 145 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 146 {
 147         u16 ddrpll, csipll;
 148
 149         ddrpll = I915_READ16(DDRMPLL1);
 150         csipll = I915_READ16(CSIPLL0);
 151
 152         switch (ddrpll & 0xff) {
 153         case 0xc:
 154                 dev_priv->mem_freq = 800;
 155                 break;
 156         case 0x10:
 157                 dev_priv->mem_freq = 1066;
 158                 break;
 159         case 0x14:
 160                 dev_priv->mem_freq = 1333;
 161                 break;
 162         case 0x18:
 163                 dev_priv->mem_freq = 1600;
 164                 break;
 165         default:
 166                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 167                                  ddrpll & 0xff);
 168                 dev_priv->mem_freq = 0;
 169                 break;
 170         }
 171
 172         dev_priv->ips.r_t = dev_priv->mem_freq;
 173
 174         switch (csipll & 0x3ff) {
 175         case 0x00c:
 176                 dev_priv->fsb_freq = 3200;
 177                 break;
 178         case 0x00e:
 179                 dev_priv->fsb_freq = 3733;
 180                 break;
 181         case 0x010:
 182                 dev_priv->fsb_freq = 4266;
 183                 break;
 184         case 0x012:
 185                 dev_priv->fsb_freq = 4800;
 186                 break;
 187         case 0x014:
 188                 dev_priv->fsb_freq = 5333;
 189                 break;
 190         case 0x016:
 191                 dev_priv->fsb_freq = 5866;
 192                 break;
 193         case 0x018:
 194                 dev_priv->fsb_freq = 6400;
 195                 break;
 196         default:
 197                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 198                                  csipll & 0x3ff);
 199                 dev_priv->fsb_freq = 0;
 200                 break;
 201         }
 202
 203         if (dev_priv->fsb_freq == 3200) {
 204                 dev_priv->ips.c_m = 0;
 205         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 206                 dev_priv->ips.c_m = 1;
 207         } else {
 208                 dev_priv->ips.c_m = 2;
 209         }
 210 }
 211
 212 static const struct cxsr_latency cxsr_latency_table[] = {
 213         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 214         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 215         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 216         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 217         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 218
 219         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 220         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 221         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 222         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 223         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 224
 225         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 226         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 227         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 228         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 229         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 230
 231         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 232         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 233         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 234         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 235         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 236
 237         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 238         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 239         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 240         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 241         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 242
 243         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 244         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 245         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 246         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 247         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 248 };
 249
 250 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 251                                                          bool is_ddr3,
 252                                                          int fsb,
 253                                                          int mem)
 254 {
 255         const struct cxsr_latency *latency;
 256         int i;
 257
 258         if (fsb == 0 || mem == 0)
 259                 return NULL;
 260
 261         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 262                 latency = &cxsr_latency_table[i];
 263                 if (is_desktop == latency->is_desktop &&
 264                     is_ddr3 == latency->is_ddr3 &&
 265                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 266                         return latency;
 267         }
 268
 269         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 270
 271         return NULL;
 272 }
 273
 274 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 275 {
 276         u32 val;
 277
 278         mutex_lock(&dev_priv->rps.hw_lock);
 279
 280         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 281         if (enable)
 282                 val &= ~FORCE_DDR_HIGH_FREQ;
 283         else
 284                 val |= FORCE_DDR_HIGH_FREQ;
 285         val &= ~FORCE_DDR_LOW_FREQ;
 286         val |= FORCE_DDR_FREQ_REQ_ACK;
 287         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 288
 289         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 290                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 291                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 292
 293         mutex_unlock(&dev_priv->rps.hw_lock);
 294 }
 295
 296 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 297 {
 298         u32 val;
 299
 300         mutex_lock(&dev_priv->rps.hw_lock);
 301
 302         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 303         if (enable)
 304                 val |= DSP_MAXFIFO_PM5_ENABLE;
 305         else
 306                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 307         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 308
 309         mutex_unlock(&dev_priv->rps.hw_lock);
 310 }
 311
 312 #define FW_WM(value, plane) \
 313         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 314
 315 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 316 {
 317         u32 val;
 318
 319         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 320                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 321                 POSTING_READ(FW_BLC_SELF_VLV);
 322                 dev_priv->wm.vlv.cxsr = enable;
 323         } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
 324                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 325                 POSTING_READ(FW_BLC_SELF);
 326         } else if (IS_PINEVIEW(dev_priv)) {
 327                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 328                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 329                 I915_WRITE(DSPFW3, val);
 330                 POSTING_READ(DSPFW3);
 331         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 332                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 333                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 334                 I915_WRITE(FW_BLC_SELF, val);
 335                 POSTING_READ(FW_BLC_SELF);
 336         } else if (IS_I915GM(dev_priv)) {
 337                 /*
 338                  * FIXME can't find a bit like this for 915G, and
 339                  * and yet it does have the related watermark in
 340                  * FW_BLC_SELF. What's going on?
 341                  */
 342                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 343                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 344                 I915_WRITE(INSTPM, val);
 345                 POSTING_READ(INSTPM);
 346         } else {
 347                 return;
 348         }
 349
 350         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 351                       enable ? "enabled" : "disabled");
 352 }
 353
 354
 355 /*
 356  * Latency for FIFO fetches is dependent on several factors:
 357  *   - memory configuration (speed, channels)
 358  *   - chipset
 359  *   - current MCH state
 360  * It can be fairly high in some situations, so here we assume a fairly
 361  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 362  * set this value too high, the FIFO will fetch frequently to stay full)
 363  * and power consumption (set it too low to save power and we might see
 364  * FIFO underruns and display "flicker").
 365  *
 366  * A value of 5us seems to be a good balance; safe for very low end
 367  * platforms but not overly aggressive on lower latency configs.
 368  */
 369 static const int pessimal_latency_ns = 5000;
 370
 371 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 372         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 373
 374 static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
 375                               enum pipe pipe, int plane)
 376 {
 377         int sprite0_start, sprite1_start, size;
 378
 379         switch (pipe) {
 380                 uint32_t dsparb, dsparb2, dsparb3;
 381         case PIPE_A:
 382                 dsparb = I915_READ(DSPARB);
 383                 dsparb2 = I915_READ(DSPARB2);
 384                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 385                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 386                 break;
 387         case PIPE_B:
 388                 dsparb = I915_READ(DSPARB);
 389                 dsparb2 = I915_READ(DSPARB2);
 390                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 391                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 392                 break;
 393         case PIPE_C:
 394                 dsparb2 = I915_READ(DSPARB2);
 395                 dsparb3 = I915_READ(DSPARB3);
 396                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 397                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 398                 break;
 399         default:
 400                 return 0;
 401         }
 402
 403         switch (plane) {
 404         case 0:
 405                 size = sprite0_start;
 406                 break;
 407         case 1:
 408                 size = sprite1_start - sprite0_start;
 409                 break;
 410         case 2:
 411                 size = 512 - 1 - sprite1_start;
 412                 break;
 413         default:
 414                 return 0;
 415         }
 416
 417         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 418                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 419                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 420                       size);
 421
 422         return size;
 423 }
 424
 425 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 426 {
 427         uint32_t dsparb = I915_READ(DSPARB);
 428         int size;
 429
 430         size = dsparb & 0x7f;
 431         if (plane)
 432                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 433
 434         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 435                       plane ? "B" : "A", size);
 436
 437         return size;
 438 }
 439
 440 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 441 {
 442         uint32_t dsparb = I915_READ(DSPARB);
 443         int size;
 444
 445         size = dsparb & 0x1ff;
 446         if (plane)
 447                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 448         size >>= 1; /* Convert to cachelines */
 449
 450         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 451                       plane ? "B" : "A", size);
 452
 453         return size;
 454 }
 455
 456 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 457 {
 458         uint32_t dsparb = I915_READ(DSPARB);
 459         int size;
 460
 461         size = dsparb & 0x7f;
 462         size >>= 2; /* Convert to cachelines */
 463
 464         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 465                       plane ? "B" : "A",
 466                       size);
 467
 468         return size;
 469 }
 470
 471 /* Pineview has different values for various configs */
 472 static const struct intel_watermark_params pineview_display_wm = {
 473         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 474         .max_wm = PINEVIEW_MAX_WM,
 475         .default_wm = PINEVIEW_DFT_WM,
 476         .guard_size = PINEVIEW_GUARD_WM,
 477         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 478 };
 479 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 480         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 481         .max_wm = PINEVIEW_MAX_WM,
 482         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 483         .guard_size = PINEVIEW_GUARD_WM,
 484         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 485 };
 486 static const struct intel_watermark_params pineview_cursor_wm = {
 487         .fifo_size = PINEVIEW_CURSOR_FIFO,
 488         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 489         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 490         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 491         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 492 };
 493 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 494         .fifo_size = PINEVIEW_CURSOR_FIFO,
 495         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 496         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 497         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 498         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 499 };
 500 static const struct intel_watermark_params g4x_wm_info = {
 501         .fifo_size = G4X_FIFO_SIZE,
 502         .max_wm = G4X_MAX_WM,
 503         .default_wm = G4X_MAX_WM,
 504         .guard_size = 2,
 505         .cacheline_size = G4X_FIFO_LINE_SIZE,
 506 };
 507 static const struct intel_watermark_params g4x_cursor_wm_info = {
 508         .fifo_size = I965_CURSOR_FIFO,
 509         .max_wm = I965_CURSOR_MAX_WM,
 510         .default_wm = I965_CURSOR_DFT_WM,
 511         .guard_size = 2,
 512         .cacheline_size = G4X_FIFO_LINE_SIZE,
 513 };
 514 static const struct intel_watermark_params i965_cursor_wm_info = {
 515         .fifo_size = I965_CURSOR_FIFO,
 516         .max_wm = I965_CURSOR_MAX_WM,
 517         .default_wm = I965_CURSOR_DFT_WM,
 518         .guard_size = 2,
 519         .cacheline_size = I915_FIFO_LINE_SIZE,
 520 };
 521 static const struct intel_watermark_params i945_wm_info = {
 522         .fifo_size = I945_FIFO_SIZE,
 523         .max_wm = I915_MAX_WM,
 524         .default_wm = 1,
 525         .guard_size = 2,
 526         .cacheline_size = I915_FIFO_LINE_SIZE,
 527 };
 528 static const struct intel_watermark_params i915_wm_info = {
 529         .fifo_size = I915_FIFO_SIZE,
 530         .max_wm = I915_MAX_WM,
 531         .default_wm = 1,
 532         .guard_size = 2,
 533         .cacheline_size = I915_FIFO_LINE_SIZE,
 534 };
 535 static const struct intel_watermark_params i830_a_wm_info = {
 536         .fifo_size = I855GM_FIFO_SIZE,
 537         .max_wm = I915_MAX_WM,
 538         .default_wm = 1,
 539         .guard_size = 2,
 540         .cacheline_size = I830_FIFO_LINE_SIZE,
 541 };
 542 static const struct intel_watermark_params i830_bc_wm_info = {
 543         .fifo_size = I855GM_FIFO_SIZE,
 544         .max_wm = I915_MAX_WM/2,
 545         .default_wm = 1,
 546         .guard_size = 2,
 547         .cacheline_size = I830_FIFO_LINE_SIZE,
 548 };
 549 static const struct intel_watermark_params i845_wm_info = {
 550         .fifo_size = I830_FIFO_SIZE,
 551         .max_wm = I915_MAX_WM,
 552         .default_wm = 1,
 553         .guard_size = 2,
 554         .cacheline_size = I830_FIFO_LINE_SIZE,
 555 };
 556
 557 /**
 558  * intel_calculate_wm - calculate watermark level
 559  * @clock_in_khz: pixel clock
 560  * @wm: chip FIFO params
 561  * @cpp: bytes per pixel
 562  * @latency_ns: memory latency for the platform
 563  *
 564  * Calculate the watermark level (the level at which the display plane will
 565  * start fetching from memory again).  Each chip has a different display
 566  * FIFO size and allocation, so the caller needs to figure that out and pass
 567  * in the correct intel_watermark_params structure.
 568  *
 569  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 570  * on the pixel size.  When it reaches the watermark level, it'll start
 571  * fetching FIFO line sized based chunks from memory until the FIFO fills
 572  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 573  * will occur, and a display engine hang could result.
 574  */
 575 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 576                                         const struct intel_watermark_params *wm,
 577                                         int fifo_size, int cpp,
 578                                         unsigned long latency_ns)
 579 {
 580         long entries_required, wm_size;
 581
 582         /*
 583          * Note: we need to make sure we don't overflow for various clock &
 584          * latency values.
 585          * clocks go from a few thousand to several hundred thousand.
 586          * latency is usually a few thousand
 587          */
 588         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 589                 1000;
 590         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 591
 592         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 593
 594         wm_size = fifo_size - (entries_required + wm->guard_size);
 595
 596         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 597
 598         /* Don't promote wm_size to unsigned... */
 599         if (wm_size > (long)wm->max_wm)
 600                 wm_size = wm->max_wm;
 601         if (wm_size <= 0)
 602                 wm_size = wm->default_wm;
 603
 604         /*
 605          * Bspec seems to indicate that the value shouldn't be lower than
 606          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 607          * Lets go for 8 which is the burst size since certain platforms
 608          * already use a hardcoded 8 (which is what the spec says should be
 609          * done).
 610          */
 611         if (wm_size <= 8)
 612                 wm_size = 8;
 613
 614         return wm_size;
 615 }
 616
 617 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 618 {
 619         struct intel_crtc *crtc, *enabled = NULL;
 620
 621         for_each_intel_crtc(&dev_priv->drm, crtc) {
 622                 if (intel_crtc_active(crtc)) {
 623                         if (enabled)
 624                                 return NULL;
 625                         enabled = crtc;
 626                 }
 627         }
 628
 629         return enabled;
 630 }
 631
 632 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 633 {
 634         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 635         struct intel_crtc *crtc;
 636         const struct cxsr_latency *latency;
 637         u32 reg;
 638         unsigned long wm;
 639
 640         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 641                                          dev_priv->is_ddr3,
 642                                          dev_priv->fsb_freq,
 643                                          dev_priv->mem_freq);
 644         if (!latency) {
 645                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 646                 intel_set_memory_cxsr(dev_priv, false);
 647                 return;
 648         }
 649
 650         crtc = single_enabled_crtc(dev_priv);
 651         if (crtc) {
 652                 const struct drm_display_mode *adjusted_mode =
 653                         &crtc->config->base.adjusted_mode;
 654                 const struct drm_framebuffer *fb =
 655                         crtc->base.primary->state->fb;
 656                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 657                 int clock = adjusted_mode->crtc_clock;
 658
 659                 /* Display SR */
 660                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 661                                         pineview_display_wm.fifo_size,
 662                                         cpp, latency->display_sr);
 663                 reg = I915_READ(DSPFW1);
 664                 reg &= ~DSPFW_SR_MASK;
 665                 reg |= FW_WM(wm, SR);
 666                 I915_WRITE(DSPFW1, reg);
 667                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 668
 669                 /* cursor SR */
 670                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 671                                         pineview_display_wm.fifo_size,
 672                                         cpp, latency->cursor_sr);
 673                 reg = I915_READ(DSPFW3);
 674                 reg &= ~DSPFW_CURSOR_SR_MASK;
 675                 reg |= FW_WM(wm, CURSOR_SR);
 676                 I915_WRITE(DSPFW3, reg);
 677
 678                 /* Display HPLL off SR */
 679                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 680                                         pineview_display_hplloff_wm.fifo_size,
 681                                         cpp, latency->display_hpll_disable);
 682                 reg = I915_READ(DSPFW3);
 683                 reg &= ~DSPFW_HPLL_SR_MASK;
 684                 reg |= FW_WM(wm, HPLL_SR);
 685                 I915_WRITE(DSPFW3, reg);
 686
 687                 /* cursor HPLL off SR */
 688                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 689                                         pineview_display_hplloff_wm.fifo_size,
 690                                         cpp, latency->cursor_hpll_disable);
 691                 reg = I915_READ(DSPFW3);
 692                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 693                 reg |= FW_WM(wm, HPLL_CURSOR);
 694                 I915_WRITE(DSPFW3, reg);
 695                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 696
 697                 intel_set_memory_cxsr(dev_priv, true);
 698         } else {
 699                 intel_set_memory_cxsr(dev_priv, false);
 700         }
 701 }
 702
 703 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
 704                             int plane,
 705                             const struct intel_watermark_params *display,
 706                             int display_latency_ns,
 707                             const struct intel_watermark_params *cursor,
 708                             int cursor_latency_ns,
 709                             int *plane_wm,
 710                             int *cursor_wm)
 711 {
 712         struct intel_crtc *crtc;
 713         const struct drm_display_mode *adjusted_mode;
 714         const struct drm_framebuffer *fb;
 715         int htotal, hdisplay, clock, cpp;
 716         int line_time_us, line_count;
 717         int entries, tlb_miss;
 718
 719         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 720         if (!intel_crtc_active(crtc)) {
 721                 *cursor_wm = cursor->guard_size;
 722                 *plane_wm = display->guard_size;
 723                 return false;
 724         }
 725
 726         adjusted_mode = &crtc->config->base.adjusted_mode;
 727         fb = crtc->base.primary->state->fb;
 728         clock = adjusted_mode->crtc_clock;
 729         htotal = adjusted_mode->crtc_htotal;
 730         hdisplay = crtc->config->pipe_src_w;
 731         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 732
 733         /* Use the small buffer method to calculate plane watermark */
 734         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 735         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 736         if (tlb_miss > 0)
 737                 entries += tlb_miss;
 738         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 739         *plane_wm = entries + display->guard_size;
 740         if (*plane_wm > (int)display->max_wm)
 741                 *plane_wm = display->max_wm;
 742
 743         /* Use the large buffer method to calculate cursor watermark */
 744         line_time_us = max(htotal * 1000 / clock, 1);
 745         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 746         entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
 747         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 748         if (tlb_miss > 0)
 749                 entries += tlb_miss;
 750         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 751         *cursor_wm = entries + cursor->guard_size;
 752         if (*cursor_wm > (int)cursor->max_wm)
 753                 *cursor_wm = (int)cursor->max_wm;
 754
 755         return true;
 756 }
 757
 758 /*
 759  * Check the wm result.
 760  *
 761  * If any calculated watermark values is larger than the maximum value that
 762  * can be programmed into the associated watermark register, that watermark
 763  * must be disabled.
 764  */
 765 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
 766                            int display_wm, int cursor_wm,
 767                            const struct intel_watermark_params *display,
 768                            const struct intel_watermark_params *cursor)
 769 {
 770         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 771                       display_wm, cursor_wm);
 772
 773         if (display_wm > display->max_wm) {
 774                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 775                               display_wm, display->max_wm);
 776                 return false;
 777         }
 778
 779         if (cursor_wm > cursor->max_wm) {
 780                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 781                               cursor_wm, cursor->max_wm);
 782                 return false;
 783         }
 784
 785         if (!(display_wm || cursor_wm)) {
 786                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 787                 return false;
 788         }
 789
 790         return true;
 791 }
 792
 793 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
 794                              int plane,
 795                              int latency_ns,
 796                              const struct intel_watermark_params *display,
 797                              const struct intel_watermark_params *cursor,
 798                              int *display_wm, int *cursor_wm)
 799 {
 800         struct intel_crtc *crtc;
 801         const struct drm_display_mode *adjusted_mode;
 802         const struct drm_framebuffer *fb;
 803         int hdisplay, htotal, cpp, clock;
 804         unsigned long line_time_us;
 805         int line_count, line_size;
 806         int small, large;
 807         int entries;
 808
 809         if (!latency_ns) {
 810                 *display_wm = *cursor_wm = 0;
 811                 return false;
 812         }
 813
 814         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 815         adjusted_mode = &crtc->config->base.adjusted_mode;
 816         fb = crtc->base.primary->state->fb;
 817         clock = adjusted_mode->crtc_clock;
 818         htotal = adjusted_mode->crtc_htotal;
 819         hdisplay = crtc->config->pipe_src_w;
 820         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 821
 822         line_time_us = max(htotal * 1000 / clock, 1);
 823         line_count = (latency_ns / line_time_us + 1000) / 1000;
 824         line_size = hdisplay * cpp;
 825
 826         /* Use the minimum of the small and large buffer method for primary */
 827         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 828         large = line_count * line_size;
 829
 830         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 831         *display_wm = entries + display->guard_size;
 832
 833         /* calculate the self-refresh watermark for display cursor */
 834         entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
 835         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 836         *cursor_wm = entries + cursor->guard_size;
 837
 838         return g4x_check_srwm(dev_priv,
 839                               *display_wm, *cursor_wm,
 840                               display, cursor);
 841 }
 842
 843 #define FW_WM_VLV(value, plane) \
 844         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 845
 846 static void vlv_write_wm_values(struct intel_crtc *crtc,
 847                                 const struct vlv_wm_values *wm)
 848 {
 849         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 850         enum pipe pipe = crtc->pipe;
 851
 852         I915_WRITE(VLV_DDL(pipe),
 853                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 854                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 855                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 856                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 857
 858         I915_WRITE(DSPFW1,
 859                    FW_WM(wm->sr.plane, SR) |
 860                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 861                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 862                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 863         I915_WRITE(DSPFW2,
 864                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 865                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 866                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 867         I915_WRITE(DSPFW3,
 868                    FW_WM(wm->sr.cursor, CURSOR_SR));
 869
 870         if (IS_CHERRYVIEW(dev_priv)) {
 871                 I915_WRITE(DSPFW7_CHV,
 872                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 873                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 874                 I915_WRITE(DSPFW8_CHV,
 875                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 876                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 877                 I915_WRITE(DSPFW9_CHV,
 878                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 879                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 880                 I915_WRITE(DSPHOWM,
 881                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 882                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 883                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 884                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 885                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 886                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 887                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 888                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 889                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 890                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 891         } else {
 892                 I915_WRITE(DSPFW7,
 893                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 894                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 895                 I915_WRITE(DSPHOWM,
 896                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 897                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 898                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 899                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 900                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 901                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 902                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 903         }
 904
 905         /* zero (unused) WM1 watermarks */
 906         I915_WRITE(DSPFW4, 0);
 907         I915_WRITE(DSPFW5, 0);
 908         I915_WRITE(DSPFW6, 0);
 909         I915_WRITE(DSPHOWM1, 0);
 910
 911         POSTING_READ(DSPFW1);
 912 }
 913
 914 #undef FW_WM_VLV
 915
 916 enum vlv_wm_level {
 917         VLV_WM_LEVEL_PM2,
 918         VLV_WM_LEVEL_PM5,
 919         VLV_WM_LEVEL_DDR_DVFS,
 920 };
 921
 922 /* latency must be in 0.1us units. */
 923 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 924                                    unsigned int pipe_htotal,
 925                                    unsigned int horiz_pixels,
 926                                    unsigned int cpp,
 927                                    unsigned int latency)
 928 {
 929         unsigned int ret;
 930
 931         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 932         ret = (ret + 1) * horiz_pixels * cpp;
 933         ret = DIV_ROUND_UP(ret, 64);
 934
 935         return ret;
 936 }
 937
 938 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
 939 {
 940         /* all latencies in usec */
 941         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 942
 943         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 944
 945         if (IS_CHERRYVIEW(dev_priv)) {
 946                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 947                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 948
 949                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 950         }
 951 }
 952
 953 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 954                                      struct intel_crtc *crtc,
 955                                      const struct intel_plane_state *state,
 956                                      int level)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 959         int clock, htotal, cpp, width, wm;
 960
 961         if (dev_priv->wm.pri_latency[level] == 0)
 962                 return USHRT_MAX;
 963
 964         if (!state->base.visible)
 965                 return 0;
 966
 967         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 968         clock = crtc->config->base.adjusted_mode.crtc_clock;
 969         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 970         width = crtc->config->pipe_src_w;
 971         if (WARN_ON(htotal == 0))
 972                 htotal = 1;
 973
 974         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 975                 /*
 976                  * FIXME the formula gives values that are
 977                  * too big for the cursor FIFO, and hence we
 978                  * would never be able to use cursors. For
 979                  * now just hardcode the watermark.
 980                  */
 981                 wm = 63;
 982         } else {
 983                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 984                                     dev_priv->wm.pri_latency[level] * 10);
 985         }
 986
 987         return min_t(int, wm, USHRT_MAX);
 988 }
 989
 990 static void vlv_compute_fifo(struct intel_crtc *crtc)
 991 {
 992         struct drm_device *dev = crtc->base.dev;
 993         struct vlv_wm_state *wm_state = &crtc->wm_state;
 994         struct intel_plane *plane;
 995         unsigned int total_rate = 0;
 996         const int fifo_size = 512 - 1;
 997         int fifo_extra, fifo_left = fifo_size;
 998
 999         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1000                 struct intel_plane_state *state =
1001                         to_intel_plane_state(plane->base.state);
1002
1003                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1004                         continue;
1005
1006                 if (state->base.visible) {
1007                         wm_state->num_active_planes++;
1008                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1009                 }
1010         }
1011
1012         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1013                 struct intel_plane_state *state =
1014                         to_intel_plane_state(plane->base.state);
1015                 unsigned int rate;
1016
1017                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1018                         plane->wm.fifo_size = 63;
1019                         continue;
1020                 }
1021
1022                 if (!state->base.visible) {
1023                         plane->wm.fifo_size = 0;
1024                         continue;
1025                 }
1026
1027                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1028                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1029                 fifo_left -= plane->wm.fifo_size;
1030         }
1031
1032         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1033
1034         /* spread the remainder evenly */
1035         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1036                 int plane_extra;
1037
1038                 if (fifo_left == 0)
1039                         break;
1040
1041                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1042                         continue;
1043
1044                 /* give it all to the first plane if none are active */
1045                 if (plane->wm.fifo_size == 0 &&
1046                     wm_state->num_active_planes)
1047                         continue;
1048
1049                 plane_extra = min(fifo_extra, fifo_left);
1050                 plane->wm.fifo_size += plane_extra;
1051                 fifo_left -= plane_extra;
1052         }
1053
1054         WARN_ON(fifo_left != 0);
1055 }
1056
1057 static void vlv_invert_wms(struct intel_crtc *crtc)
1058 {
1059         struct vlv_wm_state *wm_state = &crtc->wm_state;
1060         int level;
1061
1062         for (level = 0; level < wm_state->num_levels; level++) {
1063                 struct drm_device *dev = crtc->base.dev;
1064                 const int sr_fifo_size =
1065                         INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
1066                 struct intel_plane *plane;
1067
1068                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1069                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1070
1071                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1072                         switch (plane->base.type) {
1073                                 int sprite;
1074                         case DRM_PLANE_TYPE_CURSOR:
1075                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1076                                         wm_state->wm[level].cursor;
1077                                 break;
1078                         case DRM_PLANE_TYPE_PRIMARY:
1079                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1080                                         wm_state->wm[level].primary;
1081                                 break;
1082                         case DRM_PLANE_TYPE_OVERLAY:
1083                                 sprite = plane->plane;
1084                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1085                                         wm_state->wm[level].sprite[sprite];
1086                                 break;
1087                         }
1088                 }
1089         }
1090 }
1091
1092 static void vlv_compute_wm(struct intel_crtc *crtc)
1093 {
1094         struct drm_device *dev = crtc->base.dev;
1095         struct drm_i915_private *dev_priv = to_i915(dev);
1096         struct vlv_wm_state *wm_state = &crtc->wm_state;
1097         struct intel_plane *plane;
1098         int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1099         int level;
1100
1101         memset(wm_state, 0, sizeof(*wm_state));
1102
1103         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1104         wm_state->num_levels = dev_priv->wm.max_level + 1;
1105
1106         wm_state->num_active_planes = 0;
1107
1108         vlv_compute_fifo(crtc);
1109
1110         if (wm_state->num_active_planes != 1)
1111                 wm_state->cxsr = false;
1112
1113         if (wm_state->cxsr) {
1114                 for (level = 0; level < wm_state->num_levels; level++) {
1115                         wm_state->sr[level].plane = sr_fifo_size;
1116                         wm_state->sr[level].cursor = 63;
1117                 }
1118         }
1119
1120         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1121                 struct intel_plane_state *state =
1122                         to_intel_plane_state(plane->base.state);
1123
1124                 if (!state->base.visible)
1125                         continue;
1126
1127                 /* normal watermarks */
1128                 for (level = 0; level < wm_state->num_levels; level++) {
1129                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1130                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1131
1132                         /* hack */
1133                         if (WARN_ON(level == 0 && wm > max_wm))
1134                                 wm = max_wm;
1135
1136                         if (wm > plane->wm.fifo_size)
1137                                 break;
1138
1139                         switch (plane->base.type) {
1140                                 int sprite;
1141                         case DRM_PLANE_TYPE_CURSOR:
1142                                 wm_state->wm[level].cursor = wm;
1143                                 break;
1144                         case DRM_PLANE_TYPE_PRIMARY:
1145                                 wm_state->wm[level].primary = wm;
1146                                 break;
1147                         case DRM_PLANE_TYPE_OVERLAY:
1148                                 sprite = plane->plane;
1149                                 wm_state->wm[level].sprite[sprite] = wm;
1150                                 break;
1151                         }
1152                 }
1153
1154                 wm_state->num_levels = level;
1155
1156                 if (!wm_state->cxsr)
1157                         continue;
1158
1159                 /* maxfifo watermarks */
1160                 switch (plane->base.type) {
1161                         int sprite, level;
1162                 case DRM_PLANE_TYPE_CURSOR:
1163                         for (level = 0; level < wm_state->num_levels; level++)
1164                                 wm_state->sr[level].cursor =
1165                                         wm_state->wm[level].cursor;
1166                         break;
1167                 case DRM_PLANE_TYPE_PRIMARY:
1168                         for (level = 0; level < wm_state->num_levels; level++)
1169                                 wm_state->sr[level].plane =
1170                                         min(wm_state->sr[level].plane,
1171                                             wm_state->wm[level].primary);
1172                         break;
1173                 case DRM_PLANE_TYPE_OVERLAY:
1174                         sprite = plane->plane;
1175                         for (level = 0; level < wm_state->num_levels; level++)
1176                                 wm_state->sr[level].plane =
1177                                         min(wm_state->sr[level].plane,
1178                                             wm_state->wm[level].sprite[sprite]);
1179                         break;
1180                 }
1181         }
1182
1183         /* clear any (partially) filled invalid levels */
1184         for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
1185                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1186                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1187         }
1188
1189         vlv_invert_wms(crtc);
1190 }
1191
1192 #define VLV_FIFO(plane, value) \
1193         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1194
1195 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1196 {
1197         struct drm_device *dev = crtc->base.dev;
1198         struct drm_i915_private *dev_priv = to_i915(dev);
1199         struct intel_plane *plane;
1200         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1201
1202         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1203                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1204                         WARN_ON(plane->wm.fifo_size != 63);
1205                         continue;
1206                 }
1207
1208                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1209                         sprite0_start = plane->wm.fifo_size;
1210                 else if (plane->plane == 0)
1211                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1212                 else
1213                         fifo_size = sprite1_start + plane->wm.fifo_size;
1214         }
1215
1216         WARN_ON(fifo_size != 512 - 1);
1217
1218         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1219                       pipe_name(crtc->pipe), sprite0_start,
1220                       sprite1_start, fifo_size);
1221
1222         switch (crtc->pipe) {
1223                 uint32_t dsparb, dsparb2, dsparb3;
1224         case PIPE_A:
1225                 dsparb = I915_READ(DSPARB);
1226                 dsparb2 = I915_READ(DSPARB2);
1227
1228                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1229                             VLV_FIFO(SPRITEB, 0xff));
1230                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1231                            VLV_FIFO(SPRITEB, sprite1_start));
1232
1233                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1234                              VLV_FIFO(SPRITEB_HI, 0x1));
1235                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1236                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1237
1238                 I915_WRITE(DSPARB, dsparb);
1239                 I915_WRITE(DSPARB2, dsparb2);
1240                 break;
1241         case PIPE_B:
1242                 dsparb = I915_READ(DSPARB);
1243                 dsparb2 = I915_READ(DSPARB2);
1244
1245                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1246                             VLV_FIFO(SPRITED, 0xff));
1247                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1248                            VLV_FIFO(SPRITED, sprite1_start));
1249
1250                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1251                              VLV_FIFO(SPRITED_HI, 0xff));
1252                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1253                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1254
1255                 I915_WRITE(DSPARB, dsparb);
1256                 I915_WRITE(DSPARB2, dsparb2);
1257                 break;
1258         case PIPE_C:
1259                 dsparb3 = I915_READ(DSPARB3);
1260                 dsparb2 = I915_READ(DSPARB2);
1261
1262                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1263                              VLV_FIFO(SPRITEF, 0xff));
1264                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1265                             VLV_FIFO(SPRITEF, sprite1_start));
1266
1267                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1268                              VLV_FIFO(SPRITEF_HI, 0xff));
1269                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1270                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1271
1272                 I915_WRITE(DSPARB3, dsparb3);
1273                 I915_WRITE(DSPARB2, dsparb2);
1274                 break;
1275         default:
1276                 break;
1277         }
1278 }
1279
1280 #undef VLV_FIFO
1281
1282 static void vlv_merge_wm(struct drm_device *dev,
1283                          struct vlv_wm_values *wm)
1284 {
1285         struct intel_crtc *crtc;
1286         int num_active_crtcs = 0;
1287
1288         wm->level = to_i915(dev)->wm.max_level;
1289         wm->cxsr = true;
1290
1291         for_each_intel_crtc(dev, crtc) {
1292                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1293
1294                 if (!crtc->active)
1295                         continue;
1296
1297                 if (!wm_state->cxsr)
1298                         wm->cxsr = false;
1299
1300                 num_active_crtcs++;
1301                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1302         }
1303
1304         if (num_active_crtcs != 1)
1305                 wm->cxsr = false;
1306
1307         if (num_active_crtcs > 1)
1308                 wm->level = VLV_WM_LEVEL_PM2;
1309
1310         for_each_intel_crtc(dev, crtc) {
1311                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1312                 enum pipe pipe = crtc->pipe;
1313
1314                 if (!crtc->active)
1315                         continue;
1316
1317                 wm->pipe[pipe] = wm_state->wm[wm->level];
1318                 if (wm->cxsr)
1319                         wm->sr = wm_state->sr[wm->level];
1320
1321                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1322                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1323                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1324                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1325         }
1326 }
1327
1328 static void vlv_update_wm(struct intel_crtc *crtc)
1329 {
1330         struct drm_device *dev = crtc->base.dev;
1331         struct drm_i915_private *dev_priv = to_i915(dev);
1332         enum pipe pipe = crtc->pipe;
1333         struct vlv_wm_values wm = {};
1334
1335         vlv_compute_wm(crtc);
1336         vlv_merge_wm(dev, &wm);
1337
1338         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1339                 /* FIXME should be part of crtc atomic commit */
1340                 vlv_pipe_set_fifo_size(crtc);
1341                 return;
1342         }
1343
1344         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1345             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1346                 chv_set_memory_dvfs(dev_priv, false);
1347
1348         if (wm.level < VLV_WM_LEVEL_PM5 &&
1349             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1350                 chv_set_memory_pm5(dev_priv, false);
1351
1352         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1353                 intel_set_memory_cxsr(dev_priv, false);
1354
1355         /* FIXME should be part of crtc atomic commit */
1356         vlv_pipe_set_fifo_size(crtc);
1357
1358         vlv_write_wm_values(crtc, &wm);
1359
1360         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1361                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1362                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1363                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1364                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1365
1366         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1367                 intel_set_memory_cxsr(dev_priv, true);
1368
1369         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1370             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1371                 chv_set_memory_pm5(dev_priv, true);
1372
1373         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1374             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1375                 chv_set_memory_dvfs(dev_priv, true);
1376
1377         dev_priv->wm.vlv = wm;
1378 }
1379
1380 #define single_plane_enabled(mask) is_power_of_2(mask)
1381
1382 static void g4x_update_wm(struct intel_crtc *crtc)
1383 {
1384         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1385         static const int sr_latency_ns = 12000;
1386         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1387         int plane_sr, cursor_sr;
1388         unsigned int enabled = 0;
1389         bool cxsr_enabled;
1390
1391         if (g4x_compute_wm0(dev_priv, PIPE_A,
1392                             &g4x_wm_info, pessimal_latency_ns,
1393                             &g4x_cursor_wm_info, pessimal_latency_ns,
1394                             &planea_wm, &cursora_wm))
1395                 enabled |= 1 << PIPE_A;
1396
1397         if (g4x_compute_wm0(dev_priv, PIPE_B,
1398                             &g4x_wm_info, pessimal_latency_ns,
1399                             &g4x_cursor_wm_info, pessimal_latency_ns,
1400                             &planeb_wm, &cursorb_wm))
1401                 enabled |= 1 << PIPE_B;
1402
1403         if (single_plane_enabled(enabled) &&
1404             g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1405                              sr_latency_ns,
1406                              &g4x_wm_info,
1407                              &g4x_cursor_wm_info,
1408                              &plane_sr, &cursor_sr)) {
1409                 cxsr_enabled = true;
1410         } else {
1411                 cxsr_enabled = false;
1412                 intel_set_memory_cxsr(dev_priv, false);
1413                 plane_sr = cursor_sr = 0;
1414         }
1415
1416         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1417                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1418                       planea_wm, cursora_wm,
1419                       planeb_wm, cursorb_wm,
1420                       plane_sr, cursor_sr);
1421
1422         I915_WRITE(DSPFW1,
1423                    FW_WM(plane_sr, SR) |
1424                    FW_WM(cursorb_wm, CURSORB) |
1425                    FW_WM(planeb_wm, PLANEB) |
1426                    FW_WM(planea_wm, PLANEA));
1427         I915_WRITE(DSPFW2,
1428                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1429                    FW_WM(cursora_wm, CURSORA));
1430         /* HPLL off in SR has some issues on G4x... disable it */
1431         I915_WRITE(DSPFW3,
1432                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1433                    FW_WM(cursor_sr, CURSOR_SR));
1434
1435         if (cxsr_enabled)
1436                 intel_set_memory_cxsr(dev_priv, true);
1437 }
1438
1439 static void i965_update_wm(struct intel_crtc *unused_crtc)
1440 {
1441         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1442         struct intel_crtc *crtc;
1443         int srwm = 1;
1444         int cursor_sr = 16;
1445         bool cxsr_enabled;
1446
1447         /* Calc sr entries for one plane configs */
1448         crtc = single_enabled_crtc(dev_priv);
1449         if (crtc) {
1450                 /* self-refresh has much higher latency */
1451                 static const int sr_latency_ns = 12000;
1452                 const struct drm_display_mode *adjusted_mode =
1453                         &crtc->config->base.adjusted_mode;
1454                 const struct drm_framebuffer *fb =
1455                         crtc->base.primary->state->fb;
1456                 int clock = adjusted_mode->crtc_clock;
1457                 int htotal = adjusted_mode->crtc_htotal;
1458                 int hdisplay = crtc->config->pipe_src_w;
1459                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1460                 unsigned long line_time_us;
1461                 int entries;
1462
1463                 line_time_us = max(htotal * 1000 / clock, 1);
1464
1465                 /* Use ns/us then divide to preserve precision */
1466                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1467                         cpp * hdisplay;
1468                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1469                 srwm = I965_FIFO_SIZE - entries;
1470                 if (srwm < 0)
1471                         srwm = 1;
1472                 srwm &= 0x1ff;
1473                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1474                               entries, srwm);
1475
1476                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1477                         cpp * crtc->base.cursor->state->crtc_w;
1478                 entries = DIV_ROUND_UP(entries,
1479                                           i965_cursor_wm_info.cacheline_size);
1480                 cursor_sr = i965_cursor_wm_info.fifo_size -
1481                         (entries + i965_cursor_wm_info.guard_size);
1482
1483                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1484                         cursor_sr = i965_cursor_wm_info.max_wm;
1485
1486                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1487                               "cursor %d\n", srwm, cursor_sr);
1488
1489                 cxsr_enabled = true;
1490         } else {
1491                 cxsr_enabled = false;
1492                 /* Turn off self refresh if both pipes are enabled */
1493                 intel_set_memory_cxsr(dev_priv, false);
1494         }
1495
1496         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1497                       srwm);
1498
1499         /* 965 has limitations... */
1500         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1501                    FW_WM(8, CURSORB) |
1502                    FW_WM(8, PLANEB) |
1503                    FW_WM(8, PLANEA));
1504         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1505                    FW_WM(8, PLANEC_OLD));
1506         /* update cursor SR watermark */
1507         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1508
1509         if (cxsr_enabled)
1510                 intel_set_memory_cxsr(dev_priv, true);
1511 }
1512
1513 #undef FW_WM
1514
1515 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1516 {
1517         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1518         const struct intel_watermark_params *wm_info;
1519         uint32_t fwater_lo;
1520         uint32_t fwater_hi;
1521         int cwm, srwm = 1;
1522         int fifo_size;
1523         int planea_wm, planeb_wm;
1524         struct intel_crtc *crtc, *enabled = NULL;
1525
1526         if (IS_I945GM(dev_priv))
1527                 wm_info = &i945_wm_info;
1528         else if (!IS_GEN2(dev_priv))
1529                 wm_info = &i915_wm_info;
1530         else
1531                 wm_info = &i830_a_wm_info;
1532
1533         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1534         crtc = intel_get_crtc_for_plane(dev_priv, 0);
1535         if (intel_crtc_active(crtc)) {
1536                 const struct drm_display_mode *adjusted_mode =
1537                         &crtc->config->base.adjusted_mode;
1538                 const struct drm_framebuffer *fb =
1539                         crtc->base.primary->state->fb;
1540                 int cpp;
1541
1542                 if (IS_GEN2(dev_priv))
1543                         cpp = 4;
1544                 else
1545                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1546
1547                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1548                                                wm_info, fifo_size, cpp,
1549                                                pessimal_latency_ns);
1550                 enabled = crtc;
1551         } else {
1552                 planea_wm = fifo_size - wm_info->guard_size;
1553                 if (planea_wm > (long)wm_info->max_wm)
1554                         planea_wm = wm_info->max_wm;
1555         }
1556
1557         if (IS_GEN2(dev_priv))
1558                 wm_info = &i830_bc_wm_info;
1559
1560         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1561         crtc = intel_get_crtc_for_plane(dev_priv, 1);
1562         if (intel_crtc_active(crtc)) {
1563                 const struct drm_display_mode *adjusted_mode =
1564                         &crtc->config->base.adjusted_mode;
1565                 const struct drm_framebuffer *fb =
1566                         crtc->base.primary->state->fb;
1567                 int cpp;
1568
1569                 if (IS_GEN2(dev_priv))
1570                         cpp = 4;
1571                 else
1572                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1573
1574                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1575                                                wm_info, fifo_size, cpp,
1576                                                pessimal_latency_ns);
1577                 if (enabled == NULL)
1578                         enabled = crtc;
1579                 else
1580                         enabled = NULL;
1581         } else {
1582                 planeb_wm = fifo_size - wm_info->guard_size;
1583                 if (planeb_wm > (long)wm_info->max_wm)
1584                         planeb_wm = wm_info->max_wm;
1585         }
1586
1587         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1588
1589         if (IS_I915GM(dev_priv) && enabled) {
1590                 struct drm_i915_gem_object *obj;
1591
1592                 obj = intel_fb_obj(enabled->base.primary->state->fb);
1593
1594                 /* self-refresh seems busted with untiled */
1595                 if (!i915_gem_object_is_tiled(obj))
1596                         enabled = NULL;
1597         }
1598
1599         /*
1600          * Overlay gets an aggressive default since video jitter is bad.
1601          */
1602         cwm = 2;
1603
1604         /* Play safe and disable self-refresh before adjusting watermarks. */
1605         intel_set_memory_cxsr(dev_priv, false);
1606
1607         /* Calc sr entries for one plane configs */
1608         if (HAS_FW_BLC(dev_priv) && enabled) {
1609                 /* self-refresh has much higher latency */
1610                 static const int sr_latency_ns = 6000;
1611                 const struct drm_display_mode *adjusted_mode =
1612                         &enabled->config->base.adjusted_mode;
1613                 const struct drm_framebuffer *fb =
1614                         enabled->base.primary->state->fb;
1615                 int clock = adjusted_mode->crtc_clock;
1616                 int htotal = adjusted_mode->crtc_htotal;
1617                 int hdisplay = enabled->config->pipe_src_w;
1618                 int cpp;
1619                 unsigned long line_time_us;
1620                 int entries;
1621
1622                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1623                         cpp = 4;
1624                 else
1625                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1626
1627                 line_time_us = max(htotal * 1000 / clock, 1);
1628
1629                 /* Use ns/us then divide to preserve precision */
1630                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1631                         cpp * hdisplay;
1632                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1633                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1634                 srwm = wm_info->fifo_size - entries;
1635                 if (srwm < 0)
1636                         srwm = 1;
1637
1638                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1639                         I915_WRITE(FW_BLC_SELF,
1640                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1641                 else
1642                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1643         }
1644
1645         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1646                       planea_wm, planeb_wm, cwm, srwm);
1647
1648         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1649         fwater_hi = (cwm & 0x1f);
1650
1651         /* Set request length to 8 cachelines per fetch */
1652         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1653         fwater_hi = fwater_hi | (1 << 8);
1654
1655         I915_WRITE(FW_BLC, fwater_lo);
1656         I915_WRITE(FW_BLC2, fwater_hi);
1657
1658         if (enabled)
1659                 intel_set_memory_cxsr(dev_priv, true);
1660 }
1661
1662 static void i845_update_wm(struct intel_crtc *unused_crtc)
1663 {
1664         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1665         struct intel_crtc *crtc;
1666         const struct drm_display_mode *adjusted_mode;
1667         uint32_t fwater_lo;
1668         int planea_wm;
1669
1670         crtc = single_enabled_crtc(dev_priv);
1671         if (crtc == NULL)
1672                 return;
1673
1674         adjusted_mode = &crtc->config->base.adjusted_mode;
1675         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1676                                        &i845_wm_info,
1677                                        dev_priv->display.get_fifo_size(dev_priv, 0),
1678                                        4, pessimal_latency_ns);
1679         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1680         fwater_lo |= (3<<8) | planea_wm;
1681
1682         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1683
1684         I915_WRITE(FW_BLC, fwater_lo);
1685 }
1686
1687 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1688 {
1689         uint32_t pixel_rate;
1690
1691         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1692
1693         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1694          * adjust the pixel_rate here. */
1695
1696         if (pipe_config->pch_pfit.enabled) {
1697                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1698                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1699
1700                 pipe_w = pipe_config->pipe_src_w;
1701                 pipe_h = pipe_config->pipe_src_h;
1702
1703                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1704                 pfit_h = pfit_size & 0xFFFF;
1705                 if (pipe_w < pfit_w)
1706                         pipe_w = pfit_w;
1707                 if (pipe_h < pfit_h)
1708                         pipe_h = pfit_h;
1709
1710                 if (WARN_ON(!pfit_w || !pfit_h))
1711                         return pixel_rate;
1712
1713                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1714                                      pfit_w * pfit_h);
1715         }
1716
1717         return pixel_rate;
1718 }
1719
1720 /* latency must be in 0.1us units. */
1721 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1722 {
1723         uint64_t ret;
1724
1725         if (WARN(latency == 0, "Latency value missing\n"))
1726                 return UINT_MAX;
1727
1728         ret = (uint64_t) pixel_rate * cpp * latency;
1729         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1730
1731         return ret;
1732 }
1733
1734 /* latency must be in 0.1us units. */
1735 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1736                                uint32_t horiz_pixels, uint8_t cpp,
1737                                uint32_t latency)
1738 {
1739         uint32_t ret;
1740
1741         if (WARN(latency == 0, "Latency value missing\n"))
1742                 return UINT_MAX;
1743         if (WARN_ON(!pipe_htotal))
1744                 return UINT_MAX;
1745
1746         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1747         ret = (ret + 1) * horiz_pixels * cpp;
1748         ret = DIV_ROUND_UP(ret, 64) + 2;
1749         return ret;
1750 }
1751
1752 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1753                            uint8_t cpp)
1754 {
1755         /*
1756          * Neither of these should be possible since this function shouldn't be
1757          * called if the CRTC is off or the plane is invisible.  But let's be
1758          * extra paranoid to avoid a potential divide-by-zero if we screw up
1759          * elsewhere in the driver.
1760          */
1761         if (WARN_ON(!cpp))
1762                 return 0;
1763         if (WARN_ON(!horiz_pixels))
1764                 return 0;
1765
1766         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1767 }
1768
1769 struct ilk_wm_maximums {
1770         uint16_t pri;
1771         uint16_t spr;
1772         uint16_t cur;
1773         uint16_t fbc;
1774 };
1775
1776 /*
1777  * For both WM_PIPE and WM_LP.
1778  * mem_value must be in 0.1us units.
1779  */
1780 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1781                                    const struct intel_plane_state *pstate,
1782                                    uint32_t mem_value,
1783                                    bool is_lp)
1784 {
1785         int cpp = pstate->base.fb ?
1786                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1787         uint32_t method1, method2;
1788
1789         if (!cstate->base.active || !pstate->base.visible)
1790                 return 0;
1791
1792         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1793
1794         if (!is_lp)
1795                 return method1;
1796
1797         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1798                                  cstate->base.adjusted_mode.crtc_htotal,
1799                                  drm_rect_width(&pstate->base.dst),
1800                                  cpp, mem_value);
1801
1802         return min(method1, method2);
1803 }
1804
1805 /*
1806  * For both WM_PIPE and WM_LP.
1807  * mem_value must be in 0.1us units.
1808  */
1809 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1810                                    const struct intel_plane_state *pstate,
1811                                    uint32_t mem_value)
1812 {
1813         int cpp = pstate->base.fb ?
1814                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1815         uint32_t method1, method2;
1816
1817         if (!cstate->base.active || !pstate->base.visible)
1818                 return 0;
1819
1820         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1821         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1822                                  cstate->base.adjusted_mode.crtc_htotal,
1823                                  drm_rect_width(&pstate->base.dst),
1824                                  cpp, mem_value);
1825         return min(method1, method2);
1826 }
1827
1828 /*
1829  * For both WM_PIPE and WM_LP.
1830  * mem_value must be in 0.1us units.
1831  */
1832 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1833                                    const struct intel_plane_state *pstate,
1834                                    uint32_t mem_value)
1835 {
1836         /*
1837          * We treat the cursor plane as always-on for the purposes of watermark
1838          * calculation.  Until we have two-stage watermark programming merged,
1839          * this is necessary to avoid flickering.
1840          */
1841         int cpp = 4;
1842         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1843
1844         if (!cstate->base.active)
1845                 return 0;
1846
1847         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1848                               cstate->base.adjusted_mode.crtc_htotal,
1849                               width, cpp, mem_value);
1850 }
1851
1852 /* Only for WM_LP. */
1853 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1854                                    const struct intel_plane_state *pstate,
1855                                    uint32_t pri_val)
1856 {
1857         int cpp = pstate->base.fb ?
1858                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1859
1860         if (!cstate->base.active || !pstate->base.visible)
1861                 return 0;
1862
1863         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1864 }
1865
1866 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1867 {
1868         if (INTEL_INFO(dev)->gen >= 8)
1869                 return 3072;
1870         else if (INTEL_INFO(dev)->gen >= 7)
1871                 return 768;
1872         else
1873                 return 512;
1874 }
1875
1876 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1877                                          int level, bool is_sprite)
1878 {
1879         if (INTEL_INFO(dev)->gen >= 8)
1880                 /* BDW primary/sprite plane watermarks */
1881                 return level == 0 ? 255 : 2047;
1882         else if (INTEL_INFO(dev)->gen >= 7)
1883                 /* IVB/HSW primary/sprite plane watermarks */
1884                 return level == 0 ? 127 : 1023;
1885         else if (!is_sprite)
1886                 /* ILK/SNB primary plane watermarks */
1887                 return level == 0 ? 127 : 511;
1888         else
1889                 /* ILK/SNB sprite plane watermarks */
1890                 return level == 0 ? 63 : 255;
1891 }
1892
1893 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1894                                           int level)
1895 {
1896         if (INTEL_INFO(dev)->gen >= 7)
1897                 return level == 0 ? 63 : 255;
1898         else
1899                 return level == 0 ? 31 : 63;
1900 }
1901
1902 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1903 {
1904         if (INTEL_INFO(dev)->gen >= 8)
1905                 return 31;
1906         else
1907                 return 15;
1908 }
1909
1910 /* Calculate the maximum primary/sprite plane watermark */
1911 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1912                                      int level,
1913                                      const struct intel_wm_config *config,
1914                                      enum intel_ddb_partitioning ddb_partitioning,
1915                                      bool is_sprite)
1916 {
1917         unsigned int fifo_size = ilk_display_fifo_size(dev);
1918
1919         /* if sprites aren't enabled, sprites get nothing */
1920         if (is_sprite && !config->sprites_enabled)
1921                 return 0;
1922
1923         /* HSW allows LP1+ watermarks even with multiple pipes */
1924         if (level == 0 || config->num_pipes_active > 1) {
1925                 fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
1926
1927                 /*
1928                  * For some reason the non self refresh
1929                  * FIFO size is only half of the self
1930                  * refresh FIFO size on ILK/SNB.
1931                  */
1932                 if (INTEL_INFO(dev)->gen <= 6)
1933                         fifo_size /= 2;
1934         }
1935
1936         if (config->sprites_enabled) {
1937                 /* level 0 is always calculated with 1:1 split */
1938                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1939                         if (is_sprite)
1940                                 fifo_size *= 5;
1941                         fifo_size /= 6;
1942                 } else {
1943                         fifo_size /= 2;
1944                 }
1945         }
1946
1947         /* clamp to max that the registers can hold */
1948         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1949 }
1950
1951 /* Calculate the maximum cursor plane watermark */
1952 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1953                                       int level,
1954                                       const struct intel_wm_config *config)
1955 {
1956         /* HSW LP1+ watermarks w/ multiple pipes */
1957         if (level > 0 && config->num_pipes_active > 1)
1958                 return 64;
1959
1960         /* otherwise just report max that registers can hold */
1961         return ilk_cursor_wm_reg_max(dev, level);
1962 }
1963
1964 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1965                                     int level,
1966                                     const struct intel_wm_config *config,
1967                                     enum intel_ddb_partitioning ddb_partitioning,
1968                                     struct ilk_wm_maximums *max)
1969 {
1970         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1971         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1972         max->cur = ilk_cursor_wm_max(dev, level, config);
1973         max->fbc = ilk_fbc_wm_reg_max(dev);
1974 }
1975
1976 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1977                                         int level,
1978                                         struct ilk_wm_maximums *max)
1979 {
1980         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1981         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1982         max->cur = ilk_cursor_wm_reg_max(dev, level);
1983         max->fbc = ilk_fbc_wm_reg_max(dev);
1984 }
1985
1986 static bool ilk_validate_wm_level(int level,
1987                                   const struct ilk_wm_maximums *max,
1988                                   struct intel_wm_level *result)
1989 {
1990         bool ret;
1991
1992         /* already determined to be invalid? */
1993         if (!result->enable)
1994                 return false;
1995
1996         result->enable = result->pri_val <= max->pri &&
1997                          result->spr_val <= max->spr &&
1998                          result->cur_val <= max->cur;
1999
2000         ret = result->enable;
2001
2002         /*
2003          * HACK until we can pre-compute everything,
2004          * and thus fail gracefully if LP0 watermarks
2005          * are exceeded...
2006          */
2007         if (level == 0 && !result->enable) {
2008                 if (result->pri_val > max->pri)
2009                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2010                                       level, result->pri_val, max->pri);
2011                 if (result->spr_val > max->spr)
2012                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2013                                       level, result->spr_val, max->spr);
2014                 if (result->cur_val > max->cur)
2015                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2016                                       level, result->cur_val, max->cur);
2017
2018                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2019                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2020                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2021                 result->enable = true;
2022         }
2023
2024         return ret;
2025 }
2026
2027 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2028                                  const struct intel_crtc *intel_crtc,
2029                                  int level,
2030                                  struct intel_crtc_state *cstate,
2031                                  struct intel_plane_state *pristate,
2032                                  struct intel_plane_state *sprstate,
2033                                  struct intel_plane_state *curstate,
2034                                  struct intel_wm_level *result)
2035 {
2036         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2037         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2038         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2039
2040         /* WM1+ latency values stored in 0.5us units */
2041         if (level > 0) {
2042                 pri_latency *= 5;
2043                 spr_latency *= 5;
2044                 cur_latency *= 5;
2045         }
2046
2047         if (pristate) {
2048                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2049                                                      pri_latency, level);
2050                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2051         }
2052
2053         if (sprstate)
2054                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2055
2056         if (curstate)
2057                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2058
2059         result->enable = true;
2060 }
2061
2062 static uint32_t
2063 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2064 {
2065         const struct intel_atomic_state *intel_state =
2066                 to_intel_atomic_state(cstate->base.state);
2067         const struct drm_display_mode *adjusted_mode =
2068                 &cstate->base.adjusted_mode;
2069         u32 linetime, ips_linetime;
2070
2071         if (!cstate->base.active)
2072                 return 0;
2073         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2074                 return 0;
2075         if (WARN_ON(intel_state->cdclk == 0))
2076                 return 0;
2077
2078         /* The WM are computed with base on how long it takes to fill a single
2079          * row at the given clock rate, multiplied by 8.
2080          * */
2081         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2082                                      adjusted_mode->crtc_clock);
2083         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2084                                          intel_state->cdclk);
2085
2086         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2087                PIPE_WM_LINETIME_TIME(linetime);
2088 }
2089
2090 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2091                                   uint16_t wm[8])
2092 {
2093         if (IS_GEN9(dev_priv)) {
2094                 uint32_t val;
2095                 int ret, i;
2096                 int level, max_level = ilk_wm_max_level(dev_priv);
2097
2098                 /* read the first set of memory latencies[0:3] */
2099                 val = 0; /* data0 to be programmed to 0 for first set */
2100                 mutex_lock(&dev_priv->rps.hw_lock);
2101                 ret = sandybridge_pcode_read(dev_priv,
2102                                              GEN9_PCODE_READ_MEM_LATENCY,
2103                                              &val);
2104                 mutex_unlock(&dev_priv->rps.hw_lock);
2105
2106                 if (ret) {
2107                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2108                         return;
2109                 }
2110
2111                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2112                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2113                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2114                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2115                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2116                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2117                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2118
2119                 /* read the second set of memory latencies[4:7] */
2120                 val = 1; /* data0 to be programmed to 1 for second set */
2121                 mutex_lock(&dev_priv->rps.hw_lock);
2122                 ret = sandybridge_pcode_read(dev_priv,
2123                                              GEN9_PCODE_READ_MEM_LATENCY,
2124                                              &val);
2125                 mutex_unlock(&dev_priv->rps.hw_lock);
2126                 if (ret) {
2127                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2128                         return;
2129                 }
2130
2131                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2132                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2133                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2134                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2135                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2136                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2137                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2138
2139                 /*
2140                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2141                  * need to be disabled. We make sure to sanitize the values out
2142                  * of the punit to satisfy this requirement.
2143                  */
2144                 for (level = 1; level <= max_level; level++) {
2145                         if (wm[level] == 0) {
2146                                 for (i = level + 1; i <= max_level; i++)
2147                                         wm[i] = 0;
2148                                 break;
2149                         }
2150                 }
2151
2152                 /*
2153                  * WaWmMemoryReadLatency:skl
2154                  *
2155                  * punit doesn't take into account the read latency so we need
2156                  * to add 2us to the various latency levels we retrieve from the
2157                  * punit when level 0 response data us 0us.
2158                  */
2159                 if (wm[0] == 0) {
2160                         wm[0] += 2;
2161                         for (level = 1; level <= max_level; level++) {
2162                                 if (wm[level] == 0)
2163                                         break;
2164                                 wm[level] += 2;
2165                         }
2166                 }
2167
2168         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2169                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2170
2171                 wm[0] = (sskpd >> 56) & 0xFF;
2172                 if (wm[0] == 0)
2173                         wm[0] = sskpd & 0xF;
2174                 wm[1] = (sskpd >> 4) & 0xFF;
2175                 wm[2] = (sskpd >> 12) & 0xFF;
2176                 wm[3] = (sskpd >> 20) & 0x1FF;
2177                 wm[4] = (sskpd >> 32) & 0x1FF;
2178         } else if (INTEL_GEN(dev_priv) >= 6) {
2179                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2180
2181                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2182                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2183                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2184                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2185         } else if (INTEL_GEN(dev_priv) >= 5) {
2186                 uint32_t mltr = I915_READ(MLTR_ILK);
2187
2188                 /* ILK primary LP0 latency is 700 ns */
2189                 wm[0] = 7;
2190                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2191                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2192         }
2193 }
2194
2195 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2196                                        uint16_t wm[5])
2197 {
2198         /* ILK sprite LP0 latency is 1300 ns */
2199         if (IS_GEN5(dev_priv))
2200                 wm[0] = 13;
2201 }
2202
2203 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2204                                        uint16_t wm[5])
2205 {
2206         /* ILK cursor LP0 latency is 1300 ns */
2207         if (IS_GEN5(dev_priv))
2208                 wm[0] = 13;
2209
2210         /* WaDoubleCursorLP3Latency:ivb */
2211         if (IS_IVYBRIDGE(dev_priv))
2212                 wm[3] *= 2;
2213 }
2214
2215 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2216 {
2217         /* how many WM levels are we expecting */
2218         if (INTEL_GEN(dev_priv) >= 9)
2219                 return 7;
2220         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2221                 return 4;
2222         else if (INTEL_GEN(dev_priv) >= 6)
2223                 return 3;
2224         else
2225                 return 2;
2226 }
2227
2228 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2229                                    const char *name,
2230                                    const uint16_t wm[8])
2231 {
2232         int level, max_level = ilk_wm_max_level(dev_priv);
2233
2234         for (level = 0; level <= max_level; level++) {
2235                 unsigned int latency = wm[level];
2236
2237                 if (latency == 0) {
2238                         DRM_ERROR("%s WM%d latency not provided\n",
2239                                   name, level);
2240                         continue;
2241                 }
2242
2243                 /*
2244                  * - latencies are in us on gen9.
2245                  * - before then, WM1+ latency values are in 0.5us units
2246                  */
2247                 if (IS_GEN9(dev_priv))
2248                         latency *= 10;
2249                 else if (level > 0)
2250                         latency *= 5;
2251
2252                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2253                               name, level, wm[level],
2254                               latency / 10, latency % 10);
2255         }
2256 }
2257
2258 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2259                                     uint16_t wm[5], uint16_t min)
2260 {
2261         int level, max_level = ilk_wm_max_level(dev_priv);
2262
2263         if (wm[0] >= min)
2264                 return false;
2265
2266         wm[0] = max(wm[0], min);
2267         for (level = 1; level <= max_level; level++)
2268                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2269
2270         return true;
2271 }
2272
2273 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2274 {
2275         bool changed;
2276
2277         /*
2278          * The BIOS provided WM memory latency values are often
2279          * inadequate for high resolution displays. Adjust them.
2280          */
2281         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2282                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2283                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2284
2285         if (!changed)
2286                 return;
2287
2288         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2289         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2290         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2291         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2292 }
2293
2294 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2295 {
2296         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2297
2298         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2299                sizeof(dev_priv->wm.pri_latency));
2300         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2301                sizeof(dev_priv->wm.pri_latency));
2302
2303         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2304         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2305
2306         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2307         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2308         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2309
2310         if (IS_GEN6(dev_priv))
2311                 snb_wm_latency_quirk(dev_priv);
2312 }
2313
2314 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2315 {
2316         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2317         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2318 }
2319
2320 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2321                                  struct intel_pipe_wm *pipe_wm)
2322 {
2323         /* LP0 watermark maximums depend on this pipe alone */
2324         const struct intel_wm_config config = {
2325                 .num_pipes_active = 1,
2326                 .sprites_enabled = pipe_wm->sprites_enabled,
2327                 .sprites_scaled = pipe_wm->sprites_scaled,
2328         };
2329         struct ilk_wm_maximums max;
2330
2331         /* LP0 watermarks always use 1/2 DDB partitioning */
2332         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2333
2334         /* At least LP0 must be valid */
2335         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2336                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2337                 return false;
2338         }
2339
2340         return true;
2341 }
2342
2343 /* Compute new watermarks for the pipe */
2344 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2345 {
2346         struct drm_atomic_state *state = cstate->base.state;
2347         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2348         struct intel_pipe_wm *pipe_wm;
2349         struct drm_device *dev = state->dev;
2350         const struct drm_i915_private *dev_priv = to_i915(dev);
2351         struct intel_plane *intel_plane;
2352         struct intel_plane_state *pristate = NULL;
2353         struct intel_plane_state *sprstate = NULL;
2354         struct intel_plane_state *curstate = NULL;
2355         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2356         struct ilk_wm_maximums max;
2357
2358         pipe_wm = &cstate->wm.ilk.optimal;
2359
2360         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2361                 struct intel_plane_state *ps;
2362
2363                 ps = intel_atomic_get_existing_plane_state(state,
2364                                                            intel_plane);
2365                 if (!ps)
2366                         continue;
2367
2368                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2369                         pristate = ps;
2370                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2371                         sprstate = ps;
2372                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2373                         curstate = ps;
2374         }
2375
2376         pipe_wm->pipe_enabled = cstate->base.active;
2377         if (sprstate) {
2378                 pipe_wm->sprites_enabled = sprstate->base.visible;
2379                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2380                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2381                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2382         }
2383
2384         usable_level = max_level;
2385
2386         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2387         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2388                 usable_level = 1;
2389
2390         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2391         if (pipe_wm->sprites_scaled)
2392                 usable_level = 0;
2393
2394         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2395                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2396
2397         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2398         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2399
2400         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2401                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2402
2403         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2404                 return -EINVAL;
2405
2406         ilk_compute_wm_reg_maximums(dev, 1, &max);
2407
2408         for (level = 1; level <= max_level; level++) {
2409                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2410
2411                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2412                                      pristate, sprstate, curstate, wm);
2413
2414                 /*
2415                  * Disable any watermark level that exceeds the
2416                  * register maximums since such watermarks are
2417                  * always invalid.
2418                  */
2419                 if (level > usable_level)
2420                         continue;
2421
2422                 if (ilk_validate_wm_level(level, &max, wm))
2423                         pipe_wm->wm[level] = *wm;
2424                 else
2425                         usable_level = level;
2426         }
2427
2428         return 0;
2429 }
2430
2431 /*
2432  * Build a set of 'intermediate' watermark values that satisfy both the old
2433  * state and the new state.  These can be programmed to the hardware
2434  * immediately.
2435  */
2436 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2437                                        struct intel_crtc *intel_crtc,
2438                                        struct intel_crtc_state *newstate)
2439 {
2440         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2441         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2442         int level, max_level = ilk_wm_max_level(to_i915(dev));
2443
2444         /*
2445          * Start with the final, target watermarks, then combine with the
2446          * currently active watermarks to get values that are safe both before
2447          * and after the vblank.
2448          */
2449         *a = newstate->wm.ilk.optimal;
2450         a->pipe_enabled |= b->pipe_enabled;
2451         a->sprites_enabled |= b->sprites_enabled;
2452         a->sprites_scaled |= b->sprites_scaled;
2453
2454         for (level = 0; level <= max_level; level++) {
2455                 struct intel_wm_level *a_wm = &a->wm[level];
2456                 const struct intel_wm_level *b_wm = &b->wm[level];
2457
2458                 a_wm->enable &= b_wm->enable;
2459                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2460                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2461                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2462                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2463         }
2464
2465         /*
2466          * We need to make sure that these merged watermark values are
2467          * actually a valid configuration themselves.  If they're not,
2468          * there's no safe way to transition from the old state to
2469          * the new state, so we need to fail the atomic transaction.
2470          */
2471         if (!ilk_validate_pipe_wm(dev, a))
2472                 return -EINVAL;
2473
2474         /*
2475          * If our intermediate WM are identical to the final WM, then we can
2476          * omit the post-vblank programming; only update if it's different.
2477          */
2478         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2479                 newstate->wm.need_postvbl_update = false;
2480
2481         return 0;
2482 }
2483
2484 /*
2485  * Merge the watermarks from all active pipes for a specific level.
2486  */
2487 static void ilk_merge_wm_level(struct drm_device *dev,
2488                                int level,
2489                                struct intel_wm_level *ret_wm)
2490 {
2491         const struct intel_crtc *intel_crtc;
2492
2493         ret_wm->enable = true;
2494
2495         for_each_intel_crtc(dev, intel_crtc) {
2496                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2497                 const struct intel_wm_level *wm = &active->wm[level];
2498
2499                 if (!active->pipe_enabled)
2500                         continue;
2501
2502                 /*
2503                  * The watermark values may have been used in the past,
2504                  * so we must maintain them in the registers for some
2505                  * time even if the level is now disabled.
2506                  */
2507                 if (!wm->enable)
2508                         ret_wm->enable = false;
2509
2510                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2511                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2512                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2513                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2514         }
2515 }
2516
2517 /*
2518  * Merge all low power watermarks for all active pipes.
2519  */
2520 static void ilk_wm_merge(struct drm_device *dev,
2521                          const struct intel_wm_config *config,
2522                          const struct ilk_wm_maximums *max,
2523                          struct intel_pipe_wm *merged)
2524 {
2525         struct drm_i915_private *dev_priv = to_i915(dev);
2526         int level, max_level = ilk_wm_max_level(dev_priv);
2527         int last_enabled_level = max_level;
2528
2529         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2530         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2531             config->num_pipes_active > 1)
2532                 last_enabled_level = 0;
2533
2534         /* ILK: FBC WM must be disabled always */
2535         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2536
2537         /* merge each WM1+ level */
2538         for (level = 1; level <= max_level; level++) {
2539                 struct intel_wm_level *wm = &merged->wm[level];
2540
2541                 ilk_merge_wm_level(dev, level, wm);
2542
2543                 if (level > last_enabled_level)
2544                         wm->enable = false;
2545                 else if (!ilk_validate_wm_level(level, max, wm))
2546                         /* make sure all following levels get disabled */
2547                         last_enabled_level = level - 1;
2548
2549                 /*
2550                  * The spec says it is preferred to disable
2551                  * FBC WMs instead of disabling a WM level.
2552                  */
2553                 if (wm->fbc_val > max->fbc) {
2554                         if (wm->enable)
2555                                 merged->fbc_wm_enabled = false;
2556                         wm->fbc_val = 0;
2557                 }
2558         }
2559
2560         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2561         /*
2562          * FIXME this is racy. FBC might get enabled later.
2563          * What we should check here is whether FBC can be
2564          * enabled sometime later.
2565          */
2566         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2567             intel_fbc_is_active(dev_priv)) {
2568                 for (level = 2; level <= max_level; level++) {
2569                         struct intel_wm_level *wm = &merged->wm[level];
2570
2571                         wm->enable = false;
2572                 }
2573         }
2574 }
2575
2576 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2577 {
2578         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2579         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2580 }
2581
2582 /* The value we need to program into the WM_LPx latency field */
2583 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2584 {
2585         struct drm_i915_private *dev_priv = to_i915(dev);
2586
2587         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2588                 return 2 * level;
2589         else
2590                 return dev_priv->wm.pri_latency[level];
2591 }
2592
2593 static void ilk_compute_wm_results(struct drm_device *dev,
2594                                    const struct intel_pipe_wm *merged,
2595                                    enum intel_ddb_partitioning partitioning,
2596                                    struct ilk_wm_values *results)
2597 {
2598         struct intel_crtc *intel_crtc;
2599         int level, wm_lp;
2600
2601         results->enable_fbc_wm = merged->fbc_wm_enabled;
2602         results->partitioning = partitioning;
2603
2604         /* LP1+ register values */
2605         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2606                 const struct intel_wm_level *r;
2607
2608                 level = ilk_wm_lp_to_level(wm_lp, merged);
2609
2610                 r = &merged->wm[level];
2611
2612                 /*
2613                  * Maintain the watermark values even if the level is
2614                  * disabled. Doing otherwise could cause underruns.
2615                  */
2616                 results->wm_lp[wm_lp - 1] =
2617                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2618                         (r->pri_val << WM1_LP_SR_SHIFT) |
2619                         r->cur_val;
2620
2621                 if (r->enable)
2622                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2623
2624                 if (INTEL_INFO(dev)->gen >= 8)
2625                         results->wm_lp[wm_lp - 1] |=
2626                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2627                 else
2628                         results->wm_lp[wm_lp - 1] |=
2629                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2630
2631                 /*
2632                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2633                  * level is disabled. Doing otherwise could cause underruns.
2634                  */
2635                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2636                         WARN_ON(wm_lp != 1);
2637                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2638                 } else
2639                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2640         }
2641
2642         /* LP0 register values */
2643         for_each_intel_crtc(dev, intel_crtc) {
2644                 enum pipe pipe = intel_crtc->pipe;
2645                 const struct intel_wm_level *r =
2646                         &intel_crtc->wm.active.ilk.wm[0];
2647
2648                 if (WARN_ON(!r->enable))
2649                         continue;
2650
2651                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2652
2653                 results->wm_pipe[pipe] =
2654                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2655                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2656                         r->cur_val;
2657         }
2658 }
2659
2660 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2661  * case both are at the same level. Prefer r1 in case they're the same. */
2662 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2663                                                   struct intel_pipe_wm *r1,
2664                                                   struct intel_pipe_wm *r2)
2665 {
2666         int level, max_level = ilk_wm_max_level(to_i915(dev));
2667         int level1 = 0, level2 = 0;
2668
2669         for (level = 1; level <= max_level; level++) {
2670                 if (r1->wm[level].enable)
2671                         level1 = level;
2672                 if (r2->wm[level].enable)
2673                         level2 = level;
2674         }
2675
2676         if (level1 == level2) {
2677                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2678                         return r2;
2679                 else
2680                         return r1;
2681         } else if (level1 > level2) {
2682                 return r1;
2683         } else {
2684                 return r2;
2685         }
2686 }
2687
2688 /* dirty bits used to track which watermarks need changes */
2689 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2690 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2691 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2692 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2693 #define WM_DIRTY_FBC (1 << 24)
2694 #define WM_DIRTY_DDB (1 << 25)
2695
2696 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2697                                          const struct ilk_wm_values *old,
2698                                          const struct ilk_wm_values *new)
2699 {
2700         unsigned int dirty = 0;
2701         enum pipe pipe;
2702         int wm_lp;
2703
2704         for_each_pipe(dev_priv, pipe) {
2705                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2706                         dirty |= WM_DIRTY_LINETIME(pipe);
2707                         /* Must disable LP1+ watermarks too */
2708                         dirty |= WM_DIRTY_LP_ALL;
2709                 }
2710
2711                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2712                         dirty |= WM_DIRTY_PIPE(pipe);
2713                         /* Must disable LP1+ watermarks too */
2714                         dirty |= WM_DIRTY_LP_ALL;
2715                 }
2716         }
2717
2718         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2719                 dirty |= WM_DIRTY_FBC;
2720                 /* Must disable LP1+ watermarks too */
2721                 dirty |= WM_DIRTY_LP_ALL;
2722         }
2723
2724         if (old->partitioning != new->partitioning) {
2725                 dirty |= WM_DIRTY_DDB;
2726                 /* Must disable LP1+ watermarks too */
2727                 dirty |= WM_DIRTY_LP_ALL;
2728         }
2729
2730         /* LP1+ watermarks already deemed dirty, no need to continue */
2731         if (dirty & WM_DIRTY_LP_ALL)
2732                 return dirty;
2733
2734         /* Find the lowest numbered LP1+ watermark in need of an update... */
2735         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2736                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2737                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2738                         break;
2739         }
2740
2741         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2742         for (; wm_lp <= 3; wm_lp++)
2743                 dirty |= WM_DIRTY_LP(wm_lp);
2744
2745         return dirty;
2746 }
2747
2748 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2749                                unsigned int dirty)
2750 {
2751         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2752         bool changed = false;
2753
2754         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2755                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2756                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2757                 changed = true;
2758         }
2759         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2760                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2761                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2762                 changed = true;
2763         }
2764         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2765                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2766                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2767                 changed = true;
2768         }
2769
2770         /*
2771          * Don't touch WM1S_LP_EN here.
2772          * Doing so could cause underruns.
2773          */
2774
2775         return changed;
2776 }
2777
2778 /*
2779  * The spec says we shouldn't write when we don't need, because every write
2780  * causes WMs to be re-evaluated, expending some power.
2781  */
2782 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2783                                 struct ilk_wm_values *results)
2784 {
2785         struct drm_device *dev = &dev_priv->drm;
2786         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2787         unsigned int dirty;
2788         uint32_t val;
2789
2790         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2791         if (!dirty)
2792                 return;
2793
2794         _ilk_disable_lp_wm(dev_priv, dirty);
2795
2796         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2797                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2798         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2799                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2800         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2801                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2802
2803         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2804                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2805         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2806                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2807         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2808                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2809
2810         if (dirty & WM_DIRTY_DDB) {
2811                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2812                         val = I915_READ(WM_MISC);
2813                         if (results->partitioning == INTEL_DDB_PART_1_2)
2814                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2815                         else
2816                                 val |= WM_MISC_DATA_PARTITION_5_6;
2817                         I915_WRITE(WM_MISC, val);
2818                 } else {
2819                         val = I915_READ(DISP_ARB_CTL2);
2820                         if (results->partitioning == INTEL_DDB_PART_1_2)
2821                                 val &= ~DISP_DATA_PARTITION_5_6;
2822                         else
2823                                 val |= DISP_DATA_PARTITION_5_6;
2824                         I915_WRITE(DISP_ARB_CTL2, val);
2825                 }
2826         }
2827
2828         if (dirty & WM_DIRTY_FBC) {
2829                 val = I915_READ(DISP_ARB_CTL);
2830                 if (results->enable_fbc_wm)
2831                         val &= ~DISP_FBC_WM_DIS;
2832                 else
2833                         val |= DISP_FBC_WM_DIS;
2834                 I915_WRITE(DISP_ARB_CTL, val);
2835         }
2836
2837         if (dirty & WM_DIRTY_LP(1) &&
2838             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2839                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2840
2841         if (INTEL_INFO(dev)->gen >= 7) {
2842                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2843                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2844                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2845                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2846         }
2847
2848         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2849                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2850         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2851                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2852         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2853                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2854
2855         dev_priv->wm.hw = *results;
2856 }
2857
2858 bool ilk_disable_lp_wm(struct drm_device *dev)
2859 {
2860         struct drm_i915_private *dev_priv = to_i915(dev);
2861
2862         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2863 }
2864
2865 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2866
2867 /*
2868  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2869  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2870  * other universal planes are in indices 1..n.  Note that this may leave unused
2871  * indices between the top "sprite" plane and the cursor.
2872  */
2873 static int
2874 skl_wm_plane_id(const struct intel_plane *plane)
2875 {
2876         switch (plane->base.type) {
2877         case DRM_PLANE_TYPE_PRIMARY:
2878                 return 0;
2879         case DRM_PLANE_TYPE_CURSOR:
2880                 return PLANE_CURSOR;
2881         case DRM_PLANE_TYPE_OVERLAY:
2882                 return plane->plane + 1;
2883         default:
2884                 MISSING_CASE(plane->base.type);
2885                 return plane->plane;
2886         }
2887 }
2888
2889 /*
2890  * FIXME: We still don't have the proper code detect if we need to apply the WA,
2891  * so assume we'll always need it in order to avoid underruns.
2892  */
2893 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2894 {
2895         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2896
2897         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2898             IS_KABYLAKE(dev_priv))
2899                 return true;
2900
2901         return false;
2902 }
2903
2904 static bool
2905 intel_has_sagv(struct drm_i915_private *dev_priv)
2906 {
2907         if (IS_KABYLAKE(dev_priv))
2908                 return true;
2909
2910         if (IS_SKYLAKE(dev_priv) &&
2911             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2912                 return true;
2913
2914         return false;
2915 }
2916
2917 /*
2918  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2919  * depending on power and performance requirements. The display engine access
2920  * to system memory is blocked during the adjustment time. Because of the
2921  * blocking time, having this enabled can cause full system hangs and/or pipe
2922  * underruns if we don't meet all of the following requirements:
2923  *
2924  *  - <= 1 pipe enabled
2925  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2926  *  - We're not using an interlaced display configuration
2927  */
2928 int
2929 intel_enable_sagv(struct drm_i915_private *dev_priv)
2930 {
2931         int ret;
2932
2933         if (!intel_has_sagv(dev_priv))
2934                 return 0;
2935
2936         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2937                 return 0;
2938
2939         DRM_DEBUG_KMS("Enabling the SAGV\n");
2940         mutex_lock(&dev_priv->rps.hw_lock);
2941
2942         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2943                                       GEN9_SAGV_ENABLE);
2944
2945         /* We don't need to wait for the SAGV when enabling */
2946         mutex_unlock(&dev_priv->rps.hw_lock);
2947
2948         /*
2949          * Some skl systems, pre-release machines in particular,
2950          * don't actually have an SAGV.
2951          */
2952         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2953                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2954                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2955                 return 0;
2956         } else if (ret < 0) {
2957                 DRM_ERROR("Failed to enable the SAGV\n");
2958                 return ret;
2959         }
2960
2961         dev_priv->sagv_status = I915_SAGV_ENABLED;
2962         return 0;
2963 }
2964
2965 static int
2966 intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2967 {
2968         int ret;
2969         uint32_t temp = GEN9_SAGV_DISABLE;
2970
2971         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2972                                      &temp);
2973         if (ret)
2974                 return ret;
2975         else
2976                 return temp & GEN9_SAGV_IS_DISABLED;
2977 }
2978
2979 int
2980 intel_disable_sagv(struct drm_i915_private *dev_priv)
2981 {
2982         int ret, result;
2983
2984         if (!intel_has_sagv(dev_priv))
2985                 return 0;
2986
2987         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2988                 return 0;
2989
2990         DRM_DEBUG_KMS("Disabling the SAGV\n");
2991         mutex_lock(&dev_priv->rps.hw_lock);
2992
2993         /* bspec says to keep retrying for at least 1 ms */
2994         ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
2995         mutex_unlock(&dev_priv->rps.hw_lock);
2996
2997         if (ret == -ETIMEDOUT) {
2998                 DRM_ERROR("Request to disable SAGV timed out\n");
2999                 return -ETIMEDOUT;
3000         }
3001
3002         /*
3003          * Some skl systems, pre-release machines in particular,
3004          * don't actually have an SAGV.
3005          */
3006         if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
3007                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3008                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3009                 return 0;
3010         } else if (result < 0) {
3011                 DRM_ERROR("Failed to disable the SAGV\n");
3012                 return result;
3013         }
3014
3015         dev_priv->sagv_status = I915_SAGV_DISABLED;
3016         return 0;
3017 }
3018
3019 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3020 {
3021         struct drm_device *dev = state->dev;
3022         struct drm_i915_private *dev_priv = to_i915(dev);
3023         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3024         struct intel_crtc *crtc;
3025         struct intel_plane *plane;
3026         struct intel_crtc_state *cstate;
3027         struct skl_plane_wm *wm;
3028         enum pipe pipe;
3029         int level, latency;
3030
3031         if (!intel_has_sagv(dev_priv))
3032                 return false;
3033
3034         /*
3035          * SKL workaround: bspec recommends we disable the SAGV when we have
3036          * more then one pipe enabled
3037          *
3038          * If there are no active CRTCs, no additional checks need be performed
3039          */
3040         if (hweight32(intel_state->active_crtcs) == 0)
3041                 return true;
3042         else if (hweight32(intel_state->active_crtcs) > 1)
3043                 return false;
3044
3045         /* Since we're now guaranteed to only have one active CRTC... */
3046         pipe = ffs(intel_state->active_crtcs) - 1;
3047         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3048         cstate = to_intel_crtc_state(crtc->base.state);
3049
3050         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3051                 return false;
3052
3053         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3054                 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
3055
3056                 /* Skip this plane if it's not enabled */
3057                 if (!wm->wm[0].plane_en)
3058                         continue;
3059
3060                 /* Find the highest enabled wm level for this plane */
3061                 for (level = ilk_wm_max_level(dev_priv);
3062                      !wm->wm[level].plane_en; --level)
3063                      { }
3064
3065                 latency = dev_priv->wm.skl_latency[level];
3066
3067                 if (skl_needs_memory_bw_wa(intel_state) &&
3068                     plane->base.state->fb->modifier[0] ==
3069                     I915_FORMAT_MOD_X_TILED)
3070                         latency += 15;
3071
3072                 /*
3073                  * If any of the planes on this pipe don't enable wm levels
3074                  * that incur memory latencies higher then 30µs we can't enable
3075                  * the SAGV
3076                  */
3077                 if (latency < SKL_SAGV_BLOCK_TIME)
3078                         return false;
3079         }
3080
3081         return true;
3082 }
3083
3084 static void
3085 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3086                                    const struct intel_crtc_state *cstate,
3087                                    struct skl_ddb_entry *alloc, /* out */
3088                                    int *num_active /* out */)
3089 {
3090         struct drm_atomic_state *state = cstate->base.state;
3091         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3092         struct drm_i915_private *dev_priv = to_i915(dev);
3093         struct drm_crtc *for_crtc = cstate->base.crtc;
3094         unsigned int pipe_size, ddb_size;
3095         int nth_active_pipe;
3096
3097         if (WARN_ON(!state) || !cstate->base.active) {
3098                 alloc->start = 0;
3099                 alloc->end = 0;
3100                 *num_active = hweight32(dev_priv->active_crtcs);
3101                 return;
3102         }
3103
3104         if (intel_state->active_pipe_changes)
3105                 *num_active = hweight32(intel_state->active_crtcs);
3106         else
3107                 *num_active = hweight32(dev_priv->active_crtcs);
3108
3109         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3110         WARN_ON(ddb_size == 0);
3111
3112         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3113
3114         /*
3115          * If the state doesn't change the active CRTC's, then there's
3116          * no need to recalculate; the existing pipe allocation limits
3117          * should remain unchanged.  Note that we're safe from racing
3118          * commits since any racing commit that changes the active CRTC
3119          * list would need to grab _all_ crtc locks, including the one
3120          * we currently hold.
3121          */
3122         if (!intel_state->active_pipe_changes) {
3123                 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
3124                 return;
3125         }
3126
3127         nth_active_pipe = hweight32(intel_state->active_crtcs &
3128                                     (drm_crtc_mask(for_crtc) - 1));
3129         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3130         alloc->start = nth_active_pipe * ddb_size / *num_active;
3131         alloc->end = alloc->start + pipe_size;
3132 }
3133
3134 static unsigned int skl_cursor_allocation(int num_active)
3135 {
3136         if (num_active == 1)
3137                 return 32;
3138
3139         return 8;
3140 }
3141
3142 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3143 {
3144         entry->start = reg & 0x3ff;
3145         entry->end = (reg >> 16) & 0x3ff;
3146         if (entry->end)
3147                 entry->end += 1;
3148 }
3149
3150 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3151                           struct skl_ddb_allocation *ddb /* out */)
3152 {
3153         enum pipe pipe;
3154         int plane;
3155         u32 val;
3156
3157         memset(ddb, 0, sizeof(*ddb));
3158
3159         for_each_pipe(dev_priv, pipe) {
3160                 enum intel_display_power_domain power_domain;
3161
3162                 power_domain = POWER_DOMAIN_PIPE(pipe);
3163                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3164                         continue;
3165
3166                 for_each_universal_plane(dev_priv, pipe, plane) {
3167                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3168                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3169                                                    val);
3170                 }
3171
3172                 val = I915_READ(CUR_BUF_CFG(pipe));
3173                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3174                                            val);
3175
3176                 intel_display_power_put(dev_priv, power_domain);
3177         }
3178 }
3179
3180 /*
3181  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3182  * The bspec defines downscale amount as:
3183  *
3184  * """
3185  * Horizontal down scale amount = maximum[1, Horizontal source size /
3186  *                                           Horizontal destination size]
3187  * Vertical down scale amount = maximum[1, Vertical source size /
3188  *                                         Vertical destination size]
3189  * Total down scale amount = Horizontal down scale amount *
3190  *                           Vertical down scale amount
3191  * """
3192  *
3193  * Return value is provided in 16.16 fixed point form to retain fractional part.
3194  * Caller should take care of dividing & rounding off the value.
3195  */
3196 static uint32_t
3197 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3198 {
3199         uint32_t downscale_h, downscale_w;
3200         uint32_t src_w, src_h, dst_w, dst_h;
3201
3202         if (WARN_ON(!pstate->base.visible))
3203                 return DRM_PLANE_HELPER_NO_SCALING;
3204
3205         /* n.b., src is 16.16 fixed point, dst is whole integer */
3206         src_w = drm_rect_width(&pstate->base.src);
3207         src_h = drm_rect_height(&pstate->base.src);
3208         dst_w = drm_rect_width(&pstate->base.dst);
3209         dst_h = drm_rect_height(&pstate->base.dst);
3210         if (drm_rotation_90_or_270(pstate->base.rotation))
3211                 swap(dst_w, dst_h);
3212
3213         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3214         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3215
3216         /* Provide result in 16.16 fixed point */
3217         return (uint64_t)downscale_w * downscale_h >> 16;
3218 }
3219
3220 static unsigned int
3221 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3222                              const struct drm_plane_state *pstate,
3223                              int y)
3224 {
3225         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3226         struct drm_framebuffer *fb = pstate->fb;
3227         uint32_t down_scale_amount, data_rate;
3228         uint32_t width = 0, height = 0;
3229         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3230
3231         if (!intel_pstate->base.visible)
3232                 return 0;
3233         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3234                 return 0;
3235         if (y && format != DRM_FORMAT_NV12)
3236                 return 0;
3237
3238         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3239         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3240
3241         if (drm_rotation_90_or_270(pstate->rotation))
3242                 swap(width, height);
3243
3244         /* for planar format */
3245         if (format == DRM_FORMAT_NV12) {
3246                 if (y)  /* y-plane data rate */
3247                         data_rate = width * height *
3248                                 drm_format_plane_cpp(format, 0);
3249                 else    /* uv-plane data rate */
3250                         data_rate = (width / 2) * (height / 2) *
3251                                 drm_format_plane_cpp(format, 1);
3252         } else {
3253                 /* for packed formats */
3254                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3255         }
3256
3257         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3258
3259         return (uint64_t)data_rate * down_scale_amount >> 16;
3260 }
3261
3262 /*
3263  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3264  * a 8192x4096@32bpp framebuffer:
3265  *   3 * 4096 * 8192  * 4 < 2^32
3266  */
3267 static unsigned int
3268 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3269                                  unsigned *plane_data_rate,
3270                                  unsigned *plane_y_data_rate)
3271 {
3272         struct drm_crtc_state *cstate = &intel_cstate->base;
3273         struct drm_atomic_state *state = cstate->state;
3274         struct drm_plane *plane;
3275         const struct intel_plane *intel_plane;
3276         const struct drm_plane_state *pstate;
3277         unsigned int rate, total_data_rate = 0;
3278         int id;
3279
3280         if (WARN_ON(!state))
3281                 return 0;
3282
3283         /* Calculate and cache data rate for each plane */
3284         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3285                 id = skl_wm_plane_id(to_intel_plane(plane));
3286                 intel_plane = to_intel_plane(plane);
3287
3288                 /* packed/uv */
3289                 rate = skl_plane_relative_data_rate(intel_cstate,
3290                                                     pstate, 0);
3291                 plane_data_rate[id] = rate;
3292
3293                 total_data_rate += rate;
3294
3295                 /* y-plane */
3296                 rate = skl_plane_relative_data_rate(intel_cstate,
3297                                                     pstate, 1);
3298                 plane_y_data_rate[id] = rate;
3299
3300                 total_data_rate += rate;
3301         }
3302
3303         return total_data_rate;
3304 }
3305
3306 static uint16_t
3307 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3308                   const int y)
3309 {
3310         struct drm_framebuffer *fb = pstate->fb;
3311         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3312         uint32_t src_w, src_h;
3313         uint32_t min_scanlines = 8;
3314         uint8_t plane_bpp;
3315
3316         if (WARN_ON(!fb))
3317                 return 0;
3318
3319         /* For packed formats, no y-plane, return 0 */
3320         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3321                 return 0;
3322
3323         /* For Non Y-tile return 8-blocks */
3324         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3325             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3326                 return 8;
3327
3328         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3329         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3330
3331         if (drm_rotation_90_or_270(pstate->rotation))
3332                 swap(src_w, src_h);
3333
3334         /* Halve UV plane width and height for NV12 */
3335         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3336                 src_w /= 2;
3337                 src_h /= 2;
3338         }
3339
3340         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3341                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3342         else
3343                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3344
3345         if (drm_rotation_90_or_270(pstate->rotation)) {
3346                 switch (plane_bpp) {
3347                 case 1:
3348                         min_scanlines = 32;
3349                         break;
3350                 case 2:
3351                         min_scanlines = 16;
3352                         break;
3353                 case 4:
3354                         min_scanlines = 8;
3355                         break;
3356                 case 8:
3357                         min_scanlines = 4;
3358                         break;
3359                 default:
3360                         WARN(1, "Unsupported pixel depth %u for rotation",
3361                              plane_bpp);
3362                         min_scanlines = 32;
3363                 }
3364         }
3365
3366         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3367 }
3368
3369 static void
3370 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3371                  uint16_t *minimum, uint16_t *y_minimum)
3372 {
3373         const struct drm_plane_state *pstate;
3374         struct drm_plane *plane;
3375
3376         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3377                 struct intel_plane *intel_plane = to_intel_plane(plane);
3378                 int id = skl_wm_plane_id(intel_plane);
3379
3380                 if (id == PLANE_CURSOR)
3381                         continue;
3382
3383                 if (!pstate->visible)
3384                         continue;
3385
3386                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3387                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3388         }
3389
3390         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3391 }
3392
3393 static int
3394 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3395                       struct skl_ddb_allocation *ddb /* out */)
3396 {
3397         struct drm_atomic_state *state = cstate->base.state;
3398         struct drm_crtc *crtc = cstate->base.crtc;
3399         struct drm_device *dev = crtc->dev;
3400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3401         enum pipe pipe = intel_crtc->pipe;
3402         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3403         uint16_t alloc_size, start;
3404         uint16_t minimum[I915_MAX_PLANES] = {};
3405         uint16_t y_minimum[I915_MAX_PLANES] = {};
3406         unsigned int total_data_rate;
3407         int num_active;
3408         int id, i;
3409         unsigned plane_data_rate[I915_MAX_PLANES] = {};
3410         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3411
3412         /* Clear the partitioning for disabled planes. */
3413         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3414         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3415
3416         if (WARN_ON(!state))
3417                 return 0;
3418
3419         if (!cstate->base.active) {
3420                 alloc->start = alloc->end = 0;
3421                 return 0;
3422         }
3423
3424         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3425         alloc_size = skl_ddb_entry_size(alloc);
3426         if (alloc_size == 0) {
3427                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3428                 return 0;
3429         }
3430
3431         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3432
3433         /*
3434          * 1. Allocate the mininum required blocks for each active plane
3435          * and allocate the cursor, it doesn't require extra allocation
3436          * proportional to the data rate.
3437          */
3438
3439         for (i = 0; i < I915_MAX_PLANES; i++) {
3440                 alloc_size -= minimum[i];
3441                 alloc_size -= y_minimum[i];
3442         }
3443
3444         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3445         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3446
3447         /*
3448          * 2. Distribute the remaining space in proportion to the amount of
3449          * data each plane needs to fetch from memory.
3450          *
3451          * FIXME: we may not allocate every single block here.
3452          */
3453         total_data_rate = skl_get_total_relative_data_rate(cstate,
3454                                                            plane_data_rate,
3455                                                            plane_y_data_rate);
3456         if (total_data_rate == 0)
3457                 return 0;
3458
3459         start = alloc->start;
3460         for (id = 0; id < I915_MAX_PLANES; id++) {
3461                 unsigned int data_rate, y_data_rate;
3462                 uint16_t plane_blocks, y_plane_blocks = 0;
3463
3464                 if (id == PLANE_CURSOR)
3465                         continue;
3466
3467                 data_rate = plane_data_rate[id];
3468
3469                 /*
3470                  * allocation for (packed formats) or (uv-plane part of planar format):
3471                  * promote the expression to 64 bits to avoid overflowing, the
3472                  * result is < available as data_rate / total_data_rate < 1
3473                  */
3474                 plane_blocks = minimum[id];
3475                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3476                                         total_data_rate);
3477
3478                 /* Leave disabled planes at (0,0) */
3479                 if (data_rate) {
3480                         ddb->plane[pipe][id].start = start;
3481                         ddb->plane[pipe][id].end = start + plane_blocks;
3482                 }
3483
3484                 start += plane_blocks;
3485
3486                 /*
3487                  * allocation for y_plane part of planar format:
3488                  */
3489                 y_data_rate = plane_y_data_rate[id];
3490
3491                 y_plane_blocks = y_minimum[id];
3492                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3493                                         total_data_rate);
3494
3495                 if (y_data_rate) {
3496                         ddb->y_plane[pipe][id].start = start;
3497                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3498                 }
3499
3500                 start += y_plane_blocks;
3501         }
3502
3503         return 0;
3504 }
3505
3506 /*
3507  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3508  * for the read latency) and cpp should always be <= 8, so that
3509  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3510  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3511 */
3512 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3513 {
3514         uint32_t wm_intermediate_val, ret;
3515
3516         if (latency == 0)
3517                 return UINT_MAX;
3518
3519         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3520         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3521
3522         return ret;
3523 }
3524
3525 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3526                                uint32_t latency, uint32_t plane_blocks_per_line)
3527 {
3528         uint32_t ret;
3529         uint32_t wm_intermediate_val;
3530
3531         if (latency == 0)
3532                 return UINT_MAX;
3533
3534         wm_intermediate_val = latency * pixel_rate;
3535         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3536                                 plane_blocks_per_line;
3537
3538         return ret;
3539 }
3540
3541 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3542                                               struct intel_plane_state *pstate)
3543 {
3544         uint64_t adjusted_pixel_rate;
3545         uint64_t downscale_amount;
3546         uint64_t pixel_rate;
3547
3548         /* Shouldn't reach here on disabled planes... */
3549         if (WARN_ON(!pstate->base.visible))
3550                 return 0;
3551
3552         /*
3553          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3554          * with additional adjustments for plane-specific scaling.
3555          */
3556         adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3557         downscale_amount = skl_plane_downscale_amount(pstate);
3558
3559         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3560         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3561
3562         return pixel_rate;
3563 }
3564
3565 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3566                                 struct intel_crtc_state *cstate,
3567                                 struct intel_plane_state *intel_pstate,
3568                                 uint16_t ddb_allocation,
3569                                 int level,
3570                                 uint16_t *out_blocks, /* out */
3571                                 uint8_t *out_lines, /* out */
3572                                 bool *enabled /* out */)
3573 {
3574         struct drm_plane_state *pstate = &intel_pstate->base;
3575         struct drm_framebuffer *fb = pstate->fb;
3576         uint32_t latency = dev_priv->wm.skl_latency[level];
3577         uint32_t method1, method2;
3578         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3579         uint32_t res_blocks, res_lines;
3580         uint32_t selected_result;
3581         uint8_t cpp;
3582         uint32_t width = 0, height = 0;
3583         uint32_t plane_pixel_rate;
3584         uint32_t y_tile_minimum, y_min_scanlines;
3585         struct intel_atomic_state *state =
3586                 to_intel_atomic_state(cstate->base.state);
3587         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3588
3589         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3590                 *enabled = false;
3591                 return 0;
3592         }
3593
3594         if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3595                 latency += 15;
3596
3597         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3598         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3599
3600         if (drm_rotation_90_or_270(pstate->rotation))
3601                 swap(width, height);
3602
3603         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3604         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3605
3606         if (drm_rotation_90_or_270(pstate->rotation)) {
3607                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3608                         drm_format_plane_cpp(fb->pixel_format, 1) :
3609                         drm_format_plane_cpp(fb->pixel_format, 0);
3610
3611                 switch (cpp) {
3612                 case 1:
3613                         y_min_scanlines = 16;
3614                         break;
3615                 case 2:
3616                         y_min_scanlines = 8;
3617                         break;
3618                 case 4:
3619                         y_min_scanlines = 4;
3620                         break;
3621                 default:
3622                         MISSING_CASE(cpp);
3623                         return -EINVAL;
3624                 }
3625         } else {
3626                 y_min_scanlines = 4;
3627         }
3628
3629         if (apply_memory_bw_wa)
3630                 y_min_scanlines *= 2;
3631
3632         plane_bytes_per_line = width * cpp;
3633         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3634             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3635                 plane_blocks_per_line =
3636                       DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3637                 plane_blocks_per_line /= y_min_scanlines;
3638         } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3639                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3640                                         + 1;
3641         } else {
3642                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3643         }
3644
3645         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3646         method2 = skl_wm_method2(plane_pixel_rate,
3647                                  cstate->base.adjusted_mode.crtc_htotal,
3648                                  latency,
3649                                  plane_blocks_per_line);
3650
3651         y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3652
3653         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3654             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3655                 selected_result = max(method2, y_tile_minimum);
3656         } else {
3657                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3658                     (plane_bytes_per_line / 512 < 1))
3659                         selected_result = method2;
3660                 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
3661                         selected_result = min(method1, method2);
3662                 else
3663                         selected_result = method1;
3664         }
3665
3666         res_blocks = selected_result + 1;
3667         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3668
3669         if (level >= 1 && level <= 7) {
3670                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3671                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3672                         res_blocks += y_tile_minimum;
3673                         res_lines += y_min_scanlines;
3674                 } else {
3675                         res_blocks++;
3676                 }
3677         }
3678
3679         if (res_blocks >= ddb_allocation || res_lines > 31) {
3680                 *enabled = false;
3681
3682                 /*
3683                  * If there are no valid level 0 watermarks, then we can't
3684                  * support this display configuration.
3685                  */
3686                 if (level) {
3687                         return 0;
3688                 } else {
3689                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3690                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3691                                       to_intel_crtc(cstate->base.crtc)->pipe,
3692                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3693                                       res_blocks, ddb_allocation, res_lines);
3694
3695                         return -EINVAL;
3696                 }
3697         }
3698
3699         *out_blocks = res_blocks;
3700         *out_lines = res_lines;
3701         *enabled = true;
3702
3703         return 0;
3704 }
3705
3706 static int
3707 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3708                      struct skl_ddb_allocation *ddb,
3709                      struct intel_crtc_state *cstate,
3710                      struct intel_plane *intel_plane,
3711                      int level,
3712                      struct skl_wm_level *result)
3713 {
3714         struct drm_atomic_state *state = cstate->base.state;
3715         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3716         struct drm_plane *plane = &intel_plane->base;
3717         struct intel_plane_state *intel_pstate = NULL;
3718         uint16_t ddb_blocks;
3719         enum pipe pipe = intel_crtc->pipe;
3720         int ret;
3721         int i = skl_wm_plane_id(intel_plane);
3722
3723         if (state)
3724                 intel_pstate =
3725                         intel_atomic_get_existing_plane_state(state,
3726                                                               intel_plane);
3727
3728         /*
3729          * Note: If we start supporting multiple pending atomic commits against
3730          * the same planes/CRTC's in the future, plane->state will no longer be
3731          * the correct pre-state to use for the calculations here and we'll
3732          * need to change where we get the 'unchanged' plane data from.
3733          *
3734          * For now this is fine because we only allow one queued commit against
3735          * a CRTC.  Even if the plane isn't modified by this transaction and we
3736          * don't have a plane lock, we still have the CRTC's lock, so we know
3737          * that no other transactions are racing with us to update it.
3738          */
3739         if (!intel_pstate)
3740                 intel_pstate = to_intel_plane_state(plane->state);
3741
3742         WARN_ON(!intel_pstate->base.fb);
3743
3744         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3745
3746         ret = skl_compute_plane_wm(dev_priv,
3747                                    cstate,
3748                                    intel_pstate,
3749                                    ddb_blocks,
3750                                    level,
3751                                    &result->plane_res_b,
3752                                    &result->plane_res_l,
3753                                    &result->plane_en);
3754         if (ret)
3755                 return ret;
3756
3757         return 0;
3758 }
3759
3760 static uint32_t
3761 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3762 {
3763         uint32_t pixel_rate;
3764
3765         if (!cstate->base.active)
3766                 return 0;
3767
3768         pixel_rate = ilk_pipe_pixel_rate(cstate);
3769
3770         if (WARN_ON(pixel_rate == 0))
3771                 return 0;
3772
3773         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3774                             pixel_rate);
3775 }
3776
3777 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3778                                       struct skl_wm_level *trans_wm /* out */)
3779 {
3780         if (!cstate->base.active)
3781                 return;
3782
3783         /* Until we know more, just disable transition WMs */
3784         trans_wm->plane_en = false;
3785 }
3786
3787 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3788                              struct skl_ddb_allocation *ddb,
3789                              struct skl_pipe_wm *pipe_wm)
3790 {
3791         struct drm_device *dev = cstate->base.crtc->dev;
3792         const struct drm_i915_private *dev_priv = to_i915(dev);
3793         struct intel_plane *intel_plane;
3794         struct skl_plane_wm *wm;
3795         int level, max_level = ilk_wm_max_level(dev_priv);
3796         int ret;
3797
3798         /*
3799          * We'll only calculate watermarks for planes that are actually
3800          * enabled, so make sure all other planes are set as disabled.
3801          */
3802         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3803
3804         for_each_intel_plane_mask(&dev_priv->drm,
3805                                   intel_plane,
3806                                   cstate->base.plane_mask) {
3807                 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3808
3809                 for (level = 0; level <= max_level; level++) {
3810                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3811                                                    intel_plane, level,
3812                                                    &wm->wm[level]);
3813                         if (ret)
3814                                 return ret;
3815                 }
3816                 skl_compute_transition_wm(cstate, &wm->trans_wm);
3817         }
3818         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3819
3820         return 0;
3821 }
3822
3823 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3824                                 i915_reg_t reg,
3825                                 const struct skl_ddb_entry *entry)
3826 {
3827         if (entry->end)
3828                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3829         else
3830                 I915_WRITE(reg, 0);
3831 }
3832
3833 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3834                                i915_reg_t reg,
3835                                const struct skl_wm_level *level)
3836 {
3837         uint32_t val = 0;
3838
3839         if (level->plane_en) {
3840                 val |= PLANE_WM_EN;
3841                 val |= level->plane_res_b;
3842                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3843         }
3844
3845         I915_WRITE(reg, val);
3846 }
3847
3848 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3849                         const struct skl_plane_wm *wm,
3850                         const struct skl_ddb_allocation *ddb,
3851                         int plane)
3852 {
3853         struct drm_crtc *crtc = &intel_crtc->base;
3854         struct drm_device *dev = crtc->dev;
3855         struct drm_i915_private *dev_priv = to_i915(dev);
3856         int level, max_level = ilk_wm_max_level(dev_priv);
3857         enum pipe pipe = intel_crtc->pipe;
3858
3859         for (level = 0; level <= max_level; level++) {
3860                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3861                                    &wm->wm[level]);
3862         }
3863         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3864                            &wm->trans_wm);
3865
3866         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3867                             &ddb->plane[pipe][plane]);
3868         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3869                             &ddb->y_plane[pipe][plane]);
3870 }
3871
3872 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3873                          const struct skl_plane_wm *wm,
3874                          const struct skl_ddb_allocation *ddb)
3875 {
3876         struct drm_crtc *crtc = &intel_crtc->base;
3877         struct drm_device *dev = crtc->dev;
3878         struct drm_i915_private *dev_priv = to_i915(dev);
3879         int level, max_level = ilk_wm_max_level(dev_priv);
3880         enum pipe pipe = intel_crtc->pipe;
3881
3882         for (level = 0; level <= max_level; level++) {
3883                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3884                                    &wm->wm[level]);
3885         }
3886         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3887
3888         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3889                             &ddb->plane[pipe][PLANE_CURSOR]);
3890 }
3891
3892 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3893                          const struct skl_wm_level *l2)
3894 {
3895         if (l1->plane_en != l2->plane_en)
3896                 return false;
3897
3898         /* If both planes aren't enabled, the rest shouldn't matter */
3899         if (!l1->plane_en)
3900                 return true;
3901
3902         return (l1->plane_res_l == l2->plane_res_l &&
3903                 l1->plane_res_b == l2->plane_res_b);
3904 }
3905
3906 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3907                                            const struct skl_ddb_entry *b)
3908 {
3909         return a->start < b->end && b->start < a->end;
3910 }
3911
3912 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3913                                  struct intel_crtc *intel_crtc)
3914 {
3915         struct drm_crtc *other_crtc;
3916         struct drm_crtc_state *other_cstate;
3917         struct intel_crtc *other_intel_crtc;
3918         const struct skl_ddb_entry *ddb =
3919                 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3920         int i;
3921
3922         for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3923                 other_intel_crtc = to_intel_crtc(other_crtc);
3924
3925                 if (other_intel_crtc == intel_crtc)
3926                         continue;
3927
3928                 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
3929                         return true;
3930         }
3931
3932         return false;
3933 }
3934
3935 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3936                               const struct skl_pipe_wm *old_pipe_wm,
3937                               struct skl_pipe_wm *pipe_wm, /* out */
3938                               struct skl_ddb_allocation *ddb, /* out */
3939                               bool *changed /* out */)
3940 {
3941         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3942         int ret;
3943
3944         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3945         if (ret)
3946                 return ret;
3947
3948         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3949                 *changed = false;
3950         else
3951                 *changed = true;
3952
3953         return 0;
3954 }
3955
3956 static uint32_t
3957 pipes_modified(struct drm_atomic_state *state)
3958 {
3959         struct drm_crtc *crtc;
3960         struct drm_crtc_state *cstate;
3961         uint32_t i, ret = 0;
3962
3963         for_each_crtc_in_state(state, crtc, cstate, i)
3964                 ret |= drm_crtc_mask(crtc);
3965
3966         return ret;
3967 }
3968
3969 static int
3970 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3971 {
3972         struct drm_atomic_state *state = cstate->base.state;
3973         struct drm_device *dev = state->dev;
3974         struct drm_crtc *crtc = cstate->base.crtc;
3975         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3976         struct drm_i915_private *dev_priv = to_i915(dev);
3977         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3978         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3979         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3980         struct drm_plane_state *plane_state;
3981         struct drm_plane *plane;
3982         enum pipe pipe = intel_crtc->pipe;
3983         int id;
3984
3985         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3986
3987         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3988                 id = skl_wm_plane_id(to_intel_plane(plane));
3989
3990                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3991                                         &new_ddb->plane[pipe][id]) &&
3992                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3993                                         &new_ddb->y_plane[pipe][id]))
3994                         continue;
3995
3996                 plane_state = drm_atomic_get_plane_state(state, plane);
3997                 if (IS_ERR(plane_state))
3998                         return PTR_ERR(plane_state);
3999         }
4000
4001         return 0;
4002 }
4003
4004 static int
4005 skl_compute_ddb(struct drm_atomic_state *state)
4006 {
4007         struct drm_device *dev = state->dev;
4008         struct drm_i915_private *dev_priv = to_i915(dev);
4009         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4010         struct intel_crtc *intel_crtc;
4011         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4012         uint32_t realloc_pipes = pipes_modified(state);
4013         int ret;
4014
4015         /*
4016          * If this is our first atomic update following hardware readout,
4017          * we can't trust the DDB that the BIOS programmed for us.  Let's
4018          * pretend that all pipes switched active status so that we'll
4019          * ensure a full DDB recompute.
4020          */
4021         if (dev_priv->wm.distrust_bios_wm) {
4022                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4023                                        state->acquire_ctx);
4024                 if (ret)
4025                         return ret;
4026
4027                 intel_state->active_pipe_changes = ~0;
4028
4029                 /*
4030                  * We usually only initialize intel_state->active_crtcs if we
4031                  * we're doing a modeset; make sure this field is always
4032                  * initialized during the sanitization process that happens
4033                  * on the first commit too.
4034                  */
4035                 if (!intel_state->modeset)
4036                         intel_state->active_crtcs = dev_priv->active_crtcs;
4037         }
4038
4039         /*
4040          * If the modeset changes which CRTC's are active, we need to
4041          * recompute the DDB allocation for *all* active pipes, even
4042          * those that weren't otherwise being modified in any way by this
4043          * atomic commit.  Due to the shrinking of the per-pipe allocations
4044          * when new active CRTC's are added, it's possible for a pipe that
4045          * we were already using and aren't changing at all here to suddenly
4046          * become invalid if its DDB needs exceeds its new allocation.
4047          *
4048          * Note that if we wind up doing a full DDB recompute, we can't let
4049          * any other display updates race with this transaction, so we need
4050          * to grab the lock on *all* CRTC's.
4051          */
4052         if (intel_state->active_pipe_changes) {
4053                 realloc_pipes = ~0;
4054                 intel_state->wm_results.dirty_pipes = ~0;
4055         }
4056
4057         /*
4058          * We're not recomputing for the pipes not included in the commit, so
4059          * make sure we start with the current state.
4060          */
4061         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4062
4063         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4064                 struct intel_crtc_state *cstate;
4065
4066                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4067                 if (IS_ERR(cstate))
4068                         return PTR_ERR(cstate);
4069
4070                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4071                 if (ret)
4072                         return ret;
4073
4074                 ret = skl_ddb_add_affected_planes(cstate);
4075                 if (ret)
4076                         return ret;
4077         }
4078
4079         return 0;
4080 }
4081
4082 static void
4083 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4084                      struct skl_wm_values *src,
4085                      enum pipe pipe)
4086 {
4087         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4088                sizeof(dst->ddb.y_plane[pipe]));
4089         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4090                sizeof(dst->ddb.plane[pipe]));
4091 }
4092
4093 static void
4094 skl_print_wm_changes(const struct drm_atomic_state *state)
4095 {
4096         const struct drm_device *dev = state->dev;
4097         const struct drm_i915_private *dev_priv = to_i915(dev);
4098         const struct intel_atomic_state *intel_state =
4099                 to_intel_atomic_state(state);
4100         const struct drm_crtc *crtc;
4101         const struct drm_crtc_state *cstate;
4102         const struct intel_plane *intel_plane;
4103         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4104         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4105         int id;
4106         int i;
4107
4108         for_each_crtc_in_state(state, crtc, cstate, i) {
4109                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4110                 enum pipe pipe = intel_crtc->pipe;
4111
4112                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4113                         const struct skl_ddb_entry *old, *new;
4114
4115                         id = skl_wm_plane_id(intel_plane);
4116                         old = &old_ddb->plane[pipe][id];
4117                         new = &new_ddb->plane[pipe][id];
4118
4119                         if (skl_ddb_entry_equal(old, new))
4120                                 continue;
4121
4122                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4123                                          intel_plane->base.base.id,
4124                                          intel_plane->base.name,
4125                                          old->start, old->end,
4126                                          new->start, new->end);
4127                 }
4128         }
4129 }
4130
4131 static int
4132 skl_compute_wm(struct drm_atomic_state *state)
4133 {
4134         struct drm_crtc *crtc;
4135         struct drm_crtc_state *cstate;
4136         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4137         struct skl_wm_values *results = &intel_state->wm_results;
4138         struct skl_pipe_wm *pipe_wm;
4139         bool changed = false;
4140         int ret, i;
4141
4142         /*
4143          * If this transaction isn't actually touching any CRTC's, don't
4144          * bother with watermark calculation.  Note that if we pass this
4145          * test, we're guaranteed to hold at least one CRTC state mutex,
4146          * which means we can safely use values like dev_priv->active_crtcs
4147          * since any racing commits that want to update them would need to
4148          * hold _all_ CRTC state mutexes.
4149          */
4150         for_each_crtc_in_state(state, crtc, cstate, i)
4151                 changed = true;
4152         if (!changed)
4153                 return 0;
4154
4155         /* Clear all dirty flags */
4156         results->dirty_pipes = 0;
4157
4158         ret = skl_compute_ddb(state);
4159         if (ret)
4160                 return ret;
4161
4162         /*
4163          * Calculate WM's for all pipes that are part of this transaction.
4164          * Note that the DDB allocation above may have added more CRTC's that
4165          * weren't otherwise being modified (and set bits in dirty_pipes) if
4166          * pipe allocations had to change.
4167          *
4168          * FIXME:  Now that we're doing this in the atomic check phase, we
4169          * should allow skl_update_pipe_wm() to return failure in cases where
4170          * no suitable watermark values can be found.
4171          */
4172         for_each_crtc_in_state(state, crtc, cstate, i) {
4173                 struct intel_crtc_state *intel_cstate =
4174                         to_intel_crtc_state(cstate);
4175                 const struct skl_pipe_wm *old_pipe_wm =
4176                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4177
4178                 pipe_wm = &intel_cstate->wm.skl.optimal;
4179                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4180                                          &results->ddb, &changed);
4181                 if (ret)
4182                         return ret;
4183
4184                 if (changed)
4185                         results->dirty_pipes |= drm_crtc_mask(crtc);
4186
4187                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4188                         /* This pipe's WM's did not change */
4189                         continue;
4190
4191                 intel_cstate->update_wm_pre = true;
4192         }
4193
4194         skl_print_wm_changes(state);
4195
4196         return 0;
4197 }
4198
4199 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4200                                       struct intel_crtc_state *cstate)
4201 {
4202         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4203         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4204         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4205         enum pipe pipe = crtc->pipe;
4206
4207         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4208 }
4209
4210 static void skl_update_wm(struct intel_crtc *intel_crtc)
4211 {
4212         struct drm_device *dev = intel_crtc->base.dev;
4213         struct drm_i915_private *dev_priv = to_i915(dev);
4214         struct skl_wm_values *results = &dev_priv->wm.skl_results;
4215         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4216         struct intel_crtc_state *cstate = to_intel_crtc_state(intel_crtc->base.state);
4217         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4218         enum pipe pipe = intel_crtc->pipe;
4219
4220         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4221                 return;
4222
4223         mutex_lock(&dev_priv->wm.wm_mutex);
4224
4225         /*
4226          * If this pipe isn't active already, we're going to be enabling it
4227          * very soon. Since it's safe to update a pipe's ddb allocation while
4228          * the pipe's shut off, just do so here. Already active pipes will have
4229          * their watermarks updated once we update their planes.
4230          */
4231         if (intel_crtc->base.state->active_changed) {
4232                 int plane;
4233
4234                 for_each_universal_plane(dev_priv, pipe, plane)
4235                         skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
4236                                            &results->ddb, plane);
4237
4238                 skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
4239                                     &results->ddb);
4240         }
4241
4242         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4243
4244         intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4245
4246         mutex_unlock(&dev_priv->wm.wm_mutex);
4247 }
4248
4249 static void ilk_compute_wm_config(struct drm_device *dev,
4250                                   struct intel_wm_config *config)
4251 {
4252         struct intel_crtc *crtc;
4253
4254         /* Compute the currently _active_ config */
4255         for_each_intel_crtc(dev, crtc) {
4256                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4257
4258                 if (!wm->pipe_enabled)
4259                         continue;
4260
4261                 config->sprites_enabled |= wm->sprites_enabled;
4262                 config->sprites_scaled |= wm->sprites_scaled;
4263                 config->num_pipes_active++;
4264         }
4265 }
4266
4267 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4268 {
4269         struct drm_device *dev = &dev_priv->drm;
4270         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4271         struct ilk_wm_maximums max;
4272         struct intel_wm_config config = {};
4273         struct ilk_wm_values results = {};
4274         enum intel_ddb_partitioning partitioning;
4275
4276         ilk_compute_wm_config(dev, &config);
4277
4278         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4279         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4280
4281         /* 5/6 split only in single pipe config on IVB+ */
4282         if (INTEL_INFO(dev)->gen >= 7 &&
4283             config.num_pipes_active == 1 && config.sprites_enabled) {
4284                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4285                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4286
4287                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4288         } else {
4289                 best_lp_wm = &lp_wm_1_2;
4290         }
4291
4292         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4293                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4294
4295         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4296
4297         ilk_write_wm_values(dev_priv, &results);
4298 }
4299
4300 static void ilk_initial_watermarks(struct intel_atomic_state *state,
4301                                    struct intel_crtc_state *cstate)
4302 {
4303         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4304         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4305
4306         mutex_lock(&dev_priv->wm.wm_mutex);
4307         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4308         ilk_program_watermarks(dev_priv);
4309         mutex_unlock(&dev_priv->wm.wm_mutex);
4310 }
4311
4312 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4313                                     struct intel_crtc_state *cstate)
4314 {
4315         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4316         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4317
4318         mutex_lock(&dev_priv->wm.wm_mutex);
4319         if (cstate->wm.need_postvbl_update) {
4320                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4321                 ilk_program_watermarks(dev_priv);
4322         }
4323         mutex_unlock(&dev_priv->wm.wm_mutex);
4324 }
4325
4326 static inline void skl_wm_level_from_reg_val(uint32_t val,
4327                                              struct skl_wm_level *level)
4328 {
4329         level->plane_en = val & PLANE_WM_EN;
4330         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4331         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4332                 PLANE_WM_LINES_MASK;
4333 }
4334
4335 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4336                               struct skl_pipe_wm *out)
4337 {
4338         struct drm_device *dev = crtc->dev;
4339         struct drm_i915_private *dev_priv = to_i915(dev);
4340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4341         struct intel_plane *intel_plane;
4342         struct skl_plane_wm *wm;
4343         enum pipe pipe = intel_crtc->pipe;
4344         int level, id, max_level;
4345         uint32_t val;
4346
4347         max_level = ilk_wm_max_level(dev_priv);
4348
4349         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4350                 id = skl_wm_plane_id(intel_plane);
4351                 wm = &out->planes[id];
4352
4353                 for (level = 0; level <= max_level; level++) {
4354                         if (id != PLANE_CURSOR)
4355                                 val = I915_READ(PLANE_WM(pipe, id, level));
4356                         else
4357                                 val = I915_READ(CUR_WM(pipe, level));
4358
4359                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
4360                 }
4361
4362                 if (id != PLANE_CURSOR)
4363                         val = I915_READ(PLANE_WM_TRANS(pipe, id));
4364                 else
4365                         val = I915_READ(CUR_WM_TRANS(pipe));
4366
4367                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4368         }
4369
4370         if (!intel_crtc->active)
4371                 return;
4372
4373         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4374 }
4375
4376 void skl_wm_get_hw_state(struct drm_device *dev)
4377 {
4378         struct drm_i915_private *dev_priv = to_i915(dev);
4379         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4380         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4381         struct drm_crtc *crtc;
4382         struct intel_crtc *intel_crtc;
4383         struct intel_crtc_state *cstate;
4384
4385         skl_ddb_get_hw_state(dev_priv, ddb);
4386         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4387                 intel_crtc = to_intel_crtc(crtc);
4388                 cstate = to_intel_crtc_state(crtc->state);
4389
4390                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4391
4392                 if (intel_crtc->active)
4393                         hw->dirty_pipes |= drm_crtc_mask(crtc);
4394         }
4395
4396         if (dev_priv->active_crtcs) {
4397                 /* Fully recompute DDB on first atomic commit */
4398                 dev_priv->wm.distrust_bios_wm = true;
4399         } else {
4400                 /* Easy/common case; just sanitize DDB now if everything off */
4401                 memset(ddb, 0, sizeof(*ddb));
4402         }
4403 }
4404
4405 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4406 {
4407         struct drm_device *dev = crtc->dev;
4408         struct drm_i915_private *dev_priv = to_i915(dev);
4409         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4411         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4412         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4413         enum pipe pipe = intel_crtc->pipe;
4414         static const i915_reg_t wm0_pipe_reg[] = {
4415                 [PIPE_A] = WM0_PIPEA_ILK,
4416                 [PIPE_B] = WM0_PIPEB_ILK,
4417                 [PIPE_C] = WM0_PIPEC_IVB,
4418         };
4419
4420         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4421         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4422                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4423
4424         memset(active, 0, sizeof(*active));
4425
4426         active->pipe_enabled = intel_crtc->active;
4427
4428         if (active->pipe_enabled) {
4429                 u32 tmp = hw->wm_pipe[pipe];
4430
4431                 /*
4432                  * For active pipes LP0 watermark is marked as
4433                  * enabled, and LP1+ watermaks as disabled since
4434                  * we can't really reverse compute them in case
4435                  * multiple pipes are active.
4436                  */
4437                 active->wm[0].enable = true;
4438                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4439                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4440                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4441                 active->linetime = hw->wm_linetime[pipe];
4442         } else {
4443                 int level, max_level = ilk_wm_max_level(dev_priv);
4444
4445                 /*
4446                  * For inactive pipes, all watermark levels
4447                  * should be marked as enabled but zeroed,
4448                  * which is what we'd compute them to.
4449                  */
4450                 for (level = 0; level <= max_level; level++)
4451                         active->wm[level].enable = true;
4452         }
4453
4454         intel_crtc->wm.active.ilk = *active;
4455 }
4456
4457 #define _FW_WM(value, plane) \
4458         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4459 #define _FW_WM_VLV(value, plane) \
4460         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4461
4462 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4463                                struct vlv_wm_values *wm)
4464 {
4465         enum pipe pipe;
4466         uint32_t tmp;
4467
4468         for_each_pipe(dev_priv, pipe) {
4469                 tmp = I915_READ(VLV_DDL(pipe));
4470
4471                 wm->ddl[pipe].primary =
4472                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4473                 wm->ddl[pipe].cursor =
4474                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4475                 wm->ddl[pipe].sprite[0] =
4476                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4477                 wm->ddl[pipe].sprite[1] =
4478                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4479         }
4480
4481         tmp = I915_READ(DSPFW1);
4482         wm->sr.plane = _FW_WM(tmp, SR);
4483         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4484         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4485         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4486
4487         tmp = I915_READ(DSPFW2);
4488         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4489         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4490         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4491
4492         tmp = I915_READ(DSPFW3);
4493         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4494
4495         if (IS_CHERRYVIEW(dev_priv)) {
4496                 tmp = I915_READ(DSPFW7_CHV);
4497                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4498                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4499
4500                 tmp = I915_READ(DSPFW8_CHV);
4501                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4502                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4503
4504                 tmp = I915_READ(DSPFW9_CHV);
4505                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4506                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4507
4508                 tmp = I915_READ(DSPHOWM);
4509                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4510                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4511                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4512                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4513                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4514                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4515                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4516                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4517                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4518                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4519         } else {
4520                 tmp = I915_READ(DSPFW7);
4521                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4522                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4523
4524                 tmp = I915_READ(DSPHOWM);
4525                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4526                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4527                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4528                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4529                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4530                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4531                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4532         }
4533 }
4534
4535 #undef _FW_WM
4536 #undef _FW_WM_VLV
4537
4538 void vlv_wm_get_hw_state(struct drm_device *dev)
4539 {
4540         struct drm_i915_private *dev_priv = to_i915(dev);
4541         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4542         struct intel_plane *plane;
4543         enum pipe pipe;
4544         u32 val;
4545
4546         vlv_read_wm_values(dev_priv, wm);
4547
4548         for_each_intel_plane(dev, plane) {
4549                 switch (plane->base.type) {
4550                         int sprite;
4551                 case DRM_PLANE_TYPE_CURSOR:
4552                         plane->wm.fifo_size = 63;
4553                         break;
4554                 case DRM_PLANE_TYPE_PRIMARY:
4555                         plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, 0);
4556                         break;
4557                 case DRM_PLANE_TYPE_OVERLAY:
4558                         sprite = plane->plane;
4559                         plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
4560                         break;
4561                 }
4562         }
4563
4564         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4565         wm->level = VLV_WM_LEVEL_PM2;
4566
4567         if (IS_CHERRYVIEW(dev_priv)) {
4568                 mutex_lock(&dev_priv->rps.hw_lock);
4569
4570                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4571                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4572                         wm->level = VLV_WM_LEVEL_PM5;
4573
4574                 /*
4575                  * If DDR DVFS is disabled in the BIOS, Punit
4576                  * will never ack the request. So if that happens
4577                  * assume we don't have to enable/disable DDR DVFS
4578                  * dynamically. To test that just set the REQ_ACK
4579                  * bit to poke the Punit, but don't change the
4580                  * HIGH/LOW bits so that we don't actually change
4581                  * the current state.
4582                  */
4583                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4584                 val |= FORCE_DDR_FREQ_REQ_ACK;
4585                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4586
4587                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4588                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4589                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4590                                       "assuming DDR DVFS is disabled\n");
4591                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4592                 } else {
4593                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4594                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4595                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4596                 }
4597
4598                 mutex_unlock(&dev_priv->rps.hw_lock);
4599         }
4600
4601         for_each_pipe(dev_priv, pipe)
4602                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4603                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4604                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4605
4606         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4607                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4608 }
4609
4610 void ilk_wm_get_hw_state(struct drm_device *dev)
4611 {
4612         struct drm_i915_private *dev_priv = to_i915(dev);
4613         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4614         struct drm_crtc *crtc;
4615
4616         for_each_crtc(dev, crtc)
4617                 ilk_pipe_wm_get_hw_state(crtc);
4618
4619         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4620         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4621         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4622
4623         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4624         if (INTEL_INFO(dev)->gen >= 7) {
4625                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4626                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4627         }
4628
4629         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4630                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4631                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4632         else if (IS_IVYBRIDGE(dev_priv))
4633                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4634                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4635
4636         hw->enable_fbc_wm =
4637                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4638 }
4639
4640 /**
4641  * intel_update_watermarks - update FIFO watermark values based on current modes
4642  *
4643  * Calculate watermark values for the various WM regs based on current mode
4644  * and plane configuration.
4645  *
4646  * There are several cases to deal with here:
4647  *   - normal (i.e. non-self-refresh)
4648  *   - self-refresh (SR) mode
4649  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4650  *   - lines are small relative to FIFO size (buffer can hold more than 2
4651  *     lines), so need to account for TLB latency
4652  *
4653  *   The normal calculation is:
4654  *     watermark = dotclock * bytes per pixel * latency
4655  *   where latency is platform & configuration dependent (we assume pessimal
4656  *   values here).
4657  *
4658  *   The SR calculation is:
4659  *     watermark = (trunc(latency/line time)+1) * surface width *
4660  *       bytes per pixel
4661  *   where
4662  *     line time = htotal / dotclock
4663  *     surface width = hdisplay for normal plane and 64 for cursor
4664  *   and latency is assumed to be high, as above.
4665  *
4666  * The final value programmed to the register should always be rounded up,
4667  * and include an extra 2 entries to account for clock crossings.
4668  *
4669  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4670  * to set the non-SR watermarks to 8.
4671  */
4672 void intel_update_watermarks(struct intel_crtc *crtc)
4673 {
4674         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4675
4676         if (dev_priv->display.update_wm)
4677                 dev_priv->display.update_wm(crtc);
4678 }
4679
4680 /*
4681  * Lock protecting IPS related data structures
4682  */
4683 DEFINE_SPINLOCK(mchdev_lock);
4684
4685 /* Global for IPS driver to get at the current i915 device. Protected by
4686  * mchdev_lock. */
4687 static struct drm_i915_private *i915_mch_dev;
4688
4689 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4690 {
4691         u16 rgvswctl;
4692
4693         assert_spin_locked(&mchdev_lock);
4694
4695         rgvswctl = I915_READ16(MEMSWCTL);
4696         if (rgvswctl & MEMCTL_CMD_STS) {
4697                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4698                 return false; /* still busy with another command */
4699         }
4700
4701         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4702                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4703         I915_WRITE16(MEMSWCTL, rgvswctl);
4704         POSTING_READ16(MEMSWCTL);
4705
4706         rgvswctl |= MEMCTL_CMD_STS;
4707         I915_WRITE16(MEMSWCTL, rgvswctl);
4708
4709         return true;
4710 }
4711
4712 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4713 {
4714         u32 rgvmodectl;
4715         u8 fmax, fmin, fstart, vstart;
4716
4717         spin_lock_irq(&mchdev_lock);
4718
4719         rgvmodectl = I915_READ(MEMMODECTL);
4720
4721         /* Enable temp reporting */
4722         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4723         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4724
4725         /* 100ms RC evaluation intervals */
4726         I915_WRITE(RCUPEI, 100000);
4727         I915_WRITE(RCDNEI, 100000);
4728
4729         /* Set max/min thresholds to 90ms and 80ms respectively */
4730         I915_WRITE(RCBMAXAVG, 90000);
4731         I915_WRITE(RCBMINAVG, 80000);
4732
4733         I915_WRITE(MEMIHYST, 1);
4734
4735         /* Set up min, max, and cur for interrupt handling */
4736         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4737         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4738         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4739                 MEMMODE_FSTART_SHIFT;
4740
4741         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4742                 PXVFREQ_PX_SHIFT;
4743
4744         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4745         dev_priv->ips.fstart = fstart;
4746
4747         dev_priv->ips.max_delay = fstart;
4748         dev_priv->ips.min_delay = fmin;
4749         dev_priv->ips.cur_delay = fstart;
4750
4751         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4752                          fmax, fmin, fstart);
4753
4754         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4755
4756         /*
4757          * Interrupts will be enabled in ironlake_irq_postinstall
4758          */
4759
4760         I915_WRITE(VIDSTART, vstart);
4761         POSTING_READ(VIDSTART);
4762
4763         rgvmodectl |= MEMMODE_SWMODE_EN;
4764         I915_WRITE(MEMMODECTL, rgvmodectl);
4765
4766         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4767                 DRM_ERROR("stuck trying to change perf mode\n");
4768         mdelay(1);
4769
4770         ironlake_set_drps(dev_priv, fstart);
4771
4772         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4773                 I915_READ(DDREC) + I915_READ(CSIEC);
4774         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4775         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4776         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4777
4778         spin_unlock_irq(&mchdev_lock);
4779 }
4780
4781 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4782 {
4783         u16 rgvswctl;
4784
4785         spin_lock_irq(&mchdev_lock);
4786
4787         rgvswctl = I915_READ16(MEMSWCTL);
4788
4789         /* Ack interrupts, disable EFC interrupt */
4790         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4791         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4792         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4793         I915_WRITE(DEIIR, DE_PCU_EVENT);
4794         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4795
4796         /* Go back to the starting frequency */
4797         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4798         mdelay(1);
4799         rgvswctl |= MEMCTL_CMD_STS;
4800         I915_WRITE(MEMSWCTL, rgvswctl);
4801         mdelay(1);
4802
4803         spin_unlock_irq(&mchdev_lock);
4804 }
4805
4806 /* There's a funny hw issue where the hw returns all 0 when reading from
4807  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4808  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4809  * all limits and the gpu stuck at whatever frequency it is at atm).
4810  */
4811 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4812 {
4813         u32 limits;
4814
4815         /* Only set the down limit when we've reached the lowest level to avoid
4816          * getting more interrupts, otherwise leave this clear. This prevents a
4817          * race in the hw when coming out of rc6: There's a tiny window where
4818          * the hw runs at the minimal clock before selecting the desired
4819          * frequency, if the down threshold expires in that window we will not
4820          * receive a down interrupt. */
4821         if (IS_GEN9(dev_priv)) {
4822                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4823                 if (val <= dev_priv->rps.min_freq_softlimit)
4824                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4825         } else {
4826                 limits = dev_priv->rps.max_freq_softlimit << 24;
4827                 if (val <= dev_priv->rps.min_freq_softlimit)
4828                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4829         }
4830
4831         return limits;
4832 }
4833
4834 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4835 {
4836         int new_power;
4837         u32 threshold_up = 0, threshold_down = 0; /* in % */
4838         u32 ei_up = 0, ei_down = 0;
4839
4840         new_power = dev_priv->rps.power;
4841         switch (dev_priv->rps.power) {
4842         case LOW_POWER:
4843                 if (val > dev_priv->rps.efficient_freq + 1 &&
4844                     val > dev_priv->rps.cur_freq)
4845                         new_power = BETWEEN;
4846                 break;
4847
4848         case BETWEEN:
4849                 if (val <= dev_priv->rps.efficient_freq &&
4850                     val < dev_priv->rps.cur_freq)
4851                         new_power = LOW_POWER;
4852                 else if (val >= dev_priv->rps.rp0_freq &&
4853                          val > dev_priv->rps.cur_freq)
4854                         new_power = HIGH_POWER;
4855                 break;
4856
4857         case HIGH_POWER:
4858                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4859                     val < dev_priv->rps.cur_freq)
4860                         new_power = BETWEEN;
4861                 break;
4862         }
4863         /* Max/min bins are special */
4864         if (val <= dev_priv->rps.min_freq_softlimit)
4865                 new_power = LOW_POWER;
4866         if (val >= dev_priv->rps.max_freq_softlimit)
4867                 new_power = HIGH_POWER;
4868         if (new_power == dev_priv->rps.power)
4869                 return;
4870
4871         /* Note the units here are not exactly 1us, but 1280ns. */
4872         switch (new_power) {
4873         case LOW_POWER:
4874                 /* Upclock if more than 95% busy over 16ms */
4875                 ei_up = 16000;
4876                 threshold_up = 95;
4877
4878                 /* Downclock if less than 85% busy over 32ms */
4879                 ei_down = 32000;
4880                 threshold_down = 85;
4881                 break;
4882
4883         case BETWEEN:
4884                 /* Upclock if more than 90% busy over 13ms */
4885                 ei_up = 13000;
4886                 threshold_up = 90;
4887
4888                 /* Downclock if less than 75% busy over 32ms */
4889                 ei_down = 32000;
4890                 threshold_down = 75;
4891                 break;
4892
4893         case HIGH_POWER:
4894                 /* Upclock if more than 85% busy over 10ms */
4895                 ei_up = 10000;
4896                 threshold_up = 85;
4897
4898                 /* Downclock if less than 60% busy over 32ms */
4899                 ei_down = 32000;
4900                 threshold_down = 60;
4901                 break;
4902         }
4903
4904         I915_WRITE(GEN6_RP_UP_EI,
4905                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4906         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4907                    GT_INTERVAL_FROM_US(dev_priv,
4908                                        ei_up * threshold_up / 100));
4909
4910         I915_WRITE(GEN6_RP_DOWN_EI,
4911                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4912         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4913                    GT_INTERVAL_FROM_US(dev_priv,
4914                                        ei_down * threshold_down / 100));
4915
4916         I915_WRITE(GEN6_RP_CONTROL,
4917                    GEN6_RP_MEDIA_TURBO |
4918                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4919                    GEN6_RP_MEDIA_IS_GFX |
4920                    GEN6_RP_ENABLE |
4921                    GEN6_RP_UP_BUSY_AVG |
4922                    GEN6_RP_DOWN_IDLE_AVG);
4923
4924         dev_priv->rps.power = new_power;
4925         dev_priv->rps.up_threshold = threshold_up;
4926         dev_priv->rps.down_threshold = threshold_down;
4927         dev_priv->rps.last_adj = 0;
4928 }
4929
4930 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4931 {
4932         u32 mask = 0;
4933
4934         if (val > dev_priv->rps.min_freq_softlimit)
4935                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4936         if (val < dev_priv->rps.max_freq_softlimit)
4937                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4938
4939         mask &= dev_priv->pm_rps_events;
4940
4941         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4942 }
4943
4944 /* gen6_set_rps is called to update the frequency request, but should also be
4945  * called when the range (min_delay and max_delay) is modified so that we can
4946  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4947 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4948 {
4949         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4950         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4951                 return;
4952
4953         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4954         WARN_ON(val > dev_priv->rps.max_freq);
4955         WARN_ON(val < dev_priv->rps.min_freq);
4956
4957         /* min/max delay may still have been modified so be sure to
4958          * write the limits value.
4959          */
4960         if (val != dev_priv->rps.cur_freq) {
4961                 gen6_set_rps_thresholds(dev_priv, val);
4962
4963                 if (IS_GEN9(dev_priv))
4964                         I915_WRITE(GEN6_RPNSWREQ,
4965                                    GEN9_FREQUENCY(val));
4966                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4967                         I915_WRITE(GEN6_RPNSWREQ,
4968                                    HSW_FREQUENCY(val));
4969                 else
4970                         I915_WRITE(GEN6_RPNSWREQ,
4971                                    GEN6_FREQUENCY(val) |
4972                                    GEN6_OFFSET(0) |
4973                                    GEN6_AGGRESSIVE_TURBO);
4974         }
4975
4976         /* Make sure we continue to get interrupts
4977          * until we hit the minimum or maximum frequencies.
4978          */
4979         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4980         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4981
4982         POSTING_READ(GEN6_RPNSWREQ);
4983
4984         dev_priv->rps.cur_freq = val;
4985         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4986 }
4987
4988 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4989 {
4990         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4991         WARN_ON(val > dev_priv->rps.max_freq);
4992         WARN_ON(val < dev_priv->rps.min_freq);
4993
4994         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4995                       "Odd GPU freq value\n"))
4996                 val &= ~1;
4997
4998         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4999
5000         if (val != dev_priv->rps.cur_freq) {
5001                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
5002                 if (!IS_CHERRYVIEW(dev_priv))
5003                         gen6_set_rps_thresholds(dev_priv, val);
5004         }
5005
5006         dev_priv->rps.cur_freq = val;
5007         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5008 }
5009
5010 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5011  *
5012  * * If Gfx is Idle, then
5013  * 1. Forcewake Media well.
5014  * 2. Request idle freq.
5015  * 3. Release Forcewake of Media well.
5016 */
5017 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5018 {
5019         u32 val = dev_priv->rps.idle_freq;
5020
5021         if (dev_priv->rps.cur_freq <= val)
5022                 return;
5023
5024         /* Wake up the media well, as that takes a lot less
5025          * power than the Render well. */
5026         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5027         valleyview_set_rps(dev_priv, val);
5028         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5029 }
5030
5031 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5032 {
5033         mutex_lock(&dev_priv->rps.hw_lock);
5034         if (dev_priv->rps.enabled) {
5035                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5036                         gen6_rps_reset_ei(dev_priv);
5037                 I915_WRITE(GEN6_PMINTRMSK,
5038                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5039
5040                 gen6_enable_rps_interrupts(dev_priv);
5041
5042                 /* Ensure we start at the user's desired frequency */
5043                 intel_set_rps(dev_priv,
5044                               clamp(dev_priv->rps.cur_freq,
5045                                     dev_priv->rps.min_freq_softlimit,
5046                                     dev_priv->rps.max_freq_softlimit));
5047         }
5048         mutex_unlock(&dev_priv->rps.hw_lock);
5049 }
5050
5051 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5052 {
5053         /* Flush our bottom-half so that it does not race with us
5054          * setting the idle frequency and so that it is bounded by
5055          * our rpm wakeref. And then disable the interrupts to stop any
5056          * futher RPS reclocking whilst we are asleep.
5057          */
5058         gen6_disable_rps_interrupts(dev_priv);
5059
5060         mutex_lock(&dev_priv->rps.hw_lock);
5061         if (dev_priv->rps.enabled) {
5062                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5063                         vlv_set_rps_idle(dev_priv);
5064                 else
5065                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5066                 dev_priv->rps.last_adj = 0;
5067                 I915_WRITE(GEN6_PMINTRMSK,
5068                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5069         }
5070         mutex_unlock(&dev_priv->rps.hw_lock);
5071
5072         spin_lock(&dev_priv->rps.client_lock);
5073         while (!list_empty(&dev_priv->rps.clients))
5074                 list_del_init(dev_priv->rps.clients.next);
5075         spin_unlock(&dev_priv->rps.client_lock);
5076 }
5077
5078 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5079                     struct intel_rps_client *rps,
5080                     unsigned long submitted)
5081 {
5082         /* This is intentionally racy! We peek at the state here, then
5083          * validate inside the RPS worker.
5084          */
5085         if (!(dev_priv->gt.awake &&
5086               dev_priv->rps.enabled &&
5087               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5088                 return;
5089
5090         /* Force a RPS boost (and don't count it against the client) if
5091          * the GPU is severely congested.
5092          */
5093         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5094                 rps = NULL;
5095
5096         spin_lock(&dev_priv->rps.client_lock);
5097         if (rps == NULL || list_empty(&rps->link)) {
5098                 spin_lock_irq(&dev_priv->irq_lock);
5099                 if (dev_priv->rps.interrupts_enabled) {
5100                         dev_priv->rps.client_boost = true;
5101                         schedule_work(&dev_priv->rps.work);
5102                 }
5103                 spin_unlock_irq(&dev_priv->irq_lock);
5104
5105                 if (rps != NULL) {
5106                         list_add(&rps->link, &dev_priv->rps.clients);
5107                         rps->boosts++;
5108                 } else
5109                         dev_priv->rps.boosts++;
5110         }
5111         spin_unlock(&dev_priv->rps.client_lock);
5112 }
5113
5114 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5115 {
5116         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5117                 valleyview_set_rps(dev_priv, val);
5118         else
5119                 gen6_set_rps(dev_priv, val);
5120 }
5121
5122 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5123 {
5124         I915_WRITE(GEN6_RC_CONTROL, 0);
5125         I915_WRITE(GEN9_PG_ENABLE, 0);
5126 }
5127
5128 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5129 {
5130         I915_WRITE(GEN6_RP_CONTROL, 0);
5131 }
5132
5133 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5134 {
5135         I915_WRITE(GEN6_RC_CONTROL, 0);
5136         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5137         I915_WRITE(GEN6_RP_CONTROL, 0);
5138 }
5139
5140 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5141 {
5142         I915_WRITE(GEN6_RC_CONTROL, 0);
5143 }
5144
5145 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5146 {
5147         /* we're doing forcewake before Disabling RC6,
5148          * This what the BIOS expects when going into suspend */
5149         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5150
5151         I915_WRITE(GEN6_RC_CONTROL, 0);
5152
5153         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5154 }
5155
5156 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5157 {
5158         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5159                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5160                         mode = GEN6_RC_CTL_RC6_ENABLE;
5161                 else
5162                         mode = 0;
5163         }
5164         if (HAS_RC6p(dev_priv))
5165                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5166                                  "RC6 %s RC6p %s RC6pp %s\n",
5167                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5168                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5169                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5170
5171         else
5172                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5173                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5174 }
5175
5176 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5177 {
5178         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5179         bool enable_rc6 = true;
5180         unsigned long rc6_ctx_base;
5181         u32 rc_ctl;
5182         int rc_sw_target;
5183
5184         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5185         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5186                        RC_SW_TARGET_STATE_SHIFT;
5187         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5188                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5189                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5190                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5191                          rc_sw_target);
5192
5193         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5194                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5195                 enable_rc6 = false;
5196         }
5197
5198         /*
5199          * The exact context size is not known for BXT, so assume a page size
5200          * for this check.
5201          */
5202         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5203         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5204               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5205                                         ggtt->stolen_reserved_size))) {
5206                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5207                 enable_rc6 = false;
5208         }
5209
5210         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5211               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5212               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5213               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5214                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5215                 enable_rc6 = false;
5216         }
5217
5218         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5219             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5220             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5221                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5222                 enable_rc6 = false;
5223         }
5224
5225         if (!I915_READ(GEN6_GFXPAUSE)) {
5226                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5227                 enable_rc6 = false;
5228         }
5229
5230         if (!I915_READ(GEN8_MISC_CTRL0)) {
5231                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5232                 enable_rc6 = false;
5233         }
5234
5235         return enable_rc6;
5236 }
5237
5238 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5239 {
5240         /* No RC6 before Ironlake and code is gone for ilk. */
5241         if (INTEL_INFO(dev_priv)->gen < 6)
5242                 return 0;
5243
5244         if (!enable_rc6)
5245                 return 0;
5246
5247         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5248                 DRM_INFO("RC6 disabled by BIOS\n");
5249                 return 0;
5250         }
5251
5252         /* Respect the kernel parameter if it is set */
5253         if (enable_rc6 >= 0) {
5254                 int mask;
5255
5256                 if (HAS_RC6p(dev_priv))
5257                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5258                                INTEL_RC6pp_ENABLE;
5259                 else
5260                         mask = INTEL_RC6_ENABLE;
5261
5262                 if ((enable_rc6 & mask) != enable_rc6)
5263                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5264                                          "(requested %d, valid %d)\n",
5265                                          enable_rc6 & mask, enable_rc6, mask);
5266
5267                 return enable_rc6 & mask;
5268         }
5269
5270         if (IS_IVYBRIDGE(dev_priv))
5271                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5272
5273         return INTEL_RC6_ENABLE;
5274 }
5275
5276 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5277 {
5278         /* All of these values are in units of 50MHz */
5279
5280         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5281         if (IS_BROXTON(dev_priv)) {
5282                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5283                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5284                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5285                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5286         } else {
5287                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5288                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5289                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5290                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5291         }
5292         /* hw_max = RP0 until we check for overclocking */
5293         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5294
5295         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5296         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5297             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5298                 u32 ddcc_status = 0;
5299
5300                 if (sandybridge_pcode_read(dev_priv,
5301                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5302                                            &ddcc_status) == 0)
5303                         dev_priv->rps.efficient_freq =
5304                                 clamp_t(u8,
5305                                         ((ddcc_status >> 8) & 0xff),
5306                                         dev_priv->rps.min_freq,
5307                                         dev_priv->rps.max_freq);
5308         }
5309
5310         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5311                 /* Store the frequency values in 16.66 MHZ units, which is
5312                  * the natural hardware unit for SKL
5313                  */
5314                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5315                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5316                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5317                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5318                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5319         }
5320 }
5321
5322 static void reset_rps(struct drm_i915_private *dev_priv,
5323                       void (*set)(struct drm_i915_private *, u8))
5324 {
5325         u8 freq = dev_priv->rps.cur_freq;
5326
5327         /* force a reset */
5328         dev_priv->rps.power = -1;
5329         dev_priv->rps.cur_freq = -1;
5330
5331         set(dev_priv, freq);
5332 }
5333
5334 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5335 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5336 {
5337         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5338
5339         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5340         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5341                 /*
5342                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5343                  * clear out the Control register just to avoid inconsitency
5344                  * with debugfs interface, which will show  Turbo as enabled
5345                  * only and that is not expected by the User after adding the
5346                  * WaGsvDisableTurbo. Apart from this there is no problem even
5347                  * if the Turbo is left enabled in the Control register, as the
5348                  * Up/Down interrupts would remain masked.
5349                  */
5350                 gen9_disable_rps(dev_priv);
5351                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5352                 return;
5353         }
5354
5355         /* Program defaults and thresholds for RPS*/
5356         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5357                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5358
5359         /* 1 second timeout*/
5360         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5361                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5362
5363         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5364
5365         /* Leaning on the below call to gen6_set_rps to program/setup the
5366          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5367          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5368         reset_rps(dev_priv, gen6_set_rps);
5369
5370         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5371 }
5372
5373 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5374 {
5375         struct intel_engine_cs *engine;
5376         enum intel_engine_id id;
5377         uint32_t rc6_mask = 0;
5378
5379         /* 1a: Software RC state - RC0 */
5380         I915_WRITE(GEN6_RC_STATE, 0);
5381
5382         /* 1b: Get forcewake during program sequence. Although the driver
5383          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5384         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5385
5386         /* 2a: Disable RC states. */
5387         I915_WRITE(GEN6_RC_CONTROL, 0);
5388
5389         /* 2b: Program RC6 thresholds.*/
5390
5391         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5392         if (IS_SKYLAKE(dev_priv))
5393                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5394         else
5395                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5396         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5397         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5398         for_each_engine(engine, dev_priv, id)
5399                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5400
5401         if (HAS_GUC(dev_priv))
5402                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5403
5404         I915_WRITE(GEN6_RC_SLEEP, 0);
5405
5406         /* 2c: Program Coarse Power Gating Policies. */
5407         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5408         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5409
5410         /* 3a: Enable RC6 */
5411         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5412                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5413         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5414         /* WaRsUseTimeoutMode:bxt */
5415         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5416                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5417                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5418                            GEN7_RC_CTL_TO_MODE |
5419                            rc6_mask);
5420         } else {
5421                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5422                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5423                            GEN6_RC_CTL_EI_MODE(1) |
5424                            rc6_mask);
5425         }
5426
5427         /*
5428          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5429          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5430          */
5431         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5432                 I915_WRITE(GEN9_PG_ENABLE, 0);
5433         else
5434                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5435                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5436
5437         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5438 }
5439
5440 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5441 {
5442         struct intel_engine_cs *engine;
5443         enum intel_engine_id id;
5444         uint32_t rc6_mask = 0;
5445
5446         /* 1a: Software RC state - RC0 */
5447         I915_WRITE(GEN6_RC_STATE, 0);
5448
5449         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5450          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5451         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5452
5453         /* 2a: Disable RC states. */
5454         I915_WRITE(GEN6_RC_CONTROL, 0);
5455
5456         /* 2b: Program RC6 thresholds.*/
5457         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5458         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5459         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5460         for_each_engine(engine, dev_priv, id)
5461                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5462         I915_WRITE(GEN6_RC_SLEEP, 0);
5463         if (IS_BROADWELL(dev_priv))
5464                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5465         else
5466                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5467
5468         /* 3: Enable RC6 */
5469         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5470                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5471         intel_print_rc6_info(dev_priv, rc6_mask);
5472         if (IS_BROADWELL(dev_priv))
5473                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5474                                 GEN7_RC_CTL_TO_MODE |
5475                                 rc6_mask);
5476         else
5477                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5478                                 GEN6_RC_CTL_EI_MODE(1) |
5479                                 rc6_mask);
5480
5481         /* 4 Program defaults and thresholds for RPS*/
5482         I915_WRITE(GEN6_RPNSWREQ,
5483                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5484         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5485                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5486         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5487         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5488
5489         /* Docs recommend 900MHz, and 300 MHz respectively */
5490         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5491                    dev_priv->rps.max_freq_softlimit << 24 |
5492                    dev_priv->rps.min_freq_softlimit << 16);
5493
5494         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5495         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5496         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5497         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5498
5499         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5500
5501         /* 5: Enable RPS */
5502         I915_WRITE(GEN6_RP_CONTROL,
5503                    GEN6_RP_MEDIA_TURBO |
5504                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5505                    GEN6_RP_MEDIA_IS_GFX |
5506                    GEN6_RP_ENABLE |
5507                    GEN6_RP_UP_BUSY_AVG |
5508                    GEN6_RP_DOWN_IDLE_AVG);
5509
5510         /* 6: Ring frequency + overclocking (our driver does this later */
5511
5512         reset_rps(dev_priv, gen6_set_rps);
5513
5514         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5515 }
5516
5517 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5518 {
5519         struct intel_engine_cs *engine;
5520         enum intel_engine_id id;
5521         u32 rc6vids, rc6_mask = 0;
5522         u32 gtfifodbg;
5523         int rc6_mode;
5524         int ret;
5525
5526         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5527
5528         /* Here begins a magic sequence of register writes to enable
5529          * auto-downclocking.
5530          *
5531          * Perhaps there might be some value in exposing these to
5532          * userspace...
5533          */
5534         I915_WRITE(GEN6_RC_STATE, 0);
5535
5536         /* Clear the DBG now so we don't confuse earlier errors */
5537         gtfifodbg = I915_READ(GTFIFODBG);
5538         if (gtfifodbg) {
5539                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5540                 I915_WRITE(GTFIFODBG, gtfifodbg);
5541         }
5542
5543         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5544
5545         /* disable the counters and set deterministic thresholds */
5546         I915_WRITE(GEN6_RC_CONTROL, 0);
5547
5548         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5549         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5550         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5551         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5552         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5553
5554         for_each_engine(engine, dev_priv, id)
5555                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5556
5557         I915_WRITE(GEN6_RC_SLEEP, 0);
5558         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5559         if (IS_IVYBRIDGE(dev_priv))
5560                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5561         else
5562                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5563         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5564         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5565
5566         /* Check if we are enabling RC6 */
5567         rc6_mode = intel_enable_rc6();
5568         if (rc6_mode & INTEL_RC6_ENABLE)
5569                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5570
5571         /* We don't use those on Haswell */
5572         if (!IS_HASWELL(dev_priv)) {
5573                 if (rc6_mode & INTEL_RC6p_ENABLE)
5574                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5575
5576                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5577                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5578         }
5579
5580         intel_print_rc6_info(dev_priv, rc6_mask);
5581
5582         I915_WRITE(GEN6_RC_CONTROL,
5583                    rc6_mask |
5584                    GEN6_RC_CTL_EI_MODE(1) |
5585                    GEN6_RC_CTL_HW_ENABLE);
5586
5587         /* Power down if completely idle for over 50ms */
5588         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5589         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5590
5591         reset_rps(dev_priv, gen6_set_rps);
5592
5593         rc6vids = 0;
5594         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5595         if (IS_GEN6(dev_priv) && ret) {
5596                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5597         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5598                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5599                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5600                 rc6vids &= 0xffff00;
5601                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5602                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5603                 if (ret)
5604                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5605         }
5606
5607         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5608 }
5609
5610 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5611 {
5612         int min_freq = 15;
5613         unsigned int gpu_freq;
5614         unsigned int max_ia_freq, min_ring_freq;
5615         unsigned int max_gpu_freq, min_gpu_freq;
5616         int scaling_factor = 180;
5617         struct cpufreq_policy *policy;
5618
5619         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5620
5621         policy = cpufreq_cpu_get(0);
5622         if (policy) {
5623                 max_ia_freq = policy->cpuinfo.max_freq;
5624                 cpufreq_cpu_put(policy);
5625         } else {
5626                 /*
5627                  * Default to measured freq if none found, PCU will ensure we
5628                  * don't go over
5629                  */
5630                 max_ia_freq = tsc_khz;
5631         }
5632
5633         /* Convert from kHz to MHz */
5634         max_ia_freq /= 1000;
5635
5636         min_ring_freq = I915_READ(DCLK) & 0xf;
5637         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5638         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5639
5640         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5641                 /* Convert GT frequency to 50 HZ units */
5642                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5643                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5644         } else {
5645                 min_gpu_freq = dev_priv->rps.min_freq;
5646                 max_gpu_freq = dev_priv->rps.max_freq;
5647         }
5648
5649         /*
5650          * For each potential GPU frequency, load a ring frequency we'd like
5651          * to use for memory access.  We do this by specifying the IA frequency
5652          * the PCU should use as a reference to determine the ring frequency.
5653          */
5654         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5655                 int diff = max_gpu_freq - gpu_freq;
5656                 unsigned int ia_freq = 0, ring_freq = 0;
5657
5658                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5659                         /*
5660                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5661                          * No floor required for ring frequency on SKL.
5662                          */
5663                         ring_freq = gpu_freq;
5664                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5665                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5666                         ring_freq = max(min_ring_freq, gpu_freq);
5667                 } else if (IS_HASWELL(dev_priv)) {
5668                         ring_freq = mult_frac(gpu_freq, 5, 4);
5669                         ring_freq = max(min_ring_freq, ring_freq);
5670                         /* leave ia_freq as the default, chosen by cpufreq */
5671                 } else {
5672                         /* On older processors, there is no separate ring
5673                          * clock domain, so in order to boost the bandwidth
5674                          * of the ring, we need to upclock the CPU (ia_freq).
5675                          *
5676                          * For GPU frequencies less than 750MHz,
5677                          * just use the lowest ring freq.
5678                          */
5679                         if (gpu_freq < min_freq)
5680                                 ia_freq = 800;
5681                         else
5682                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5683                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5684                 }
5685
5686                 sandybridge_pcode_write(dev_priv,
5687                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5688                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5689                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5690                                         gpu_freq);
5691         }
5692 }
5693
5694 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5695 {
5696         u32 val, rp0;
5697
5698         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5699
5700         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5701         case 8:
5702                 /* (2 * 4) config */
5703                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5704                 break;
5705         case 12:
5706                 /* (2 * 6) config */
5707                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5708                 break;
5709         case 16:
5710                 /* (2 * 8) config */
5711         default:
5712                 /* Setting (2 * 8) Min RP0 for any other combination */
5713                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5714                 break;
5715         }
5716
5717         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5718
5719         return rp0;
5720 }
5721
5722 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5723 {
5724         u32 val, rpe;
5725
5726         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5727         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5728
5729         return rpe;
5730 }
5731
5732 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5733 {
5734         u32 val, rp1;
5735
5736         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5737         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5738
5739         return rp1;
5740 }
5741
5742 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5743 {
5744         u32 val, rp1;
5745
5746         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5747
5748         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5749
5750         return rp1;
5751 }
5752
5753 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5754 {
5755         u32 val, rp0;
5756
5757         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5758
5759         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5760         /* Clamp to max */
5761         rp0 = min_t(u32, rp0, 0xea);
5762
5763         return rp0;
5764 }
5765
5766 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5767 {
5768         u32 val, rpe;
5769
5770         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5771         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5772         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5773         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5774
5775         return rpe;
5776 }
5777
5778 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5779 {
5780         u32 val;
5781
5782         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5783         /*
5784          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5785          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5786          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5787          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5788          * to make sure it matches what Punit accepts.
5789          */
5790         return max_t(u32, val, 0xc0);
5791 }
5792
5793 /* Check that the pctx buffer wasn't move under us. */
5794 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5795 {
5796         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5797
5798         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5799                              dev_priv->vlv_pctx->stolen->start);
5800 }
5801
5802
5803 /* Check that the pcbr address is not empty. */
5804 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5805 {
5806         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5807
5808         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5809 }
5810
5811 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5812 {
5813         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5814         unsigned long pctx_paddr, paddr;
5815         u32 pcbr;
5816         int pctx_size = 32*1024;
5817
5818         pcbr = I915_READ(VLV_PCBR);
5819         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5820                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5821                 paddr = (dev_priv->mm.stolen_base +
5822                          (ggtt->stolen_size - pctx_size));
5823
5824                 pctx_paddr = (paddr & (~4095));
5825                 I915_WRITE(VLV_PCBR, pctx_paddr);
5826         }
5827
5828         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5829 }
5830
5831 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5832 {
5833         struct drm_i915_gem_object *pctx;
5834         unsigned long pctx_paddr;
5835         u32 pcbr;
5836         int pctx_size = 24*1024;
5837
5838         pcbr = I915_READ(VLV_PCBR);
5839         if (pcbr) {
5840                 /* BIOS set it up already, grab the pre-alloc'd space */
5841                 int pcbr_offset;
5842
5843                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5844                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5845                                                                       pcbr_offset,
5846                                                                       I915_GTT_OFFSET_NONE,
5847                                                                       pctx_size);
5848                 goto out;
5849         }
5850
5851         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5852
5853         /*
5854          * From the Gunit register HAS:
5855          * The Gfx driver is expected to program this register and ensure
5856          * proper allocation within Gfx stolen memory.  For example, this
5857          * register should be programmed such than the PCBR range does not
5858          * overlap with other ranges, such as the frame buffer, protected
5859          * memory, or any other relevant ranges.
5860          */
5861         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5862         if (!pctx) {
5863                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5864                 goto out;
5865         }
5866
5867         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5868         I915_WRITE(VLV_PCBR, pctx_paddr);
5869
5870 out:
5871         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5872         dev_priv->vlv_pctx = pctx;
5873 }
5874
5875 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5876 {
5877         if (WARN_ON(!dev_priv->vlv_pctx))
5878                 return;
5879
5880         i915_gem_object_put(dev_priv->vlv_pctx);
5881         dev_priv->vlv_pctx = NULL;
5882 }
5883
5884 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5885 {
5886         dev_priv->rps.gpll_ref_freq =
5887                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5888                                   CCK_GPLL_CLOCK_CONTROL,
5889                                   dev_priv->czclk_freq);
5890
5891         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5892                          dev_priv->rps.gpll_ref_freq);
5893 }
5894
5895 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5896 {
5897         u32 val;
5898
5899         valleyview_setup_pctx(dev_priv);
5900
5901         vlv_init_gpll_ref_freq(dev_priv);
5902
5903         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5904         switch ((val >> 6) & 3) {
5905         case 0:
5906         case 1:
5907                 dev_priv->mem_freq = 800;
5908                 break;
5909         case 2:
5910                 dev_priv->mem_freq = 1066;
5911                 break;
5912         case 3:
5913                 dev_priv->mem_freq = 1333;
5914                 break;
5915         }
5916         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5917
5918         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5919         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5920         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5921                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5922                          dev_priv->rps.max_freq);
5923
5924         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5925         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5926                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5927                          dev_priv->rps.efficient_freq);
5928
5929         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5930         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5931                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5932                          dev_priv->rps.rp1_freq);
5933
5934         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5935         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5936                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5937                          dev_priv->rps.min_freq);
5938 }
5939
5940 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5941 {
5942         u32 val;
5943
5944         cherryview_setup_pctx(dev_priv);
5945
5946         vlv_init_gpll_ref_freq(dev_priv);
5947
5948         mutex_lock(&dev_priv->sb_lock);
5949         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5950         mutex_unlock(&dev_priv->sb_lock);
5951
5952         switch ((val >> 2) & 0x7) {
5953         case 3:
5954                 dev_priv->mem_freq = 2000;
5955                 break;
5956         default:
5957                 dev_priv->mem_freq = 1600;
5958                 break;
5959         }
5960         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5961
5962         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5963         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5964         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5965                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5966                          dev_priv->rps.max_freq);
5967
5968         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5969         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5970                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5971                          dev_priv->rps.efficient_freq);
5972
5973         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5974         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5975                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5976                          dev_priv->rps.rp1_freq);
5977
5978         /* PUnit validated range is only [RPe, RP0] */
5979         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5980         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5981                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5982                          dev_priv->rps.min_freq);
5983
5984         WARN_ONCE((dev_priv->rps.max_freq |
5985                    dev_priv->rps.efficient_freq |
5986                    dev_priv->rps.rp1_freq |
5987                    dev_priv->rps.min_freq) & 1,
5988                   "Odd GPU freq values\n");
5989 }
5990
5991 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5992 {
5993         valleyview_cleanup_pctx(dev_priv);
5994 }
5995
5996 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5997 {
5998         struct intel_engine_cs *engine;
5999         enum intel_engine_id id;
6000         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
6001
6002         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6003
6004         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6005                                              GT_FIFO_FREE_ENTRIES_CHV);
6006         if (gtfifodbg) {
6007                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6008                                  gtfifodbg);
6009                 I915_WRITE(GTFIFODBG, gtfifodbg);
6010         }
6011
6012         cherryview_check_pctx(dev_priv);
6013
6014         /* 1a & 1b: Get forcewake during program sequence. Although the driver
6015          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6016         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6017
6018         /*  Disable RC states. */
6019         I915_WRITE(GEN6_RC_CONTROL, 0);
6020
6021         /* 2a: Program RC6 thresholds.*/
6022         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6023         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6024         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6025
6026         for_each_engine(engine, dev_priv, id)
6027                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6028         I915_WRITE(GEN6_RC_SLEEP, 0);
6029
6030         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6031         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6032
6033         /* allows RC6 residency counter to work */
6034         I915_WRITE(VLV_COUNTER_CONTROL,
6035                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6036                                       VLV_MEDIA_RC6_COUNT_EN |
6037                                       VLV_RENDER_RC6_COUNT_EN));
6038
6039         /* For now we assume BIOS is allocating and populating the PCBR  */
6040         pcbr = I915_READ(VLV_PCBR);
6041
6042         /* 3: Enable RC6 */
6043         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6044             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6045                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6046
6047         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6048
6049         /* 4 Program defaults and thresholds for RPS*/
6050         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6051         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6052         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6053         I915_WRITE(GEN6_RP_UP_EI, 66000);
6054         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6055
6056         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6057
6058         /* 5: Enable RPS */
6059         I915_WRITE(GEN6_RP_CONTROL,
6060                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6061                    GEN6_RP_MEDIA_IS_GFX |
6062                    GEN6_RP_ENABLE |
6063                    GEN6_RP_UP_BUSY_AVG |
6064                    GEN6_RP_DOWN_IDLE_AVG);
6065
6066         /* Setting Fixed Bias */
6067         val = VLV_OVERRIDE_EN |
6068                   VLV_SOC_TDP_EN |
6069                   CHV_BIAS_CPU_50_SOC_50;
6070         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6071
6072         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6073
6074         /* RPS code assumes GPLL is used */
6075         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6076
6077         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6078         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6079
6080         reset_rps(dev_priv, valleyview_set_rps);
6081
6082         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6083 }
6084
6085 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6086 {
6087         struct intel_engine_cs *engine;
6088         enum intel_engine_id id;
6089         u32 gtfifodbg, val, rc6_mode = 0;
6090
6091         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6092
6093         valleyview_check_pctx(dev_priv);
6094
6095         gtfifodbg = I915_READ(GTFIFODBG);
6096         if (gtfifodbg) {
6097                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6098                                  gtfifodbg);
6099                 I915_WRITE(GTFIFODBG, gtfifodbg);
6100         }
6101
6102         /* If VLV, Forcewake all wells, else re-direct to regular path */
6103         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6104
6105         /*  Disable RC states. */
6106         I915_WRITE(GEN6_RC_CONTROL, 0);
6107
6108         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6109         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6110         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6111         I915_WRITE(GEN6_RP_UP_EI, 66000);
6112         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6113
6114         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6115
6116         I915_WRITE(GEN6_RP_CONTROL,
6117                    GEN6_RP_MEDIA_TURBO |
6118                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6119                    GEN6_RP_MEDIA_IS_GFX |
6120                    GEN6_RP_ENABLE |
6121                    GEN6_RP_UP_BUSY_AVG |
6122                    GEN6_RP_DOWN_IDLE_CONT);
6123
6124         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6125         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6126         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6127
6128         for_each_engine(engine, dev_priv, id)
6129                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6130
6131         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6132
6133         /* allows RC6 residency counter to work */
6134         I915_WRITE(VLV_COUNTER_CONTROL,
6135                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6136                                       VLV_RENDER_RC0_COUNT_EN |
6137                                       VLV_MEDIA_RC6_COUNT_EN |
6138                                       VLV_RENDER_RC6_COUNT_EN));
6139
6140         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6141                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6142
6143         intel_print_rc6_info(dev_priv, rc6_mode);
6144
6145         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6146
6147         /* Setting Fixed Bias */
6148         val = VLV_OVERRIDE_EN |
6149                   VLV_SOC_TDP_EN |
6150                   VLV_BIAS_CPU_125_SOC_875;
6151         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6152
6153         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6154
6155         /* RPS code assumes GPLL is used */
6156         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6157
6158         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6159         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6160
6161         reset_rps(dev_priv, valleyview_set_rps);
6162
6163         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6164 }
6165
6166 static unsigned long intel_pxfreq(u32 vidfreq)
6167 {
6168         unsigned long freq;
6169         int div = (vidfreq & 0x3f0000) >> 16;
6170         int post = (vidfreq & 0x3000) >> 12;
6171         int pre = (vidfreq & 0x7);
6172
6173         if (!pre)
6174                 return 0;
6175
6176         freq = ((div * 133333) / ((1<<post) * pre));
6177
6178         return freq;
6179 }
6180
6181 static const struct cparams {
6182         u16 i;
6183         u16 t;
6184         u16 m;
6185         u16 c;
6186 } cparams[] = {
6187         { 1, 1333, 301, 28664 },
6188         { 1, 1066, 294, 24460 },
6189         { 1, 800, 294, 25192 },
6190         { 0, 1333, 276, 27605 },
6191         { 0, 1066, 276, 27605 },
6192         { 0, 800, 231, 23784 },
6193 };
6194
6195 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6196 {
6197         u64 total_count, diff, ret;
6198         u32 count1, count2, count3, m = 0, c = 0;
6199         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6200         int i;
6201
6202         assert_spin_locked(&mchdev_lock);
6203
6204         diff1 = now - dev_priv->ips.last_time1;
6205
6206         /* Prevent division-by-zero if we are asking too fast.
6207          * Also, we don't get interesting results if we are polling
6208          * faster than once in 10ms, so just return the saved value
6209          * in such cases.
6210          */
6211         if (diff1 <= 10)
6212                 return dev_priv->ips.chipset_power;
6213
6214         count1 = I915_READ(DMIEC);
6215         count2 = I915_READ(DDREC);
6216         count3 = I915_READ(CSIEC);
6217
6218         total_count = count1 + count2 + count3;
6219
6220         /* FIXME: handle per-counter overflow */
6221         if (total_count < dev_priv->ips.last_count1) {
6222                 diff = ~0UL - dev_priv->ips.last_count1;
6223                 diff += total_count;
6224         } else {
6225                 diff = total_count - dev_priv->ips.last_count1;
6226         }
6227
6228         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6229                 if (cparams[i].i == dev_priv->ips.c_m &&
6230                     cparams[i].t == dev_priv->ips.r_t) {
6231                         m = cparams[i].m;
6232                         c = cparams[i].c;
6233                         break;
6234                 }
6235         }
6236
6237         diff = div_u64(diff, diff1);
6238         ret = ((m * diff) + c);
6239         ret = div_u64(ret, 10);
6240
6241         dev_priv->ips.last_count1 = total_count;
6242         dev_priv->ips.last_time1 = now;
6243
6244         dev_priv->ips.chipset_power = ret;
6245
6246         return ret;
6247 }
6248
6249 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6250 {
6251         unsigned long val;
6252
6253         if (INTEL_INFO(dev_priv)->gen != 5)
6254                 return 0;
6255
6256         spin_lock_irq(&mchdev_lock);
6257
6258         val = __i915_chipset_val(dev_priv);
6259
6260         spin_unlock_irq(&mchdev_lock);
6261
6262         return val;
6263 }
6264
6265 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6266 {
6267         unsigned long m, x, b;
6268         u32 tsfs;
6269
6270         tsfs = I915_READ(TSFS);
6271
6272         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6273         x = I915_READ8(TR1);
6274
6275         b = tsfs & TSFS_INTR_MASK;
6276
6277         return ((m * x) / 127) - b;
6278 }
6279
6280 static int _pxvid_to_vd(u8 pxvid)
6281 {
6282         if (pxvid == 0)
6283                 return 0;
6284
6285         if (pxvid >= 8 && pxvid < 31)
6286                 pxvid = 31;
6287
6288         return (pxvid + 2) * 125;
6289 }
6290
6291 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6292 {
6293         const int vd = _pxvid_to_vd(pxvid);
6294         const int vm = vd - 1125;
6295
6296         if (INTEL_INFO(dev_priv)->is_mobile)
6297                 return vm > 0 ? vm : 0;
6298
6299         return vd;
6300 }
6301
6302 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6303 {
6304         u64 now, diff, diffms;
6305         u32 count;
6306
6307         assert_spin_locked(&mchdev_lock);
6308
6309         now = ktime_get_raw_ns();
6310         diffms = now - dev_priv->ips.last_time2;
6311         do_div(diffms, NSEC_PER_MSEC);
6312
6313         /* Don't divide by 0 */
6314         if (!diffms)
6315                 return;
6316
6317         count = I915_READ(GFXEC);
6318
6319         if (count < dev_priv->ips.last_count2) {
6320                 diff = ~0UL - dev_priv->ips.last_count2;
6321                 diff += count;
6322         } else {
6323                 diff = count - dev_priv->ips.last_count2;
6324         }
6325
6326         dev_priv->ips.last_count2 = count;
6327         dev_priv->ips.last_time2 = now;
6328
6329         /* More magic constants... */
6330         diff = diff * 1181;
6331         diff = div_u64(diff, diffms * 10);
6332         dev_priv->ips.gfx_power = diff;
6333 }
6334
6335 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6336 {
6337         if (INTEL_INFO(dev_priv)->gen != 5)
6338                 return;
6339
6340         spin_lock_irq(&mchdev_lock);
6341
6342         __i915_update_gfx_val(dev_priv);
6343
6344         spin_unlock_irq(&mchdev_lock);
6345 }
6346
6347 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6348 {
6349         unsigned long t, corr, state1, corr2, state2;
6350         u32 pxvid, ext_v;
6351
6352         assert_spin_locked(&mchdev_lock);
6353
6354         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6355         pxvid = (pxvid >> 24) & 0x7f;
6356         ext_v = pvid_to_extvid(dev_priv, pxvid);
6357
6358         state1 = ext_v;
6359
6360         t = i915_mch_val(dev_priv);
6361
6362         /* Revel in the empirically derived constants */
6363
6364         /* Correction factor in 1/100000 units */
6365         if (t > 80)
6366                 corr = ((t * 2349) + 135940);
6367         else if (t >= 50)
6368                 corr = ((t * 964) + 29317);
6369         else /* < 50 */
6370                 corr = ((t * 301) + 1004);
6371
6372         corr = corr * ((150142 * state1) / 10000 - 78642);
6373         corr /= 100000;
6374         corr2 = (corr * dev_priv->ips.corr);
6375
6376         state2 = (corr2 * state1) / 10000;
6377         state2 /= 100; /* convert to mW */
6378
6379         __i915_update_gfx_val(dev_priv);
6380
6381         return dev_priv->ips.gfx_power + state2;
6382 }
6383
6384 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6385 {
6386         unsigned long val;
6387
6388         if (INTEL_INFO(dev_priv)->gen != 5)
6389                 return 0;
6390
6391         spin_lock_irq(&mchdev_lock);
6392
6393         val = __i915_gfx_val(dev_priv);
6394
6395         spin_unlock_irq(&mchdev_lock);
6396
6397         return val;
6398 }
6399
6400 /**
6401  * i915_read_mch_val - return value for IPS use
6402  *
6403  * Calculate and return a value for the IPS driver to use when deciding whether
6404  * we have thermal and power headroom to increase CPU or GPU power budget.
6405  */
6406 unsigned long i915_read_mch_val(void)
6407 {
6408         struct drm_i915_private *dev_priv;
6409         unsigned long chipset_val, graphics_val, ret = 0;
6410
6411         spin_lock_irq(&mchdev_lock);
6412         if (!i915_mch_dev)
6413                 goto out_unlock;
6414         dev_priv = i915_mch_dev;
6415
6416         chipset_val = __i915_chipset_val(dev_priv);
6417         graphics_val = __i915_gfx_val(dev_priv);
6418
6419         ret = chipset_val + graphics_val;
6420
6421 out_unlock:
6422         spin_unlock_irq(&mchdev_lock);
6423
6424         return ret;
6425 }
6426 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6427
6428 /**
6429  * i915_gpu_raise - raise GPU frequency limit
6430  *
6431  * Raise the limit; IPS indicates we have thermal headroom.
6432  */
6433 bool i915_gpu_raise(void)
6434 {
6435         struct drm_i915_private *dev_priv;
6436         bool ret = true;
6437
6438         spin_lock_irq(&mchdev_lock);
6439         if (!i915_mch_dev) {
6440                 ret = false;
6441                 goto out_unlock;
6442         }
6443         dev_priv = i915_mch_dev;
6444
6445         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6446                 dev_priv->ips.max_delay--;
6447
6448 out_unlock:
6449         spin_unlock_irq(&mchdev_lock);
6450
6451         return ret;
6452 }
6453 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6454
6455 /**
6456  * i915_gpu_lower - lower GPU frequency limit
6457  *
6458  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6459  * frequency maximum.
6460  */
6461 bool i915_gpu_lower(void)
6462 {
6463         struct drm_i915_private *dev_priv;
6464         bool ret = true;
6465
6466         spin_lock_irq(&mchdev_lock);
6467         if (!i915_mch_dev) {
6468                 ret = false;
6469                 goto out_unlock;
6470         }
6471         dev_priv = i915_mch_dev;
6472
6473         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6474                 dev_priv->ips.max_delay++;
6475
6476 out_unlock:
6477         spin_unlock_irq(&mchdev_lock);
6478
6479         return ret;
6480 }
6481 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6482
6483 /**
6484  * i915_gpu_busy - indicate GPU business to IPS
6485  *
6486  * Tell the IPS driver whether or not the GPU is busy.
6487  */
6488 bool i915_gpu_busy(void)
6489 {
6490         bool ret = false;
6491
6492         spin_lock_irq(&mchdev_lock);
6493         if (i915_mch_dev)
6494                 ret = i915_mch_dev->gt.awake;
6495         spin_unlock_irq(&mchdev_lock);
6496
6497         return ret;
6498 }
6499 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6500
6501 /**
6502  * i915_gpu_turbo_disable - disable graphics turbo
6503  *
6504  * Disable graphics turbo by resetting the max frequency and setting the
6505  * current frequency to the default.
6506  */
6507 bool i915_gpu_turbo_disable(void)
6508 {
6509         struct drm_i915_private *dev_priv;
6510         bool ret = true;
6511
6512         spin_lock_irq(&mchdev_lock);
6513         if (!i915_mch_dev) {
6514                 ret = false;
6515                 goto out_unlock;
6516         }
6517         dev_priv = i915_mch_dev;
6518
6519         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6520
6521         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6522                 ret = false;
6523
6524 out_unlock:
6525         spin_unlock_irq(&mchdev_lock);
6526
6527         return ret;
6528 }
6529 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6530
6531 /**
6532  * Tells the intel_ips driver that the i915 driver is now loaded, if
6533  * IPS got loaded first.
6534  *
6535  * This awkward dance is so that neither module has to depend on the
6536  * other in order for IPS to do the appropriate communication of
6537  * GPU turbo limits to i915.
6538  */
6539 static void
6540 ips_ping_for_i915_load(void)
6541 {
6542         void (*link)(void);
6543
6544         link = symbol_get(ips_link_to_i915_driver);
6545         if (link) {
6546                 link();
6547                 symbol_put(ips_link_to_i915_driver);
6548         }
6549 }
6550
6551 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6552 {
6553         /* We only register the i915 ips part with intel-ips once everything is
6554          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6555         spin_lock_irq(&mchdev_lock);
6556         i915_mch_dev = dev_priv;
6557         spin_unlock_irq(&mchdev_lock);
6558
6559         ips_ping_for_i915_load();
6560 }
6561
6562 void intel_gpu_ips_teardown(void)
6563 {
6564         spin_lock_irq(&mchdev_lock);
6565         i915_mch_dev = NULL;
6566         spin_unlock_irq(&mchdev_lock);
6567 }
6568
6569 static void intel_init_emon(struct drm_i915_private *dev_priv)
6570 {
6571         u32 lcfuse;
6572         u8 pxw[16];
6573         int i;
6574
6575         /* Disable to program */
6576         I915_WRITE(ECR, 0);
6577         POSTING_READ(ECR);
6578
6579         /* Program energy weights for various events */
6580         I915_WRITE(SDEW, 0x15040d00);
6581         I915_WRITE(CSIEW0, 0x007f0000);
6582         I915_WRITE(CSIEW1, 0x1e220004);
6583         I915_WRITE(CSIEW2, 0x04000004);
6584
6585         for (i = 0; i < 5; i++)
6586                 I915_WRITE(PEW(i), 0);
6587         for (i = 0; i < 3; i++)
6588                 I915_WRITE(DEW(i), 0);
6589
6590         /* Program P-state weights to account for frequency power adjustment */
6591         for (i = 0; i < 16; i++) {
6592                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6593                 unsigned long freq = intel_pxfreq(pxvidfreq);
6594                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6595                         PXVFREQ_PX_SHIFT;
6596                 unsigned long val;
6597
6598                 val = vid * vid;
6599                 val *= (freq / 1000);
6600                 val *= 255;
6601                 val /= (127*127*900);
6602                 if (val > 0xff)
6603                         DRM_ERROR("bad pxval: %ld\n", val);
6604                 pxw[i] = val;
6605         }
6606         /* Render standby states get 0 weight */
6607         pxw[14] = 0;
6608         pxw[15] = 0;
6609
6610         for (i = 0; i < 4; i++) {
6611                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6612                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6613                 I915_WRITE(PXW(i), val);
6614         }
6615
6616         /* Adjust magic regs to magic values (more experimental results) */
6617         I915_WRITE(OGW0, 0);
6618         I915_WRITE(OGW1, 0);
6619         I915_WRITE(EG0, 0x00007f00);
6620         I915_WRITE(EG1, 0x0000000e);
6621         I915_WRITE(EG2, 0x000e0000);
6622         I915_WRITE(EG3, 0x68000300);
6623         I915_WRITE(EG4, 0x42000000);
6624         I915_WRITE(EG5, 0x00140031);
6625         I915_WRITE(EG6, 0);
6626         I915_WRITE(EG7, 0);
6627
6628         for (i = 0; i < 8; i++)
6629                 I915_WRITE(PXWL(i), 0);
6630
6631         /* Enable PMON + select events */
6632         I915_WRITE(ECR, 0x80000019);
6633
6634         lcfuse = I915_READ(LCFUSE02);
6635
6636         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6637 }
6638
6639 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6640 {
6641         /*
6642          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6643          * requirement.
6644          */
6645         if (!i915.enable_rc6) {
6646                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6647                 intel_runtime_pm_get(dev_priv);
6648         }
6649
6650         mutex_lock(&dev_priv->drm.struct_mutex);
6651         mutex_lock(&dev_priv->rps.hw_lock);
6652
6653         /* Initialize RPS limits (for userspace) */
6654         if (IS_CHERRYVIEW(dev_priv))
6655                 cherryview_init_gt_powersave(dev_priv);
6656         else if (IS_VALLEYVIEW(dev_priv))
6657                 valleyview_init_gt_powersave(dev_priv);
6658         else if (INTEL_GEN(dev_priv) >= 6)
6659                 gen6_init_rps_frequencies(dev_priv);
6660
6661         /* Derive initial user preferences/limits from the hardware limits */
6662         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6663         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6664
6665         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6666         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6667
6668         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6669                 dev_priv->rps.min_freq_softlimit =
6670                         max_t(int,
6671                               dev_priv->rps.efficient_freq,
6672                               intel_freq_opcode(dev_priv, 450));
6673
6674         /* After setting max-softlimit, find the overclock max freq */
6675         if (IS_GEN6(dev_priv) ||
6676             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6677                 u32 params = 0;
6678
6679                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6680                 if (params & BIT(31)) { /* OC supported */
6681                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6682                                          (dev_priv->rps.max_freq & 0xff) * 50,
6683                                          (params & 0xff) * 50);
6684                         dev_priv->rps.max_freq = params & 0xff;
6685                 }
6686         }
6687
6688         /* Finally allow us to boost to max by default */
6689         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6690
6691         mutex_unlock(&dev_priv->rps.hw_lock);
6692         mutex_unlock(&dev_priv->drm.struct_mutex);
6693
6694         intel_autoenable_gt_powersave(dev_priv);
6695 }
6696
6697 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6698 {
6699         if (IS_VALLEYVIEW(dev_priv))
6700                 valleyview_cleanup_gt_powersave(dev_priv);
6701
6702         if (!i915.enable_rc6)
6703                 intel_runtime_pm_put(dev_priv);
6704 }
6705
6706 /**
6707  * intel_suspend_gt_powersave - suspend PM work and helper threads
6708  * @dev_priv: i915 device
6709  *
6710  * We don't want to disable RC6 or other features here, we just want
6711  * to make sure any work we've queued has finished and won't bother
6712  * us while we're suspended.
6713  */
6714 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6715 {
6716         if (INTEL_GEN(dev_priv) < 6)
6717                 return;
6718
6719         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6720                 intel_runtime_pm_put(dev_priv);
6721
6722         /* gen6_rps_idle() will be called later to disable interrupts */
6723 }
6724
6725 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6726 {
6727         dev_priv->rps.enabled = true; /* force disabling */
6728         intel_disable_gt_powersave(dev_priv);
6729
6730         gen6_reset_rps_interrupts(dev_priv);
6731 }
6732
6733 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6734 {
6735         if (!READ_ONCE(dev_priv->rps.enabled))
6736                 return;
6737
6738         mutex_lock(&dev_priv->rps.hw_lock);
6739
6740         if (INTEL_GEN(dev_priv) >= 9) {
6741                 gen9_disable_rc6(dev_priv);
6742                 gen9_disable_rps(dev_priv);
6743         } else if (IS_CHERRYVIEW(dev_priv)) {
6744                 cherryview_disable_rps(dev_priv);
6745         } else if (IS_VALLEYVIEW(dev_priv)) {
6746                 valleyview_disable_rps(dev_priv);
6747         } else if (INTEL_GEN(dev_priv) >= 6) {
6748                 gen6_disable_rps(dev_priv);
6749         }  else if (IS_IRONLAKE_M(dev_priv)) {
6750                 ironlake_disable_drps(dev_priv);
6751         }
6752
6753         dev_priv->rps.enabled = false;
6754         mutex_unlock(&dev_priv->rps.hw_lock);
6755 }
6756
6757 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6758 {
6759         /* We shouldn't be disabling as we submit, so this should be less
6760          * racy than it appears!
6761          */
6762         if (READ_ONCE(dev_priv->rps.enabled))
6763                 return;
6764
6765         /* Powersaving is controlled by the host when inside a VM */
6766         if (intel_vgpu_active(dev_priv))
6767                 return;
6768
6769         mutex_lock(&dev_priv->rps.hw_lock);
6770
6771         if (IS_CHERRYVIEW(dev_priv)) {
6772                 cherryview_enable_rps(dev_priv);
6773         } else if (IS_VALLEYVIEW(dev_priv)) {
6774                 valleyview_enable_rps(dev_priv);
6775         } else if (INTEL_GEN(dev_priv) >= 9) {
6776                 gen9_enable_rc6(dev_priv);
6777                 gen9_enable_rps(dev_priv);
6778                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6779                         gen6_update_ring_freq(dev_priv);
6780         } else if (IS_BROADWELL(dev_priv)) {
6781                 gen8_enable_rps(dev_priv);
6782                 gen6_update_ring_freq(dev_priv);
6783         } else if (INTEL_GEN(dev_priv) >= 6) {
6784                 gen6_enable_rps(dev_priv);
6785                 gen6_update_ring_freq(dev_priv);
6786         } else if (IS_IRONLAKE_M(dev_priv)) {
6787                 ironlake_enable_drps(dev_priv);
6788                 intel_init_emon(dev_priv);
6789         }
6790
6791         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6792         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6793
6794         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6795         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6796
6797         dev_priv->rps.enabled = true;
6798         mutex_unlock(&dev_priv->rps.hw_lock);
6799 }
6800
6801 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6802 {
6803         struct drm_i915_private *dev_priv =
6804                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6805         struct intel_engine_cs *rcs;
6806         struct drm_i915_gem_request *req;
6807
6808         if (READ_ONCE(dev_priv->rps.enabled))
6809                 goto out;
6810
6811         rcs = dev_priv->engine[RCS];
6812         if (rcs->last_context)
6813                 goto out;
6814
6815         if (!rcs->init_context)
6816                 goto out;
6817
6818         mutex_lock(&dev_priv->drm.struct_mutex);
6819
6820         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6821         if (IS_ERR(req))
6822                 goto unlock;
6823
6824         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6825                 rcs->init_context(req);
6826
6827         /* Mark the device busy, calling intel_enable_gt_powersave() */
6828         i915_add_request_no_flush(req);
6829
6830 unlock:
6831         mutex_unlock(&dev_priv->drm.struct_mutex);
6832 out:
6833         intel_runtime_pm_put(dev_priv);
6834 }
6835
6836 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6837 {
6838         if (READ_ONCE(dev_priv->rps.enabled))
6839                 return;
6840
6841         if (IS_IRONLAKE_M(dev_priv)) {
6842                 ironlake_enable_drps(dev_priv);
6843                 intel_init_emon(dev_priv);
6844         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6845                 /*
6846                  * PCU communication is slow and this doesn't need to be
6847                  * done at any specific time, so do this out of our fast path
6848                  * to make resume and init faster.
6849                  *
6850                  * We depend on the HW RC6 power context save/restore
6851                  * mechanism when entering D3 through runtime PM suspend. So
6852                  * disable RPM until RPS/RC6 is properly setup. We can only
6853                  * get here via the driver load/system resume/runtime resume
6854                  * paths, so the _noresume version is enough (and in case of
6855                  * runtime resume it's necessary).
6856                  */
6857                 if (queue_delayed_work(dev_priv->wq,
6858                                        &dev_priv->rps.autoenable_work,
6859                                        round_jiffies_up_relative(HZ)))
6860                         intel_runtime_pm_get_noresume(dev_priv);
6861         }
6862 }
6863
6864 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6865 {
6866         /*
6867          * On Ibex Peak and Cougar Point, we need to disable clock
6868          * gating for the panel power sequencer or it will fail to
6869          * start up when no ports are active.
6870          */
6871         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6872 }
6873
6874 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6875 {
6876         enum pipe pipe;
6877
6878         for_each_pipe(dev_priv, pipe) {
6879                 I915_WRITE(DSPCNTR(pipe),
6880                            I915_READ(DSPCNTR(pipe)) |
6881                            DISPPLANE_TRICKLE_FEED_DISABLE);
6882
6883                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6884                 POSTING_READ(DSPSURF(pipe));
6885         }
6886 }
6887
6888 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6889 {
6890         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6891         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6892         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6893
6894         /*
6895          * Don't touch WM1S_LP_EN here.
6896          * Doing so could cause underruns.
6897          */
6898 }
6899
6900 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6901 {
6902         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6903
6904         /*
6905          * Required for FBC
6906          * WaFbcDisableDpfcClockGating:ilk
6907          */
6908         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6909                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6910                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6911
6912         I915_WRITE(PCH_3DCGDIS0,
6913                    MARIUNIT_CLOCK_GATE_DISABLE |
6914                    SVSMUNIT_CLOCK_GATE_DISABLE);
6915         I915_WRITE(PCH_3DCGDIS1,
6916                    VFMUNIT_CLOCK_GATE_DISABLE);
6917
6918         /*
6919          * According to the spec the following bits should be set in
6920          * order to enable memory self-refresh
6921          * The bit 22/21 of 0x42004
6922          * The bit 5 of 0x42020
6923          * The bit 15 of 0x45000
6924          */
6925         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6926                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6927                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6928         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6929         I915_WRITE(DISP_ARB_CTL,
6930                    (I915_READ(DISP_ARB_CTL) |
6931                     DISP_FBC_WM_DIS));
6932
6933         ilk_init_lp_watermarks(dev_priv);
6934
6935         /*
6936          * Based on the document from hardware guys the following bits
6937          * should be set unconditionally in order to enable FBC.
6938          * The bit 22 of 0x42000
6939          * The bit 22 of 0x42004
6940          * The bit 7,8,9 of 0x42020.
6941          */
6942         if (IS_IRONLAKE_M(dev_priv)) {
6943                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6944                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6945                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6946                            ILK_FBCQ_DIS);
6947                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6948                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6949                            ILK_DPARB_GATE);
6950         }
6951
6952         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6953
6954         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6955                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6956                    ILK_ELPIN_409_SELECT);
6957         I915_WRITE(_3D_CHICKEN2,
6958                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6959                    _3D_CHICKEN2_WM_READ_PIPELINED);
6960
6961         /* WaDisableRenderCachePipelinedFlush:ilk */
6962         I915_WRITE(CACHE_MODE_0,
6963                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6964
6965         /* WaDisable_RenderCache_OperationalFlush:ilk */
6966         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6967
6968         g4x_disable_trickle_feed(dev_priv);
6969
6970         ibx_init_clock_gating(dev_priv);
6971 }
6972
6973 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6974 {
6975         int pipe;
6976         uint32_t val;
6977
6978         /*
6979          * On Ibex Peak and Cougar Point, we need to disable clock
6980          * gating for the panel power sequencer or it will fail to
6981          * start up when no ports are active.
6982          */
6983         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6984                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6985                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6986         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6987                    DPLS_EDP_PPS_FIX_DIS);
6988         /* The below fixes the weird display corruption, a few pixels shifted
6989          * downward, on (only) LVDS of some HP laptops with IVY.
6990          */
6991         for_each_pipe(dev_priv, pipe) {
6992                 val = I915_READ(TRANS_CHICKEN2(pipe));
6993                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6994                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6995                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6996                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6997                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6998                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6999                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
7000                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7001         }
7002         /* WADP0ClockGatingDisable */
7003         for_each_pipe(dev_priv, pipe) {
7004                 I915_WRITE(TRANS_CHICKEN1(pipe),
7005                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7006         }
7007 }
7008
7009 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
7010 {
7011         uint32_t tmp;
7012
7013         tmp = I915_READ(MCH_SSKPD);
7014         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7015                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7016                               tmp);
7017 }
7018
7019 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7020 {
7021         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7022
7023         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7024
7025         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7026                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7027                    ILK_ELPIN_409_SELECT);
7028
7029         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7030         I915_WRITE(_3D_CHICKEN,
7031                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7032
7033         /* WaDisable_RenderCache_OperationalFlush:snb */
7034         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7035
7036         /*
7037          * BSpec recoomends 8x4 when MSAA is used,
7038          * however in practice 16x4 seems fastest.
7039          *
7040          * Note that PS/WM thread counts depend on the WIZ hashing
7041          * disable bit, which we don't touch here, but it's good
7042          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7043          */
7044         I915_WRITE(GEN6_GT_MODE,
7045                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7046
7047         ilk_init_lp_watermarks(dev_priv);
7048
7049         I915_WRITE(CACHE_MODE_0,
7050                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7051
7052         I915_WRITE(GEN6_UCGCTL1,
7053                    I915_READ(GEN6_UCGCTL1) |
7054                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7055                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7056
7057         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7058          * gating disable must be set.  Failure to set it results in
7059          * flickering pixels due to Z write ordering failures after
7060          * some amount of runtime in the Mesa "fire" demo, and Unigine
7061          * Sanctuary and Tropics, and apparently anything else with
7062          * alpha test or pixel discard.
7063          *
7064          * According to the spec, bit 11 (RCCUNIT) must also be set,
7065          * but we didn't debug actual testcases to find it out.
7066          *
7067          * WaDisableRCCUnitClockGating:snb
7068          * WaDisableRCPBUnitClockGating:snb
7069          */
7070         I915_WRITE(GEN6_UCGCTL2,
7071                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7072                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7073
7074         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7075         I915_WRITE(_3D_CHICKEN3,
7076                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7077
7078         /*
7079          * Bspec says:
7080          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7081          * 3DSTATE_SF number of SF output attributes is more than 16."
7082          */
7083         I915_WRITE(_3D_CHICKEN3,
7084                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7085
7086         /*
7087          * According to the spec the following bits should be
7088          * set in order to enable memory self-refresh and fbc:
7089          * The bit21 and bit22 of 0x42000
7090          * The bit21 and bit22 of 0x42004
7091          * The bit5 and bit7 of 0x42020
7092          * The bit14 of 0x70180
7093          * The bit14 of 0x71180
7094          *
7095          * WaFbcAsynchFlipDisableFbcQueue:snb
7096          */
7097         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7098                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7099                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7100         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7101                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7102                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7103         I915_WRITE(ILK_DSPCLK_GATE_D,
7104                    I915_READ(ILK_DSPCLK_GATE_D) |
7105                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7106                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7107
7108         g4x_disable_trickle_feed(dev_priv);
7109
7110         cpt_init_clock_gating(dev_priv);
7111
7112         gen6_check_mch_setup(dev_priv);
7113 }
7114
7115 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7116 {
7117         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7118
7119         /*
7120          * WaVSThreadDispatchOverride:ivb,vlv
7121          *
7122          * This actually overrides the dispatch
7123          * mode for all thread types.
7124          */
7125         reg &= ~GEN7_FF_SCHED_MASK;
7126         reg |= GEN7_FF_TS_SCHED_HW;
7127         reg |= GEN7_FF_VS_SCHED_HW;
7128         reg |= GEN7_FF_DS_SCHED_HW;
7129
7130         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7131 }
7132
7133 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7134 {
7135         /*
7136          * TODO: this bit should only be enabled when really needed, then
7137          * disabled when not needed anymore in order to save power.
7138          */
7139         if (HAS_PCH_LPT_LP(dev_priv))
7140                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7141                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7142                            PCH_LP_PARTITION_LEVEL_DISABLE);
7143
7144         /* WADPOClockGatingDisable:hsw */
7145         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7146                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7147                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7148 }
7149
7150 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7151 {
7152         if (HAS_PCH_LPT_LP(dev_priv)) {
7153                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7154
7155                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7156                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7157         }
7158 }
7159
7160 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7161                                    int general_prio_credits,
7162                                    int high_prio_credits)
7163 {
7164         u32 misccpctl;
7165
7166         /* WaTempDisableDOPClkGating:bdw */
7167         misccpctl = I915_READ(GEN7_MISCCPCTL);
7168         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7169
7170         I915_WRITE(GEN8_L3SQCREG1,
7171                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7172                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7173
7174         /*
7175          * Wait at least 100 clocks before re-enabling clock gating.
7176          * See the definition of L3SQCREG1 in BSpec.
7177          */
7178         POSTING_READ(GEN8_L3SQCREG1);
7179         udelay(1);
7180         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7181 }
7182
7183 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7184 {
7185         gen9_init_clock_gating(dev_priv);
7186
7187         /* WaDisableSDEUnitClockGating:kbl */
7188         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7189                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7190                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7191
7192         /* WaDisableGamClockGating:kbl */
7193         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7194                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7195                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7196
7197         /* WaFbcNukeOnHostModify:kbl */
7198         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7199                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7200 }
7201
7202 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7203 {
7204         gen9_init_clock_gating(dev_priv);
7205
7206         /* WAC6entrylatency:skl */
7207         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7208                    FBC_LLC_FULLY_OPEN);
7209
7210         /* WaFbcNukeOnHostModify:skl */
7211         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7212                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7213 }
7214
7215 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7216 {
7217         enum pipe pipe;
7218
7219         ilk_init_lp_watermarks(dev_priv);
7220
7221         /* WaSwitchSolVfFArbitrationPriority:bdw */
7222         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7223
7224         /* WaPsrDPAMaskVBlankInSRD:bdw */
7225         I915_WRITE(CHICKEN_PAR1_1,
7226                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7227
7228         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7229         for_each_pipe(dev_priv, pipe) {
7230                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7231                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7232                            BDW_DPRS_MASK_VBLANK_SRD);
7233         }
7234
7235         /* WaVSRefCountFullforceMissDisable:bdw */
7236         /* WaDSRefCountFullforceMissDisable:bdw */
7237         I915_WRITE(GEN7_FF_THREAD_MODE,
7238                    I915_READ(GEN7_FF_THREAD_MODE) &
7239                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7240
7241         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7242                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7243
7244         /* WaDisableSDEUnitClockGating:bdw */
7245         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7246                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7247
7248         /* WaProgramL3SqcReg1Default:bdw */
7249         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7250
7251         /*
7252          * WaGttCachingOffByDefault:bdw
7253          * GTT cache may not work with big pages, so if those
7254          * are ever enabled GTT cache may need to be disabled.
7255          */
7256         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7257
7258         /* WaKVMNotificationOnConfigChange:bdw */
7259         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7260                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7261
7262         lpt_init_clock_gating(dev_priv);
7263 }
7264
7265 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7266 {
7267         ilk_init_lp_watermarks(dev_priv);
7268
7269         /* L3 caching of data atomics doesn't work -- disable it. */
7270         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7271         I915_WRITE(HSW_ROW_CHICKEN3,
7272                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7273
7274         /* This is required by WaCatErrorRejectionIssue:hsw */
7275         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7276                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7277                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7278
7279         /* WaVSRefCountFullforceMissDisable:hsw */
7280         I915_WRITE(GEN7_FF_THREAD_MODE,
7281                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7282
7283         /* WaDisable_RenderCache_OperationalFlush:hsw */
7284         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7285
7286         /* enable HiZ Raw Stall Optimization */
7287         I915_WRITE(CACHE_MODE_0_GEN7,
7288                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7289
7290         /* WaDisable4x2SubspanOptimization:hsw */
7291         I915_WRITE(CACHE_MODE_1,
7292                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7293
7294         /*
7295          * BSpec recommends 8x4 when MSAA is used,
7296          * however in practice 16x4 seems fastest.
7297          *
7298          * Note that PS/WM thread counts depend on the WIZ hashing
7299          * disable bit, which we don't touch here, but it's good
7300          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7301          */
7302         I915_WRITE(GEN7_GT_MODE,
7303                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7304
7305         /* WaSampleCChickenBitEnable:hsw */
7306         I915_WRITE(HALF_SLICE_CHICKEN3,
7307                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7308
7309         /* WaSwitchSolVfFArbitrationPriority:hsw */
7310         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7311
7312         /* WaRsPkgCStateDisplayPMReq:hsw */
7313         I915_WRITE(CHICKEN_PAR1_1,
7314                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7315
7316         lpt_init_clock_gating(dev_priv);
7317 }
7318
7319 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7320 {
7321         uint32_t snpcr;
7322
7323         ilk_init_lp_watermarks(dev_priv);
7324
7325         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7326
7327         /* WaDisableEarlyCull:ivb */
7328         I915_WRITE(_3D_CHICKEN3,
7329                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7330
7331         /* WaDisableBackToBackFlipFix:ivb */
7332         I915_WRITE(IVB_CHICKEN3,
7333                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7334                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7335
7336         /* WaDisablePSDDualDispatchEnable:ivb */
7337         if (IS_IVB_GT1(dev_priv))
7338                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7339                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7340
7341         /* WaDisable_RenderCache_OperationalFlush:ivb */
7342         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7343
7344         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7345         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7346                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7347
7348         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7349         I915_WRITE(GEN7_L3CNTLREG1,
7350                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7351         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7352                    GEN7_WA_L3_CHICKEN_MODE);
7353         if (IS_IVB_GT1(dev_priv))
7354                 I915_WRITE(GEN7_ROW_CHICKEN2,
7355                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7356         else {
7357                 /* must write both registers */
7358                 I915_WRITE(GEN7_ROW_CHICKEN2,
7359                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7360                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7361                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7362         }
7363
7364         /* WaForceL3Serialization:ivb */
7365         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7366                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7367
7368         /*
7369          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7370          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7371          */
7372         I915_WRITE(GEN6_UCGCTL2,
7373                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7374
7375         /* This is required by WaCatErrorRejectionIssue:ivb */
7376         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7377                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7378                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7379
7380         g4x_disable_trickle_feed(dev_priv);
7381
7382         gen7_setup_fixed_func_scheduler(dev_priv);
7383
7384         if (0) { /* causes HiZ corruption on ivb:gt1 */
7385                 /* enable HiZ Raw Stall Optimization */
7386                 I915_WRITE(CACHE_MODE_0_GEN7,
7387                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7388         }
7389
7390         /* WaDisable4x2SubspanOptimization:ivb */
7391         I915_WRITE(CACHE_MODE_1,
7392                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7393
7394         /*
7395          * BSpec recommends 8x4 when MSAA is used,
7396          * however in practice 16x4 seems fastest.
7397          *
7398          * Note that PS/WM thread counts depend on the WIZ hashing
7399          * disable bit, which we don't touch here, but it's good
7400          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7401          */
7402         I915_WRITE(GEN7_GT_MODE,
7403                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7404
7405         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7406         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7407         snpcr |= GEN6_MBC_SNPCR_MED;
7408         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7409
7410         if (!HAS_PCH_NOP(dev_priv))
7411                 cpt_init_clock_gating(dev_priv);
7412
7413         gen6_check_mch_setup(dev_priv);
7414 }
7415
7416 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7417 {
7418         /* WaDisableEarlyCull:vlv */
7419         I915_WRITE(_3D_CHICKEN3,
7420                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7421
7422         /* WaDisableBackToBackFlipFix:vlv */
7423         I915_WRITE(IVB_CHICKEN3,
7424                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7425                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7426
7427         /* WaPsdDispatchEnable:vlv */
7428         /* WaDisablePSDDualDispatchEnable:vlv */
7429         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7430                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7431                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7432
7433         /* WaDisable_RenderCache_OperationalFlush:vlv */
7434         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7435
7436         /* WaForceL3Serialization:vlv */
7437         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7438                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7439
7440         /* WaDisableDopClockGating:vlv */
7441         I915_WRITE(GEN7_ROW_CHICKEN2,
7442                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7443
7444         /* This is required by WaCatErrorRejectionIssue:vlv */
7445         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7446                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7447                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7448
7449         gen7_setup_fixed_func_scheduler(dev_priv);
7450
7451         /*
7452          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7453          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7454          */
7455         I915_WRITE(GEN6_UCGCTL2,
7456                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7457
7458         /* WaDisableL3Bank2xClockGate:vlv
7459          * Disabling L3 clock gating- MMIO 940c[25] = 1
7460          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7461         I915_WRITE(GEN7_UCGCTL4,
7462                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7463
7464         /*
7465          * BSpec says this must be set, even though
7466          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7467          */
7468         I915_WRITE(CACHE_MODE_1,
7469                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7470
7471         /*
7472          * BSpec recommends 8x4 when MSAA is used,
7473          * however in practice 16x4 seems fastest.
7474          *
7475          * Note that PS/WM thread counts depend on the WIZ hashing
7476          * disable bit, which we don't touch here, but it's good
7477          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7478          */
7479         I915_WRITE(GEN7_GT_MODE,
7480                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7481
7482         /*
7483          * WaIncreaseL3CreditsForVLVB0:vlv
7484          * This is the hardware default actually.
7485          */
7486         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7487
7488         /*
7489          * WaDisableVLVClockGating_VBIIssue:vlv
7490          * Disable clock gating on th GCFG unit to prevent a delay
7491          * in the reporting of vblank events.
7492          */
7493         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7494 }
7495
7496 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7497 {
7498         /* WaVSRefCountFullforceMissDisable:chv */
7499         /* WaDSRefCountFullforceMissDisable:chv */
7500         I915_WRITE(GEN7_FF_THREAD_MODE,
7501                    I915_READ(GEN7_FF_THREAD_MODE) &
7502                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7503
7504         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7505         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7506                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7507
7508         /* WaDisableCSUnitClockGating:chv */
7509         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7510                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7511
7512         /* WaDisableSDEUnitClockGating:chv */
7513         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7514                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7515
7516         /*
7517          * WaProgramL3SqcReg1Default:chv
7518          * See gfxspecs/Related Documents/Performance Guide/
7519          * LSQC Setting Recommendations.
7520          */
7521         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7522
7523         /*
7524          * GTT cache may not work with big pages, so if those
7525          * are ever enabled GTT cache may need to be disabled.
7526          */
7527         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7528 }
7529
7530 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7531 {
7532         uint32_t dspclk_gate;
7533
7534         I915_WRITE(RENCLK_GATE_D1, 0);
7535         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7536                    GS_UNIT_CLOCK_GATE_DISABLE |
7537                    CL_UNIT_CLOCK_GATE_DISABLE);
7538         I915_WRITE(RAMCLK_GATE_D, 0);
7539         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7540                 OVRUNIT_CLOCK_GATE_DISABLE |
7541                 OVCUNIT_CLOCK_GATE_DISABLE;
7542         if (IS_GM45(dev_priv))
7543                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7544         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7545
7546         /* WaDisableRenderCachePipelinedFlush */
7547         I915_WRITE(CACHE_MODE_0,
7548                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7549
7550         /* WaDisable_RenderCache_OperationalFlush:g4x */
7551         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7552
7553         g4x_disable_trickle_feed(dev_priv);
7554 }
7555
7556 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7557 {
7558         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7559         I915_WRITE(RENCLK_GATE_D2, 0);
7560         I915_WRITE(DSPCLK_GATE_D, 0);
7561         I915_WRITE(RAMCLK_GATE_D, 0);
7562         I915_WRITE16(DEUC, 0);
7563         I915_WRITE(MI_ARB_STATE,
7564                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7565
7566         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7567         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7568 }
7569
7570 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7571 {
7572         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7573                    I965_RCC_CLOCK_GATE_DISABLE |
7574                    I965_RCPB_CLOCK_GATE_DISABLE |
7575                    I965_ISC_CLOCK_GATE_DISABLE |
7576                    I965_FBC_CLOCK_GATE_DISABLE);
7577         I915_WRITE(RENCLK_GATE_D2, 0);
7578         I915_WRITE(MI_ARB_STATE,
7579                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7580
7581         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7582         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7583 }
7584
7585 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7586 {
7587         u32 dstate = I915_READ(D_STATE);
7588
7589         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7590                 DSTATE_DOT_CLOCK_GATING;
7591         I915_WRITE(D_STATE, dstate);
7592
7593         if (IS_PINEVIEW(dev_priv))
7594                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7595
7596         /* IIR "flip pending" means done if this bit is set */
7597         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7598
7599         /* interrupts should cause a wake up from C3 */
7600         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7601
7602         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7603         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7604
7605         I915_WRITE(MI_ARB_STATE,
7606                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7607 }
7608
7609 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7610 {
7611         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7612
7613         /* interrupts should cause a wake up from C3 */
7614         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7615                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7616
7617         I915_WRITE(MEM_MODE,
7618                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7619 }
7620
7621 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7622 {
7623         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7624
7625         I915_WRITE(MEM_MODE,
7626                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7627                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7628 }
7629
7630 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7631 {
7632         dev_priv->display.init_clock_gating(dev_priv);
7633 }
7634
7635 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7636 {
7637         if (HAS_PCH_LPT(dev_priv))
7638                 lpt_suspend_hw(dev_priv);
7639 }
7640
7641 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7642 {
7643         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7644 }
7645
7646 /**
7647  * intel_init_clock_gating_hooks - setup the clock gating hooks
7648  * @dev_priv: device private
7649  *
7650  * Setup the hooks that configure which clocks of a given platform can be
7651  * gated and also apply various GT and display specific workarounds for these
7652  * platforms. Note that some GT specific workarounds are applied separately
7653  * when GPU contexts or batchbuffers start their execution.
7654  */
7655 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7656 {
7657         if (IS_SKYLAKE(dev_priv))
7658                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7659         else if (IS_KABYLAKE(dev_priv))
7660                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7661         else if (IS_BROXTON(dev_priv))
7662                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7663         else if (IS_BROADWELL(dev_priv))
7664                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7665         else if (IS_CHERRYVIEW(dev_priv))
7666                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7667         else if (IS_HASWELL(dev_priv))
7668                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7669         else if (IS_IVYBRIDGE(dev_priv))
7670                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7671         else if (IS_VALLEYVIEW(dev_priv))
7672                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7673         else if (IS_GEN6(dev_priv))
7674                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7675         else if (IS_GEN5(dev_priv))
7676                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7677         else if (IS_G4X(dev_priv))
7678                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7679         else if (IS_CRESTLINE(dev_priv))
7680                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7681         else if (IS_BROADWATER(dev_priv))
7682                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7683         else if (IS_GEN3(dev_priv))
7684                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7685         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7686                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7687         else if (IS_GEN2(dev_priv))
7688                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7689         else {
7690                 MISSING_CASE(INTEL_DEVID(dev_priv));
7691                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7692         }
7693 }
7694
7695 /* Set up chip specific power management-related functions */
7696 void intel_init_pm(struct drm_i915_private *dev_priv)
7697 {
7698         intel_fbc_init(dev_priv);
7699
7700         /* For cxsr */
7701         if (IS_PINEVIEW(dev_priv))
7702                 i915_pineview_get_mem_freq(dev_priv);
7703         else if (IS_GEN5(dev_priv))
7704                 i915_ironlake_get_mem_freq(dev_priv);
7705
7706         /* For FIFO watermark updates */
7707         if (INTEL_GEN(dev_priv) >= 9) {
7708                 skl_setup_wm_latency(dev_priv);
7709                 dev_priv->display.update_wm = skl_update_wm;
7710                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
7711                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7712         } else if (HAS_PCH_SPLIT(dev_priv)) {
7713                 ilk_setup_wm_latency(dev_priv);
7714
7715                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7716                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7717                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7718                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7719                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7720                         dev_priv->display.compute_intermediate_wm =
7721                                 ilk_compute_intermediate_wm;
7722                         dev_priv->display.initial_watermarks =
7723                                 ilk_initial_watermarks;
7724                         dev_priv->display.optimize_watermarks =
7725                                 ilk_optimize_watermarks;
7726                 } else {
7727                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7728                                       "Disable CxSR\n");
7729                 }
7730         } else if (IS_CHERRYVIEW(dev_priv)) {
7731                 vlv_setup_wm_latency(dev_priv);
7732                 dev_priv->display.update_wm = vlv_update_wm;
7733         } else if (IS_VALLEYVIEW(dev_priv)) {
7734                 vlv_setup_wm_latency(dev_priv);
7735                 dev_priv->display.update_wm = vlv_update_wm;
7736         } else if (IS_PINEVIEW(dev_priv)) {
7737                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7738                                             dev_priv->is_ddr3,
7739                                             dev_priv->fsb_freq,
7740                                             dev_priv->mem_freq)) {
7741                         DRM_INFO("failed to find known CxSR latency "
7742                                  "(found ddr%s fsb freq %d, mem freq %d), "
7743                                  "disabling CxSR\n",
7744                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7745                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7746                         /* Disable CxSR and never update its watermark again */
7747                         intel_set_memory_cxsr(dev_priv, false);
7748                         dev_priv->display.update_wm = NULL;
7749                 } else
7750                         dev_priv->display.update_wm = pineview_update_wm;
7751         } else if (IS_G4X(dev_priv)) {
7752                 dev_priv->display.update_wm = g4x_update_wm;
7753         } else if (IS_GEN4(dev_priv)) {
7754                 dev_priv->display.update_wm = i965_update_wm;
7755         } else if (IS_GEN3(dev_priv)) {
7756                 dev_priv->display.update_wm = i9xx_update_wm;
7757                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7758         } else if (IS_GEN2(dev_priv)) {
7759                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7760                         dev_priv->display.update_wm = i845_update_wm;
7761                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7762                 } else {
7763                         dev_priv->display.update_wm = i9xx_update_wm;
7764                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7765                 }
7766         } else {
7767                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7768         }
7769 }
7770
7771 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7772 {
7773         uint32_t flags =
7774                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7775
7776         switch (flags) {
7777         case GEN6_PCODE_SUCCESS:
7778                 return 0;
7779         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7780         case GEN6_PCODE_ILLEGAL_CMD:
7781                 return -ENXIO;
7782         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7783         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7784                 return -EOVERFLOW;
7785         case GEN6_PCODE_TIMEOUT:
7786                 return -ETIMEDOUT;
7787         default:
7788                 MISSING_CASE(flags)
7789                 return 0;
7790         }
7791 }
7792
7793 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7794 {
7795         uint32_t flags =
7796                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7797
7798         switch (flags) {
7799         case GEN6_PCODE_SUCCESS:
7800                 return 0;
7801         case GEN6_PCODE_ILLEGAL_CMD:
7802                 return -ENXIO;
7803         case GEN7_PCODE_TIMEOUT:
7804                 return -ETIMEDOUT;
7805         case GEN7_PCODE_ILLEGAL_DATA:
7806                 return -EINVAL;
7807         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7808                 return -EOVERFLOW;
7809         default:
7810                 MISSING_CASE(flags);
7811                 return 0;
7812         }
7813 }
7814
7815 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7816 {
7817         int status;
7818
7819         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7820
7821         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7822          * use te fw I915_READ variants to reduce the amount of work
7823          * required when reading/writing.
7824          */
7825
7826         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7827                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7828                 return -EAGAIN;
7829         }
7830
7831         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7832         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7833         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7834
7835         if (intel_wait_for_register_fw(dev_priv,
7836                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7837                                        500)) {
7838                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7839                 return -ETIMEDOUT;
7840         }
7841
7842         *val = I915_READ_FW(GEN6_PCODE_DATA);
7843         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7844
7845         if (INTEL_GEN(dev_priv) > 6)
7846                 status = gen7_check_mailbox_status(dev_priv);
7847         else
7848                 status = gen6_check_mailbox_status(dev_priv);
7849
7850         if (status) {
7851                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7852                                  status);
7853                 return status;
7854         }
7855
7856         return 0;
7857 }
7858
7859 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7860                             u32 mbox, u32 val)
7861 {
7862         int status;
7863
7864         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7865
7866         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7867          * use te fw I915_READ variants to reduce the amount of work
7868          * required when reading/writing.
7869          */
7870
7871         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7872                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7873                 return -EAGAIN;
7874         }
7875
7876         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7877         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7878
7879         if (intel_wait_for_register_fw(dev_priv,
7880                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7881                                        500)) {
7882                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7883                 return -ETIMEDOUT;
7884         }
7885
7886         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7887
7888         if (INTEL_GEN(dev_priv) > 6)
7889                 status = gen7_check_mailbox_status(dev_priv);
7890         else
7891                 status = gen6_check_mailbox_status(dev_priv);
7892
7893         if (status) {
7894                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7895                                  status);
7896                 return status;
7897         }
7898
7899         return 0;
7900 }
7901
7902 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7903 {
7904         /*
7905          * N = val - 0xb7
7906          * Slow = Fast = GPLL ref * N
7907          */
7908         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7909 }
7910
7911 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7912 {
7913         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7914 }
7915
7916 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7917 {
7918         /*
7919          * N = val / 2
7920          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7921          */
7922         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7923 }
7924
7925 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7926 {
7927         /* CHV needs even values */
7928         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7929 }
7930
7931 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7932 {
7933         if (IS_GEN9(dev_priv))
7934                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7935                                          GEN9_FREQ_SCALER);
7936         else if (IS_CHERRYVIEW(dev_priv))
7937                 return chv_gpu_freq(dev_priv, val);
7938         else if (IS_VALLEYVIEW(dev_priv))
7939                 return byt_gpu_freq(dev_priv, val);
7940         else
7941                 return val * GT_FREQUENCY_MULTIPLIER;
7942 }
7943
7944 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7945 {
7946         if (IS_GEN9(dev_priv))
7947                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7948                                          GT_FREQUENCY_MULTIPLIER);
7949         else if (IS_CHERRYVIEW(dev_priv))
7950                 return chv_freq_opcode(dev_priv, val);
7951         else if (IS_VALLEYVIEW(dev_priv))
7952                 return byt_freq_opcode(dev_priv, val);
7953         else
7954                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7955 }
7956
7957 struct request_boost {
7958         struct work_struct work;
7959         struct drm_i915_gem_request *req;
7960 };
7961
7962 static void __intel_rps_boost_work(struct work_struct *work)
7963 {
7964         struct request_boost *boost = container_of(work, struct request_boost, work);
7965         struct drm_i915_gem_request *req = boost->req;
7966
7967         if (!i915_gem_request_completed(req))
7968                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7969
7970         i915_gem_request_put(req);
7971         kfree(boost);
7972 }
7973
7974 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7975 {
7976         struct request_boost *boost;
7977
7978         if (req == NULL || INTEL_GEN(req->i915) < 6)
7979                 return;
7980
7981         if (i915_gem_request_completed(req))
7982                 return;
7983
7984         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7985         if (boost == NULL)
7986                 return;
7987
7988         boost->req = i915_gem_request_get(req);
7989
7990         INIT_WORK(&boost->work, __intel_rps_boost_work);
7991         queue_work(req->i915->wq, &boost->work);
7992 }
7993
7994 void intel_pm_setup(struct drm_device *dev)
7995 {
7996         struct drm_i915_private *dev_priv = to_i915(dev);
7997
7998         mutex_init(&dev_priv->rps.hw_lock);
7999         spin_lock_init(&dev_priv->rps.client_lock);
8000
8001         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8002                           __intel_autoenable_gt_powersave);
8003         INIT_LIST_HEAD(&dev_priv->rps.clients);
8004
8005         dev_priv->pm.suspended = false;
8006         atomic_set(&dev_priv->pm.wakeref_count, 0);
8007 }