drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <drm/i915_powerwell.h>
  34
  35 /**
  36  * RC6 is a special power stage which allows the GPU to enter an very
  37  * low-voltage mode when idle, using down to 0V while at this stage.  This
  38  * stage is entered automatically when the GPU is idle when RC6 support is
  39  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  40  *
  41  * There are different RC6 modes available in Intel GPU, which differentiate
  42  * among each other with the latency required to enter and leave RC6 and
  43  * voltage consumed by the GPU in different states.
  44  *
  45  * The combination of the following flags define which states GPU is allowed
  46  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  47  * RC6pp is deepest RC6. Their support by hardware varies according to the
  48  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  49  * which brings the most power savings; deeper states save more power, but
  50  * require higher latency to switch to and wake up.
  51  */
  52 #define INTEL_RC6_ENABLE                        (1<<0)
  53 #define INTEL_RC6p_ENABLE                       (1<<1)
  54 #define INTEL_RC6pp_ENABLE                      (1<<2)
  55
  56 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  57  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  58  * during in-memory transfers and, therefore, reduce the power packet.
  59  *
  60  * The benefits of FBC are mostly visible with solid backgrounds and
  61  * variation-less patterns.
  62  *
  63  * FBC-related functionality can be enabled by the means of the
  64  * i915.i915_enable_fbc parameter
  65  */
  66
  67 static void i8xx_disable_fbc(struct drm_device *dev)
  68 {
  69         struct drm_i915_private *dev_priv = dev->dev_private;
  70         u32 fbc_ctl;
  71
  72         /* Disable compression */
  73         fbc_ctl = I915_READ(FBC_CONTROL);
  74         if ((fbc_ctl & FBC_CTL_EN) == 0)
  75                 return;
  76
  77         fbc_ctl &= ~FBC_CTL_EN;
  78         I915_WRITE(FBC_CONTROL, fbc_ctl);
  79
  80         /* Wait for compressing bit to clear */
  81         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  82                 DRM_DEBUG_KMS("FBC idle timed out\n");
  83                 return;
  84         }
  85
  86         DRM_DEBUG_KMS("disabled FBC\n");
  87 }
  88
  89 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  90 {
  91         struct drm_device *dev = crtc->dev;
  92         struct drm_i915_private *dev_priv = dev->dev_private;
  93         struct drm_framebuffer *fb = crtc->fb;
  94         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  95         struct drm_i915_gem_object *obj = intel_fb->obj;
  96         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  97         int cfb_pitch;
  98         int plane, i;
  99         u32 fbc_ctl, fbc_ctl2;
 100
 101         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 102         if (fb->pitches[0] < cfb_pitch)
 103                 cfb_pitch = fb->pitches[0];
 104
 105         /* FBC_CTL wants 64B units */
 106         cfb_pitch = (cfb_pitch / 64) - 1;
 107         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 108
 109         /* Clear old tags */
 110         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 111                 I915_WRITE(FBC_TAG + (i * 4), 0);
 112
 113         /* Set it up... */
 114         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 115         fbc_ctl2 |= plane;
 116         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 117         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 118
 119         /* enable it... */
 120         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 121         if (IS_I945GM(dev))
 122                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 123         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 124         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 125         fbc_ctl |= obj->fence_reg;
 126         I915_WRITE(FBC_CONTROL, fbc_ctl);
 127
 128         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 129                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 130 }
 131
 132 static bool i8xx_fbc_enabled(struct drm_device *dev)
 133 {
 134         struct drm_i915_private *dev_priv = dev->dev_private;
 135
 136         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 137 }
 138
 139 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 140 {
 141         struct drm_device *dev = crtc->dev;
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         struct drm_framebuffer *fb = crtc->fb;
 144         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 145         struct drm_i915_gem_object *obj = intel_fb->obj;
 146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 147         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 148         unsigned long stall_watermark = 200;
 149         u32 dpfc_ctl;
 150
 151         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 152         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 153         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 154
 155         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 156                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 157                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 158         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 159
 160         /* enable it... */
 161         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 162
 163         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 164 }
 165
 166 static void g4x_disable_fbc(struct drm_device *dev)
 167 {
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169         u32 dpfc_ctl;
 170
 171         /* Disable compression */
 172         dpfc_ctl = I915_READ(DPFC_CONTROL);
 173         if (dpfc_ctl & DPFC_CTL_EN) {
 174                 dpfc_ctl &= ~DPFC_CTL_EN;
 175                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 176
 177                 DRM_DEBUG_KMS("disabled FBC\n");
 178         }
 179 }
 180
 181 static bool g4x_fbc_enabled(struct drm_device *dev)
 182 {
 183         struct drm_i915_private *dev_priv = dev->dev_private;
 184
 185         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 186 }
 187
 188 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         u32 blt_ecoskpd;
 192
 193         /* Make sure blitter notifies FBC of writes */
 194         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 195
 196         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 197         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 198                 GEN6_BLITTER_LOCK_SHIFT;
 199         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 200         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 201         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 202         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 203                          GEN6_BLITTER_LOCK_SHIFT);
 204         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 205         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 206
 207         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 208 }
 209
 210 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 211 {
 212         struct drm_device *dev = crtc->dev;
 213         struct drm_i915_private *dev_priv = dev->dev_private;
 214         struct drm_framebuffer *fb = crtc->fb;
 215         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 216         struct drm_i915_gem_object *obj = intel_fb->obj;
 217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 218         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 219         unsigned long stall_watermark = 200;
 220         u32 dpfc_ctl;
 221
 222         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 223         dpfc_ctl &= DPFC_RESERVED;
 224         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 225         /* Set persistent mode for front-buffer rendering, ala X. */
 226         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 227         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 228         if (IS_GEN5(dev))
 229                 dpfc_ctl |= obj->fence_reg;
 230         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 231
 232         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 233                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 234                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 235         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 236         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 237         /* enable it... */
 238         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 239
 240         if (IS_GEN6(dev)) {
 241                 I915_WRITE(SNB_DPFC_CTL_SA,
 242                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 243                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 244                 sandybridge_blit_fbc_update(dev);
 245         }
 246
 247         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 248 }
 249
 250 static void ironlake_disable_fbc(struct drm_device *dev)
 251 {
 252         struct drm_i915_private *dev_priv = dev->dev_private;
 253         u32 dpfc_ctl;
 254
 255         /* Disable compression */
 256         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 257         if (dpfc_ctl & DPFC_CTL_EN) {
 258                 dpfc_ctl &= ~DPFC_CTL_EN;
 259                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 260
 261                 DRM_DEBUG_KMS("disabled FBC\n");
 262         }
 263 }
 264
 265 static bool ironlake_fbc_enabled(struct drm_device *dev)
 266 {
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268
 269         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 270 }
 271
 272 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 273 {
 274         struct drm_device *dev = crtc->dev;
 275         struct drm_i915_private *dev_priv = dev->dev_private;
 276         struct drm_framebuffer *fb = crtc->fb;
 277         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 278         struct drm_i915_gem_object *obj = intel_fb->obj;
 279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 280
 281         I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
 282
 283         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 284                    IVB_DPFC_CTL_FENCE_EN |
 285                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 286
 287         if (IS_IVYBRIDGE(dev)) {
 288                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 289                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 290         } else {
 291                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 292                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 293                            HSW_BYPASS_FBC_QUEUE);
 294         }
 295
 296         I915_WRITE(SNB_DPFC_CTL_SA,
 297                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 298         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 299
 300         sandybridge_blit_fbc_update(dev);
 301
 302         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 303 }
 304
 305 bool intel_fbc_enabled(struct drm_device *dev)
 306 {
 307         struct drm_i915_private *dev_priv = dev->dev_private;
 308
 309         if (!dev_priv->display.fbc_enabled)
 310                 return false;
 311
 312         return dev_priv->display.fbc_enabled(dev);
 313 }
 314
 315 static void intel_fbc_work_fn(struct work_struct *__work)
 316 {
 317         struct intel_fbc_work *work =
 318                 container_of(to_delayed_work(__work),
 319                              struct intel_fbc_work, work);
 320         struct drm_device *dev = work->crtc->dev;
 321         struct drm_i915_private *dev_priv = dev->dev_private;
 322
 323         mutex_lock(&dev->struct_mutex);
 324         if (work == dev_priv->fbc.fbc_work) {
 325                 /* Double check that we haven't switched fb without cancelling
 326                  * the prior work.
 327                  */
 328                 if (work->crtc->fb == work->fb) {
 329                         dev_priv->display.enable_fbc(work->crtc,
 330                                                      work->interval);
 331
 332                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 333                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 334                         dev_priv->fbc.y = work->crtc->y;
 335                 }
 336
 337                 dev_priv->fbc.fbc_work = NULL;
 338         }
 339         mutex_unlock(&dev->struct_mutex);
 340
 341         kfree(work);
 342 }
 343
 344 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 345 {
 346         if (dev_priv->fbc.fbc_work == NULL)
 347                 return;
 348
 349         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 350
 351         /* Synchronisation is provided by struct_mutex and checking of
 352          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 353          * entirely asynchronously.
 354          */
 355         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 356                 /* tasklet was killed before being run, clean up */
 357                 kfree(dev_priv->fbc.fbc_work);
 358
 359         /* Mark the work as no longer wanted so that if it does
 360          * wake-up (because the work was already running and waiting
 361          * for our mutex), it will discover that is no longer
 362          * necessary to run.
 363          */
 364         dev_priv->fbc.fbc_work = NULL;
 365 }
 366
 367 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 368 {
 369         struct intel_fbc_work *work;
 370         struct drm_device *dev = crtc->dev;
 371         struct drm_i915_private *dev_priv = dev->dev_private;
 372
 373         if (!dev_priv->display.enable_fbc)
 374                 return;
 375
 376         intel_cancel_fbc_work(dev_priv);
 377
 378         work = kzalloc(sizeof(*work), GFP_KERNEL);
 379         if (work == NULL) {
 380                 DRM_ERROR("Failed to allocate FBC work structure\n");
 381                 dev_priv->display.enable_fbc(crtc, interval);
 382                 return;
 383         }
 384
 385         work->crtc = crtc;
 386         work->fb = crtc->fb;
 387         work->interval = interval;
 388         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 389
 390         dev_priv->fbc.fbc_work = work;
 391
 392         /* Delay the actual enabling to let pageflipping cease and the
 393          * display to settle before starting the compression. Note that
 394          * this delay also serves a second purpose: it allows for a
 395          * vblank to pass after disabling the FBC before we attempt
 396          * to modify the control registers.
 397          *
 398          * A more complicated solution would involve tracking vblanks
 399          * following the termination of the page-flipping sequence
 400          * and indeed performing the enable as a co-routine and not
 401          * waiting synchronously upon the vblank.
 402          *
 403          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 404          */
 405         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 406 }
 407
 408 void intel_disable_fbc(struct drm_device *dev)
 409 {
 410         struct drm_i915_private *dev_priv = dev->dev_private;
 411
 412         intel_cancel_fbc_work(dev_priv);
 413
 414         if (!dev_priv->display.disable_fbc)
 415                 return;
 416
 417         dev_priv->display.disable_fbc(dev);
 418         dev_priv->fbc.plane = -1;
 419 }
 420
 421 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 422                               enum no_fbc_reason reason)
 423 {
 424         if (dev_priv->fbc.no_fbc_reason == reason)
 425                 return false;
 426
 427         dev_priv->fbc.no_fbc_reason = reason;
 428         return true;
 429 }
 430
 431 /**
 432  * intel_update_fbc - enable/disable FBC as needed
 433  * @dev: the drm_device
 434  *
 435  * Set up the framebuffer compression hardware at mode set time.  We
 436  * enable it if possible:
 437  *   - plane A only (on pre-965)
 438  *   - no pixel mulitply/line duplication
 439  *   - no alpha buffer discard
 440  *   - no dual wide
 441  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 442  *
 443  * We can't assume that any compression will take place (worst case),
 444  * so the compressed buffer has to be the same size as the uncompressed
 445  * one.  It also must reside (along with the line length buffer) in
 446  * stolen memory.
 447  *
 448  * We need to enable/disable FBC on a global basis.
 449  */
 450 void intel_update_fbc(struct drm_device *dev)
 451 {
 452         struct drm_i915_private *dev_priv = dev->dev_private;
 453         struct drm_crtc *crtc = NULL, *tmp_crtc;
 454         struct intel_crtc *intel_crtc;
 455         struct drm_framebuffer *fb;
 456         struct intel_framebuffer *intel_fb;
 457         struct drm_i915_gem_object *obj;
 458         const struct drm_display_mode *adjusted_mode;
 459         unsigned int max_width, max_height;
 460
 461         if (!I915_HAS_FBC(dev)) {
 462                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 463                 return;
 464         }
 465
 466         if (!i915_powersave) {
 467                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 468                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 469                 return;
 470         }
 471
 472         /*
 473          * If FBC is already on, we just have to verify that we can
 474          * keep it that way...
 475          * Need to disable if:
 476          *   - more than one pipe is active
 477          *   - changing FBC params (stride, fence, mode)
 478          *   - new fb is too large to fit in compressed buffer
 479          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 480          */
 481         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 482                 if (intel_crtc_active(tmp_crtc) &&
 483                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 484                         if (crtc) {
 485                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 486                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 487                                 goto out_disable;
 488                         }
 489                         crtc = tmp_crtc;
 490                 }
 491         }
 492
 493         if (!crtc || crtc->fb == NULL) {
 494                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 495                         DRM_DEBUG_KMS("no output, disabling\n");
 496                 goto out_disable;
 497         }
 498
 499         intel_crtc = to_intel_crtc(crtc);
 500         fb = crtc->fb;
 501         intel_fb = to_intel_framebuffer(fb);
 502         obj = intel_fb->obj;
 503         adjusted_mode = &intel_crtc->config.adjusted_mode;
 504
 505         if (i915_enable_fbc < 0 &&
 506             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 507                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 508                         DRM_DEBUG_KMS("disabled per chip default\n");
 509                 goto out_disable;
 510         }
 511         if (!i915_enable_fbc) {
 512                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 513                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 514                 goto out_disable;
 515         }
 516         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 517             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 518                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 519                         DRM_DEBUG_KMS("mode incompatible with compression, "
 520                                       "disabling\n");
 521                 goto out_disable;
 522         }
 523
 524         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 525                 max_width = 4096;
 526                 max_height = 2048;
 527         } else {
 528                 max_width = 2048;
 529                 max_height = 1536;
 530         }
 531         if (intel_crtc->config.pipe_src_w > max_width ||
 532             intel_crtc->config.pipe_src_h > max_height) {
 533                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 534                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 535                 goto out_disable;
 536         }
 537         if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
 538             intel_crtc->plane != 0) {
 539                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 540                         DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 541                 goto out_disable;
 542         }
 543
 544         /* The use of a CPU fence is mandatory in order to detect writes
 545          * by the CPU to the scanout and trigger updates to the FBC.
 546          */
 547         if (obj->tiling_mode != I915_TILING_X ||
 548             obj->fence_reg == I915_FENCE_REG_NONE) {
 549                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 550                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 551                 goto out_disable;
 552         }
 553
 554         /* If the kernel debugger is active, always disable compression */
 555         if (in_dbg_master())
 556                 goto out_disable;
 557
 558         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 559                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 560                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 561                 goto out_disable;
 562         }
 563
 564         /* If the scanout has not changed, don't modify the FBC settings.
 565          * Note that we make the fundamental assumption that the fb->obj
 566          * cannot be unpinned (and have its GTT offset and fence revoked)
 567          * without first being decoupled from the scanout and FBC disabled.
 568          */
 569         if (dev_priv->fbc.plane == intel_crtc->plane &&
 570             dev_priv->fbc.fb_id == fb->base.id &&
 571             dev_priv->fbc.y == crtc->y)
 572                 return;
 573
 574         if (intel_fbc_enabled(dev)) {
 575                 /* We update FBC along two paths, after changing fb/crtc
 576                  * configuration (modeswitching) and after page-flipping
 577                  * finishes. For the latter, we know that not only did
 578                  * we disable the FBC at the start of the page-flip
 579                  * sequence, but also more than one vblank has passed.
 580                  *
 581                  * For the former case of modeswitching, it is possible
 582                  * to switch between two FBC valid configurations
 583                  * instantaneously so we do need to disable the FBC
 584                  * before we can modify its control registers. We also
 585                  * have to wait for the next vblank for that to take
 586                  * effect. However, since we delay enabling FBC we can
 587                  * assume that a vblank has passed since disabling and
 588                  * that we can safely alter the registers in the deferred
 589                  * callback.
 590                  *
 591                  * In the scenario that we go from a valid to invalid
 592                  * and then back to valid FBC configuration we have
 593                  * no strict enforcement that a vblank occurred since
 594                  * disabling the FBC. However, along all current pipe
 595                  * disabling paths we do need to wait for a vblank at
 596                  * some point. And we wait before enabling FBC anyway.
 597                  */
 598                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 599                 intel_disable_fbc(dev);
 600         }
 601
 602         intel_enable_fbc(crtc, 500);
 603         dev_priv->fbc.no_fbc_reason = FBC_OK;
 604         return;
 605
 606 out_disable:
 607         /* Multiple disables should be harmless */
 608         if (intel_fbc_enabled(dev)) {
 609                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 610                 intel_disable_fbc(dev);
 611         }
 612         i915_gem_stolen_cleanup_compression(dev);
 613 }
 614
 615 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 616 {
 617         drm_i915_private_t *dev_priv = dev->dev_private;
 618         u32 tmp;
 619
 620         tmp = I915_READ(CLKCFG);
 621
 622         switch (tmp & CLKCFG_FSB_MASK) {
 623         case CLKCFG_FSB_533:
 624                 dev_priv->fsb_freq = 533; /* 133*4 */
 625                 break;
 626         case CLKCFG_FSB_800:
 627                 dev_priv->fsb_freq = 800; /* 200*4 */
 628                 break;
 629         case CLKCFG_FSB_667:
 630                 dev_priv->fsb_freq =  667; /* 167*4 */
 631                 break;
 632         case CLKCFG_FSB_400:
 633                 dev_priv->fsb_freq = 400; /* 100*4 */
 634                 break;
 635         }
 636
 637         switch (tmp & CLKCFG_MEM_MASK) {
 638         case CLKCFG_MEM_533:
 639                 dev_priv->mem_freq = 533;
 640                 break;
 641         case CLKCFG_MEM_667:
 642                 dev_priv->mem_freq = 667;
 643                 break;
 644         case CLKCFG_MEM_800:
 645                 dev_priv->mem_freq = 800;
 646                 break;
 647         }
 648
 649         /* detect pineview DDR3 setting */
 650         tmp = I915_READ(CSHRDDR3CTL);
 651         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 652 }
 653
 654 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 655 {
 656         drm_i915_private_t *dev_priv = dev->dev_private;
 657         u16 ddrpll, csipll;
 658
 659         ddrpll = I915_READ16(DDRMPLL1);
 660         csipll = I915_READ16(CSIPLL0);
 661
 662         switch (ddrpll & 0xff) {
 663         case 0xc:
 664                 dev_priv->mem_freq = 800;
 665                 break;
 666         case 0x10:
 667                 dev_priv->mem_freq = 1066;
 668                 break;
 669         case 0x14:
 670                 dev_priv->mem_freq = 1333;
 671                 break;
 672         case 0x18:
 673                 dev_priv->mem_freq = 1600;
 674                 break;
 675         default:
 676                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 677                                  ddrpll & 0xff);
 678                 dev_priv->mem_freq = 0;
 679                 break;
 680         }
 681
 682         dev_priv->ips.r_t = dev_priv->mem_freq;
 683
 684         switch (csipll & 0x3ff) {
 685         case 0x00c:
 686                 dev_priv->fsb_freq = 3200;
 687                 break;
 688         case 0x00e:
 689                 dev_priv->fsb_freq = 3733;
 690                 break;
 691         case 0x010:
 692                 dev_priv->fsb_freq = 4266;
 693                 break;
 694         case 0x012:
 695                 dev_priv->fsb_freq = 4800;
 696                 break;
 697         case 0x014:
 698                 dev_priv->fsb_freq = 5333;
 699                 break;
 700         case 0x016:
 701                 dev_priv->fsb_freq = 5866;
 702                 break;
 703         case 0x018:
 704                 dev_priv->fsb_freq = 6400;
 705                 break;
 706         default:
 707                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 708                                  csipll & 0x3ff);
 709                 dev_priv->fsb_freq = 0;
 710                 break;
 711         }
 712
 713         if (dev_priv->fsb_freq == 3200) {
 714                 dev_priv->ips.c_m = 0;
 715         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 716                 dev_priv->ips.c_m = 1;
 717         } else {
 718                 dev_priv->ips.c_m = 2;
 719         }
 720 }
 721
 722 static const struct cxsr_latency cxsr_latency_table[] = {
 723         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 724         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 725         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 726         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 727         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 728
 729         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 730         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 731         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 732         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 733         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 734
 735         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 736         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 737         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 738         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 739         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 740
 741         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 742         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 743         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 744         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 745         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 746
 747         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 748         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 749         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 750         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 751         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 752
 753         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 754         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 755         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 756         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 757         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 758 };
 759
 760 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 761                                                          int is_ddr3,
 762                                                          int fsb,
 763                                                          int mem)
 764 {
 765         const struct cxsr_latency *latency;
 766         int i;
 767
 768         if (fsb == 0 || mem == 0)
 769                 return NULL;
 770
 771         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 772                 latency = &cxsr_latency_table[i];
 773                 if (is_desktop == latency->is_desktop &&
 774                     is_ddr3 == latency->is_ddr3 &&
 775                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 776                         return latency;
 777         }
 778
 779         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 780
 781         return NULL;
 782 }
 783
 784 static void pineview_disable_cxsr(struct drm_device *dev)
 785 {
 786         struct drm_i915_private *dev_priv = dev->dev_private;
 787
 788         /* deactivate cxsr */
 789         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 790 }
 791
 792 /*
 793  * Latency for FIFO fetches is dependent on several factors:
 794  *   - memory configuration (speed, channels)
 795  *   - chipset
 796  *   - current MCH state
 797  * It can be fairly high in some situations, so here we assume a fairly
 798  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 799  * set this value too high, the FIFO will fetch frequently to stay full)
 800  * and power consumption (set it too low to save power and we might see
 801  * FIFO underruns and display "flicker").
 802  *
 803  * A value of 5us seems to be a good balance; safe for very low end
 804  * platforms but not overly aggressive on lower latency configs.
 805  */
 806 static const int latency_ns = 5000;
 807
 808 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 809 {
 810         struct drm_i915_private *dev_priv = dev->dev_private;
 811         uint32_t dsparb = I915_READ(DSPARB);
 812         int size;
 813
 814         size = dsparb & 0x7f;
 815         if (plane)
 816                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 817
 818         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 819                       plane ? "B" : "A", size);
 820
 821         return size;
 822 }
 823
 824 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 825 {
 826         struct drm_i915_private *dev_priv = dev->dev_private;
 827         uint32_t dsparb = I915_READ(DSPARB);
 828         int size;
 829
 830         size = dsparb & 0x1ff;
 831         if (plane)
 832                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 833         size >>= 1; /* Convert to cachelines */
 834
 835         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 836                       plane ? "B" : "A", size);
 837
 838         return size;
 839 }
 840
 841 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 842 {
 843         struct drm_i915_private *dev_priv = dev->dev_private;
 844         uint32_t dsparb = I915_READ(DSPARB);
 845         int size;
 846
 847         size = dsparb & 0x7f;
 848         size >>= 2; /* Convert to cachelines */
 849
 850         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 851                       plane ? "B" : "A",
 852                       size);
 853
 854         return size;
 855 }
 856
 857 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 858 {
 859         struct drm_i915_private *dev_priv = dev->dev_private;
 860         uint32_t dsparb = I915_READ(DSPARB);
 861         int size;
 862
 863         size = dsparb & 0x7f;
 864         size >>= 1; /* Convert to cachelines */
 865
 866         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 867                       plane ? "B" : "A", size);
 868
 869         return size;
 870 }
 871
 872 /* Pineview has different values for various configs */
 873 static const struct intel_watermark_params pineview_display_wm = {
 874         PINEVIEW_DISPLAY_FIFO,
 875         PINEVIEW_MAX_WM,
 876         PINEVIEW_DFT_WM,
 877         PINEVIEW_GUARD_WM,
 878         PINEVIEW_FIFO_LINE_SIZE
 879 };
 880 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 881         PINEVIEW_DISPLAY_FIFO,
 882         PINEVIEW_MAX_WM,
 883         PINEVIEW_DFT_HPLLOFF_WM,
 884         PINEVIEW_GUARD_WM,
 885         PINEVIEW_FIFO_LINE_SIZE
 886 };
 887 static const struct intel_watermark_params pineview_cursor_wm = {
 888         PINEVIEW_CURSOR_FIFO,
 889         PINEVIEW_CURSOR_MAX_WM,
 890         PINEVIEW_CURSOR_DFT_WM,
 891         PINEVIEW_CURSOR_GUARD_WM,
 892         PINEVIEW_FIFO_LINE_SIZE,
 893 };
 894 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 895         PINEVIEW_CURSOR_FIFO,
 896         PINEVIEW_CURSOR_MAX_WM,
 897         PINEVIEW_CURSOR_DFT_WM,
 898         PINEVIEW_CURSOR_GUARD_WM,
 899         PINEVIEW_FIFO_LINE_SIZE
 900 };
 901 static const struct intel_watermark_params g4x_wm_info = {
 902         G4X_FIFO_SIZE,
 903         G4X_MAX_WM,
 904         G4X_MAX_WM,
 905         2,
 906         G4X_FIFO_LINE_SIZE,
 907 };
 908 static const struct intel_watermark_params g4x_cursor_wm_info = {
 909         I965_CURSOR_FIFO,
 910         I965_CURSOR_MAX_WM,
 911         I965_CURSOR_DFT_WM,
 912         2,
 913         G4X_FIFO_LINE_SIZE,
 914 };
 915 static const struct intel_watermark_params valleyview_wm_info = {
 916         VALLEYVIEW_FIFO_SIZE,
 917         VALLEYVIEW_MAX_WM,
 918         VALLEYVIEW_MAX_WM,
 919         2,
 920         G4X_FIFO_LINE_SIZE,
 921 };
 922 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 923         I965_CURSOR_FIFO,
 924         VALLEYVIEW_CURSOR_MAX_WM,
 925         I965_CURSOR_DFT_WM,
 926         2,
 927         G4X_FIFO_LINE_SIZE,
 928 };
 929 static const struct intel_watermark_params i965_cursor_wm_info = {
 930         I965_CURSOR_FIFO,
 931         I965_CURSOR_MAX_WM,
 932         I965_CURSOR_DFT_WM,
 933         2,
 934         I915_FIFO_LINE_SIZE,
 935 };
 936 static const struct intel_watermark_params i945_wm_info = {
 937         I945_FIFO_SIZE,
 938         I915_MAX_WM,
 939         1,
 940         2,
 941         I915_FIFO_LINE_SIZE
 942 };
 943 static const struct intel_watermark_params i915_wm_info = {
 944         I915_FIFO_SIZE,
 945         I915_MAX_WM,
 946         1,
 947         2,
 948         I915_FIFO_LINE_SIZE
 949 };
 950 static const struct intel_watermark_params i855_wm_info = {
 951         I855GM_FIFO_SIZE,
 952         I915_MAX_WM,
 953         1,
 954         2,
 955         I830_FIFO_LINE_SIZE
 956 };
 957 static const struct intel_watermark_params i830_wm_info = {
 958         I830_FIFO_SIZE,
 959         I915_MAX_WM,
 960         1,
 961         2,
 962         I830_FIFO_LINE_SIZE
 963 };
 964
 965 static const struct intel_watermark_params ironlake_display_wm_info = {
 966         ILK_DISPLAY_FIFO,
 967         ILK_DISPLAY_MAXWM,
 968         ILK_DISPLAY_DFTWM,
 969         2,
 970         ILK_FIFO_LINE_SIZE
 971 };
 972 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 973         ILK_CURSOR_FIFO,
 974         ILK_CURSOR_MAXWM,
 975         ILK_CURSOR_DFTWM,
 976         2,
 977         ILK_FIFO_LINE_SIZE
 978 };
 979 static const struct intel_watermark_params ironlake_display_srwm_info = {
 980         ILK_DISPLAY_SR_FIFO,
 981         ILK_DISPLAY_MAX_SRWM,
 982         ILK_DISPLAY_DFT_SRWM,
 983         2,
 984         ILK_FIFO_LINE_SIZE
 985 };
 986 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 987         ILK_CURSOR_SR_FIFO,
 988         ILK_CURSOR_MAX_SRWM,
 989         ILK_CURSOR_DFT_SRWM,
 990         2,
 991         ILK_FIFO_LINE_SIZE
 992 };
 993
 994 static const struct intel_watermark_params sandybridge_display_wm_info = {
 995         SNB_DISPLAY_FIFO,
 996         SNB_DISPLAY_MAXWM,
 997         SNB_DISPLAY_DFTWM,
 998         2,
 999         SNB_FIFO_LINE_SIZE
1000 };
1001 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1002         SNB_CURSOR_FIFO,
1003         SNB_CURSOR_MAXWM,
1004         SNB_CURSOR_DFTWM,
1005         2,
1006         SNB_FIFO_LINE_SIZE
1007 };
1008 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1009         SNB_DISPLAY_SR_FIFO,
1010         SNB_DISPLAY_MAX_SRWM,
1011         SNB_DISPLAY_DFT_SRWM,
1012         2,
1013         SNB_FIFO_LINE_SIZE
1014 };
1015 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1016         SNB_CURSOR_SR_FIFO,
1017         SNB_CURSOR_MAX_SRWM,
1018         SNB_CURSOR_DFT_SRWM,
1019         2,
1020         SNB_FIFO_LINE_SIZE
1021 };
1022
1023
1024 /**
1025  * intel_calculate_wm - calculate watermark level
1026  * @clock_in_khz: pixel clock
1027  * @wm: chip FIFO params
1028  * @pixel_size: display pixel size
1029  * @latency_ns: memory latency for the platform
1030  *
1031  * Calculate the watermark level (the level at which the display plane will
1032  * start fetching from memory again).  Each chip has a different display
1033  * FIFO size and allocation, so the caller needs to figure that out and pass
1034  * in the correct intel_watermark_params structure.
1035  *
1036  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1037  * on the pixel size.  When it reaches the watermark level, it'll start
1038  * fetching FIFO line sized based chunks from memory until the FIFO fills
1039  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1040  * will occur, and a display engine hang could result.
1041  */
1042 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1043                                         const struct intel_watermark_params *wm,
1044                                         int fifo_size,
1045                                         int pixel_size,
1046                                         unsigned long latency_ns)
1047 {
1048         long entries_required, wm_size;
1049
1050         /*
1051          * Note: we need to make sure we don't overflow for various clock &
1052          * latency values.
1053          * clocks go from a few thousand to several hundred thousand.
1054          * latency is usually a few thousand
1055          */
1056         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1057                 1000;
1058         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1059
1060         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1061
1062         wm_size = fifo_size - (entries_required + wm->guard_size);
1063
1064         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1065
1066         /* Don't promote wm_size to unsigned... */
1067         if (wm_size > (long)wm->max_wm)
1068                 wm_size = wm->max_wm;
1069         if (wm_size <= 0)
1070                 wm_size = wm->default_wm;
1071         return wm_size;
1072 }
1073
1074 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1075 {
1076         struct drm_crtc *crtc, *enabled = NULL;
1077
1078         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1079                 if (intel_crtc_active(crtc)) {
1080                         if (enabled)
1081                                 return NULL;
1082                         enabled = crtc;
1083                 }
1084         }
1085
1086         return enabled;
1087 }
1088
1089 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1090 {
1091         struct drm_device *dev = unused_crtc->dev;
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         struct drm_crtc *crtc;
1094         const struct cxsr_latency *latency;
1095         u32 reg;
1096         unsigned long wm;
1097
1098         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1099                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1100         if (!latency) {
1101                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1102                 pineview_disable_cxsr(dev);
1103                 return;
1104         }
1105
1106         crtc = single_enabled_crtc(dev);
1107         if (crtc) {
1108                 const struct drm_display_mode *adjusted_mode;
1109                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1110                 int clock;
1111
1112                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1113                 clock = adjusted_mode->crtc_clock;
1114
1115                 /* Display SR */
1116                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1117                                         pineview_display_wm.fifo_size,
1118                                         pixel_size, latency->display_sr);
1119                 reg = I915_READ(DSPFW1);
1120                 reg &= ~DSPFW_SR_MASK;
1121                 reg |= wm << DSPFW_SR_SHIFT;
1122                 I915_WRITE(DSPFW1, reg);
1123                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1124
1125                 /* cursor SR */
1126                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1127                                         pineview_display_wm.fifo_size,
1128                                         pixel_size, latency->cursor_sr);
1129                 reg = I915_READ(DSPFW3);
1130                 reg &= ~DSPFW_CURSOR_SR_MASK;
1131                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1132                 I915_WRITE(DSPFW3, reg);
1133
1134                 /* Display HPLL off SR */
1135                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1136                                         pineview_display_hplloff_wm.fifo_size,
1137                                         pixel_size, latency->display_hpll_disable);
1138                 reg = I915_READ(DSPFW3);
1139                 reg &= ~DSPFW_HPLL_SR_MASK;
1140                 reg |= wm & DSPFW_HPLL_SR_MASK;
1141                 I915_WRITE(DSPFW3, reg);
1142
1143                 /* cursor HPLL off SR */
1144                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1145                                         pineview_display_hplloff_wm.fifo_size,
1146                                         pixel_size, latency->cursor_hpll_disable);
1147                 reg = I915_READ(DSPFW3);
1148                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1149                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1150                 I915_WRITE(DSPFW3, reg);
1151                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1152
1153                 /* activate cxsr */
1154                 I915_WRITE(DSPFW3,
1155                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1156                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1157         } else {
1158                 pineview_disable_cxsr(dev);
1159                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1160         }
1161 }
1162
1163 static bool g4x_compute_wm0(struct drm_device *dev,
1164                             int plane,
1165                             const struct intel_watermark_params *display,
1166                             int display_latency_ns,
1167                             const struct intel_watermark_params *cursor,
1168                             int cursor_latency_ns,
1169                             int *plane_wm,
1170                             int *cursor_wm)
1171 {
1172         struct drm_crtc *crtc;
1173         const struct drm_display_mode *adjusted_mode;
1174         int htotal, hdisplay, clock, pixel_size;
1175         int line_time_us, line_count;
1176         int entries, tlb_miss;
1177
1178         crtc = intel_get_crtc_for_plane(dev, plane);
1179         if (!intel_crtc_active(crtc)) {
1180                 *cursor_wm = cursor->guard_size;
1181                 *plane_wm = display->guard_size;
1182                 return false;
1183         }
1184
1185         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1186         clock = adjusted_mode->crtc_clock;
1187         htotal = adjusted_mode->htotal;
1188         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1189         pixel_size = crtc->fb->bits_per_pixel / 8;
1190
1191         /* Use the small buffer method to calculate plane watermark */
1192         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1193         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1194         if (tlb_miss > 0)
1195                 entries += tlb_miss;
1196         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1197         *plane_wm = entries + display->guard_size;
1198         if (*plane_wm > (int)display->max_wm)
1199                 *plane_wm = display->max_wm;
1200
1201         /* Use the large buffer method to calculate cursor watermark */
1202         line_time_us = ((htotal * 1000) / clock);
1203         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1204         entries = line_count * 64 * pixel_size;
1205         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1206         if (tlb_miss > 0)
1207                 entries += tlb_miss;
1208         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1209         *cursor_wm = entries + cursor->guard_size;
1210         if (*cursor_wm > (int)cursor->max_wm)
1211                 *cursor_wm = (int)cursor->max_wm;
1212
1213         return true;
1214 }
1215
1216 /*
1217  * Check the wm result.
1218  *
1219  * If any calculated watermark values is larger than the maximum value that
1220  * can be programmed into the associated watermark register, that watermark
1221  * must be disabled.
1222  */
1223 static bool g4x_check_srwm(struct drm_device *dev,
1224                            int display_wm, int cursor_wm,
1225                            const struct intel_watermark_params *display,
1226                            const struct intel_watermark_params *cursor)
1227 {
1228         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1229                       display_wm, cursor_wm);
1230
1231         if (display_wm > display->max_wm) {
1232                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1233                               display_wm, display->max_wm);
1234                 return false;
1235         }
1236
1237         if (cursor_wm > cursor->max_wm) {
1238                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1239                               cursor_wm, cursor->max_wm);
1240                 return false;
1241         }
1242
1243         if (!(display_wm || cursor_wm)) {
1244                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1245                 return false;
1246         }
1247
1248         return true;
1249 }
1250
1251 static bool g4x_compute_srwm(struct drm_device *dev,
1252                              int plane,
1253                              int latency_ns,
1254                              const struct intel_watermark_params *display,
1255                              const struct intel_watermark_params *cursor,
1256                              int *display_wm, int *cursor_wm)
1257 {
1258         struct drm_crtc *crtc;
1259         const struct drm_display_mode *adjusted_mode;
1260         int hdisplay, htotal, pixel_size, clock;
1261         unsigned long line_time_us;
1262         int line_count, line_size;
1263         int small, large;
1264         int entries;
1265
1266         if (!latency_ns) {
1267                 *display_wm = *cursor_wm = 0;
1268                 return false;
1269         }
1270
1271         crtc = intel_get_crtc_for_plane(dev, plane);
1272         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1273         clock = adjusted_mode->crtc_clock;
1274         htotal = adjusted_mode->htotal;
1275         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1276         pixel_size = crtc->fb->bits_per_pixel / 8;
1277
1278         line_time_us = (htotal * 1000) / clock;
1279         line_count = (latency_ns / line_time_us + 1000) / 1000;
1280         line_size = hdisplay * pixel_size;
1281
1282         /* Use the minimum of the small and large buffer method for primary */
1283         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1284         large = line_count * line_size;
1285
1286         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1287         *display_wm = entries + display->guard_size;
1288
1289         /* calculate the self-refresh watermark for display cursor */
1290         entries = line_count * pixel_size * 64;
1291         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1292         *cursor_wm = entries + cursor->guard_size;
1293
1294         return g4x_check_srwm(dev,
1295                               *display_wm, *cursor_wm,
1296                               display, cursor);
1297 }
1298
1299 static bool vlv_compute_drain_latency(struct drm_device *dev,
1300                                      int plane,
1301                                      int *plane_prec_mult,
1302                                      int *plane_dl,
1303                                      int *cursor_prec_mult,
1304                                      int *cursor_dl)
1305 {
1306         struct drm_crtc *crtc;
1307         int clock, pixel_size;
1308         int entries;
1309
1310         crtc = intel_get_crtc_for_plane(dev, plane);
1311         if (!intel_crtc_active(crtc))
1312                 return false;
1313
1314         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1315         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1316
1317         entries = (clock / 1000) * pixel_size;
1318         *plane_prec_mult = (entries > 256) ?
1319                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1320         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1321                                                      pixel_size);
1322
1323         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1324         *cursor_prec_mult = (entries > 256) ?
1325                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1326         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1327
1328         return true;
1329 }
1330
1331 /*
1332  * Update drain latency registers of memory arbiter
1333  *
1334  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1335  * to be programmed. Each plane has a drain latency multiplier and a drain
1336  * latency value.
1337  */
1338
1339 static void vlv_update_drain_latency(struct drm_device *dev)
1340 {
1341         struct drm_i915_private *dev_priv = dev->dev_private;
1342         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1343         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1344         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1345                                                         either 16 or 32 */
1346
1347         /* For plane A, Cursor A */
1348         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1349                                       &cursor_prec_mult, &cursora_dl)) {
1350                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1351                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1352                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1353                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1354
1355                 I915_WRITE(VLV_DDL1, cursora_prec |
1356                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1357                                 planea_prec | planea_dl);
1358         }
1359
1360         /* For plane B, Cursor B */
1361         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1362                                       &cursor_prec_mult, &cursorb_dl)) {
1363                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1364                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1365                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1366                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1367
1368                 I915_WRITE(VLV_DDL2, cursorb_prec |
1369                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1370                                 planeb_prec | planeb_dl);
1371         }
1372 }
1373
1374 #define single_plane_enabled(mask) is_power_of_2(mask)
1375
1376 static void valleyview_update_wm(struct drm_crtc *crtc)
1377 {
1378         struct drm_device *dev = crtc->dev;
1379         static const int sr_latency_ns = 12000;
1380         struct drm_i915_private *dev_priv = dev->dev_private;
1381         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1382         int plane_sr, cursor_sr;
1383         int ignore_plane_sr, ignore_cursor_sr;
1384         unsigned int enabled = 0;
1385
1386         vlv_update_drain_latency(dev);
1387
1388         if (g4x_compute_wm0(dev, PIPE_A,
1389                             &valleyview_wm_info, latency_ns,
1390                             &valleyview_cursor_wm_info, latency_ns,
1391                             &planea_wm, &cursora_wm))
1392                 enabled |= 1 << PIPE_A;
1393
1394         if (g4x_compute_wm0(dev, PIPE_B,
1395                             &valleyview_wm_info, latency_ns,
1396                             &valleyview_cursor_wm_info, latency_ns,
1397                             &planeb_wm, &cursorb_wm))
1398                 enabled |= 1 << PIPE_B;
1399
1400         if (single_plane_enabled(enabled) &&
1401             g4x_compute_srwm(dev, ffs(enabled) - 1,
1402                              sr_latency_ns,
1403                              &valleyview_wm_info,
1404                              &valleyview_cursor_wm_info,
1405                              &plane_sr, &ignore_cursor_sr) &&
1406             g4x_compute_srwm(dev, ffs(enabled) - 1,
1407                              2*sr_latency_ns,
1408                              &valleyview_wm_info,
1409                              &valleyview_cursor_wm_info,
1410                              &ignore_plane_sr, &cursor_sr)) {
1411                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1412         } else {
1413                 I915_WRITE(FW_BLC_SELF_VLV,
1414                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1415                 plane_sr = cursor_sr = 0;
1416         }
1417
1418         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1419                       planea_wm, cursora_wm,
1420                       planeb_wm, cursorb_wm,
1421                       plane_sr, cursor_sr);
1422
1423         I915_WRITE(DSPFW1,
1424                    (plane_sr << DSPFW_SR_SHIFT) |
1425                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1426                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1427                    planea_wm);
1428         I915_WRITE(DSPFW2,
1429                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1430                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1431         I915_WRITE(DSPFW3,
1432                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1433                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1434 }
1435
1436 static void g4x_update_wm(struct drm_crtc *crtc)
1437 {
1438         struct drm_device *dev = crtc->dev;
1439         static const int sr_latency_ns = 12000;
1440         struct drm_i915_private *dev_priv = dev->dev_private;
1441         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1442         int plane_sr, cursor_sr;
1443         unsigned int enabled = 0;
1444
1445         if (g4x_compute_wm0(dev, PIPE_A,
1446                             &g4x_wm_info, latency_ns,
1447                             &g4x_cursor_wm_info, latency_ns,
1448                             &planea_wm, &cursora_wm))
1449                 enabled |= 1 << PIPE_A;
1450
1451         if (g4x_compute_wm0(dev, PIPE_B,
1452                             &g4x_wm_info, latency_ns,
1453                             &g4x_cursor_wm_info, latency_ns,
1454                             &planeb_wm, &cursorb_wm))
1455                 enabled |= 1 << PIPE_B;
1456
1457         if (single_plane_enabled(enabled) &&
1458             g4x_compute_srwm(dev, ffs(enabled) - 1,
1459                              sr_latency_ns,
1460                              &g4x_wm_info,
1461                              &g4x_cursor_wm_info,
1462                              &plane_sr, &cursor_sr)) {
1463                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1464         } else {
1465                 I915_WRITE(FW_BLC_SELF,
1466                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1467                 plane_sr = cursor_sr = 0;
1468         }
1469
1470         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1471                       planea_wm, cursora_wm,
1472                       planeb_wm, cursorb_wm,
1473                       plane_sr, cursor_sr);
1474
1475         I915_WRITE(DSPFW1,
1476                    (plane_sr << DSPFW_SR_SHIFT) |
1477                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1478                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1479                    planea_wm);
1480         I915_WRITE(DSPFW2,
1481                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1482                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1483         /* HPLL off in SR has some issues on G4x... disable it */
1484         I915_WRITE(DSPFW3,
1485                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1486                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1487 }
1488
1489 static void i965_update_wm(struct drm_crtc *unused_crtc)
1490 {
1491         struct drm_device *dev = unused_crtc->dev;
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493         struct drm_crtc *crtc;
1494         int srwm = 1;
1495         int cursor_sr = 16;
1496
1497         /* Calc sr entries for one plane configs */
1498         crtc = single_enabled_crtc(dev);
1499         if (crtc) {
1500                 /* self-refresh has much higher latency */
1501                 static const int sr_latency_ns = 12000;
1502                 const struct drm_display_mode *adjusted_mode =
1503                         &to_intel_crtc(crtc)->config.adjusted_mode;
1504                 int clock = adjusted_mode->crtc_clock;
1505                 int htotal = adjusted_mode->htotal;
1506                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1507                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1508                 unsigned long line_time_us;
1509                 int entries;
1510
1511                 line_time_us = ((htotal * 1000) / clock);
1512
1513                 /* Use ns/us then divide to preserve precision */
1514                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1515                         pixel_size * hdisplay;
1516                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1517                 srwm = I965_FIFO_SIZE - entries;
1518                 if (srwm < 0)
1519                         srwm = 1;
1520                 srwm &= 0x1ff;
1521                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1522                               entries, srwm);
1523
1524                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1525                         pixel_size * 64;
1526                 entries = DIV_ROUND_UP(entries,
1527                                           i965_cursor_wm_info.cacheline_size);
1528                 cursor_sr = i965_cursor_wm_info.fifo_size -
1529                         (entries + i965_cursor_wm_info.guard_size);
1530
1531                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1532                         cursor_sr = i965_cursor_wm_info.max_wm;
1533
1534                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1535                               "cursor %d\n", srwm, cursor_sr);
1536
1537                 if (IS_CRESTLINE(dev))
1538                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1539         } else {
1540                 /* Turn off self refresh if both pipes are enabled */
1541                 if (IS_CRESTLINE(dev))
1542                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1543                                    & ~FW_BLC_SELF_EN);
1544         }
1545
1546         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1547                       srwm);
1548
1549         /* 965 has limitations... */
1550         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1551                    (8 << 16) | (8 << 8) | (8 << 0));
1552         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1553         /* update cursor SR watermark */
1554         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1555 }
1556
1557 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1558 {
1559         struct drm_device *dev = unused_crtc->dev;
1560         struct drm_i915_private *dev_priv = dev->dev_private;
1561         const struct intel_watermark_params *wm_info;
1562         uint32_t fwater_lo;
1563         uint32_t fwater_hi;
1564         int cwm, srwm = 1;
1565         int fifo_size;
1566         int planea_wm, planeb_wm;
1567         struct drm_crtc *crtc, *enabled = NULL;
1568
1569         if (IS_I945GM(dev))
1570                 wm_info = &i945_wm_info;
1571         else if (!IS_GEN2(dev))
1572                 wm_info = &i915_wm_info;
1573         else
1574                 wm_info = &i855_wm_info;
1575
1576         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1577         crtc = intel_get_crtc_for_plane(dev, 0);
1578         if (intel_crtc_active(crtc)) {
1579                 const struct drm_display_mode *adjusted_mode;
1580                 int cpp = crtc->fb->bits_per_pixel / 8;
1581                 if (IS_GEN2(dev))
1582                         cpp = 4;
1583
1584                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1585                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1586                                                wm_info, fifo_size, cpp,
1587                                                latency_ns);
1588                 enabled = crtc;
1589         } else
1590                 planea_wm = fifo_size - wm_info->guard_size;
1591
1592         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1593         crtc = intel_get_crtc_for_plane(dev, 1);
1594         if (intel_crtc_active(crtc)) {
1595                 const struct drm_display_mode *adjusted_mode;
1596                 int cpp = crtc->fb->bits_per_pixel / 8;
1597                 if (IS_GEN2(dev))
1598                         cpp = 4;
1599
1600                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1601                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1602                                                wm_info, fifo_size, cpp,
1603                                                latency_ns);
1604                 if (enabled == NULL)
1605                         enabled = crtc;
1606                 else
1607                         enabled = NULL;
1608         } else
1609                 planeb_wm = fifo_size - wm_info->guard_size;
1610
1611         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1612
1613         /*
1614          * Overlay gets an aggressive default since video jitter is bad.
1615          */
1616         cwm = 2;
1617
1618         /* Play safe and disable self-refresh before adjusting watermarks. */
1619         if (IS_I945G(dev) || IS_I945GM(dev))
1620                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1621         else if (IS_I915GM(dev))
1622                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1623
1624         /* Calc sr entries for one plane configs */
1625         if (HAS_FW_BLC(dev) && enabled) {
1626                 /* self-refresh has much higher latency */
1627                 static const int sr_latency_ns = 6000;
1628                 const struct drm_display_mode *adjusted_mode =
1629                         &to_intel_crtc(enabled)->config.adjusted_mode;
1630                 int clock = adjusted_mode->crtc_clock;
1631                 int htotal = adjusted_mode->htotal;
1632                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1633                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1634                 unsigned long line_time_us;
1635                 int entries;
1636
1637                 line_time_us = (htotal * 1000) / clock;
1638
1639                 /* Use ns/us then divide to preserve precision */
1640                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1641                         pixel_size * hdisplay;
1642                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1643                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1644                 srwm = wm_info->fifo_size - entries;
1645                 if (srwm < 0)
1646                         srwm = 1;
1647
1648                 if (IS_I945G(dev) || IS_I945GM(dev))
1649                         I915_WRITE(FW_BLC_SELF,
1650                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1651                 else if (IS_I915GM(dev))
1652                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1653         }
1654
1655         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1656                       planea_wm, planeb_wm, cwm, srwm);
1657
1658         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1659         fwater_hi = (cwm & 0x1f);
1660
1661         /* Set request length to 8 cachelines per fetch */
1662         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1663         fwater_hi = fwater_hi | (1 << 8);
1664
1665         I915_WRITE(FW_BLC, fwater_lo);
1666         I915_WRITE(FW_BLC2, fwater_hi);
1667
1668         if (HAS_FW_BLC(dev)) {
1669                 if (enabled) {
1670                         if (IS_I945G(dev) || IS_I945GM(dev))
1671                                 I915_WRITE(FW_BLC_SELF,
1672                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1673                         else if (IS_I915GM(dev))
1674                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1675                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1676                 } else
1677                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1678         }
1679 }
1680
1681 static void i830_update_wm(struct drm_crtc *unused_crtc)
1682 {
1683         struct drm_device *dev = unused_crtc->dev;
1684         struct drm_i915_private *dev_priv = dev->dev_private;
1685         struct drm_crtc *crtc;
1686         const struct drm_display_mode *adjusted_mode;
1687         uint32_t fwater_lo;
1688         int planea_wm;
1689
1690         crtc = single_enabled_crtc(dev);
1691         if (crtc == NULL)
1692                 return;
1693
1694         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1695         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1696                                        &i830_wm_info,
1697                                        dev_priv->display.get_fifo_size(dev, 0),
1698                                        4, latency_ns);
1699         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1700         fwater_lo |= (3<<8) | planea_wm;
1701
1702         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1703
1704         I915_WRITE(FW_BLC, fwater_lo);
1705 }
1706
1707 /*
1708  * Check the wm result.
1709  *
1710  * If any calculated watermark values is larger than the maximum value that
1711  * can be programmed into the associated watermark register, that watermark
1712  * must be disabled.
1713  */
1714 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1715                                 int fbc_wm, int display_wm, int cursor_wm,
1716                                 const struct intel_watermark_params *display,
1717                                 const struct intel_watermark_params *cursor)
1718 {
1719         struct drm_i915_private *dev_priv = dev->dev_private;
1720
1721         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1722                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1723
1724         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1725                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1726                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1727
1728                 /* fbc has it's own way to disable FBC WM */
1729                 I915_WRITE(DISP_ARB_CTL,
1730                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1731                 return false;
1732         } else if (INTEL_INFO(dev)->gen >= 6) {
1733                 /* enable FBC WM (except on ILK, where it must remain off) */
1734                 I915_WRITE(DISP_ARB_CTL,
1735                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1736         }
1737
1738         if (display_wm > display->max_wm) {
1739                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1740                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1741                 return false;
1742         }
1743
1744         if (cursor_wm > cursor->max_wm) {
1745                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1746                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1747                 return false;
1748         }
1749
1750         if (!(fbc_wm || display_wm || cursor_wm)) {
1751                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1752                 return false;
1753         }
1754
1755         return true;
1756 }
1757
1758 /*
1759  * Compute watermark values of WM[1-3],
1760  */
1761 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1762                                   int latency_ns,
1763                                   const struct intel_watermark_params *display,
1764                                   const struct intel_watermark_params *cursor,
1765                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1766 {
1767         struct drm_crtc *crtc;
1768         const struct drm_display_mode *adjusted_mode;
1769         unsigned long line_time_us;
1770         int hdisplay, htotal, pixel_size, clock;
1771         int line_count, line_size;
1772         int small, large;
1773         int entries;
1774
1775         if (!latency_ns) {
1776                 *fbc_wm = *display_wm = *cursor_wm = 0;
1777                 return false;
1778         }
1779
1780         crtc = intel_get_crtc_for_plane(dev, plane);
1781         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1782         clock = adjusted_mode->crtc_clock;
1783         htotal = adjusted_mode->htotal;
1784         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1785         pixel_size = crtc->fb->bits_per_pixel / 8;
1786
1787         line_time_us = (htotal * 1000) / clock;
1788         line_count = (latency_ns / line_time_us + 1000) / 1000;
1789         line_size = hdisplay * pixel_size;
1790
1791         /* Use the minimum of the small and large buffer method for primary */
1792         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1793         large = line_count * line_size;
1794
1795         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1796         *display_wm = entries + display->guard_size;
1797
1798         /*
1799          * Spec says:
1800          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1801          */
1802         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1803
1804         /* calculate the self-refresh watermark for display cursor */
1805         entries = line_count * pixel_size * 64;
1806         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1807         *cursor_wm = entries + cursor->guard_size;
1808
1809         return ironlake_check_srwm(dev, level,
1810                                    *fbc_wm, *display_wm, *cursor_wm,
1811                                    display, cursor);
1812 }
1813
1814 static void ironlake_update_wm(struct drm_crtc *crtc)
1815 {
1816         struct drm_device *dev = crtc->dev;
1817         struct drm_i915_private *dev_priv = dev->dev_private;
1818         int fbc_wm, plane_wm, cursor_wm;
1819         unsigned int enabled;
1820
1821         enabled = 0;
1822         if (g4x_compute_wm0(dev, PIPE_A,
1823                             &ironlake_display_wm_info,
1824                             dev_priv->wm.pri_latency[0] * 100,
1825                             &ironlake_cursor_wm_info,
1826                             dev_priv->wm.cur_latency[0] * 100,
1827                             &plane_wm, &cursor_wm)) {
1828                 I915_WRITE(WM0_PIPEA_ILK,
1829                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1830                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1831                               " plane %d, " "cursor: %d\n",
1832                               plane_wm, cursor_wm);
1833                 enabled |= 1 << PIPE_A;
1834         }
1835
1836         if (g4x_compute_wm0(dev, PIPE_B,
1837                             &ironlake_display_wm_info,
1838                             dev_priv->wm.pri_latency[0] * 100,
1839                             &ironlake_cursor_wm_info,
1840                             dev_priv->wm.cur_latency[0] * 100,
1841                             &plane_wm, &cursor_wm)) {
1842                 I915_WRITE(WM0_PIPEB_ILK,
1843                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1844                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1845                               " plane %d, cursor: %d\n",
1846                               plane_wm, cursor_wm);
1847                 enabled |= 1 << PIPE_B;
1848         }
1849
1850         /*
1851          * Calculate and update the self-refresh watermark only when one
1852          * display plane is used.
1853          */
1854         I915_WRITE(WM3_LP_ILK, 0);
1855         I915_WRITE(WM2_LP_ILK, 0);
1856         I915_WRITE(WM1_LP_ILK, 0);
1857
1858         if (!single_plane_enabled(enabled))
1859                 return;
1860         enabled = ffs(enabled) - 1;
1861
1862         /* WM1 */
1863         if (!ironlake_compute_srwm(dev, 1, enabled,
1864                                    dev_priv->wm.pri_latency[1] * 500,
1865                                    &ironlake_display_srwm_info,
1866                                    &ironlake_cursor_srwm_info,
1867                                    &fbc_wm, &plane_wm, &cursor_wm))
1868                 return;
1869
1870         I915_WRITE(WM1_LP_ILK,
1871                    WM1_LP_SR_EN |
1872                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1873                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1874                    (plane_wm << WM1_LP_SR_SHIFT) |
1875                    cursor_wm);
1876
1877         /* WM2 */
1878         if (!ironlake_compute_srwm(dev, 2, enabled,
1879                                    dev_priv->wm.pri_latency[2] * 500,
1880                                    &ironlake_display_srwm_info,
1881                                    &ironlake_cursor_srwm_info,
1882                                    &fbc_wm, &plane_wm, &cursor_wm))
1883                 return;
1884
1885         I915_WRITE(WM2_LP_ILK,
1886                    WM2_LP_EN |
1887                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1888                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1889                    (plane_wm << WM1_LP_SR_SHIFT) |
1890                    cursor_wm);
1891
1892         /*
1893          * WM3 is unsupported on ILK, probably because we don't have latency
1894          * data for that power state
1895          */
1896 }
1897
1898 static void sandybridge_update_wm(struct drm_crtc *crtc)
1899 {
1900         struct drm_device *dev = crtc->dev;
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
1903         u32 val;
1904         int fbc_wm, plane_wm, cursor_wm;
1905         unsigned int enabled;
1906
1907         enabled = 0;
1908         if (g4x_compute_wm0(dev, PIPE_A,
1909                             &sandybridge_display_wm_info, latency,
1910                             &sandybridge_cursor_wm_info, latency,
1911                             &plane_wm, &cursor_wm)) {
1912                 val = I915_READ(WM0_PIPEA_ILK);
1913                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1914                 I915_WRITE(WM0_PIPEA_ILK, val |
1915                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1916                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1917                               " plane %d, " "cursor: %d\n",
1918                               plane_wm, cursor_wm);
1919                 enabled |= 1 << PIPE_A;
1920         }
1921
1922         if (g4x_compute_wm0(dev, PIPE_B,
1923                             &sandybridge_display_wm_info, latency,
1924                             &sandybridge_cursor_wm_info, latency,
1925                             &plane_wm, &cursor_wm)) {
1926                 val = I915_READ(WM0_PIPEB_ILK);
1927                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1928                 I915_WRITE(WM0_PIPEB_ILK, val |
1929                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1930                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1931                               " plane %d, cursor: %d\n",
1932                               plane_wm, cursor_wm);
1933                 enabled |= 1 << PIPE_B;
1934         }
1935
1936         /*
1937          * Calculate and update the self-refresh watermark only when one
1938          * display plane is used.
1939          *
1940          * SNB support 3 levels of watermark.
1941          *
1942          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1943          * and disabled in the descending order
1944          *
1945          */
1946         I915_WRITE(WM3_LP_ILK, 0);
1947         I915_WRITE(WM2_LP_ILK, 0);
1948         I915_WRITE(WM1_LP_ILK, 0);
1949
1950         if (!single_plane_enabled(enabled) ||
1951             dev_priv->sprite_scaling_enabled)
1952                 return;
1953         enabled = ffs(enabled) - 1;
1954
1955         /* WM1 */
1956         if (!ironlake_compute_srwm(dev, 1, enabled,
1957                                    dev_priv->wm.pri_latency[1] * 500,
1958                                    &sandybridge_display_srwm_info,
1959                                    &sandybridge_cursor_srwm_info,
1960                                    &fbc_wm, &plane_wm, &cursor_wm))
1961                 return;
1962
1963         I915_WRITE(WM1_LP_ILK,
1964                    WM1_LP_SR_EN |
1965                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1966                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1967                    (plane_wm << WM1_LP_SR_SHIFT) |
1968                    cursor_wm);
1969
1970         /* WM2 */
1971         if (!ironlake_compute_srwm(dev, 2, enabled,
1972                                    dev_priv->wm.pri_latency[2] * 500,
1973                                    &sandybridge_display_srwm_info,
1974                                    &sandybridge_cursor_srwm_info,
1975                                    &fbc_wm, &plane_wm, &cursor_wm))
1976                 return;
1977
1978         I915_WRITE(WM2_LP_ILK,
1979                    WM2_LP_EN |
1980                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1981                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1982                    (plane_wm << WM1_LP_SR_SHIFT) |
1983                    cursor_wm);
1984
1985         /* WM3 */
1986         if (!ironlake_compute_srwm(dev, 3, enabled,
1987                                    dev_priv->wm.pri_latency[3] * 500,
1988                                    &sandybridge_display_srwm_info,
1989                                    &sandybridge_cursor_srwm_info,
1990                                    &fbc_wm, &plane_wm, &cursor_wm))
1991                 return;
1992
1993         I915_WRITE(WM3_LP_ILK,
1994                    WM3_LP_EN |
1995                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1996                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1997                    (plane_wm << WM1_LP_SR_SHIFT) |
1998                    cursor_wm);
1999 }
2000
2001 static void ivybridge_update_wm(struct drm_crtc *crtc)
2002 {
2003         struct drm_device *dev = crtc->dev;
2004         struct drm_i915_private *dev_priv = dev->dev_private;
2005         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
2006         u32 val;
2007         int fbc_wm, plane_wm, cursor_wm;
2008         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2009         unsigned int enabled;
2010
2011         enabled = 0;
2012         if (g4x_compute_wm0(dev, PIPE_A,
2013                             &sandybridge_display_wm_info, latency,
2014                             &sandybridge_cursor_wm_info, latency,
2015                             &plane_wm, &cursor_wm)) {
2016                 val = I915_READ(WM0_PIPEA_ILK);
2017                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2018                 I915_WRITE(WM0_PIPEA_ILK, val |
2019                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2020                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2021                               " plane %d, " "cursor: %d\n",
2022                               plane_wm, cursor_wm);
2023                 enabled |= 1 << PIPE_A;
2024         }
2025
2026         if (g4x_compute_wm0(dev, PIPE_B,
2027                             &sandybridge_display_wm_info, latency,
2028                             &sandybridge_cursor_wm_info, latency,
2029                             &plane_wm, &cursor_wm)) {
2030                 val = I915_READ(WM0_PIPEB_ILK);
2031                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2032                 I915_WRITE(WM0_PIPEB_ILK, val |
2033                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2034                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2035                               " plane %d, cursor: %d\n",
2036                               plane_wm, cursor_wm);
2037                 enabled |= 1 << PIPE_B;
2038         }
2039
2040         if (g4x_compute_wm0(dev, PIPE_C,
2041                             &sandybridge_display_wm_info, latency,
2042                             &sandybridge_cursor_wm_info, latency,
2043                             &plane_wm, &cursor_wm)) {
2044                 val = I915_READ(WM0_PIPEC_IVB);
2045                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2046                 I915_WRITE(WM0_PIPEC_IVB, val |
2047                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2048                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2049                               " plane %d, cursor: %d\n",
2050                               plane_wm, cursor_wm);
2051                 enabled |= 1 << PIPE_C;
2052         }
2053
2054         /*
2055          * Calculate and update the self-refresh watermark only when one
2056          * display plane is used.
2057          *
2058          * SNB support 3 levels of watermark.
2059          *
2060          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2061          * and disabled in the descending order
2062          *
2063          */
2064         I915_WRITE(WM3_LP_ILK, 0);
2065         I915_WRITE(WM2_LP_ILK, 0);
2066         I915_WRITE(WM1_LP_ILK, 0);
2067
2068         if (!single_plane_enabled(enabled) ||
2069             dev_priv->sprite_scaling_enabled)
2070                 return;
2071         enabled = ffs(enabled) - 1;
2072
2073         /* WM1 */
2074         if (!ironlake_compute_srwm(dev, 1, enabled,
2075                                    dev_priv->wm.pri_latency[1] * 500,
2076                                    &sandybridge_display_srwm_info,
2077                                    &sandybridge_cursor_srwm_info,
2078                                    &fbc_wm, &plane_wm, &cursor_wm))
2079                 return;
2080
2081         I915_WRITE(WM1_LP_ILK,
2082                    WM1_LP_SR_EN |
2083                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2084                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2085                    (plane_wm << WM1_LP_SR_SHIFT) |
2086                    cursor_wm);
2087
2088         /* WM2 */
2089         if (!ironlake_compute_srwm(dev, 2, enabled,
2090                                    dev_priv->wm.pri_latency[2] * 500,
2091                                    &sandybridge_display_srwm_info,
2092                                    &sandybridge_cursor_srwm_info,
2093                                    &fbc_wm, &plane_wm, &cursor_wm))
2094                 return;
2095
2096         I915_WRITE(WM2_LP_ILK,
2097                    WM2_LP_EN |
2098                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2099                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2100                    (plane_wm << WM1_LP_SR_SHIFT) |
2101                    cursor_wm);
2102
2103         /* WM3, note we have to correct the cursor latency */
2104         if (!ironlake_compute_srwm(dev, 3, enabled,
2105                                    dev_priv->wm.pri_latency[3] * 500,
2106                                    &sandybridge_display_srwm_info,
2107                                    &sandybridge_cursor_srwm_info,
2108                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2109             !ironlake_compute_srwm(dev, 3, enabled,
2110                                    dev_priv->wm.cur_latency[3] * 500,
2111                                    &sandybridge_display_srwm_info,
2112                                    &sandybridge_cursor_srwm_info,
2113                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2114                 return;
2115
2116         I915_WRITE(WM3_LP_ILK,
2117                    WM3_LP_EN |
2118                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2119                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2120                    (plane_wm << WM1_LP_SR_SHIFT) |
2121                    cursor_wm);
2122 }
2123
2124 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2125                                     struct drm_crtc *crtc)
2126 {
2127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2128         uint32_t pixel_rate;
2129
2130         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2131
2132         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2133          * adjust the pixel_rate here. */
2134
2135         if (intel_crtc->config.pch_pfit.enabled) {
2136                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2137                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2138
2139                 pipe_w = intel_crtc->config.pipe_src_w;
2140                 pipe_h = intel_crtc->config.pipe_src_h;
2141                 pfit_w = (pfit_size >> 16) & 0xFFFF;
2142                 pfit_h = pfit_size & 0xFFFF;
2143                 if (pipe_w < pfit_w)
2144                         pipe_w = pfit_w;
2145                 if (pipe_h < pfit_h)
2146                         pipe_h = pfit_h;
2147
2148                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2149                                      pfit_w * pfit_h);
2150         }
2151
2152         return pixel_rate;
2153 }
2154
2155 /* latency must be in 0.1us units. */
2156 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2157                                uint32_t latency)
2158 {
2159         uint64_t ret;
2160
2161         if (WARN(latency == 0, "Latency value missing\n"))
2162                 return UINT_MAX;
2163
2164         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2165         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2166
2167         return ret;
2168 }
2169
2170 /* latency must be in 0.1us units. */
2171 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2172                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2173                                uint32_t latency)
2174 {
2175         uint32_t ret;
2176
2177         if (WARN(latency == 0, "Latency value missing\n"))
2178                 return UINT_MAX;
2179
2180         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2181         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2182         ret = DIV_ROUND_UP(ret, 64) + 2;
2183         return ret;
2184 }
2185
2186 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2187                            uint8_t bytes_per_pixel)
2188 {
2189         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2190 }
2191
2192 struct hsw_pipe_wm_parameters {
2193         bool active;
2194         uint32_t pipe_htotal;
2195         uint32_t pixel_rate;
2196         struct intel_plane_wm_parameters pri;
2197         struct intel_plane_wm_parameters spr;
2198         struct intel_plane_wm_parameters cur;
2199 };
2200
2201 struct hsw_wm_maximums {
2202         uint16_t pri;
2203         uint16_t spr;
2204         uint16_t cur;
2205         uint16_t fbc;
2206 };
2207
2208 /* used in computing the new watermarks state */
2209 struct intel_wm_config {
2210         unsigned int num_pipes_active;
2211         bool sprites_enabled;
2212         bool sprites_scaled;
2213 };
2214
2215 /*
2216  * For both WM_PIPE and WM_LP.
2217  * mem_value must be in 0.1us units.
2218  */
2219 static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2220                                    uint32_t mem_value,
2221                                    bool is_lp)
2222 {
2223         uint32_t method1, method2;
2224
2225         if (!params->active || !params->pri.enabled)
2226                 return 0;
2227
2228         method1 = ilk_wm_method1(params->pixel_rate,
2229                                  params->pri.bytes_per_pixel,
2230                                  mem_value);
2231
2232         if (!is_lp)
2233                 return method1;
2234
2235         method2 = ilk_wm_method2(params->pixel_rate,
2236                                  params->pipe_htotal,
2237                                  params->pri.horiz_pixels,
2238                                  params->pri.bytes_per_pixel,
2239                                  mem_value);
2240
2241         return min(method1, method2);
2242 }
2243
2244 /*
2245  * For both WM_PIPE and WM_LP.
2246  * mem_value must be in 0.1us units.
2247  */
2248 static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2249                                    uint32_t mem_value)
2250 {
2251         uint32_t method1, method2;
2252
2253         if (!params->active || !params->spr.enabled)
2254                 return 0;
2255
2256         method1 = ilk_wm_method1(params->pixel_rate,
2257                                  params->spr.bytes_per_pixel,
2258                                  mem_value);
2259         method2 = ilk_wm_method2(params->pixel_rate,
2260                                  params->pipe_htotal,
2261                                  params->spr.horiz_pixels,
2262                                  params->spr.bytes_per_pixel,
2263                                  mem_value);
2264         return min(method1, method2);
2265 }
2266
2267 /*
2268  * For both WM_PIPE and WM_LP.
2269  * mem_value must be in 0.1us units.
2270  */
2271 static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2272                                    uint32_t mem_value)
2273 {
2274         if (!params->active || !params->cur.enabled)
2275                 return 0;
2276
2277         return ilk_wm_method2(params->pixel_rate,
2278                               params->pipe_htotal,
2279                               params->cur.horiz_pixels,
2280                               params->cur.bytes_per_pixel,
2281                               mem_value);
2282 }
2283
2284 /* Only for WM_LP. */
2285 static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2286                                    uint32_t pri_val)
2287 {
2288         if (!params->active || !params->pri.enabled)
2289                 return 0;
2290
2291         return ilk_wm_fbc(pri_val,
2292                           params->pri.horiz_pixels,
2293                           params->pri.bytes_per_pixel);
2294 }
2295
2296 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2297 {
2298         if (INTEL_INFO(dev)->gen >= 8)
2299                 return 3072;
2300         else if (INTEL_INFO(dev)->gen >= 7)
2301                 return 768;
2302         else
2303                 return 512;
2304 }
2305
2306 /* Calculate the maximum primary/sprite plane watermark */
2307 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2308                                      int level,
2309                                      const struct intel_wm_config *config,
2310                                      enum intel_ddb_partitioning ddb_partitioning,
2311                                      bool is_sprite)
2312 {
2313         unsigned int fifo_size = ilk_display_fifo_size(dev);
2314         unsigned int max;
2315
2316         /* if sprites aren't enabled, sprites get nothing */
2317         if (is_sprite && !config->sprites_enabled)
2318                 return 0;
2319
2320         /* HSW allows LP1+ watermarks even with multiple pipes */
2321         if (level == 0 || config->num_pipes_active > 1) {
2322                 fifo_size /= INTEL_INFO(dev)->num_pipes;
2323
2324                 /*
2325                  * For some reason the non self refresh
2326                  * FIFO size is only half of the self
2327                  * refresh FIFO size on ILK/SNB.
2328                  */
2329                 if (INTEL_INFO(dev)->gen <= 6)
2330                         fifo_size /= 2;
2331         }
2332
2333         if (config->sprites_enabled) {
2334                 /* level 0 is always calculated with 1:1 split */
2335                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2336                         if (is_sprite)
2337                                 fifo_size *= 5;
2338                         fifo_size /= 6;
2339                 } else {
2340                         fifo_size /= 2;
2341                 }
2342         }
2343
2344         /* clamp to max that the registers can hold */
2345         if (INTEL_INFO(dev)->gen >= 8)
2346                 max = level == 0 ? 255 : 2047;
2347         else if (INTEL_INFO(dev)->gen >= 7)
2348                 /* IVB/HSW primary/sprite plane watermarks */
2349                 max = level == 0 ? 127 : 1023;
2350         else if (!is_sprite)
2351                 /* ILK/SNB primary plane watermarks */
2352                 max = level == 0 ? 127 : 511;
2353         else
2354                 /* ILK/SNB sprite plane watermarks */
2355                 max = level == 0 ? 63 : 255;
2356
2357         return min(fifo_size, max);
2358 }
2359
2360 /* Calculate the maximum cursor plane watermark */
2361 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2362                                       int level,
2363                                       const struct intel_wm_config *config)
2364 {
2365         /* HSW LP1+ watermarks w/ multiple pipes */
2366         if (level > 0 && config->num_pipes_active > 1)
2367                 return 64;
2368
2369         /* otherwise just report max that registers can hold */
2370         if (INTEL_INFO(dev)->gen >= 7)
2371                 return level == 0 ? 63 : 255;
2372         else
2373                 return level == 0 ? 31 : 63;
2374 }
2375
2376 /* Calculate the maximum FBC watermark */
2377 static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
2378 {
2379         /* max that registers can hold */
2380         if (INTEL_INFO(dev)->gen >= 8)
2381                 return 31;
2382         else
2383                 return 15;
2384 }
2385
2386 static void ilk_compute_wm_maximums(struct drm_device *dev,
2387                                     int level,
2388                                     const struct intel_wm_config *config,
2389                                     enum intel_ddb_partitioning ddb_partitioning,
2390                                     struct hsw_wm_maximums *max)
2391 {
2392         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2393         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2394         max->cur = ilk_cursor_wm_max(dev, level, config);
2395         max->fbc = ilk_fbc_wm_max(dev);
2396 }
2397
2398 static bool ilk_validate_wm_level(int level,
2399                                   const struct hsw_wm_maximums *max,
2400                                   struct intel_wm_level *result)
2401 {
2402         bool ret;
2403
2404         /* already determined to be invalid? */
2405         if (!result->enable)
2406                 return false;
2407
2408         result->enable = result->pri_val <= max->pri &&
2409                          result->spr_val <= max->spr &&
2410                          result->cur_val <= max->cur;
2411
2412         ret = result->enable;
2413
2414         /*
2415          * HACK until we can pre-compute everything,
2416          * and thus fail gracefully if LP0 watermarks
2417          * are exceeded...
2418          */
2419         if (level == 0 && !result->enable) {
2420                 if (result->pri_val > max->pri)
2421                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2422                                       level, result->pri_val, max->pri);
2423                 if (result->spr_val > max->spr)
2424                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2425                                       level, result->spr_val, max->spr);
2426                 if (result->cur_val > max->cur)
2427                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2428                                       level, result->cur_val, max->cur);
2429
2430                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2431                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2432                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2433                 result->enable = true;
2434         }
2435
2436         return ret;
2437 }
2438
2439 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2440                                  int level,
2441                                  const struct hsw_pipe_wm_parameters *p,
2442                                  struct intel_wm_level *result)
2443 {
2444         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2445         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2446         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2447
2448         /* WM1+ latency values stored in 0.5us units */
2449         if (level > 0) {
2450                 pri_latency *= 5;
2451                 spr_latency *= 5;
2452                 cur_latency *= 5;
2453         }
2454
2455         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2456         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2457         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2458         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2459         result->enable = true;
2460 }
2461
2462 static uint32_t
2463 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2464 {
2465         struct drm_i915_private *dev_priv = dev->dev_private;
2466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2467         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2468         u32 linetime, ips_linetime;
2469
2470         if (!intel_crtc_active(crtc))
2471                 return 0;
2472
2473         /* The WM are computed with base on how long it takes to fill a single
2474          * row at the given clock rate, multiplied by 8.
2475          * */
2476         linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2477         ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2478                                          intel_ddi_get_cdclk_freq(dev_priv));
2479
2480         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2481                PIPE_WM_LINETIME_TIME(linetime);
2482 }
2483
2484 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2485 {
2486         struct drm_i915_private *dev_priv = dev->dev_private;
2487
2488         if (IS_HASWELL(dev)) {
2489                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2490
2491                 wm[0] = (sskpd >> 56) & 0xFF;
2492                 if (wm[0] == 0)
2493                         wm[0] = sskpd & 0xF;
2494                 wm[1] = (sskpd >> 4) & 0xFF;
2495                 wm[2] = (sskpd >> 12) & 0xFF;
2496                 wm[3] = (sskpd >> 20) & 0x1FF;
2497                 wm[4] = (sskpd >> 32) & 0x1FF;
2498         } else if (INTEL_INFO(dev)->gen >= 6) {
2499                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2500
2501                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2502                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2503                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2504                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2505         } else if (INTEL_INFO(dev)->gen >= 5) {
2506                 uint32_t mltr = I915_READ(MLTR_ILK);
2507
2508                 /* ILK primary LP0 latency is 700 ns */
2509                 wm[0] = 7;
2510                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2511                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2512         }
2513 }
2514
2515 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2516 {
2517         /* ILK sprite LP0 latency is 1300 ns */
2518         if (INTEL_INFO(dev)->gen == 5)
2519                 wm[0] = 13;
2520 }
2521
2522 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2523 {
2524         /* ILK cursor LP0 latency is 1300 ns */
2525         if (INTEL_INFO(dev)->gen == 5)
2526                 wm[0] = 13;
2527
2528         /* WaDoubleCursorLP3Latency:ivb */
2529         if (IS_IVYBRIDGE(dev))
2530                 wm[3] *= 2;
2531 }
2532
2533 static int ilk_wm_max_level(const struct drm_device *dev)
2534 {
2535         /* how many WM levels are we expecting */
2536         if (IS_HASWELL(dev))
2537                 return 4;
2538         else if (INTEL_INFO(dev)->gen >= 6)
2539                 return 3;
2540         else
2541                 return 2;
2542 }
2543
2544 static void intel_print_wm_latency(struct drm_device *dev,
2545                                    const char *name,
2546                                    const uint16_t wm[5])
2547 {
2548         int level, max_level = ilk_wm_max_level(dev);
2549
2550         for (level = 0; level <= max_level; level++) {
2551                 unsigned int latency = wm[level];
2552
2553                 if (latency == 0) {
2554                         DRM_ERROR("%s WM%d latency not provided\n",
2555                                   name, level);
2556                         continue;
2557                 }
2558
2559                 /* WM1+ latency values in 0.5us units */
2560                 if (level > 0)
2561                         latency *= 5;
2562
2563                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2564                               name, level, wm[level],
2565                               latency / 10, latency % 10);
2566         }
2567 }
2568
2569 static void intel_setup_wm_latency(struct drm_device *dev)
2570 {
2571         struct drm_i915_private *dev_priv = dev->dev_private;
2572
2573         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2574
2575         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2576                sizeof(dev_priv->wm.pri_latency));
2577         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2578                sizeof(dev_priv->wm.pri_latency));
2579
2580         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2581         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2582
2583         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2584         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2585         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2586 }
2587
2588 static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2589                                       struct hsw_pipe_wm_parameters *p,
2590                                       struct intel_wm_config *config)
2591 {
2592         struct drm_device *dev = crtc->dev;
2593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2594         enum pipe pipe = intel_crtc->pipe;
2595         struct drm_plane *plane;
2596
2597         p->active = intel_crtc_active(crtc);
2598         if (p->active) {
2599                 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2600                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2601                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2602                 p->cur.bytes_per_pixel = 4;
2603                 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2604                 p->cur.horiz_pixels = 64;
2605                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2606                 p->pri.enabled = true;
2607                 p->cur.enabled = true;
2608         }
2609
2610         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2611                 config->num_pipes_active += intel_crtc_active(crtc);
2612
2613         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2614                 struct intel_plane *intel_plane = to_intel_plane(plane);
2615
2616                 if (intel_plane->pipe == pipe)
2617                         p->spr = intel_plane->wm;
2618
2619                 config->sprites_enabled |= intel_plane->wm.enabled;
2620                 config->sprites_scaled |= intel_plane->wm.scaled;
2621         }
2622 }
2623
2624 /* Compute new watermarks for the pipe */
2625 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2626                                   const struct hsw_pipe_wm_parameters *params,
2627                                   struct intel_pipe_wm *pipe_wm)
2628 {
2629         struct drm_device *dev = crtc->dev;
2630         struct drm_i915_private *dev_priv = dev->dev_private;
2631         int level, max_level = ilk_wm_max_level(dev);
2632         /* LP0 watermark maximums depend on this pipe alone */
2633         struct intel_wm_config config = {
2634                 .num_pipes_active = 1,
2635                 .sprites_enabled = params->spr.enabled,
2636                 .sprites_scaled = params->spr.scaled,
2637         };
2638         struct hsw_wm_maximums max;
2639
2640         /* LP0 watermarks always use 1/2 DDB partitioning */
2641         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2642
2643         for (level = 0; level <= max_level; level++)
2644                 ilk_compute_wm_level(dev_priv, level, params,
2645                                      &pipe_wm->wm[level]);
2646
2647         pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2648
2649         /* At least LP0 must be valid */
2650         return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2651 }
2652
2653 /*
2654  * Merge the watermarks from all active pipes for a specific level.
2655  */
2656 static void ilk_merge_wm_level(struct drm_device *dev,
2657                                int level,
2658                                struct intel_wm_level *ret_wm)
2659 {
2660         const struct intel_crtc *intel_crtc;
2661
2662         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2663                 const struct intel_wm_level *wm =
2664                         &intel_crtc->wm.active.wm[level];
2665
2666                 if (!wm->enable)
2667                         return;
2668
2669                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2670                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2671                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2672                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2673         }
2674
2675         ret_wm->enable = true;
2676 }
2677
2678 /*
2679  * Merge all low power watermarks for all active pipes.
2680  */
2681 static void ilk_wm_merge(struct drm_device *dev,
2682                          const struct hsw_wm_maximums *max,
2683                          struct intel_pipe_wm *merged)
2684 {
2685         int level, max_level = ilk_wm_max_level(dev);
2686
2687         merged->fbc_wm_enabled = true;
2688
2689         /* merge each WM1+ level */
2690         for (level = 1; level <= max_level; level++) {
2691                 struct intel_wm_level *wm = &merged->wm[level];
2692
2693                 ilk_merge_wm_level(dev, level, wm);
2694
2695                 if (!ilk_validate_wm_level(level, max, wm))
2696                         break;
2697
2698                 /*
2699                  * The spec says it is preferred to disable
2700                  * FBC WMs instead of disabling a WM level.
2701                  */
2702                 if (wm->fbc_val > max->fbc) {
2703                         merged->fbc_wm_enabled = false;
2704                         wm->fbc_val = 0;
2705                 }
2706         }
2707 }
2708
2709 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2710 {
2711         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2712         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2713 }
2714
2715 static void hsw_compute_wm_results(struct drm_device *dev,
2716                                    const struct intel_pipe_wm *merged,
2717                                    enum intel_ddb_partitioning partitioning,
2718                                    struct hsw_wm_values *results)
2719 {
2720         struct intel_crtc *intel_crtc;
2721         int level, wm_lp;
2722
2723         results->enable_fbc_wm = merged->fbc_wm_enabled;
2724         results->partitioning = partitioning;
2725
2726         /* LP1+ register values */
2727         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2728                 const struct intel_wm_level *r;
2729
2730                 level = ilk_wm_lp_to_level(wm_lp, merged);
2731
2732                 r = &merged->wm[level];
2733                 if (!r->enable)
2734                         break;
2735
2736                 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2737                         ((level * 2) << WM1_LP_LATENCY_SHIFT) |
2738                         (r->pri_val << WM1_LP_SR_SHIFT) |
2739                         r->cur_val;
2740
2741                 if (INTEL_INFO(dev)->gen >= 8)
2742                         results->wm_lp[wm_lp - 1] |=
2743                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2744                 else
2745                         results->wm_lp[wm_lp - 1] |=
2746                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2747
2748                 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2749         }
2750
2751         /* LP0 register values */
2752         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2753                 enum pipe pipe = intel_crtc->pipe;
2754                 const struct intel_wm_level *r =
2755                         &intel_crtc->wm.active.wm[0];
2756
2757                 if (WARN_ON(!r->enable))
2758                         continue;
2759
2760                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2761
2762                 results->wm_pipe[pipe] =
2763                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2764                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2765                         r->cur_val;
2766         }
2767 }
2768
2769 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2770  * case both are at the same level. Prefer r1 in case they're the same. */
2771 static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2772                                                   struct intel_pipe_wm *r1,
2773                                                   struct intel_pipe_wm *r2)
2774 {
2775         int level, max_level = ilk_wm_max_level(dev);
2776         int level1 = 0, level2 = 0;
2777
2778         for (level = 1; level <= max_level; level++) {
2779                 if (r1->wm[level].enable)
2780                         level1 = level;
2781                 if (r2->wm[level].enable)
2782                         level2 = level;
2783         }
2784
2785         if (level1 == level2) {
2786                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2787                         return r2;
2788                 else
2789                         return r1;
2790         } else if (level1 > level2) {
2791                 return r1;
2792         } else {
2793                 return r2;
2794         }
2795 }
2796
2797 /* dirty bits used to track which watermarks need changes */
2798 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2799 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2800 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2801 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2802 #define WM_DIRTY_FBC (1 << 24)
2803 #define WM_DIRTY_DDB (1 << 25)
2804
2805 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2806                                          const struct hsw_wm_values *old,
2807                                          const struct hsw_wm_values *new)
2808 {
2809         unsigned int dirty = 0;
2810         enum pipe pipe;
2811         int wm_lp;
2812
2813         for_each_pipe(pipe) {
2814                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2815                         dirty |= WM_DIRTY_LINETIME(pipe);
2816                         /* Must disable LP1+ watermarks too */
2817                         dirty |= WM_DIRTY_LP_ALL;
2818                 }
2819
2820                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2821                         dirty |= WM_DIRTY_PIPE(pipe);
2822                         /* Must disable LP1+ watermarks too */
2823                         dirty |= WM_DIRTY_LP_ALL;
2824                 }
2825         }
2826
2827         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2828                 dirty |= WM_DIRTY_FBC;
2829                 /* Must disable LP1+ watermarks too */
2830                 dirty |= WM_DIRTY_LP_ALL;
2831         }
2832
2833         if (old->partitioning != new->partitioning) {
2834                 dirty |= WM_DIRTY_DDB;
2835                 /* Must disable LP1+ watermarks too */
2836                 dirty |= WM_DIRTY_LP_ALL;
2837         }
2838
2839         /* LP1+ watermarks already deemed dirty, no need to continue */
2840         if (dirty & WM_DIRTY_LP_ALL)
2841                 return dirty;
2842
2843         /* Find the lowest numbered LP1+ watermark in need of an update... */
2844         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2845                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2846                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2847                         break;
2848         }
2849
2850         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2851         for (; wm_lp <= 3; wm_lp++)
2852                 dirty |= WM_DIRTY_LP(wm_lp);
2853
2854         return dirty;
2855 }
2856
2857 /*
2858  * The spec says we shouldn't write when we don't need, because every write
2859  * causes WMs to be re-evaluated, expending some power.
2860  */
2861 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2862                                 struct hsw_wm_values *results)
2863 {
2864         struct hsw_wm_values *previous = &dev_priv->wm.hw;
2865         unsigned int dirty;
2866         uint32_t val;
2867
2868         dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2869         if (!dirty)
2870                 return;
2871
2872         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2873                 I915_WRITE(WM3_LP_ILK, 0);
2874         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2875                 I915_WRITE(WM2_LP_ILK, 0);
2876         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2877                 I915_WRITE(WM1_LP_ILK, 0);
2878
2879         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2880                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2881         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2882                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2883         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2884                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2885
2886         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2887                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2888         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2889                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2890         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2891                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2892
2893         if (dirty & WM_DIRTY_DDB) {
2894                 val = I915_READ(WM_MISC);
2895                 if (results->partitioning == INTEL_DDB_PART_1_2)
2896                         val &= ~WM_MISC_DATA_PARTITION_5_6;
2897                 else
2898                         val |= WM_MISC_DATA_PARTITION_5_6;
2899                 I915_WRITE(WM_MISC, val);
2900         }
2901
2902         if (dirty & WM_DIRTY_FBC) {
2903                 val = I915_READ(DISP_ARB_CTL);
2904                 if (results->enable_fbc_wm)
2905                         val &= ~DISP_FBC_WM_DIS;
2906                 else
2907                         val |= DISP_FBC_WM_DIS;
2908                 I915_WRITE(DISP_ARB_CTL, val);
2909         }
2910
2911         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2912                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2913         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2914                 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2915         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2916                 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2917
2918         if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2919                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2920         if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2921                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2922         if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2923                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2924
2925         dev_priv->wm.hw = *results;
2926 }
2927
2928 static void haswell_update_wm(struct drm_crtc *crtc)
2929 {
2930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2931         struct drm_device *dev = crtc->dev;
2932         struct drm_i915_private *dev_priv = dev->dev_private;
2933         struct hsw_wm_maximums max;
2934         struct hsw_pipe_wm_parameters params = {};
2935         struct hsw_wm_values results = {};
2936         enum intel_ddb_partitioning partitioning;
2937         struct intel_pipe_wm pipe_wm = {};
2938         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2939         struct intel_wm_config config = {};
2940
2941         hsw_compute_wm_parameters(crtc, &params, &config);
2942
2943         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2944
2945         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2946                 return;
2947
2948         intel_crtc->wm.active = pipe_wm;
2949
2950         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2951         ilk_wm_merge(dev, &max, &lp_wm_1_2);
2952
2953         /* 5/6 split only in single pipe config on IVB+ */
2954         if (INTEL_INFO(dev)->gen >= 7 &&
2955             config.num_pipes_active == 1 && config.sprites_enabled) {
2956                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2957                 ilk_wm_merge(dev, &max, &lp_wm_5_6);
2958
2959                 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2960         } else {
2961                 best_lp_wm = &lp_wm_1_2;
2962         }
2963
2964         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2965                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2966
2967         hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2968
2969         hsw_write_wm_values(dev_priv, &results);
2970 }
2971
2972 static void haswell_update_sprite_wm(struct drm_plane *plane,
2973                                      struct drm_crtc *crtc,
2974                                      uint32_t sprite_width, int pixel_size,
2975                                      bool enabled, bool scaled)
2976 {
2977         struct intel_plane *intel_plane = to_intel_plane(plane);
2978
2979         intel_plane->wm.enabled = enabled;
2980         intel_plane->wm.scaled = scaled;
2981         intel_plane->wm.horiz_pixels = sprite_width;
2982         intel_plane->wm.bytes_per_pixel = pixel_size;
2983
2984         haswell_update_wm(crtc);
2985 }
2986
2987 static bool
2988 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2989                               uint32_t sprite_width, int pixel_size,
2990                               const struct intel_watermark_params *display,
2991                               int display_latency_ns, int *sprite_wm)
2992 {
2993         struct drm_crtc *crtc;
2994         int clock;
2995         int entries, tlb_miss;
2996
2997         crtc = intel_get_crtc_for_plane(dev, plane);
2998         if (!intel_crtc_active(crtc)) {
2999                 *sprite_wm = display->guard_size;
3000                 return false;
3001         }
3002
3003         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3004
3005         /* Use the small buffer method to calculate the sprite watermark */
3006         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3007         tlb_miss = display->fifo_size*display->cacheline_size -
3008                 sprite_width * 8;
3009         if (tlb_miss > 0)
3010                 entries += tlb_miss;
3011         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3012         *sprite_wm = entries + display->guard_size;
3013         if (*sprite_wm > (int)display->max_wm)
3014                 *sprite_wm = display->max_wm;
3015
3016         return true;
3017 }
3018
3019 static bool
3020 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3021                                 uint32_t sprite_width, int pixel_size,
3022                                 const struct intel_watermark_params *display,
3023                                 int latency_ns, int *sprite_wm)
3024 {
3025         struct drm_crtc *crtc;
3026         unsigned long line_time_us;
3027         int clock;
3028         int line_count, line_size;
3029         int small, large;
3030         int entries;
3031
3032         if (!latency_ns) {
3033                 *sprite_wm = 0;
3034                 return false;
3035         }
3036
3037         crtc = intel_get_crtc_for_plane(dev, plane);
3038         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3039         if (!clock) {
3040                 *sprite_wm = 0;
3041                 return false;
3042         }
3043
3044         line_time_us = (sprite_width * 1000) / clock;
3045         if (!line_time_us) {
3046                 *sprite_wm = 0;
3047                 return false;
3048         }
3049
3050         line_count = (latency_ns / line_time_us + 1000) / 1000;
3051         line_size = sprite_width * pixel_size;
3052
3053         /* Use the minimum of the small and large buffer method for primary */
3054         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3055         large = line_count * line_size;
3056
3057         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3058         *sprite_wm = entries + display->guard_size;
3059
3060         return *sprite_wm > 0x3ff ? false : true;
3061 }
3062
3063 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3064                                          struct drm_crtc *crtc,
3065                                          uint32_t sprite_width, int pixel_size,
3066                                          bool enabled, bool scaled)
3067 {
3068         struct drm_device *dev = plane->dev;
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070         int pipe = to_intel_plane(plane)->pipe;
3071         int latency = dev_priv->wm.spr_latency[0] * 100;        /* In unit 0.1us */
3072         u32 val;
3073         int sprite_wm, reg;
3074         int ret;
3075
3076         if (!enabled)
3077                 return;
3078
3079         switch (pipe) {
3080         case 0:
3081                 reg = WM0_PIPEA_ILK;
3082                 break;
3083         case 1:
3084                 reg = WM0_PIPEB_ILK;
3085                 break;
3086         case 2:
3087                 reg = WM0_PIPEC_IVB;
3088                 break;
3089         default:
3090                 return; /* bad pipe */
3091         }
3092
3093         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3094                                             &sandybridge_display_wm_info,
3095                                             latency, &sprite_wm);
3096         if (!ret) {
3097                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3098                               pipe_name(pipe));
3099                 return;
3100         }
3101
3102         val = I915_READ(reg);
3103         val &= ~WM0_PIPE_SPRITE_MASK;
3104         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3105         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3106
3107
3108         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3109                                               pixel_size,
3110                                               &sandybridge_display_srwm_info,
3111                                               dev_priv->wm.spr_latency[1] * 500,
3112                                               &sprite_wm);
3113         if (!ret) {
3114                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3115                               pipe_name(pipe));
3116                 return;
3117         }
3118         I915_WRITE(WM1S_LP_ILK, sprite_wm);
3119
3120         /* Only IVB has two more LP watermarks for sprite */
3121         if (!IS_IVYBRIDGE(dev))
3122                 return;
3123
3124         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3125                                               pixel_size,
3126                                               &sandybridge_display_srwm_info,
3127                                               dev_priv->wm.spr_latency[2] * 500,
3128                                               &sprite_wm);
3129         if (!ret) {
3130                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3131                               pipe_name(pipe));
3132                 return;
3133         }
3134         I915_WRITE(WM2S_LP_IVB, sprite_wm);
3135
3136         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3137                                               pixel_size,
3138                                               &sandybridge_display_srwm_info,
3139                                               dev_priv->wm.spr_latency[3] * 500,
3140                                               &sprite_wm);
3141         if (!ret) {
3142                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3143                               pipe_name(pipe));
3144                 return;
3145         }
3146         I915_WRITE(WM3S_LP_IVB, sprite_wm);
3147 }
3148
3149 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3150 {
3151         struct drm_device *dev = crtc->dev;
3152         struct drm_i915_private *dev_priv = dev->dev_private;
3153         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3155         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3156         enum pipe pipe = intel_crtc->pipe;
3157         static const unsigned int wm0_pipe_reg[] = {
3158                 [PIPE_A] = WM0_PIPEA_ILK,
3159                 [PIPE_B] = WM0_PIPEB_ILK,
3160                 [PIPE_C] = WM0_PIPEC_IVB,
3161         };
3162
3163         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3164         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3165
3166         if (intel_crtc_active(crtc)) {
3167                 u32 tmp = hw->wm_pipe[pipe];
3168
3169                 /*
3170                  * For active pipes LP0 watermark is marked as
3171                  * enabled, and LP1+ watermaks as disabled since
3172                  * we can't really reverse compute them in case
3173                  * multiple pipes are active.
3174                  */
3175                 active->wm[0].enable = true;
3176                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3177                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3178                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3179                 active->linetime = hw->wm_linetime[pipe];
3180         } else {
3181                 int level, max_level = ilk_wm_max_level(dev);
3182
3183                 /*
3184                  * For inactive pipes, all watermark levels
3185                  * should be marked as enabled but zeroed,
3186                  * which is what we'd compute them to.
3187                  */
3188                 for (level = 0; level <= max_level; level++)
3189                         active->wm[level].enable = true;
3190         }
3191 }
3192
3193 void ilk_wm_get_hw_state(struct drm_device *dev)
3194 {
3195         struct drm_i915_private *dev_priv = dev->dev_private;
3196         struct hsw_wm_values *hw = &dev_priv->wm.hw;
3197         struct drm_crtc *crtc;
3198
3199         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3200                 ilk_pipe_wm_get_hw_state(crtc);
3201
3202         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3203         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3204         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3205
3206         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3207         hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3208         hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3209
3210         hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3211                 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3212
3213         hw->enable_fbc_wm =
3214                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3215 }
3216
3217 /**
3218  * intel_update_watermarks - update FIFO watermark values based on current modes
3219  *
3220  * Calculate watermark values for the various WM regs based on current mode
3221  * and plane configuration.
3222  *
3223  * There are several cases to deal with here:
3224  *   - normal (i.e. non-self-refresh)
3225  *   - self-refresh (SR) mode
3226  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3227  *   - lines are small relative to FIFO size (buffer can hold more than 2
3228  *     lines), so need to account for TLB latency
3229  *
3230  *   The normal calculation is:
3231  *     watermark = dotclock * bytes per pixel * latency
3232  *   where latency is platform & configuration dependent (we assume pessimal
3233  *   values here).
3234  *
3235  *   The SR calculation is:
3236  *     watermark = (trunc(latency/line time)+1) * surface width *
3237  *       bytes per pixel
3238  *   where
3239  *     line time = htotal / dotclock
3240  *     surface width = hdisplay for normal plane and 64 for cursor
3241  *   and latency is assumed to be high, as above.
3242  *
3243  * The final value programmed to the register should always be rounded up,
3244  * and include an extra 2 entries to account for clock crossings.
3245  *
3246  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3247  * to set the non-SR watermarks to 8.
3248  */
3249 void intel_update_watermarks(struct drm_crtc *crtc)
3250 {
3251         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3252
3253         if (dev_priv->display.update_wm)
3254                 dev_priv->display.update_wm(crtc);
3255 }
3256
3257 void intel_update_sprite_watermarks(struct drm_plane *plane,
3258                                     struct drm_crtc *crtc,
3259                                     uint32_t sprite_width, int pixel_size,
3260                                     bool enabled, bool scaled)
3261 {
3262         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3263
3264         if (dev_priv->display.update_sprite_wm)
3265                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3266                                                    pixel_size, enabled, scaled);
3267 }
3268
3269 static struct drm_i915_gem_object *
3270 intel_alloc_context_page(struct drm_device *dev)
3271 {
3272         struct drm_i915_gem_object *ctx;
3273         int ret;
3274
3275         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3276
3277         ctx = i915_gem_alloc_object(dev, 4096);
3278         if (!ctx) {
3279                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3280                 return NULL;
3281         }
3282
3283         ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3284         if (ret) {
3285                 DRM_ERROR("failed to pin power context: %d\n", ret);
3286                 goto err_unref;
3287         }
3288
3289         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3290         if (ret) {
3291                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3292                 goto err_unpin;
3293         }
3294
3295         return ctx;
3296
3297 err_unpin:
3298         i915_gem_object_unpin(ctx);
3299 err_unref:
3300         drm_gem_object_unreference(&ctx->base);
3301         return NULL;
3302 }
3303
3304 /**
3305  * Lock protecting IPS related data structures
3306  */
3307 DEFINE_SPINLOCK(mchdev_lock);
3308
3309 /* Global for IPS driver to get at the current i915 device. Protected by
3310  * mchdev_lock. */
3311 static struct drm_i915_private *i915_mch_dev;
3312
3313 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3314 {
3315         struct drm_i915_private *dev_priv = dev->dev_private;
3316         u16 rgvswctl;
3317
3318         assert_spin_locked(&mchdev_lock);
3319
3320         rgvswctl = I915_READ16(MEMSWCTL);
3321         if (rgvswctl & MEMCTL_CMD_STS) {
3322                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3323                 return false; /* still busy with another command */
3324         }
3325
3326         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3327                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3328         I915_WRITE16(MEMSWCTL, rgvswctl);
3329         POSTING_READ16(MEMSWCTL);
3330
3331         rgvswctl |= MEMCTL_CMD_STS;
3332         I915_WRITE16(MEMSWCTL, rgvswctl);
3333
3334         return true;
3335 }
3336
3337 static void ironlake_enable_drps(struct drm_device *dev)
3338 {
3339         struct drm_i915_private *dev_priv = dev->dev_private;
3340         u32 rgvmodectl = I915_READ(MEMMODECTL);
3341         u8 fmax, fmin, fstart, vstart;
3342
3343         spin_lock_irq(&mchdev_lock);
3344
3345         /* Enable temp reporting */
3346         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3347         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3348
3349         /* 100ms RC evaluation intervals */
3350         I915_WRITE(RCUPEI, 100000);
3351         I915_WRITE(RCDNEI, 100000);
3352
3353         /* Set max/min thresholds to 90ms and 80ms respectively */
3354         I915_WRITE(RCBMAXAVG, 90000);
3355         I915_WRITE(RCBMINAVG, 80000);
3356
3357         I915_WRITE(MEMIHYST, 1);
3358
3359         /* Set up min, max, and cur for interrupt handling */
3360         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3361         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3362         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3363                 MEMMODE_FSTART_SHIFT;
3364
3365         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3366                 PXVFREQ_PX_SHIFT;
3367
3368         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3369         dev_priv->ips.fstart = fstart;
3370
3371         dev_priv->ips.max_delay = fstart;
3372         dev_priv->ips.min_delay = fmin;
3373         dev_priv->ips.cur_delay = fstart;
3374
3375         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3376                          fmax, fmin, fstart);
3377
3378         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3379
3380         /*
3381          * Interrupts will be enabled in ironlake_irq_postinstall
3382          */
3383
3384         I915_WRITE(VIDSTART, vstart);
3385         POSTING_READ(VIDSTART);
3386
3387         rgvmodectl |= MEMMODE_SWMODE_EN;
3388         I915_WRITE(MEMMODECTL, rgvmodectl);
3389
3390         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3391                 DRM_ERROR("stuck trying to change perf mode\n");
3392         mdelay(1);
3393
3394         ironlake_set_drps(dev, fstart);
3395
3396         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3397                 I915_READ(0x112e0);
3398         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3399         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3400         getrawmonotonic(&dev_priv->ips.last_time2);
3401
3402         spin_unlock_irq(&mchdev_lock);
3403 }
3404
3405 static void ironlake_disable_drps(struct drm_device *dev)
3406 {
3407         struct drm_i915_private *dev_priv = dev->dev_private;
3408         u16 rgvswctl;
3409
3410         spin_lock_irq(&mchdev_lock);
3411
3412         rgvswctl = I915_READ16(MEMSWCTL);
3413
3414         /* Ack interrupts, disable EFC interrupt */
3415         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3416         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3417         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3418         I915_WRITE(DEIIR, DE_PCU_EVENT);
3419         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3420
3421         /* Go back to the starting frequency */
3422         ironlake_set_drps(dev, dev_priv->ips.fstart);
3423         mdelay(1);
3424         rgvswctl |= MEMCTL_CMD_STS;
3425         I915_WRITE(MEMSWCTL, rgvswctl);
3426         mdelay(1);
3427
3428         spin_unlock_irq(&mchdev_lock);
3429 }
3430
3431 /* There's a funny hw issue where the hw returns all 0 when reading from
3432  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3433  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3434  * all limits and the gpu stuck at whatever frequency it is at atm).
3435  */
3436 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3437 {
3438         u32 limits;
3439
3440         /* Only set the down limit when we've reached the lowest level to avoid
3441          * getting more interrupts, otherwise leave this clear. This prevents a
3442          * race in the hw when coming out of rc6: There's a tiny window where
3443          * the hw runs at the minimal clock before selecting the desired
3444          * frequency, if the down threshold expires in that window we will not
3445          * receive a down interrupt. */
3446         limits = dev_priv->rps.max_delay << 24;
3447         if (val <= dev_priv->rps.min_delay)
3448                 limits |= dev_priv->rps.min_delay << 16;
3449
3450         return limits;
3451 }
3452
3453 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3454 {
3455         int new_power;
3456
3457         new_power = dev_priv->rps.power;
3458         switch (dev_priv->rps.power) {
3459         case LOW_POWER:
3460                 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3461                         new_power = BETWEEN;
3462                 break;
3463
3464         case BETWEEN:
3465                 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3466                         new_power = LOW_POWER;
3467                 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3468                         new_power = HIGH_POWER;
3469                 break;
3470
3471         case HIGH_POWER:
3472                 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3473                         new_power = BETWEEN;
3474                 break;
3475         }
3476         /* Max/min bins are special */
3477         if (val == dev_priv->rps.min_delay)
3478                 new_power = LOW_POWER;
3479         if (val == dev_priv->rps.max_delay)
3480                 new_power = HIGH_POWER;
3481         if (new_power == dev_priv->rps.power)
3482                 return;
3483
3484         /* Note the units here are not exactly 1us, but 1280ns. */
3485         switch (new_power) {
3486         case LOW_POWER:
3487                 /* Upclock if more than 95% busy over 16ms */
3488                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3489                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3490
3491                 /* Downclock if less than 85% busy over 32ms */
3492                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3493                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3494
3495                 I915_WRITE(GEN6_RP_CONTROL,
3496                            GEN6_RP_MEDIA_TURBO |
3497                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3498                            GEN6_RP_MEDIA_IS_GFX |
3499                            GEN6_RP_ENABLE |
3500                            GEN6_RP_UP_BUSY_AVG |
3501                            GEN6_RP_DOWN_IDLE_AVG);
3502                 break;
3503
3504         case BETWEEN:
3505                 /* Upclock if more than 90% busy over 13ms */
3506                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3507                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3508
3509                 /* Downclock if less than 75% busy over 32ms */
3510                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3511                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3512
3513                 I915_WRITE(GEN6_RP_CONTROL,
3514                            GEN6_RP_MEDIA_TURBO |
3515                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3516                            GEN6_RP_MEDIA_IS_GFX |
3517                            GEN6_RP_ENABLE |
3518                            GEN6_RP_UP_BUSY_AVG |
3519                            GEN6_RP_DOWN_IDLE_AVG);
3520                 break;
3521
3522         case HIGH_POWER:
3523                 /* Upclock if more than 85% busy over 10ms */
3524                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3525                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3526
3527                 /* Downclock if less than 60% busy over 32ms */
3528                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3529                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3530
3531                 I915_WRITE(GEN6_RP_CONTROL,
3532                            GEN6_RP_MEDIA_TURBO |
3533                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3534                            GEN6_RP_MEDIA_IS_GFX |
3535                            GEN6_RP_ENABLE |
3536                            GEN6_RP_UP_BUSY_AVG |
3537                            GEN6_RP_DOWN_IDLE_AVG);
3538                 break;
3539         }
3540
3541         dev_priv->rps.power = new_power;
3542         dev_priv->rps.last_adj = 0;
3543 }
3544
3545 void gen6_set_rps(struct drm_device *dev, u8 val)
3546 {
3547         struct drm_i915_private *dev_priv = dev->dev_private;
3548
3549         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3550         WARN_ON(val > dev_priv->rps.max_delay);
3551         WARN_ON(val < dev_priv->rps.min_delay);
3552
3553         if (val == dev_priv->rps.cur_delay)
3554                 return;
3555
3556         gen6_set_rps_thresholds(dev_priv, val);
3557
3558         if (IS_HASWELL(dev))
3559                 I915_WRITE(GEN6_RPNSWREQ,
3560                            HSW_FREQUENCY(val));
3561         else
3562                 I915_WRITE(GEN6_RPNSWREQ,
3563                            GEN6_FREQUENCY(val) |
3564                            GEN6_OFFSET(0) |
3565                            GEN6_AGGRESSIVE_TURBO);
3566
3567         /* Make sure we continue to get interrupts
3568          * until we hit the minimum or maximum frequencies.
3569          */
3570         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3571                    gen6_rps_limits(dev_priv, val));
3572
3573         POSTING_READ(GEN6_RPNSWREQ);
3574
3575         dev_priv->rps.cur_delay = val;
3576
3577         trace_intel_gpu_freq_change(val * 50);
3578 }
3579
3580 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3581 {
3582         mutex_lock(&dev_priv->rps.hw_lock);
3583         if (dev_priv->rps.enabled) {
3584                 if (dev_priv->info->is_valleyview)
3585                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3586                 else
3587                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3588                 dev_priv->rps.last_adj = 0;
3589         }
3590         mutex_unlock(&dev_priv->rps.hw_lock);
3591 }
3592
3593 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3594 {
3595         mutex_lock(&dev_priv->rps.hw_lock);
3596         if (dev_priv->rps.enabled) {
3597                 if (dev_priv->info->is_valleyview)
3598                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3599                 else
3600                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3601                 dev_priv->rps.last_adj = 0;
3602         }
3603         mutex_unlock(&dev_priv->rps.hw_lock);
3604 }
3605
3606 void valleyview_set_rps(struct drm_device *dev, u8 val)
3607 {
3608         struct drm_i915_private *dev_priv = dev->dev_private;
3609
3610         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3611         WARN_ON(val > dev_priv->rps.max_delay);
3612         WARN_ON(val < dev_priv->rps.min_delay);
3613
3614         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3615                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3616                          dev_priv->rps.cur_delay,
3617                          vlv_gpu_freq(dev_priv, val), val);
3618
3619         if (val == dev_priv->rps.cur_delay)
3620                 return;
3621
3622         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3623
3624         dev_priv->rps.cur_delay = val;
3625
3626         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3627 }
3628
3629 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3630 {
3631         struct drm_i915_private *dev_priv = dev->dev_private;
3632
3633         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3634         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3635         /* Complete PM interrupt masking here doesn't race with the rps work
3636          * item again unmasking PM interrupts because that is using a different
3637          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3638          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3639
3640         spin_lock_irq(&dev_priv->irq_lock);
3641         dev_priv->rps.pm_iir = 0;
3642         spin_unlock_irq(&dev_priv->irq_lock);
3643
3644         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3645 }
3646
3647 static void gen6_disable_rps(struct drm_device *dev)
3648 {
3649         struct drm_i915_private *dev_priv = dev->dev_private;
3650
3651         I915_WRITE(GEN6_RC_CONTROL, 0);
3652         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3653
3654         gen6_disable_rps_interrupts(dev);
3655 }
3656
3657 static void valleyview_disable_rps(struct drm_device *dev)
3658 {
3659         struct drm_i915_private *dev_priv = dev->dev_private;
3660
3661         I915_WRITE(GEN6_RC_CONTROL, 0);
3662
3663         gen6_disable_rps_interrupts(dev);
3664
3665         if (dev_priv->vlv_pctx) {
3666                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3667                 dev_priv->vlv_pctx = NULL;
3668         }
3669 }
3670
3671 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3672 {
3673         if (IS_GEN6(dev))
3674                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3675
3676         if (IS_HASWELL(dev))
3677                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3678
3679         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3680                         (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3681                         (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3682                         (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3683 }
3684
3685 int intel_enable_rc6(const struct drm_device *dev)
3686 {
3687         /* No RC6 before Ironlake */
3688         if (INTEL_INFO(dev)->gen < 5)
3689                 return 0;
3690
3691         /* Respect the kernel parameter if it is set */
3692         if (i915_enable_rc6 >= 0)
3693                 return i915_enable_rc6;
3694
3695         /* Disable RC6 on Ironlake */
3696         if (INTEL_INFO(dev)->gen == 5)
3697                 return 0;
3698
3699         if (IS_HASWELL(dev))
3700                 return INTEL_RC6_ENABLE;
3701
3702         /* snb/ivb have more than one rc6 state. */
3703         if (INTEL_INFO(dev)->gen == 6)
3704                 return INTEL_RC6_ENABLE;
3705
3706         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3707 }
3708
3709 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3710 {
3711         struct drm_i915_private *dev_priv = dev->dev_private;
3712         u32 enabled_intrs;
3713
3714         spin_lock_irq(&dev_priv->irq_lock);
3715         WARN_ON(dev_priv->rps.pm_iir);
3716         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3717         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3718         spin_unlock_irq(&dev_priv->irq_lock);
3719
3720         /* only unmask PM interrupts we need. Mask all others. */
3721         enabled_intrs = GEN6_PM_RPS_EVENTS;
3722
3723         /* IVB and SNB hard hangs on looping batchbuffer
3724          * if GEN6_PM_UP_EI_EXPIRED is masked.
3725          */
3726         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3727                 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3728
3729         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3730 }
3731
3732 static void gen8_enable_rps(struct drm_device *dev)
3733 {
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735         struct intel_ring_buffer *ring;
3736         uint32_t rc6_mask = 0, rp_state_cap;
3737         int unused;
3738
3739         /* 1a: Software RC state - RC0 */
3740         I915_WRITE(GEN6_RC_STATE, 0);
3741
3742         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3743          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3744         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3745
3746         /* 2a: Disable RC states. */
3747         I915_WRITE(GEN6_RC_CONTROL, 0);
3748
3749         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3750
3751         /* 2b: Program RC6 thresholds.*/
3752         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3753         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3754         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3755         for_each_ring(ring, dev_priv, unused)
3756                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3757         I915_WRITE(GEN6_RC_SLEEP, 0);
3758         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3759
3760         /* 3: Enable RC6 */
3761         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3762                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3763         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3764         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3765                         GEN6_RC_CTL_EI_MODE(1) |
3766                         rc6_mask);
3767
3768         /* 4 Program defaults and thresholds for RPS*/
3769         I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3770         I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3771         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3772         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3773
3774         /* Docs recommend 900MHz, and 300 MHz respectively */
3775         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3776                    dev_priv->rps.max_delay << 24 |
3777                    dev_priv->rps.min_delay << 16);
3778
3779         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3780         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3781         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3782         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3783
3784         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3785
3786         /* 5: Enable RPS */
3787         I915_WRITE(GEN6_RP_CONTROL,
3788                    GEN6_RP_MEDIA_TURBO |
3789                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3790                    GEN6_RP_MEDIA_IS_GFX |
3791                    GEN6_RP_ENABLE |
3792                    GEN6_RP_UP_BUSY_AVG |
3793                    GEN6_RP_DOWN_IDLE_AVG);
3794
3795         /* 6: Ring frequency + overclocking (our driver does this later */
3796
3797         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3798
3799         gen6_enable_rps_interrupts(dev);
3800
3801         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3802 }
3803
3804 static void gen6_enable_rps(struct drm_device *dev)
3805 {
3806         struct drm_i915_private *dev_priv = dev->dev_private;
3807         struct intel_ring_buffer *ring;
3808         u32 rp_state_cap;
3809         u32 gt_perf_status;
3810         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3811         u32 gtfifodbg;
3812         int rc6_mode;
3813         int i, ret;
3814
3815         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3816
3817         /* Here begins a magic sequence of register writes to enable
3818          * auto-downclocking.
3819          *
3820          * Perhaps there might be some value in exposing these to
3821          * userspace...
3822          */
3823         I915_WRITE(GEN6_RC_STATE, 0);
3824
3825         /* Clear the DBG now so we don't confuse earlier errors */
3826         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3827                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3828                 I915_WRITE(GTFIFODBG, gtfifodbg);
3829         }
3830
3831         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3832
3833         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3834         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3835
3836         /* In units of 50MHz */
3837         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3838         dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3839         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
3840         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
3841         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3842         dev_priv->rps.cur_delay = 0;
3843
3844         /* disable the counters and set deterministic thresholds */
3845         I915_WRITE(GEN6_RC_CONTROL, 0);
3846
3847         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3848         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3849         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3850         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3851         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3852
3853         for_each_ring(ring, dev_priv, i)
3854                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3855
3856         I915_WRITE(GEN6_RC_SLEEP, 0);
3857         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3858         if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3859                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3860         else
3861                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3862         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3863         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3864
3865         /* Check if we are enabling RC6 */
3866         rc6_mode = intel_enable_rc6(dev_priv->dev);
3867         if (rc6_mode & INTEL_RC6_ENABLE)
3868                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3869
3870         /* We don't use those on Haswell */
3871         if (!IS_HASWELL(dev)) {
3872                 if (rc6_mode & INTEL_RC6p_ENABLE)
3873                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3874
3875                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3876                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3877         }
3878
3879         intel_print_rc6_info(dev, rc6_mask);
3880
3881         I915_WRITE(GEN6_RC_CONTROL,
3882                    rc6_mask |
3883                    GEN6_RC_CTL_EI_MODE(1) |
3884                    GEN6_RC_CTL_HW_ENABLE);
3885
3886         /* Power down if completely idle for over 50ms */
3887         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3888         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3889
3890         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3891         if (!ret) {
3892                 pcu_mbox = 0;
3893                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3894                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3895                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3896                                          (dev_priv->rps.max_delay & 0xff) * 50,
3897                                          (pcu_mbox & 0xff) * 50);
3898                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3899                 }
3900         } else {
3901                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3902         }
3903
3904         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3905         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3906
3907         gen6_enable_rps_interrupts(dev);
3908
3909         rc6vids = 0;
3910         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3911         if (IS_GEN6(dev) && ret) {
3912                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3913         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3914                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3915                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3916                 rc6vids &= 0xffff00;
3917                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3918                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3919                 if (ret)
3920                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3921         }
3922
3923         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3924 }
3925
3926 void gen6_update_ring_freq(struct drm_device *dev)
3927 {
3928         struct drm_i915_private *dev_priv = dev->dev_private;
3929         int min_freq = 15;
3930         unsigned int gpu_freq;
3931         unsigned int max_ia_freq, min_ring_freq;
3932         int scaling_factor = 180;
3933         struct cpufreq_policy *policy;
3934
3935         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3936
3937         policy = cpufreq_cpu_get(0);
3938         if (policy) {
3939                 max_ia_freq = policy->cpuinfo.max_freq;
3940                 cpufreq_cpu_put(policy);
3941         } else {
3942                 /*
3943                  * Default to measured freq if none found, PCU will ensure we
3944                  * don't go over
3945                  */
3946                 max_ia_freq = tsc_khz;
3947         }
3948
3949         /* Convert from kHz to MHz */
3950         max_ia_freq /= 1000;
3951
3952         min_ring_freq = I915_READ(DCLK) & 0xf;
3953         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3954         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3955
3956         /*
3957          * For each potential GPU frequency, load a ring frequency we'd like
3958          * to use for memory access.  We do this by specifying the IA frequency
3959          * the PCU should use as a reference to determine the ring frequency.
3960          */
3961         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3962              gpu_freq--) {
3963                 int diff = dev_priv->rps.max_delay - gpu_freq;
3964                 unsigned int ia_freq = 0, ring_freq = 0;
3965
3966                 if (INTEL_INFO(dev)->gen >= 8) {
3967                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3968                         ring_freq = max(min_ring_freq, gpu_freq);
3969                 } else if (IS_HASWELL(dev)) {
3970                         ring_freq = mult_frac(gpu_freq, 5, 4);
3971                         ring_freq = max(min_ring_freq, ring_freq);
3972                         /* leave ia_freq as the default, chosen by cpufreq */
3973                 } else {
3974                         /* On older processors, there is no separate ring
3975                          * clock domain, so in order to boost the bandwidth
3976                          * of the ring, we need to upclock the CPU (ia_freq).
3977                          *
3978                          * For GPU frequencies less than 750MHz,
3979                          * just use the lowest ring freq.
3980                          */
3981                         if (gpu_freq < min_freq)
3982                                 ia_freq = 800;
3983                         else
3984                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3985                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3986                 }
3987
3988                 sandybridge_pcode_write(dev_priv,
3989                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3990                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3991                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3992                                         gpu_freq);
3993         }
3994 }
3995
3996 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3997 {
3998         u32 val, rp0;
3999
4000         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4001
4002         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4003         /* Clamp to max */
4004         rp0 = min_t(u32, rp0, 0xea);
4005
4006         return rp0;
4007 }
4008
4009 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4010 {
4011         u32 val, rpe;
4012
4013         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4014         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4015         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4016         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4017
4018         return rpe;
4019 }
4020
4021 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4022 {
4023         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4024 }
4025
4026 static void valleyview_setup_pctx(struct drm_device *dev)
4027 {
4028         struct drm_i915_private *dev_priv = dev->dev_private;
4029         struct drm_i915_gem_object *pctx;
4030         unsigned long pctx_paddr;
4031         u32 pcbr;
4032         int pctx_size = 24*1024;
4033
4034         pcbr = I915_READ(VLV_PCBR);
4035         if (pcbr) {
4036                 /* BIOS set it up already, grab the pre-alloc'd space */
4037                 int pcbr_offset;
4038
4039                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4040                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4041                                                                       pcbr_offset,
4042                                                                       I915_GTT_OFFSET_NONE,
4043                                                                       pctx_size);
4044                 goto out;
4045         }
4046
4047         /*
4048          * From the Gunit register HAS:
4049          * The Gfx driver is expected to program this register and ensure
4050          * proper allocation within Gfx stolen memory.  For example, this
4051          * register should be programmed such than the PCBR range does not
4052          * overlap with other ranges, such as the frame buffer, protected
4053          * memory, or any other relevant ranges.
4054          */
4055         pctx = i915_gem_object_create_stolen(dev, pctx_size);
4056         if (!pctx) {
4057                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4058                 return;
4059         }
4060
4061         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4062         I915_WRITE(VLV_PCBR, pctx_paddr);
4063
4064 out:
4065         dev_priv->vlv_pctx = pctx;
4066 }
4067
4068 static void valleyview_enable_rps(struct drm_device *dev)
4069 {
4070         struct drm_i915_private *dev_priv = dev->dev_private;
4071         struct intel_ring_buffer *ring;
4072         u32 gtfifodbg, val, rc6_mode = 0;
4073         int i;
4074
4075         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4076
4077         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4078                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4079                                  gtfifodbg);
4080                 I915_WRITE(GTFIFODBG, gtfifodbg);
4081         }
4082
4083         valleyview_setup_pctx(dev);
4084
4085         /* If VLV, Forcewake all wells, else re-direct to regular path */
4086         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4087
4088         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4089         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4090         I915_WRITE(GEN6_RP_UP_EI, 66000);
4091         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4092
4093         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4094
4095         I915_WRITE(GEN6_RP_CONTROL,
4096                    GEN6_RP_MEDIA_TURBO |
4097                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4098                    GEN6_RP_MEDIA_IS_GFX |
4099                    GEN6_RP_ENABLE |
4100                    GEN6_RP_UP_BUSY_AVG |
4101                    GEN6_RP_DOWN_IDLE_CONT);
4102
4103         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4104         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4105         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4106
4107         for_each_ring(ring, dev_priv, i)
4108                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4109
4110         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
4111
4112         /* allows RC6 residency counter to work */
4113         I915_WRITE(VLV_COUNTER_CONTROL,
4114                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4115                                       VLV_MEDIA_RC6_COUNT_EN |
4116                                       VLV_RENDER_RC6_COUNT_EN));
4117         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4118                 rc6_mode = GEN7_RC_CTL_TO_MODE;
4119
4120         intel_print_rc6_info(dev, rc6_mode);
4121
4122         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4123
4124         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4125
4126         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4127         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4128
4129         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4130         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4131                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
4132                          dev_priv->rps.cur_delay);
4133
4134         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4135         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4136         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4137                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
4138                          dev_priv->rps.max_delay);
4139
4140         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4141         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4142                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4143                          dev_priv->rps.rpe_delay);
4144
4145         dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4146         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4147                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
4148                          dev_priv->rps.min_delay);
4149
4150         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4151                          vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4152                          dev_priv->rps.rpe_delay);
4153
4154         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4155
4156         gen6_enable_rps_interrupts(dev);
4157
4158         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4159 }
4160
4161 void ironlake_teardown_rc6(struct drm_device *dev)
4162 {
4163         struct drm_i915_private *dev_priv = dev->dev_private;
4164
4165         if (dev_priv->ips.renderctx) {
4166                 i915_gem_object_unpin(dev_priv->ips.renderctx);
4167                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4168                 dev_priv->ips.renderctx = NULL;
4169         }
4170
4171         if (dev_priv->ips.pwrctx) {
4172                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4173                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4174                 dev_priv->ips.pwrctx = NULL;
4175         }
4176 }
4177
4178 static void ironlake_disable_rc6(struct drm_device *dev)
4179 {
4180         struct drm_i915_private *dev_priv = dev->dev_private;
4181
4182         if (I915_READ(PWRCTXA)) {
4183                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4184                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4185                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4186                          50);
4187
4188                 I915_WRITE(PWRCTXA, 0);
4189                 POSTING_READ(PWRCTXA);
4190
4191                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4192                 POSTING_READ(RSTDBYCTL);
4193         }
4194 }
4195
4196 static int ironlake_setup_rc6(struct drm_device *dev)
4197 {
4198         struct drm_i915_private *dev_priv = dev->dev_private;
4199
4200         if (dev_priv->ips.renderctx == NULL)
4201                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4202         if (!dev_priv->ips.renderctx)
4203                 return -ENOMEM;
4204
4205         if (dev_priv->ips.pwrctx == NULL)
4206                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4207         if (!dev_priv->ips.pwrctx) {
4208                 ironlake_teardown_rc6(dev);
4209                 return -ENOMEM;
4210         }
4211
4212         return 0;
4213 }
4214
4215 static void ironlake_enable_rc6(struct drm_device *dev)
4216 {
4217         struct drm_i915_private *dev_priv = dev->dev_private;
4218         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4219         bool was_interruptible;
4220         int ret;
4221
4222         /* rc6 disabled by default due to repeated reports of hanging during
4223          * boot and resume.
4224          */
4225         if (!intel_enable_rc6(dev))
4226                 return;
4227
4228         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4229
4230         ret = ironlake_setup_rc6(dev);
4231         if (ret)
4232                 return;
4233
4234         was_interruptible = dev_priv->mm.interruptible;
4235         dev_priv->mm.interruptible = false;
4236
4237         /*
4238          * GPU can automatically power down the render unit if given a page
4239          * to save state.
4240          */
4241         ret = intel_ring_begin(ring, 6);
4242         if (ret) {
4243                 ironlake_teardown_rc6(dev);
4244                 dev_priv->mm.interruptible = was_interruptible;
4245                 return;
4246         }
4247
4248         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4249         intel_ring_emit(ring, MI_SET_CONTEXT);
4250         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4251                         MI_MM_SPACE_GTT |
4252                         MI_SAVE_EXT_STATE_EN |
4253                         MI_RESTORE_EXT_STATE_EN |
4254                         MI_RESTORE_INHIBIT);
4255         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4256         intel_ring_emit(ring, MI_NOOP);
4257         intel_ring_emit(ring, MI_FLUSH);
4258         intel_ring_advance(ring);
4259
4260         /*
4261          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4262          * does an implicit flush, combined with MI_FLUSH above, it should be
4263          * safe to assume that renderctx is valid
4264          */
4265         ret = intel_ring_idle(ring);
4266         dev_priv->mm.interruptible = was_interruptible;
4267         if (ret) {
4268                 DRM_ERROR("failed to enable ironlake power savings\n");
4269                 ironlake_teardown_rc6(dev);
4270                 return;
4271         }
4272
4273         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4274         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4275
4276         intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
4277 }
4278
4279 static unsigned long intel_pxfreq(u32 vidfreq)
4280 {
4281         unsigned long freq;
4282         int div = (vidfreq & 0x3f0000) >> 16;
4283         int post = (vidfreq & 0x3000) >> 12;
4284         int pre = (vidfreq & 0x7);
4285
4286         if (!pre)
4287                 return 0;
4288
4289         freq = ((div * 133333) / ((1<<post) * pre));
4290
4291         return freq;
4292 }
4293
4294 static const struct cparams {
4295         u16 i;
4296         u16 t;
4297         u16 m;
4298         u16 c;
4299 } cparams[] = {
4300         { 1, 1333, 301, 28664 },
4301         { 1, 1066, 294, 24460 },
4302         { 1, 800, 294, 25192 },
4303         { 0, 1333, 276, 27605 },
4304         { 0, 1066, 276, 27605 },
4305         { 0, 800, 231, 23784 },
4306 };
4307
4308 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4309 {
4310         u64 total_count, diff, ret;
4311         u32 count1, count2, count3, m = 0, c = 0;
4312         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4313         int i;
4314
4315         assert_spin_locked(&mchdev_lock);
4316
4317         diff1 = now - dev_priv->ips.last_time1;
4318
4319         /* Prevent division-by-zero if we are asking too fast.
4320          * Also, we don't get interesting results if we are polling
4321          * faster than once in 10ms, so just return the saved value
4322          * in such cases.
4323          */
4324         if (diff1 <= 10)
4325                 return dev_priv->ips.chipset_power;
4326
4327         count1 = I915_READ(DMIEC);
4328         count2 = I915_READ(DDREC);
4329         count3 = I915_READ(CSIEC);
4330
4331         total_count = count1 + count2 + count3;
4332
4333         /* FIXME: handle per-counter overflow */
4334         if (total_count < dev_priv->ips.last_count1) {
4335                 diff = ~0UL - dev_priv->ips.last_count1;
4336                 diff += total_count;
4337         } else {
4338                 diff = total_count - dev_priv->ips.last_count1;
4339         }
4340
4341         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4342                 if (cparams[i].i == dev_priv->ips.c_m &&
4343                     cparams[i].t == dev_priv->ips.r_t) {
4344                         m = cparams[i].m;
4345                         c = cparams[i].c;
4346                         break;
4347                 }
4348         }
4349
4350         diff = div_u64(diff, diff1);
4351         ret = ((m * diff) + c);
4352         ret = div_u64(ret, 10);
4353
4354         dev_priv->ips.last_count1 = total_count;
4355         dev_priv->ips.last_time1 = now;
4356
4357         dev_priv->ips.chipset_power = ret;
4358
4359         return ret;
4360 }
4361
4362 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4363 {
4364         unsigned long val;
4365
4366         if (dev_priv->info->gen != 5)
4367                 return 0;
4368
4369         spin_lock_irq(&mchdev_lock);
4370
4371         val = __i915_chipset_val(dev_priv);
4372
4373         spin_unlock_irq(&mchdev_lock);
4374
4375         return val;
4376 }
4377
4378 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4379 {
4380         unsigned long m, x, b;
4381         u32 tsfs;
4382
4383         tsfs = I915_READ(TSFS);
4384
4385         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4386         x = I915_READ8(TR1);
4387
4388         b = tsfs & TSFS_INTR_MASK;
4389
4390         return ((m * x) / 127) - b;
4391 }
4392
4393 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4394 {
4395         static const struct v_table {
4396                 u16 vd; /* in .1 mil */
4397                 u16 vm; /* in .1 mil */
4398         } v_table[] = {
4399                 { 0, 0, },
4400                 { 375, 0, },
4401                 { 500, 0, },
4402                 { 625, 0, },
4403                 { 750, 0, },
4404                 { 875, 0, },
4405                 { 1000, 0, },
4406                 { 1125, 0, },
4407                 { 4125, 3000, },
4408                 { 4125, 3000, },
4409                 { 4125, 3000, },
4410                 { 4125, 3000, },
4411                 { 4125, 3000, },
4412                 { 4125, 3000, },
4413                 { 4125, 3000, },
4414                 { 4125, 3000, },
4415                 { 4125, 3000, },
4416                 { 4125, 3000, },
4417                 { 4125, 3000, },
4418                 { 4125, 3000, },
4419                 { 4125, 3000, },
4420                 { 4125, 3000, },
4421                 { 4125, 3000, },
4422                 { 4125, 3000, },
4423                 { 4125, 3000, },
4424                 { 4125, 3000, },
4425                 { 4125, 3000, },
4426                 { 4125, 3000, },
4427                 { 4125, 3000, },
4428                 { 4125, 3000, },
4429                 { 4125, 3000, },
4430                 { 4125, 3000, },
4431                 { 4250, 3125, },
4432                 { 4375, 3250, },
4433                 { 4500, 3375, },
4434                 { 4625, 3500, },
4435                 { 4750, 3625, },
4436                 { 4875, 3750, },
4437                 { 5000, 3875, },
4438                 { 5125, 4000, },
4439                 { 5250, 4125, },
4440                 { 5375, 4250, },
4441                 { 5500, 4375, },
4442                 { 5625, 4500, },
4443                 { 5750, 4625, },
4444                 { 5875, 4750, },
4445                 { 6000, 4875, },
4446                 { 6125, 5000, },
4447                 { 6250, 5125, },
4448                 { 6375, 5250, },
4449                 { 6500, 5375, },
4450                 { 6625, 5500, },
4451                 { 6750, 5625, },
4452                 { 6875, 5750, },
4453                 { 7000, 5875, },
4454                 { 7125, 6000, },
4455                 { 7250, 6125, },
4456                 { 7375, 6250, },
4457                 { 7500, 6375, },
4458                 { 7625, 6500, },
4459                 { 7750, 6625, },
4460                 { 7875, 6750, },
4461                 { 8000, 6875, },
4462                 { 8125, 7000, },
4463                 { 8250, 7125, },
4464                 { 8375, 7250, },
4465                 { 8500, 7375, },
4466                 { 8625, 7500, },
4467                 { 8750, 7625, },
4468                 { 8875, 7750, },
4469                 { 9000, 7875, },
4470                 { 9125, 8000, },
4471                 { 9250, 8125, },
4472                 { 9375, 8250, },
4473                 { 9500, 8375, },
4474                 { 9625, 8500, },
4475                 { 9750, 8625, },
4476                 { 9875, 8750, },
4477                 { 10000, 8875, },
4478                 { 10125, 9000, },
4479                 { 10250, 9125, },
4480                 { 10375, 9250, },
4481                 { 10500, 9375, },
4482                 { 10625, 9500, },
4483                 { 10750, 9625, },
4484                 { 10875, 9750, },
4485                 { 11000, 9875, },
4486                 { 11125, 10000, },
4487                 { 11250, 10125, },
4488                 { 11375, 10250, },
4489                 { 11500, 10375, },
4490                 { 11625, 10500, },
4491                 { 11750, 10625, },
4492                 { 11875, 10750, },
4493                 { 12000, 10875, },
4494                 { 12125, 11000, },
4495                 { 12250, 11125, },
4496                 { 12375, 11250, },
4497                 { 12500, 11375, },
4498                 { 12625, 11500, },
4499                 { 12750, 11625, },
4500                 { 12875, 11750, },
4501                 { 13000, 11875, },
4502                 { 13125, 12000, },
4503                 { 13250, 12125, },
4504                 { 13375, 12250, },
4505                 { 13500, 12375, },
4506                 { 13625, 12500, },
4507                 { 13750, 12625, },
4508                 { 13875, 12750, },
4509                 { 14000, 12875, },
4510                 { 14125, 13000, },
4511                 { 14250, 13125, },
4512                 { 14375, 13250, },
4513                 { 14500, 13375, },
4514                 { 14625, 13500, },
4515                 { 14750, 13625, },
4516                 { 14875, 13750, },
4517                 { 15000, 13875, },
4518                 { 15125, 14000, },
4519                 { 15250, 14125, },
4520                 { 15375, 14250, },
4521                 { 15500, 14375, },
4522                 { 15625, 14500, },
4523                 { 15750, 14625, },
4524                 { 15875, 14750, },
4525                 { 16000, 14875, },
4526                 { 16125, 15000, },
4527         };
4528         if (dev_priv->info->is_mobile)
4529                 return v_table[pxvid].vm;
4530         else
4531                 return v_table[pxvid].vd;
4532 }
4533
4534 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4535 {
4536         struct timespec now, diff1;
4537         u64 diff;
4538         unsigned long diffms;
4539         u32 count;
4540
4541         assert_spin_locked(&mchdev_lock);
4542
4543         getrawmonotonic(&now);
4544         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4545
4546         /* Don't divide by 0 */
4547         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4548         if (!diffms)
4549                 return;
4550
4551         count = I915_READ(GFXEC);
4552
4553         if (count < dev_priv->ips.last_count2) {
4554                 diff = ~0UL - dev_priv->ips.last_count2;
4555                 diff += count;
4556         } else {
4557                 diff = count - dev_priv->ips.last_count2;
4558         }
4559
4560         dev_priv->ips.last_count2 = count;
4561         dev_priv->ips.last_time2 = now;
4562
4563         /* More magic constants... */
4564         diff = diff * 1181;
4565         diff = div_u64(diff, diffms * 10);
4566         dev_priv->ips.gfx_power = diff;
4567 }
4568
4569 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4570 {
4571         if (dev_priv->info->gen != 5)
4572                 return;
4573
4574         spin_lock_irq(&mchdev_lock);
4575
4576         __i915_update_gfx_val(dev_priv);
4577
4578         spin_unlock_irq(&mchdev_lock);
4579 }
4580
4581 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4582 {
4583         unsigned long t, corr, state1, corr2, state2;
4584         u32 pxvid, ext_v;
4585
4586         assert_spin_locked(&mchdev_lock);
4587
4588         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4589         pxvid = (pxvid >> 24) & 0x7f;
4590         ext_v = pvid_to_extvid(dev_priv, pxvid);
4591
4592         state1 = ext_v;
4593
4594         t = i915_mch_val(dev_priv);
4595
4596         /* Revel in the empirically derived constants */
4597
4598         /* Correction factor in 1/100000 units */
4599         if (t > 80)
4600                 corr = ((t * 2349) + 135940);
4601         else if (t >= 50)
4602                 corr = ((t * 964) + 29317);
4603         else /* < 50 */
4604                 corr = ((t * 301) + 1004);
4605
4606         corr = corr * ((150142 * state1) / 10000 - 78642);
4607         corr /= 100000;
4608         corr2 = (corr * dev_priv->ips.corr);
4609
4610         state2 = (corr2 * state1) / 10000;
4611         state2 /= 100; /* convert to mW */
4612
4613         __i915_update_gfx_val(dev_priv);
4614
4615         return dev_priv->ips.gfx_power + state2;
4616 }
4617
4618 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4619 {
4620         unsigned long val;
4621
4622         if (dev_priv->info->gen != 5)
4623                 return 0;
4624
4625         spin_lock_irq(&mchdev_lock);
4626
4627         val = __i915_gfx_val(dev_priv);
4628
4629         spin_unlock_irq(&mchdev_lock);
4630
4631         return val;
4632 }
4633
4634 /**
4635  * i915_read_mch_val - return value for IPS use
4636  *
4637  * Calculate and return a value for the IPS driver to use when deciding whether
4638  * we have thermal and power headroom to increase CPU or GPU power budget.
4639  */
4640 unsigned long i915_read_mch_val(void)
4641 {
4642         struct drm_i915_private *dev_priv;
4643         unsigned long chipset_val, graphics_val, ret = 0;
4644
4645         spin_lock_irq(&mchdev_lock);
4646         if (!i915_mch_dev)
4647                 goto out_unlock;
4648         dev_priv = i915_mch_dev;
4649
4650         chipset_val = __i915_chipset_val(dev_priv);
4651         graphics_val = __i915_gfx_val(dev_priv);
4652
4653         ret = chipset_val + graphics_val;
4654
4655 out_unlock:
4656         spin_unlock_irq(&mchdev_lock);
4657
4658         return ret;
4659 }
4660 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4661
4662 /**
4663  * i915_gpu_raise - raise GPU frequency limit
4664  *
4665  * Raise the limit; IPS indicates we have thermal headroom.
4666  */
4667 bool i915_gpu_raise(void)
4668 {
4669         struct drm_i915_private *dev_priv;
4670         bool ret = true;
4671
4672         spin_lock_irq(&mchdev_lock);
4673         if (!i915_mch_dev) {
4674                 ret = false;
4675                 goto out_unlock;
4676         }
4677         dev_priv = i915_mch_dev;
4678
4679         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4680                 dev_priv->ips.max_delay--;
4681
4682 out_unlock:
4683         spin_unlock_irq(&mchdev_lock);
4684
4685         return ret;
4686 }
4687 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4688
4689 /**
4690  * i915_gpu_lower - lower GPU frequency limit
4691  *
4692  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4693  * frequency maximum.
4694  */
4695 bool i915_gpu_lower(void)
4696 {
4697         struct drm_i915_private *dev_priv;
4698         bool ret = true;
4699
4700         spin_lock_irq(&mchdev_lock);
4701         if (!i915_mch_dev) {
4702                 ret = false;
4703                 goto out_unlock;
4704         }
4705         dev_priv = i915_mch_dev;
4706
4707         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4708                 dev_priv->ips.max_delay++;
4709
4710 out_unlock:
4711         spin_unlock_irq(&mchdev_lock);
4712
4713         return ret;
4714 }
4715 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4716
4717 /**
4718  * i915_gpu_busy - indicate GPU business to IPS
4719  *
4720  * Tell the IPS driver whether or not the GPU is busy.
4721  */
4722 bool i915_gpu_busy(void)
4723 {
4724         struct drm_i915_private *dev_priv;
4725         struct intel_ring_buffer *ring;
4726         bool ret = false;
4727         int i;
4728
4729         spin_lock_irq(&mchdev_lock);
4730         if (!i915_mch_dev)
4731                 goto out_unlock;
4732         dev_priv = i915_mch_dev;
4733
4734         for_each_ring(ring, dev_priv, i)
4735                 ret |= !list_empty(&ring->request_list);
4736
4737 out_unlock:
4738         spin_unlock_irq(&mchdev_lock);
4739
4740         return ret;
4741 }
4742 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4743
4744 /**
4745  * i915_gpu_turbo_disable - disable graphics turbo
4746  *
4747  * Disable graphics turbo by resetting the max frequency and setting the
4748  * current frequency to the default.
4749  */
4750 bool i915_gpu_turbo_disable(void)
4751 {
4752         struct drm_i915_private *dev_priv;
4753         bool ret = true;
4754
4755         spin_lock_irq(&mchdev_lock);
4756         if (!i915_mch_dev) {
4757                 ret = false;
4758                 goto out_unlock;
4759         }
4760         dev_priv = i915_mch_dev;
4761
4762         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4763
4764         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4765                 ret = false;
4766
4767 out_unlock:
4768         spin_unlock_irq(&mchdev_lock);
4769
4770         return ret;
4771 }
4772 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4773
4774 /**
4775  * Tells the intel_ips driver that the i915 driver is now loaded, if
4776  * IPS got loaded first.
4777  *
4778  * This awkward dance is so that neither module has to depend on the
4779  * other in order for IPS to do the appropriate communication of
4780  * GPU turbo limits to i915.
4781  */
4782 static void
4783 ips_ping_for_i915_load(void)
4784 {
4785         void (*link)(void);
4786
4787         link = symbol_get(ips_link_to_i915_driver);
4788         if (link) {
4789                 link();
4790                 symbol_put(ips_link_to_i915_driver);
4791         }
4792 }
4793
4794 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4795 {
4796         /* We only register the i915 ips part with intel-ips once everything is
4797          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4798         spin_lock_irq(&mchdev_lock);
4799         i915_mch_dev = dev_priv;
4800         spin_unlock_irq(&mchdev_lock);
4801
4802         ips_ping_for_i915_load();
4803 }
4804
4805 void intel_gpu_ips_teardown(void)
4806 {
4807         spin_lock_irq(&mchdev_lock);
4808         i915_mch_dev = NULL;
4809         spin_unlock_irq(&mchdev_lock);
4810 }
4811 static void intel_init_emon(struct drm_device *dev)
4812 {
4813         struct drm_i915_private *dev_priv = dev->dev_private;
4814         u32 lcfuse;
4815         u8 pxw[16];
4816         int i;
4817
4818         /* Disable to program */
4819         I915_WRITE(ECR, 0);
4820         POSTING_READ(ECR);
4821
4822         /* Program energy weights for various events */
4823         I915_WRITE(SDEW, 0x15040d00);
4824         I915_WRITE(CSIEW0, 0x007f0000);
4825         I915_WRITE(CSIEW1, 0x1e220004);
4826         I915_WRITE(CSIEW2, 0x04000004);
4827
4828         for (i = 0; i < 5; i++)
4829                 I915_WRITE(PEW + (i * 4), 0);
4830         for (i = 0; i < 3; i++)
4831                 I915_WRITE(DEW + (i * 4), 0);
4832
4833         /* Program P-state weights to account for frequency power adjustment */
4834         for (i = 0; i < 16; i++) {
4835                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4836                 unsigned long freq = intel_pxfreq(pxvidfreq);
4837                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4838                         PXVFREQ_PX_SHIFT;
4839                 unsigned long val;
4840
4841                 val = vid * vid;
4842                 val *= (freq / 1000);
4843                 val *= 255;
4844                 val /= (127*127*900);
4845                 if (val > 0xff)
4846                         DRM_ERROR("bad pxval: %ld\n", val);
4847                 pxw[i] = val;
4848         }
4849         /* Render standby states get 0 weight */
4850         pxw[14] = 0;
4851         pxw[15] = 0;
4852
4853         for (i = 0; i < 4; i++) {
4854                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4855                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4856                 I915_WRITE(PXW + (i * 4), val);
4857         }
4858
4859         /* Adjust magic regs to magic values (more experimental results) */
4860         I915_WRITE(OGW0, 0);
4861         I915_WRITE(OGW1, 0);
4862         I915_WRITE(EG0, 0x00007f00);
4863         I915_WRITE(EG1, 0x0000000e);
4864         I915_WRITE(EG2, 0x000e0000);
4865         I915_WRITE(EG3, 0x68000300);
4866         I915_WRITE(EG4, 0x42000000);
4867         I915_WRITE(EG5, 0x00140031);
4868         I915_WRITE(EG6, 0);
4869         I915_WRITE(EG7, 0);
4870
4871         for (i = 0; i < 8; i++)
4872                 I915_WRITE(PXWL + (i * 4), 0);
4873
4874         /* Enable PMON + select events */
4875         I915_WRITE(ECR, 0x80000019);
4876
4877         lcfuse = I915_READ(LCFUSE02);
4878
4879         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4880 }
4881
4882 void intel_disable_gt_powersave(struct drm_device *dev)
4883 {
4884         struct drm_i915_private *dev_priv = dev->dev_private;
4885
4886         /* Interrupts should be disabled already to avoid re-arming. */
4887         WARN_ON(dev->irq_enabled);
4888
4889         if (IS_IRONLAKE_M(dev)) {
4890                 ironlake_disable_drps(dev);
4891                 ironlake_disable_rc6(dev);
4892         } else if (INTEL_INFO(dev)->gen >= 6) {
4893                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4894                 cancel_work_sync(&dev_priv->rps.work);
4895                 mutex_lock(&dev_priv->rps.hw_lock);
4896                 if (IS_VALLEYVIEW(dev))
4897                         valleyview_disable_rps(dev);
4898                 else
4899                         gen6_disable_rps(dev);
4900                 dev_priv->rps.enabled = false;
4901                 mutex_unlock(&dev_priv->rps.hw_lock);
4902         }
4903 }
4904
4905 static void intel_gen6_powersave_work(struct work_struct *work)
4906 {
4907         struct drm_i915_private *dev_priv =
4908                 container_of(work, struct drm_i915_private,
4909                              rps.delayed_resume_work.work);
4910         struct drm_device *dev = dev_priv->dev;
4911
4912         mutex_lock(&dev_priv->rps.hw_lock);
4913
4914         if (IS_VALLEYVIEW(dev)) {
4915                 valleyview_enable_rps(dev);
4916         } else if (IS_BROADWELL(dev)) {
4917                 gen8_enable_rps(dev);
4918                 gen6_update_ring_freq(dev);
4919         } else {
4920                 gen6_enable_rps(dev);
4921                 gen6_update_ring_freq(dev);
4922         }
4923         dev_priv->rps.enabled = true;
4924         mutex_unlock(&dev_priv->rps.hw_lock);
4925 }
4926
4927 void intel_enable_gt_powersave(struct drm_device *dev)
4928 {
4929         struct drm_i915_private *dev_priv = dev->dev_private;
4930
4931         if (IS_IRONLAKE_M(dev)) {
4932                 ironlake_enable_drps(dev);
4933                 ironlake_enable_rc6(dev);
4934                 intel_init_emon(dev);
4935         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4936                 /*
4937                  * PCU communication is slow and this doesn't need to be
4938                  * done at any specific time, so do this out of our fast path
4939                  * to make resume and init faster.
4940                  */
4941                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4942                                       round_jiffies_up_relative(HZ));
4943         }
4944 }
4945
4946 static void ibx_init_clock_gating(struct drm_device *dev)
4947 {
4948         struct drm_i915_private *dev_priv = dev->dev_private;
4949
4950         /*
4951          * On Ibex Peak and Cougar Point, we need to disable clock
4952          * gating for the panel power sequencer or it will fail to
4953          * start up when no ports are active.
4954          */
4955         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4956 }
4957
4958 static void g4x_disable_trickle_feed(struct drm_device *dev)
4959 {
4960         struct drm_i915_private *dev_priv = dev->dev_private;
4961         int pipe;
4962
4963         for_each_pipe(pipe) {
4964                 I915_WRITE(DSPCNTR(pipe),
4965                            I915_READ(DSPCNTR(pipe)) |
4966                            DISPPLANE_TRICKLE_FEED_DISABLE);
4967                 intel_flush_primary_plane(dev_priv, pipe);
4968         }
4969 }
4970
4971 static void ironlake_init_clock_gating(struct drm_device *dev)
4972 {
4973         struct drm_i915_private *dev_priv = dev->dev_private;
4974         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4975
4976         /*
4977          * Required for FBC
4978          * WaFbcDisableDpfcClockGating:ilk
4979          */
4980         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4981                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4982                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4983
4984         I915_WRITE(PCH_3DCGDIS0,
4985                    MARIUNIT_CLOCK_GATE_DISABLE |
4986                    SVSMUNIT_CLOCK_GATE_DISABLE);
4987         I915_WRITE(PCH_3DCGDIS1,
4988                    VFMUNIT_CLOCK_GATE_DISABLE);
4989
4990         /*
4991          * According to the spec the following bits should be set in
4992          * order to enable memory self-refresh
4993          * The bit 22/21 of 0x42004
4994          * The bit 5 of 0x42020
4995          * The bit 15 of 0x45000
4996          */
4997         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4998                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4999                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5000         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5001         I915_WRITE(DISP_ARB_CTL,
5002                    (I915_READ(DISP_ARB_CTL) |
5003                     DISP_FBC_WM_DIS));
5004         I915_WRITE(WM3_LP_ILK, 0);
5005         I915_WRITE(WM2_LP_ILK, 0);
5006         I915_WRITE(WM1_LP_ILK, 0);
5007
5008         /*
5009          * Based on the document from hardware guys the following bits
5010          * should be set unconditionally in order to enable FBC.
5011          * The bit 22 of 0x42000
5012          * The bit 22 of 0x42004
5013          * The bit 7,8,9 of 0x42020.
5014          */
5015         if (IS_IRONLAKE_M(dev)) {
5016                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5017                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5018                            I915_READ(ILK_DISPLAY_CHICKEN1) |
5019                            ILK_FBCQ_DIS);
5020                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5021                            I915_READ(ILK_DISPLAY_CHICKEN2) |
5022                            ILK_DPARB_GATE);
5023         }
5024
5025         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5026
5027         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5028                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5029                    ILK_ELPIN_409_SELECT);
5030         I915_WRITE(_3D_CHICKEN2,
5031                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5032                    _3D_CHICKEN2_WM_READ_PIPELINED);
5033
5034         /* WaDisableRenderCachePipelinedFlush:ilk */
5035         I915_WRITE(CACHE_MODE_0,
5036                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5037
5038         g4x_disable_trickle_feed(dev);
5039
5040         ibx_init_clock_gating(dev);
5041 }
5042
5043 static void cpt_init_clock_gating(struct drm_device *dev)
5044 {
5045         struct drm_i915_private *dev_priv = dev->dev_private;
5046         int pipe;
5047         uint32_t val;
5048
5049         /*
5050          * On Ibex Peak and Cougar Point, we need to disable clock
5051          * gating for the panel power sequencer or it will fail to
5052          * start up when no ports are active.
5053          */
5054         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5055                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5056                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
5057         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5058                    DPLS_EDP_PPS_FIX_DIS);
5059         /* The below fixes the weird display corruption, a few pixels shifted
5060          * downward, on (only) LVDS of some HP laptops with IVY.
5061          */
5062         for_each_pipe(pipe) {
5063                 val = I915_READ(TRANS_CHICKEN2(pipe));
5064                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5065                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5066                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5067                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5068                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5069                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5070                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5071                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5072         }
5073         /* WADP0ClockGatingDisable */
5074         for_each_pipe(pipe) {
5075                 I915_WRITE(TRANS_CHICKEN1(pipe),
5076                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5077         }
5078 }
5079
5080 static void gen6_check_mch_setup(struct drm_device *dev)
5081 {
5082         struct drm_i915_private *dev_priv = dev->dev_private;
5083         uint32_t tmp;
5084
5085         tmp = I915_READ(MCH_SSKPD);
5086         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5087                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5088                 DRM_INFO("This can cause pipe underruns and display issues.\n");
5089                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5090         }
5091 }
5092
5093 static void gen6_init_clock_gating(struct drm_device *dev)
5094 {
5095         struct drm_i915_private *dev_priv = dev->dev_private;
5096         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5097
5098         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5099
5100         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5101                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5102                    ILK_ELPIN_409_SELECT);
5103
5104         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5105         I915_WRITE(_3D_CHICKEN,
5106                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5107
5108         /* WaSetupGtModeTdRowDispatch:snb */
5109         if (IS_SNB_GT1(dev))
5110                 I915_WRITE(GEN6_GT_MODE,
5111                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5112
5113         I915_WRITE(WM3_LP_ILK, 0);
5114         I915_WRITE(WM2_LP_ILK, 0);
5115         I915_WRITE(WM1_LP_ILK, 0);
5116
5117         I915_WRITE(CACHE_MODE_0,
5118                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5119
5120         I915_WRITE(GEN6_UCGCTL1,
5121                    I915_READ(GEN6_UCGCTL1) |
5122                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5123                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5124
5125         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5126          * gating disable must be set.  Failure to set it results in
5127          * flickering pixels due to Z write ordering failures after
5128          * some amount of runtime in the Mesa "fire" demo, and Unigine
5129          * Sanctuary and Tropics, and apparently anything else with
5130          * alpha test or pixel discard.
5131          *
5132          * According to the spec, bit 11 (RCCUNIT) must also be set,
5133          * but we didn't debug actual testcases to find it out.
5134          *
5135          * Also apply WaDisableVDSUnitClockGating:snb and
5136          * WaDisableRCPBUnitClockGating:snb.
5137          */
5138         I915_WRITE(GEN6_UCGCTL2,
5139                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5140                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5141                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5142
5143         /* Bspec says we need to always set all mask bits. */
5144         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5145                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5146
5147         /*
5148          * According to the spec the following bits should be
5149          * set in order to enable memory self-refresh and fbc:
5150          * The bit21 and bit22 of 0x42000
5151          * The bit21 and bit22 of 0x42004
5152          * The bit5 and bit7 of 0x42020
5153          * The bit14 of 0x70180
5154          * The bit14 of 0x71180
5155          *
5156          * WaFbcAsynchFlipDisableFbcQueue:snb
5157          */
5158         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5159                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5160                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5161         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5162                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5163                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5164         I915_WRITE(ILK_DSPCLK_GATE_D,
5165                    I915_READ(ILK_DSPCLK_GATE_D) |
5166                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5167                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5168
5169         g4x_disable_trickle_feed(dev);
5170
5171         /* The default value should be 0x200 according to docs, but the two
5172          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5173         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5174         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5175
5176         cpt_init_clock_gating(dev);
5177
5178         gen6_check_mch_setup(dev);
5179 }
5180
5181 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5182 {
5183         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5184
5185         reg &= ~GEN7_FF_SCHED_MASK;
5186         reg |= GEN7_FF_TS_SCHED_HW;
5187         reg |= GEN7_FF_VS_SCHED_HW;
5188         reg |= GEN7_FF_DS_SCHED_HW;
5189
5190         if (IS_HASWELL(dev_priv->dev))
5191                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5192
5193         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5194 }
5195
5196 static void lpt_init_clock_gating(struct drm_device *dev)
5197 {
5198         struct drm_i915_private *dev_priv = dev->dev_private;
5199
5200         /*
5201          * TODO: this bit should only be enabled when really needed, then
5202          * disabled when not needed anymore in order to save power.
5203          */
5204         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5205                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5206                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5207                            PCH_LP_PARTITION_LEVEL_DISABLE);
5208
5209         /* WADPOClockGatingDisable:hsw */
5210         I915_WRITE(_TRANSA_CHICKEN1,
5211                    I915_READ(_TRANSA_CHICKEN1) |
5212                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5213 }
5214
5215 static void lpt_suspend_hw(struct drm_device *dev)
5216 {
5217         struct drm_i915_private *dev_priv = dev->dev_private;
5218
5219         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5220                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5221
5222                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5223                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5224         }
5225 }
5226
5227 static void gen8_init_clock_gating(struct drm_device *dev)
5228 {
5229         struct drm_i915_private *dev_priv = dev->dev_private;
5230         enum pipe i;
5231
5232         I915_WRITE(WM3_LP_ILK, 0);
5233         I915_WRITE(WM2_LP_ILK, 0);
5234         I915_WRITE(WM1_LP_ILK, 0);
5235
5236         /* FIXME(BDW): Check all the w/a, some might only apply to
5237          * pre-production hw. */
5238
5239         WARN(!i915_preliminary_hw_support,
5240              "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5241         I915_WRITE(HALF_SLICE_CHICKEN3,
5242                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5243         I915_WRITE(HALF_SLICE_CHICKEN3,
5244                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5245         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5246
5247         I915_WRITE(_3D_CHICKEN3,
5248                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5249
5250         I915_WRITE(COMMON_SLICE_CHICKEN2,
5251                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5252
5253         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5254                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5255
5256         /* WaSwitchSolVfFArbitrationPriority */
5257         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5258
5259         /* WaPsrDPAMaskVBlankInSRD */
5260         I915_WRITE(CHICKEN_PAR1_1,
5261                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5262
5263         /* WaPsrDPRSUnmaskVBlankInSRD */
5264         for_each_pipe(i) {
5265                 I915_WRITE(CHICKEN_PIPESL_1(i),
5266                            I915_READ(CHICKEN_PIPESL_1(i) |
5267                                      DPRS_MASK_VBLANK_SRD));
5268         }
5269 }
5270
5271 static void haswell_init_clock_gating(struct drm_device *dev)
5272 {
5273         struct drm_i915_private *dev_priv = dev->dev_private;
5274
5275         I915_WRITE(WM3_LP_ILK, 0);
5276         I915_WRITE(WM2_LP_ILK, 0);
5277         I915_WRITE(WM1_LP_ILK, 0);
5278
5279         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5280          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5281          */
5282         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5283
5284         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5285         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5286                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5287
5288         /* WaApplyL3ControlAndL3ChickenMode:hsw */
5289         I915_WRITE(GEN7_L3CNTLREG1,
5290                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5291         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5292                         GEN7_WA_L3_CHICKEN_MODE);
5293
5294         /* L3 caching of data atomics doesn't work -- disable it. */
5295         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5296         I915_WRITE(HSW_ROW_CHICKEN3,
5297                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5298
5299         /* This is required by WaCatErrorRejectionIssue:hsw */
5300         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5301                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5302                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5303
5304         /* WaVSRefCountFullforceMissDisable:hsw */
5305         gen7_setup_fixed_func_scheduler(dev_priv);
5306
5307         /* WaDisable4x2SubspanOptimization:hsw */
5308         I915_WRITE(CACHE_MODE_1,
5309                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5310
5311         /* WaSwitchSolVfFArbitrationPriority:hsw */
5312         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5313
5314         /* WaRsPkgCStateDisplayPMReq:hsw */
5315         I915_WRITE(CHICKEN_PAR1_1,
5316                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5317
5318         lpt_init_clock_gating(dev);
5319 }
5320
5321 static void ivybridge_init_clock_gating(struct drm_device *dev)
5322 {
5323         struct drm_i915_private *dev_priv = dev->dev_private;
5324         uint32_t snpcr;
5325
5326         I915_WRITE(WM3_LP_ILK, 0);
5327         I915_WRITE(WM2_LP_ILK, 0);
5328         I915_WRITE(WM1_LP_ILK, 0);
5329
5330         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5331
5332         /* WaDisableEarlyCull:ivb */
5333         I915_WRITE(_3D_CHICKEN3,
5334                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5335
5336         /* WaDisableBackToBackFlipFix:ivb */
5337         I915_WRITE(IVB_CHICKEN3,
5338                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5339                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5340
5341         /* WaDisablePSDDualDispatchEnable:ivb */
5342         if (IS_IVB_GT1(dev))
5343                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5344                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5345         else
5346                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5347                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5348
5349         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5350         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5351                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5352
5353         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5354         I915_WRITE(GEN7_L3CNTLREG1,
5355                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5356         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5357                    GEN7_WA_L3_CHICKEN_MODE);
5358         if (IS_IVB_GT1(dev))
5359                 I915_WRITE(GEN7_ROW_CHICKEN2,
5360                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5361         else
5362                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5363                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5364
5365
5366         /* WaForceL3Serialization:ivb */
5367         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5368                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5369
5370         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5371          * gating disable must be set.  Failure to set it results in
5372          * flickering pixels due to Z write ordering failures after
5373          * some amount of runtime in the Mesa "fire" demo, and Unigine
5374          * Sanctuary and Tropics, and apparently anything else with
5375          * alpha test or pixel discard.
5376          *
5377          * According to the spec, bit 11 (RCCUNIT) must also be set,
5378          * but we didn't debug actual testcases to find it out.
5379          *
5380          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5381          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5382          */
5383         I915_WRITE(GEN6_UCGCTL2,
5384                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5385                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5386
5387         /* This is required by WaCatErrorRejectionIssue:ivb */
5388         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5389                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5390                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5391
5392         g4x_disable_trickle_feed(dev);
5393
5394         /* WaVSRefCountFullforceMissDisable:ivb */
5395         gen7_setup_fixed_func_scheduler(dev_priv);
5396
5397         /* WaDisable4x2SubspanOptimization:ivb */
5398         I915_WRITE(CACHE_MODE_1,
5399                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5400
5401         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5402         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5403         snpcr |= GEN6_MBC_SNPCR_MED;
5404         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5405
5406         if (!HAS_PCH_NOP(dev))
5407                 cpt_init_clock_gating(dev);
5408
5409         gen6_check_mch_setup(dev);
5410 }
5411
5412 static void valleyview_init_clock_gating(struct drm_device *dev)
5413 {
5414         struct drm_i915_private *dev_priv = dev->dev_private;
5415         u32 val;
5416
5417         mutex_lock(&dev_priv->rps.hw_lock);
5418         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5419         mutex_unlock(&dev_priv->rps.hw_lock);
5420         switch ((val >> 6) & 3) {
5421         case 0:
5422                 dev_priv->mem_freq = 800;
5423                 break;
5424         case 1:
5425                 dev_priv->mem_freq = 1066;
5426                 break;
5427         case 2:
5428                 dev_priv->mem_freq = 1333;
5429                 break;
5430         case 3:
5431                 dev_priv->mem_freq = 1333;
5432                 break;
5433         }
5434         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5435
5436         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5437
5438         /* WaDisableEarlyCull:vlv */
5439         I915_WRITE(_3D_CHICKEN3,
5440                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5441
5442         /* WaDisableBackToBackFlipFix:vlv */
5443         I915_WRITE(IVB_CHICKEN3,
5444                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5445                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5446
5447         /* WaDisablePSDDualDispatchEnable:vlv */
5448         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5449                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5450                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5451
5452         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5453         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5454                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5455
5456         /* WaApplyL3ControlAndL3ChickenMode:vlv */
5457         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5458         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5459
5460         /* WaForceL3Serialization:vlv */
5461         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5462                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5463
5464         /* WaDisableDopClockGating:vlv */
5465         I915_WRITE(GEN7_ROW_CHICKEN2,
5466                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5467
5468         /* This is required by WaCatErrorRejectionIssue:vlv */
5469         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5470                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5471                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5472
5473         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5474          * gating disable must be set.  Failure to set it results in
5475          * flickering pixels due to Z write ordering failures after
5476          * some amount of runtime in the Mesa "fire" demo, and Unigine
5477          * Sanctuary and Tropics, and apparently anything else with
5478          * alpha test or pixel discard.
5479          *
5480          * According to the spec, bit 11 (RCCUNIT) must also be set,
5481          * but we didn't debug actual testcases to find it out.
5482          *
5483          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5484          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5485          *
5486          * Also apply WaDisableVDSUnitClockGating:vlv and
5487          * WaDisableRCPBUnitClockGating:vlv.
5488          */
5489         I915_WRITE(GEN6_UCGCTL2,
5490                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5491                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5492                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5493                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5494                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5495
5496         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5497
5498         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5499
5500         I915_WRITE(CACHE_MODE_1,
5501                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5502
5503         /*
5504          * WaDisableVLVClockGating_VBIIssue:vlv
5505          * Disable clock gating on th GCFG unit to prevent a delay
5506          * in the reporting of vblank events.
5507          */
5508         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5509
5510         /* Conservative clock gating settings for now */
5511         I915_WRITE(0x9400, 0xffffffff);
5512         I915_WRITE(0x9404, 0xffffffff);
5513         I915_WRITE(0x9408, 0xffffffff);
5514         I915_WRITE(0x940c, 0xffffffff);
5515         I915_WRITE(0x9410, 0xffffffff);
5516         I915_WRITE(0x9414, 0xffffffff);
5517         I915_WRITE(0x9418, 0xffffffff);
5518 }
5519
5520 static void g4x_init_clock_gating(struct drm_device *dev)
5521 {
5522         struct drm_i915_private *dev_priv = dev->dev_private;
5523         uint32_t dspclk_gate;
5524
5525         I915_WRITE(RENCLK_GATE_D1, 0);
5526         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5527                    GS_UNIT_CLOCK_GATE_DISABLE |
5528                    CL_UNIT_CLOCK_GATE_DISABLE);
5529         I915_WRITE(RAMCLK_GATE_D, 0);
5530         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5531                 OVRUNIT_CLOCK_GATE_DISABLE |
5532                 OVCUNIT_CLOCK_GATE_DISABLE;
5533         if (IS_GM45(dev))
5534                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5535         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5536
5537         /* WaDisableRenderCachePipelinedFlush */
5538         I915_WRITE(CACHE_MODE_0,
5539                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5540
5541         g4x_disable_trickle_feed(dev);
5542 }
5543
5544 static void crestline_init_clock_gating(struct drm_device *dev)
5545 {
5546         struct drm_i915_private *dev_priv = dev->dev_private;
5547
5548         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5549         I915_WRITE(RENCLK_GATE_D2, 0);
5550         I915_WRITE(DSPCLK_GATE_D, 0);
5551         I915_WRITE(RAMCLK_GATE_D, 0);
5552         I915_WRITE16(DEUC, 0);
5553         I915_WRITE(MI_ARB_STATE,
5554                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5555 }
5556
5557 static void broadwater_init_clock_gating(struct drm_device *dev)
5558 {
5559         struct drm_i915_private *dev_priv = dev->dev_private;
5560
5561         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5562                    I965_RCC_CLOCK_GATE_DISABLE |
5563                    I965_RCPB_CLOCK_GATE_DISABLE |
5564                    I965_ISC_CLOCK_GATE_DISABLE |
5565                    I965_FBC_CLOCK_GATE_DISABLE);
5566         I915_WRITE(RENCLK_GATE_D2, 0);
5567         I915_WRITE(MI_ARB_STATE,
5568                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5569 }
5570
5571 static void gen3_init_clock_gating(struct drm_device *dev)
5572 {
5573         struct drm_i915_private *dev_priv = dev->dev_private;
5574         u32 dstate = I915_READ(D_STATE);
5575
5576         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5577                 DSTATE_DOT_CLOCK_GATING;
5578         I915_WRITE(D_STATE, dstate);
5579
5580         if (IS_PINEVIEW(dev))
5581                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5582
5583         /* IIR "flip pending" means done if this bit is set */
5584         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5585 }
5586
5587 static void i85x_init_clock_gating(struct drm_device *dev)
5588 {
5589         struct drm_i915_private *dev_priv = dev->dev_private;
5590
5591         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5592 }
5593
5594 static void i830_init_clock_gating(struct drm_device *dev)
5595 {
5596         struct drm_i915_private *dev_priv = dev->dev_private;
5597
5598         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5599 }
5600
5601 void intel_init_clock_gating(struct drm_device *dev)
5602 {
5603         struct drm_i915_private *dev_priv = dev->dev_private;
5604
5605         dev_priv->display.init_clock_gating(dev);
5606 }
5607
5608 void intel_suspend_hw(struct drm_device *dev)
5609 {
5610         if (HAS_PCH_LPT(dev))
5611                 lpt_suspend_hw(dev);
5612 }
5613
5614 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5615         for (i = 0;                                                     \
5616              i < (power_domains)->power_well_count &&                   \
5617                  ((power_well) = &(power_domains)->power_wells[i]);     \
5618              i++)                                                       \
5619                 if ((power_well)->domains & (domain_mask))
5620
5621 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5622         for (i = (power_domains)->power_well_count - 1;                  \
5623              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5624              i--)                                                        \
5625                 if ((power_well)->domains & (domain_mask))
5626
5627 /**
5628  * We should only use the power well if we explicitly asked the hardware to
5629  * enable it, so check if it's enabled and also check if we've requested it to
5630  * be enabled.
5631  */
5632 static bool hsw_power_well_enabled(struct drm_device *dev,
5633                                    struct i915_power_well *power_well)
5634 {
5635         struct drm_i915_private *dev_priv = dev->dev_private;
5636
5637         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5638                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5639 }
5640
5641 bool intel_display_power_enabled(struct drm_device *dev,
5642                                  enum intel_display_power_domain domain)
5643 {
5644         struct drm_i915_private *dev_priv = dev->dev_private;
5645         struct i915_power_domains *power_domains;
5646         struct i915_power_well *power_well;
5647         bool is_enabled;
5648         int i;
5649
5650         power_domains = &dev_priv->power_domains;
5651
5652         is_enabled = true;
5653
5654         mutex_lock(&power_domains->lock);
5655         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5656                 if (power_well->always_on)
5657                         continue;
5658
5659                 if (!power_well->is_enabled(dev, power_well)) {
5660                         is_enabled = false;
5661                         break;
5662                 }
5663         }
5664         mutex_unlock(&power_domains->lock);
5665
5666         return is_enabled;
5667 }
5668
5669 static void hsw_set_power_well(struct drm_device *dev,
5670                                struct i915_power_well *power_well, bool enable)
5671 {
5672         struct drm_i915_private *dev_priv = dev->dev_private;
5673         bool is_enabled, enable_requested;
5674         unsigned long irqflags;
5675         uint32_t tmp;
5676
5677         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5678         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5679         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5680
5681         if (enable) {
5682                 if (!enable_requested)
5683                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5684                                    HSW_PWR_WELL_ENABLE_REQUEST);
5685
5686                 if (!is_enabled) {
5687                         DRM_DEBUG_KMS("Enabling power well\n");
5688                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5689                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5690                                 DRM_ERROR("Timeout enabling power well\n");
5691                 }
5692
5693                 if (IS_BROADWELL(dev)) {
5694                         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5695                         I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5696                                    dev_priv->de_irq_mask[PIPE_B]);
5697                         I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5698                                    ~dev_priv->de_irq_mask[PIPE_B] |
5699                                    GEN8_PIPE_VBLANK);
5700                         I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5701                                    dev_priv->de_irq_mask[PIPE_C]);
5702                         I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5703                                    ~dev_priv->de_irq_mask[PIPE_C] |
5704                                    GEN8_PIPE_VBLANK);
5705                         POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5706                         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5707                 }
5708         } else {
5709                 if (enable_requested) {
5710                         enum pipe p;
5711
5712                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5713                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5714                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5715
5716                         /*
5717                          * After this, the registers on the pipes that are part
5718                          * of the power well will become zero, so we have to
5719                          * adjust our counters according to that.
5720                          *
5721                          * FIXME: Should we do this in general in
5722                          * drm_vblank_post_modeset?
5723                          */
5724                         spin_lock_irqsave(&dev->vbl_lock, irqflags);
5725                         for_each_pipe(p)
5726                                 if (p != PIPE_A)
5727                                         dev->vblank[p].last = 0;
5728                         spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5729                 }
5730         }
5731 }
5732
5733 static void __intel_power_well_get(struct drm_device *dev,
5734                                    struct i915_power_well *power_well)
5735 {
5736         if (!power_well->count++ && power_well->set)
5737                 power_well->set(dev, power_well, true);
5738 }
5739
5740 static void __intel_power_well_put(struct drm_device *dev,
5741                                    struct i915_power_well *power_well)
5742 {
5743         WARN_ON(!power_well->count);
5744
5745         if (!--power_well->count && power_well->set && i915_disable_power_well)
5746                 power_well->set(dev, power_well, false);
5747 }
5748
5749 void intel_display_power_get(struct drm_device *dev,
5750                              enum intel_display_power_domain domain)
5751 {
5752         struct drm_i915_private *dev_priv = dev->dev_private;
5753         struct i915_power_domains *power_domains;
5754         struct i915_power_well *power_well;
5755         int i;
5756
5757         power_domains = &dev_priv->power_domains;
5758
5759         mutex_lock(&power_domains->lock);
5760
5761 #if IS_ENABLED(CONFIG_DEBUG_FS)
5762         power_domains->domain_use_count[domain]++;
5763 #endif
5764         for_each_power_well(i, power_well, BIT(domain), power_domains)
5765                 __intel_power_well_get(dev, power_well);
5766
5767         mutex_unlock(&power_domains->lock);
5768 }
5769
5770 void intel_display_power_put(struct drm_device *dev,
5771                              enum intel_display_power_domain domain)
5772 {
5773         struct drm_i915_private *dev_priv = dev->dev_private;
5774         struct i915_power_domains *power_domains;
5775         struct i915_power_well *power_well;
5776         int i;
5777
5778         power_domains = &dev_priv->power_domains;
5779
5780         mutex_lock(&power_domains->lock);
5781
5782         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5783                 __intel_power_well_put(dev, power_well);
5784
5785 #if IS_ENABLED(CONFIG_DEBUG_FS)
5786         WARN_ON(!power_domains->domain_use_count[domain]);
5787         power_domains->domain_use_count[domain]--;
5788 #endif
5789
5790         mutex_unlock(&power_domains->lock);
5791 }
5792
5793 static struct i915_power_domains *hsw_pwr;
5794
5795 /* Display audio driver power well request */
5796 void i915_request_power_well(void)
5797 {
5798         struct drm_i915_private *dev_priv;
5799
5800         if (WARN_ON(!hsw_pwr))
5801                 return;
5802
5803         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5804                                 power_domains);
5805         intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5806 }
5807 EXPORT_SYMBOL_GPL(i915_request_power_well);
5808
5809 /* Display audio driver power well release */
5810 void i915_release_power_well(void)
5811 {
5812         struct drm_i915_private *dev_priv;
5813
5814         if (WARN_ON(!hsw_pwr))
5815                 return;
5816
5817         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5818                                 power_domains);
5819         intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5820 }
5821 EXPORT_SYMBOL_GPL(i915_release_power_well);
5822
5823 static struct i915_power_well i9xx_always_on_power_well[] = {
5824         {
5825                 .name = "always-on",
5826                 .always_on = 1,
5827                 .domains = POWER_DOMAIN_MASK,
5828         },
5829 };
5830
5831 static struct i915_power_well hsw_power_wells[] = {
5832         {
5833                 .name = "always-on",
5834                 .always_on = 1,
5835                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5836         },
5837         {
5838                 .name = "display",
5839                 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5840                 .is_enabled = hsw_power_well_enabled,
5841                 .set = hsw_set_power_well,
5842         },
5843 };
5844
5845 static struct i915_power_well bdw_power_wells[] = {
5846         {
5847                 .name = "always-on",
5848                 .always_on = 1,
5849                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5850         },
5851         {
5852                 .name = "display",
5853                 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5854                 .is_enabled = hsw_power_well_enabled,
5855                 .set = hsw_set_power_well,
5856         },
5857 };
5858
5859 #define set_power_wells(power_domains, __power_wells) ({                \
5860         (power_domains)->power_wells = (__power_wells);                 \
5861         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
5862 })
5863
5864 int intel_power_domains_init(struct drm_device *dev)
5865 {
5866         struct drm_i915_private *dev_priv = dev->dev_private;
5867         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5868
5869         mutex_init(&power_domains->lock);
5870
5871         /*
5872          * The enabling order will be from lower to higher indexed wells,
5873          * the disabling order is reversed.
5874          */
5875         if (IS_HASWELL(dev)) {
5876                 set_power_wells(power_domains, hsw_power_wells);
5877                 hsw_pwr = power_domains;
5878         } else if (IS_BROADWELL(dev)) {
5879                 set_power_wells(power_domains, bdw_power_wells);
5880                 hsw_pwr = power_domains;
5881         } else {
5882                 set_power_wells(power_domains, i9xx_always_on_power_well);
5883         }
5884
5885         return 0;
5886 }
5887
5888 void intel_power_domains_remove(struct drm_device *dev)
5889 {
5890         hsw_pwr = NULL;
5891 }
5892
5893 static void intel_power_domains_resume(struct drm_device *dev)
5894 {
5895         struct drm_i915_private *dev_priv = dev->dev_private;
5896         struct i915_power_domains *power_domains = &dev_priv->power_domains;
5897         struct i915_power_well *power_well;
5898         int i;
5899
5900         mutex_lock(&power_domains->lock);
5901         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5902                 if (power_well->set)
5903                         power_well->set(dev, power_well, power_well->count > 0);
5904         }
5905         mutex_unlock(&power_domains->lock);
5906 }
5907
5908 /*
5909  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5910  * when not needed anymore. We have 4 registers that can request the power well
5911  * to be enabled, and it will only be disabled if none of the registers is
5912  * requesting it to be enabled.
5913  */
5914 void intel_power_domains_init_hw(struct drm_device *dev)
5915 {
5916         struct drm_i915_private *dev_priv = dev->dev_private;
5917
5918         /* For now, we need the power well to be always enabled. */
5919         intel_display_set_init_power(dev, true);
5920         intel_power_domains_resume(dev);
5921
5922         if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5923                 return;
5924
5925         /* We're taking over the BIOS, so clear any requests made by it since
5926          * the driver is in charge now. */
5927         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5928                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5929 }
5930
5931 /* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5932 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5933 {
5934         hsw_disable_package_c8(dev_priv);
5935 }
5936
5937 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5938 {
5939         hsw_enable_package_c8(dev_priv);
5940 }
5941
5942 /* Set up chip specific power management-related functions */
5943 void intel_init_pm(struct drm_device *dev)
5944 {
5945         struct drm_i915_private *dev_priv = dev->dev_private;
5946
5947         if (I915_HAS_FBC(dev)) {
5948                 if (HAS_PCH_SPLIT(dev)) {
5949                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5950                         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5951                                 dev_priv->display.enable_fbc =
5952                                         gen7_enable_fbc;
5953                         else
5954                                 dev_priv->display.enable_fbc =
5955                                         ironlake_enable_fbc;
5956                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5957                 } else if (IS_GM45(dev)) {
5958                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5959                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5960                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5961                 } else if (IS_CRESTLINE(dev)) {
5962                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5963                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5964                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5965                 }
5966                 /* 855GM needs testing */
5967         }
5968
5969         /* For cxsr */
5970         if (IS_PINEVIEW(dev))
5971                 i915_pineview_get_mem_freq(dev);
5972         else if (IS_GEN5(dev))
5973                 i915_ironlake_get_mem_freq(dev);
5974
5975         /* For FIFO watermark updates */
5976         if (HAS_PCH_SPLIT(dev)) {
5977                 intel_setup_wm_latency(dev);
5978
5979                 if (IS_GEN5(dev)) {
5980                         if (dev_priv->wm.pri_latency[1] &&
5981                             dev_priv->wm.spr_latency[1] &&
5982                             dev_priv->wm.cur_latency[1])
5983                                 dev_priv->display.update_wm = ironlake_update_wm;
5984                         else {
5985                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5986                                               "Disable CxSR\n");
5987                                 dev_priv->display.update_wm = NULL;
5988                         }
5989                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5990                 } else if (IS_GEN6(dev)) {
5991                         if (dev_priv->wm.pri_latency[0] &&
5992                             dev_priv->wm.spr_latency[0] &&
5993                             dev_priv->wm.cur_latency[0]) {
5994                                 dev_priv->display.update_wm = sandybridge_update_wm;
5995                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5996                         } else {
5997                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5998                                               "Disable CxSR\n");
5999                                 dev_priv->display.update_wm = NULL;
6000                         }
6001                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6002                 } else if (IS_IVYBRIDGE(dev)) {
6003                         if (dev_priv->wm.pri_latency[0] &&
6004                             dev_priv->wm.spr_latency[0] &&
6005                             dev_priv->wm.cur_latency[0]) {
6006                                 dev_priv->display.update_wm = ivybridge_update_wm;
6007                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6008                         } else {
6009                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6010                                               "Disable CxSR\n");
6011                                 dev_priv->display.update_wm = NULL;
6012                         }
6013                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6014                 } else if (IS_HASWELL(dev)) {
6015                         if (dev_priv->wm.pri_latency[0] &&
6016                             dev_priv->wm.spr_latency[0] &&
6017                             dev_priv->wm.cur_latency[0]) {
6018                                 dev_priv->display.update_wm = haswell_update_wm;
6019                                 dev_priv->display.update_sprite_wm =
6020                                         haswell_update_sprite_wm;
6021                         } else {
6022                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
6023                                               "Disable CxSR\n");
6024                                 dev_priv->display.update_wm = NULL;
6025                         }
6026                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6027                 } else if (INTEL_INFO(dev)->gen == 8) {
6028                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6029                 } else
6030                         dev_priv->display.update_wm = NULL;
6031         } else if (IS_VALLEYVIEW(dev)) {
6032                 dev_priv->display.update_wm = valleyview_update_wm;
6033                 dev_priv->display.init_clock_gating =
6034                         valleyview_init_clock_gating;
6035         } else if (IS_PINEVIEW(dev)) {
6036                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6037                                             dev_priv->is_ddr3,
6038                                             dev_priv->fsb_freq,
6039                                             dev_priv->mem_freq)) {
6040                         DRM_INFO("failed to find known CxSR latency "
6041                                  "(found ddr%s fsb freq %d, mem freq %d), "
6042                                  "disabling CxSR\n",
6043                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6044                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6045                         /* Disable CxSR and never update its watermark again */
6046                         pineview_disable_cxsr(dev);
6047                         dev_priv->display.update_wm = NULL;
6048                 } else
6049                         dev_priv->display.update_wm = pineview_update_wm;
6050                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6051         } else if (IS_G4X(dev)) {
6052                 dev_priv->display.update_wm = g4x_update_wm;
6053                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6054         } else if (IS_GEN4(dev)) {
6055                 dev_priv->display.update_wm = i965_update_wm;
6056                 if (IS_CRESTLINE(dev))
6057                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6058                 else if (IS_BROADWATER(dev))
6059                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6060         } else if (IS_GEN3(dev)) {
6061                 dev_priv->display.update_wm = i9xx_update_wm;
6062                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6063                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6064         } else if (IS_I865G(dev)) {
6065                 dev_priv->display.update_wm = i830_update_wm;
6066                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6067                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6068         } else if (IS_I85X(dev)) {
6069                 dev_priv->display.update_wm = i9xx_update_wm;
6070                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6071                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6072         } else {
6073                 dev_priv->display.update_wm = i830_update_wm;
6074                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6075                 if (IS_845G(dev))
6076                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6077                 else
6078                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6079         }
6080 }
6081
6082 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6083 {
6084         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6085
6086         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6087                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6088                 return -EAGAIN;
6089         }
6090
6091         I915_WRITE(GEN6_PCODE_DATA, *val);
6092         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6093
6094         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6095                      500)) {
6096                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6097                 return -ETIMEDOUT;
6098         }
6099
6100         *val = I915_READ(GEN6_PCODE_DATA);
6101         I915_WRITE(GEN6_PCODE_DATA, 0);
6102
6103         return 0;
6104 }
6105
6106 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6107 {
6108         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6109
6110         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6111                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6112                 return -EAGAIN;
6113         }
6114
6115         I915_WRITE(GEN6_PCODE_DATA, val);
6116         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6117
6118         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6119                      500)) {
6120                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6121                 return -ETIMEDOUT;
6122         }
6123
6124         I915_WRITE(GEN6_PCODE_DATA, 0);
6125
6126         return 0;
6127 }
6128
6129 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6130 {
6131         int div;
6132
6133         /* 4 x czclk */
6134         switch (dev_priv->mem_freq) {
6135         case 800:
6136                 div = 10;
6137                 break;
6138         case 1066:
6139                 div = 12;
6140                 break;
6141         case 1333:
6142                 div = 16;
6143                 break;
6144         default:
6145                 return -1;
6146         }
6147
6148         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6149 }
6150
6151 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6152 {
6153         int mul;
6154
6155         /* 4 x czclk */
6156         switch (dev_priv->mem_freq) {
6157         case 800:
6158                 mul = 10;
6159                 break;
6160         case 1066:
6161                 mul = 12;
6162                 break;
6163         case 1333:
6164                 mul = 16;
6165                 break;
6166         default:
6167                 return -1;
6168         }
6169
6170         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6171 }
6172
6173 void intel_pm_init(struct drm_device *dev)
6174 {
6175         struct drm_i915_private *dev_priv = dev->dev_private;
6176
6177         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6178                           intel_gen6_powersave_work);
6179 }