drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void gen9_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /* WaEnableLbsSlaRetryTimerDecrement:skl */
  60         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
  61                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
  62 }
  63
  64 static void skl_init_clock_gating(struct drm_device *dev)
  65 {
  66         struct drm_i915_private *dev_priv = dev->dev_private;
  67
  68         gen9_init_clock_gating(dev);
  69
  70         if (INTEL_REVID(dev) <= SKL_REVID_B0) {
  71                 /*
  72                  * WaDisableSDEUnitClockGating:skl
  73                  * WaSetGAPSunitClckGateDisable:skl
  74                  */
  75                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  76                            GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
  77                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  78
  79                 /* WaDisableVFUnitClockGating:skl */
  80                 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
  81                            GEN6_VFUNIT_CLOCK_GATE_DISABLE);
  82         }
  83
  84         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
  85                 /* WaDisableHDCInvalidation:skl */
  86                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  87                            BDW_DISABLE_HDC_INVALIDATION);
  88
  89                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
  90                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
  91                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
  92         }
  93
  94         if (INTEL_REVID(dev) <= SKL_REVID_E0)
  95                 /* WaDisableLSQCROPERFforOCL:skl */
  96                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
  97                            GEN8_LQSC_RO_PERF_DIS);
  98 }
  99
 100 static void bxt_init_clock_gating(struct drm_device *dev)
 101 {
 102         struct drm_i915_private *dev_priv = dev->dev_private;
 103
 104         gen9_init_clock_gating(dev);
 105
 106         /*
 107          * FIXME:
 108          * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
 109          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 110          */
 111          /* WaDisableSDEUnitClockGating:bxt */
 112         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 113                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
 114                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 115
 116         /* FIXME: apply on A0 only */
 117         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 118 }
 119
 120 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         u32 tmp;
 124
 125         tmp = I915_READ(CLKCFG);
 126
 127         switch (tmp & CLKCFG_FSB_MASK) {
 128         case CLKCFG_FSB_533:
 129                 dev_priv->fsb_freq = 533; /* 133*4 */
 130                 break;
 131         case CLKCFG_FSB_800:
 132                 dev_priv->fsb_freq = 800; /* 200*4 */
 133                 break;
 134         case CLKCFG_FSB_667:
 135                 dev_priv->fsb_freq =  667; /* 167*4 */
 136                 break;
 137         case CLKCFG_FSB_400:
 138                 dev_priv->fsb_freq = 400; /* 100*4 */
 139                 break;
 140         }
 141
 142         switch (tmp & CLKCFG_MEM_MASK) {
 143         case CLKCFG_MEM_533:
 144                 dev_priv->mem_freq = 533;
 145                 break;
 146         case CLKCFG_MEM_667:
 147                 dev_priv->mem_freq = 667;
 148                 break;
 149         case CLKCFG_MEM_800:
 150                 dev_priv->mem_freq = 800;
 151                 break;
 152         }
 153
 154         /* detect pineview DDR3 setting */
 155         tmp = I915_READ(CSHRDDR3CTL);
 156         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 157 }
 158
 159 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 160 {
 161         struct drm_i915_private *dev_priv = dev->dev_private;
 162         u16 ddrpll, csipll;
 163
 164         ddrpll = I915_READ16(DDRMPLL1);
 165         csipll = I915_READ16(CSIPLL0);
 166
 167         switch (ddrpll & 0xff) {
 168         case 0xc:
 169                 dev_priv->mem_freq = 800;
 170                 break;
 171         case 0x10:
 172                 dev_priv->mem_freq = 1066;
 173                 break;
 174         case 0x14:
 175                 dev_priv->mem_freq = 1333;
 176                 break;
 177         case 0x18:
 178                 dev_priv->mem_freq = 1600;
 179                 break;
 180         default:
 181                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 182                                  ddrpll & 0xff);
 183                 dev_priv->mem_freq = 0;
 184                 break;
 185         }
 186
 187         dev_priv->ips.r_t = dev_priv->mem_freq;
 188
 189         switch (csipll & 0x3ff) {
 190         case 0x00c:
 191                 dev_priv->fsb_freq = 3200;
 192                 break;
 193         case 0x00e:
 194                 dev_priv->fsb_freq = 3733;
 195                 break;
 196         case 0x010:
 197                 dev_priv->fsb_freq = 4266;
 198                 break;
 199         case 0x012:
 200                 dev_priv->fsb_freq = 4800;
 201                 break;
 202         case 0x014:
 203                 dev_priv->fsb_freq = 5333;
 204                 break;
 205         case 0x016:
 206                 dev_priv->fsb_freq = 5866;
 207                 break;
 208         case 0x018:
 209                 dev_priv->fsb_freq = 6400;
 210                 break;
 211         default:
 212                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 213                                  csipll & 0x3ff);
 214                 dev_priv->fsb_freq = 0;
 215                 break;
 216         }
 217
 218         if (dev_priv->fsb_freq == 3200) {
 219                 dev_priv->ips.c_m = 0;
 220         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 221                 dev_priv->ips.c_m = 1;
 222         } else {
 223                 dev_priv->ips.c_m = 2;
 224         }
 225 }
 226
 227 static const struct cxsr_latency cxsr_latency_table[] = {
 228         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 229         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 230         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 231         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 232         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 233
 234         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 235         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 236         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 237         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 238         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 239
 240         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 241         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 242         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 243         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 244         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 245
 246         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 247         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 248         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 249         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 250         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 251
 252         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 253         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 254         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 255         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 256         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 257
 258         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 259         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 260         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 261         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 262         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 263 };
 264
 265 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 266                                                          int is_ddr3,
 267                                                          int fsb,
 268                                                          int mem)
 269 {
 270         const struct cxsr_latency *latency;
 271         int i;
 272
 273         if (fsb == 0 || mem == 0)
 274                 return NULL;
 275
 276         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 277                 latency = &cxsr_latency_table[i];
 278                 if (is_desktop == latency->is_desktop &&
 279                     is_ddr3 == latency->is_ddr3 &&
 280                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 281                         return latency;
 282         }
 283
 284         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 285
 286         return NULL;
 287 }
 288
 289 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 290 {
 291         u32 val;
 292
 293         mutex_lock(&dev_priv->rps.hw_lock);
 294
 295         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 296         if (enable)
 297                 val &= ~FORCE_DDR_HIGH_FREQ;
 298         else
 299                 val |= FORCE_DDR_HIGH_FREQ;
 300         val &= ~FORCE_DDR_LOW_FREQ;
 301         val |= FORCE_DDR_FREQ_REQ_ACK;
 302         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 303
 304         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 305                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 306                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 307
 308         mutex_unlock(&dev_priv->rps.hw_lock);
 309 }
 310
 311 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 312 {
 313         u32 val;
 314
 315         mutex_lock(&dev_priv->rps.hw_lock);
 316
 317         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 318         if (enable)
 319                 val |= DSP_MAXFIFO_PM5_ENABLE;
 320         else
 321                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 322         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 323
 324         mutex_unlock(&dev_priv->rps.hw_lock);
 325 }
 326
 327 #define FW_WM(value, plane) \
 328         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 329
 330 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 331 {
 332         struct drm_device *dev = dev_priv->dev;
 333         u32 val;
 334
 335         if (IS_VALLEYVIEW(dev)) {
 336                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 337                 if (IS_CHERRYVIEW(dev))
 338                         chv_set_memory_pm5(dev_priv, enable);
 339         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 340                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 341         } else if (IS_PINEVIEW(dev)) {
 342                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 343                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 344                 I915_WRITE(DSPFW3, val);
 345         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 346                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 347                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 348                 I915_WRITE(FW_BLC_SELF, val);
 349         } else if (IS_I915GM(dev)) {
 350                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 351                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 352                 I915_WRITE(INSTPM, val);
 353         } else {
 354                 return;
 355         }
 356
 357         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 358                       enable ? "enabled" : "disabled");
 359 }
 360
 361
 362 /*
 363  * Latency for FIFO fetches is dependent on several factors:
 364  *   - memory configuration (speed, channels)
 365  *   - chipset
 366  *   - current MCH state
 367  * It can be fairly high in some situations, so here we assume a fairly
 368  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 369  * set this value too high, the FIFO will fetch frequently to stay full)
 370  * and power consumption (set it too low to save power and we might see
 371  * FIFO underruns and display "flicker").
 372  *
 373  * A value of 5us seems to be a good balance; safe for very low end
 374  * platforms but not overly aggressive on lower latency configs.
 375  */
 376 static const int pessimal_latency_ns = 5000;
 377
 378 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 379         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 380
 381 static int vlv_get_fifo_size(struct drm_device *dev,
 382                               enum pipe pipe, int plane)
 383 {
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         int sprite0_start, sprite1_start, size;
 386
 387         switch (pipe) {
 388                 uint32_t dsparb, dsparb2, dsparb3;
 389         case PIPE_A:
 390                 dsparb = I915_READ(DSPARB);
 391                 dsparb2 = I915_READ(DSPARB2);
 392                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 393                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 394                 break;
 395         case PIPE_B:
 396                 dsparb = I915_READ(DSPARB);
 397                 dsparb2 = I915_READ(DSPARB2);
 398                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 399                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 400                 break;
 401         case PIPE_C:
 402                 dsparb2 = I915_READ(DSPARB2);
 403                 dsparb3 = I915_READ(DSPARB3);
 404                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 405                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 406                 break;
 407         default:
 408                 return 0;
 409         }
 410
 411         switch (plane) {
 412         case 0:
 413                 size = sprite0_start;
 414                 break;
 415         case 1:
 416                 size = sprite1_start - sprite0_start;
 417                 break;
 418         case 2:
 419                 size = 512 - 1 - sprite1_start;
 420                 break;
 421         default:
 422                 return 0;
 423         }
 424
 425         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 426                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 427                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 428                       size);
 429
 430         return size;
 431 }
 432
 433 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 434 {
 435         struct drm_i915_private *dev_priv = dev->dev_private;
 436         uint32_t dsparb = I915_READ(DSPARB);
 437         int size;
 438
 439         size = dsparb & 0x7f;
 440         if (plane)
 441                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 442
 443         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 444                       plane ? "B" : "A", size);
 445
 446         return size;
 447 }
 448
 449 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 450 {
 451         struct drm_i915_private *dev_priv = dev->dev_private;
 452         uint32_t dsparb = I915_READ(DSPARB);
 453         int size;
 454
 455         size = dsparb & 0x1ff;
 456         if (plane)
 457                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 458         size >>= 1; /* Convert to cachelines */
 459
 460         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 461                       plane ? "B" : "A", size);
 462
 463         return size;
 464 }
 465
 466 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469         uint32_t dsparb = I915_READ(DSPARB);
 470         int size;
 471
 472         size = dsparb & 0x7f;
 473         size >>= 2; /* Convert to cachelines */
 474
 475         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 476                       plane ? "B" : "A",
 477                       size);
 478
 479         return size;
 480 }
 481
 482 /* Pineview has different values for various configs */
 483 static const struct intel_watermark_params pineview_display_wm = {
 484         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 485         .max_wm = PINEVIEW_MAX_WM,
 486         .default_wm = PINEVIEW_DFT_WM,
 487         .guard_size = PINEVIEW_GUARD_WM,
 488         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 489 };
 490 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 491         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 492         .max_wm = PINEVIEW_MAX_WM,
 493         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 494         .guard_size = PINEVIEW_GUARD_WM,
 495         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 496 };
 497 static const struct intel_watermark_params pineview_cursor_wm = {
 498         .fifo_size = PINEVIEW_CURSOR_FIFO,
 499         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 500         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 501         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 502         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 503 };
 504 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 505         .fifo_size = PINEVIEW_CURSOR_FIFO,
 506         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 507         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 508         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 509         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 510 };
 511 static const struct intel_watermark_params g4x_wm_info = {
 512         .fifo_size = G4X_FIFO_SIZE,
 513         .max_wm = G4X_MAX_WM,
 514         .default_wm = G4X_MAX_WM,
 515         .guard_size = 2,
 516         .cacheline_size = G4X_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params g4x_cursor_wm_info = {
 519         .fifo_size = I965_CURSOR_FIFO,
 520         .max_wm = I965_CURSOR_MAX_WM,
 521         .default_wm = I965_CURSOR_DFT_WM,
 522         .guard_size = 2,
 523         .cacheline_size = G4X_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params valleyview_wm_info = {
 526         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 527         .max_wm = VALLEYVIEW_MAX_WM,
 528         .default_wm = VALLEYVIEW_MAX_WM,
 529         .guard_size = 2,
 530         .cacheline_size = G4X_FIFO_LINE_SIZE,
 531 };
 532 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 533         .fifo_size = I965_CURSOR_FIFO,
 534         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 535         .default_wm = I965_CURSOR_DFT_WM,
 536         .guard_size = 2,
 537         .cacheline_size = G4X_FIFO_LINE_SIZE,
 538 };
 539 static const struct intel_watermark_params i965_cursor_wm_info = {
 540         .fifo_size = I965_CURSOR_FIFO,
 541         .max_wm = I965_CURSOR_MAX_WM,
 542         .default_wm = I965_CURSOR_DFT_WM,
 543         .guard_size = 2,
 544         .cacheline_size = I915_FIFO_LINE_SIZE,
 545 };
 546 static const struct intel_watermark_params i945_wm_info = {
 547         .fifo_size = I945_FIFO_SIZE,
 548         .max_wm = I915_MAX_WM,
 549         .default_wm = 1,
 550         .guard_size = 2,
 551         .cacheline_size = I915_FIFO_LINE_SIZE,
 552 };
 553 static const struct intel_watermark_params i915_wm_info = {
 554         .fifo_size = I915_FIFO_SIZE,
 555         .max_wm = I915_MAX_WM,
 556         .default_wm = 1,
 557         .guard_size = 2,
 558         .cacheline_size = I915_FIFO_LINE_SIZE,
 559 };
 560 static const struct intel_watermark_params i830_a_wm_info = {
 561         .fifo_size = I855GM_FIFO_SIZE,
 562         .max_wm = I915_MAX_WM,
 563         .default_wm = 1,
 564         .guard_size = 2,
 565         .cacheline_size = I830_FIFO_LINE_SIZE,
 566 };
 567 static const struct intel_watermark_params i830_bc_wm_info = {
 568         .fifo_size = I855GM_FIFO_SIZE,
 569         .max_wm = I915_MAX_WM/2,
 570         .default_wm = 1,
 571         .guard_size = 2,
 572         .cacheline_size = I830_FIFO_LINE_SIZE,
 573 };
 574 static const struct intel_watermark_params i845_wm_info = {
 575         .fifo_size = I830_FIFO_SIZE,
 576         .max_wm = I915_MAX_WM,
 577         .default_wm = 1,
 578         .guard_size = 2,
 579         .cacheline_size = I830_FIFO_LINE_SIZE,
 580 };
 581
 582 /**
 583  * intel_calculate_wm - calculate watermark level
 584  * @clock_in_khz: pixel clock
 585  * @wm: chip FIFO params
 586  * @pixel_size: display pixel size
 587  * @latency_ns: memory latency for the platform
 588  *
 589  * Calculate the watermark level (the level at which the display plane will
 590  * start fetching from memory again).  Each chip has a different display
 591  * FIFO size and allocation, so the caller needs to figure that out and pass
 592  * in the correct intel_watermark_params structure.
 593  *
 594  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 595  * on the pixel size.  When it reaches the watermark level, it'll start
 596  * fetching FIFO line sized based chunks from memory until the FIFO fills
 597  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 598  * will occur, and a display engine hang could result.
 599  */
 600 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 601                                         const struct intel_watermark_params *wm,
 602                                         int fifo_size,
 603                                         int pixel_size,
 604                                         unsigned long latency_ns)
 605 {
 606         long entries_required, wm_size;
 607
 608         /*
 609          * Note: we need to make sure we don't overflow for various clock &
 610          * latency values.
 611          * clocks go from a few thousand to several hundred thousand.
 612          * latency is usually a few thousand
 613          */
 614         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 615                 1000;
 616         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 617
 618         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 619
 620         wm_size = fifo_size - (entries_required + wm->guard_size);
 621
 622         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 623
 624         /* Don't promote wm_size to unsigned... */
 625         if (wm_size > (long)wm->max_wm)
 626                 wm_size = wm->max_wm;
 627         if (wm_size <= 0)
 628                 wm_size = wm->default_wm;
 629
 630         /*
 631          * Bspec seems to indicate that the value shouldn't be lower than
 632          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 633          * Lets go for 8 which is the burst size since certain platforms
 634          * already use a hardcoded 8 (which is what the spec says should be
 635          * done).
 636          */
 637         if (wm_size <= 8)
 638                 wm_size = 8;
 639
 640         return wm_size;
 641 }
 642
 643 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 644 {
 645         struct drm_crtc *crtc, *enabled = NULL;
 646
 647         for_each_crtc(dev, crtc) {
 648                 if (intel_crtc_active(crtc)) {
 649                         if (enabled)
 650                                 return NULL;
 651                         enabled = crtc;
 652                 }
 653         }
 654
 655         return enabled;
 656 }
 657
 658 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 659 {
 660         struct drm_device *dev = unused_crtc->dev;
 661         struct drm_i915_private *dev_priv = dev->dev_private;
 662         struct drm_crtc *crtc;
 663         const struct cxsr_latency *latency;
 664         u32 reg;
 665         unsigned long wm;
 666
 667         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 668                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 669         if (!latency) {
 670                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 671                 intel_set_memory_cxsr(dev_priv, false);
 672                 return;
 673         }
 674
 675         crtc = single_enabled_crtc(dev);
 676         if (crtc) {
 677                 const struct drm_display_mode *adjusted_mode;
 678                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 679                 int clock;
 680
 681                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 682                 clock = adjusted_mode->crtc_clock;
 683
 684                 /* Display SR */
 685                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 686                                         pineview_display_wm.fifo_size,
 687                                         pixel_size, latency->display_sr);
 688                 reg = I915_READ(DSPFW1);
 689                 reg &= ~DSPFW_SR_MASK;
 690                 reg |= FW_WM(wm, SR);
 691                 I915_WRITE(DSPFW1, reg);
 692                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 693
 694                 /* cursor SR */
 695                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 696                                         pineview_display_wm.fifo_size,
 697                                         pixel_size, latency->cursor_sr);
 698                 reg = I915_READ(DSPFW3);
 699                 reg &= ~DSPFW_CURSOR_SR_MASK;
 700                 reg |= FW_WM(wm, CURSOR_SR);
 701                 I915_WRITE(DSPFW3, reg);
 702
 703                 /* Display HPLL off SR */
 704                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 705                                         pineview_display_hplloff_wm.fifo_size,
 706                                         pixel_size, latency->display_hpll_disable);
 707                 reg = I915_READ(DSPFW3);
 708                 reg &= ~DSPFW_HPLL_SR_MASK;
 709                 reg |= FW_WM(wm, HPLL_SR);
 710                 I915_WRITE(DSPFW3, reg);
 711
 712                 /* cursor HPLL off SR */
 713                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 714                                         pineview_display_hplloff_wm.fifo_size,
 715                                         pixel_size, latency->cursor_hpll_disable);
 716                 reg = I915_READ(DSPFW3);
 717                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 718                 reg |= FW_WM(wm, HPLL_CURSOR);
 719                 I915_WRITE(DSPFW3, reg);
 720                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 721
 722                 intel_set_memory_cxsr(dev_priv, true);
 723         } else {
 724                 intel_set_memory_cxsr(dev_priv, false);
 725         }
 726 }
 727
 728 static bool g4x_compute_wm0(struct drm_device *dev,
 729                             int plane,
 730                             const struct intel_watermark_params *display,
 731                             int display_latency_ns,
 732                             const struct intel_watermark_params *cursor,
 733                             int cursor_latency_ns,
 734                             int *plane_wm,
 735                             int *cursor_wm)
 736 {
 737         struct drm_crtc *crtc;
 738         const struct drm_display_mode *adjusted_mode;
 739         int htotal, hdisplay, clock, pixel_size;
 740         int line_time_us, line_count;
 741         int entries, tlb_miss;
 742
 743         crtc = intel_get_crtc_for_plane(dev, plane);
 744         if (!intel_crtc_active(crtc)) {
 745                 *cursor_wm = cursor->guard_size;
 746                 *plane_wm = display->guard_size;
 747                 return false;
 748         }
 749
 750         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 751         clock = adjusted_mode->crtc_clock;
 752         htotal = adjusted_mode->crtc_htotal;
 753         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 754         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 755
 756         /* Use the small buffer method to calculate plane watermark */
 757         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 758         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 759         if (tlb_miss > 0)
 760                 entries += tlb_miss;
 761         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 762         *plane_wm = entries + display->guard_size;
 763         if (*plane_wm > (int)display->max_wm)
 764                 *plane_wm = display->max_wm;
 765
 766         /* Use the large buffer method to calculate cursor watermark */
 767         line_time_us = max(htotal * 1000 / clock, 1);
 768         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 769         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 770         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 771         if (tlb_miss > 0)
 772                 entries += tlb_miss;
 773         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 774         *cursor_wm = entries + cursor->guard_size;
 775         if (*cursor_wm > (int)cursor->max_wm)
 776                 *cursor_wm = (int)cursor->max_wm;
 777
 778         return true;
 779 }
 780
 781 /*
 782  * Check the wm result.
 783  *
 784  * If any calculated watermark values is larger than the maximum value that
 785  * can be programmed into the associated watermark register, that watermark
 786  * must be disabled.
 787  */
 788 static bool g4x_check_srwm(struct drm_device *dev,
 789                            int display_wm, int cursor_wm,
 790                            const struct intel_watermark_params *display,
 791                            const struct intel_watermark_params *cursor)
 792 {
 793         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 794                       display_wm, cursor_wm);
 795
 796         if (display_wm > display->max_wm) {
 797                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 798                               display_wm, display->max_wm);
 799                 return false;
 800         }
 801
 802         if (cursor_wm > cursor->max_wm) {
 803                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 804                               cursor_wm, cursor->max_wm);
 805                 return false;
 806         }
 807
 808         if (!(display_wm || cursor_wm)) {
 809                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 810                 return false;
 811         }
 812
 813         return true;
 814 }
 815
 816 static bool g4x_compute_srwm(struct drm_device *dev,
 817                              int plane,
 818                              int latency_ns,
 819                              const struct intel_watermark_params *display,
 820                              const struct intel_watermark_params *cursor,
 821                              int *display_wm, int *cursor_wm)
 822 {
 823         struct drm_crtc *crtc;
 824         const struct drm_display_mode *adjusted_mode;
 825         int hdisplay, htotal, pixel_size, clock;
 826         unsigned long line_time_us;
 827         int line_count, line_size;
 828         int small, large;
 829         int entries;
 830
 831         if (!latency_ns) {
 832                 *display_wm = *cursor_wm = 0;
 833                 return false;
 834         }
 835
 836         crtc = intel_get_crtc_for_plane(dev, plane);
 837         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 838         clock = adjusted_mode->crtc_clock;
 839         htotal = adjusted_mode->crtc_htotal;
 840         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 841         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 842
 843         line_time_us = max(htotal * 1000 / clock, 1);
 844         line_count = (latency_ns / line_time_us + 1000) / 1000;
 845         line_size = hdisplay * pixel_size;
 846
 847         /* Use the minimum of the small and large buffer method for primary */
 848         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 849         large = line_count * line_size;
 850
 851         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 852         *display_wm = entries + display->guard_size;
 853
 854         /* calculate the self-refresh watermark for display cursor */
 855         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 856         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 857         *cursor_wm = entries + cursor->guard_size;
 858
 859         return g4x_check_srwm(dev,
 860                               *display_wm, *cursor_wm,
 861                               display, cursor);
 862 }
 863
 864 #define FW_WM_VLV(value, plane) \
 865         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 866
 867 static void vlv_write_wm_values(struct intel_crtc *crtc,
 868                                 const struct vlv_wm_values *wm)
 869 {
 870         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 871         enum pipe pipe = crtc->pipe;
 872
 873         I915_WRITE(VLV_DDL(pipe),
 874                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 875                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 876                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 877                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 878
 879         I915_WRITE(DSPFW1,
 880                    FW_WM(wm->sr.plane, SR) |
 881                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 882                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 883                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 884         I915_WRITE(DSPFW2,
 885                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 886                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 887                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 888         I915_WRITE(DSPFW3,
 889                    FW_WM(wm->sr.cursor, CURSOR_SR));
 890
 891         if (IS_CHERRYVIEW(dev_priv)) {
 892                 I915_WRITE(DSPFW7_CHV,
 893                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 894                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 895                 I915_WRITE(DSPFW8_CHV,
 896                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 897                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 898                 I915_WRITE(DSPFW9_CHV,
 899                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 900                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 901                 I915_WRITE(DSPHOWM,
 902                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 903                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 904                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 905                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 906                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 907                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 908                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 909                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 910                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 911                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 912         } else {
 913                 I915_WRITE(DSPFW7,
 914                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 915                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 916                 I915_WRITE(DSPHOWM,
 917                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 918                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 919                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 920                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 921                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 922                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 923                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 924         }
 925
 926         POSTING_READ(DSPFW1);
 927
 928         dev_priv->wm.vlv = *wm;
 929 }
 930
 931 #undef FW_WM_VLV
 932
 933 static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
 934                                          struct drm_plane *plane)
 935 {
 936         struct drm_device *dev = crtc->dev;
 937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 938         int entries, prec_mult, drain_latency, pixel_size;
 939         int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
 940         const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
 941
 942         /*
 943          * FIXME the plane might have an fb
 944          * but be invisible (eg. due to clipping)
 945          */
 946         if (!intel_crtc->active || !plane->state->fb)
 947                 return 0;
 948
 949         if (WARN(clock == 0, "Pixel clock is zero!\n"))
 950                 return 0;
 951
 952         pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
 953
 954         if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
 955                 return 0;
 956
 957         entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
 958
 959         prec_mult = high_precision;
 960         drain_latency = 64 * prec_mult * 4 / entries;
 961
 962         if (drain_latency > DRAIN_LATENCY_MASK) {
 963                 prec_mult /= 2;
 964                 drain_latency = 64 * prec_mult * 4 / entries;
 965         }
 966
 967         if (drain_latency > DRAIN_LATENCY_MASK)
 968                 drain_latency = DRAIN_LATENCY_MASK;
 969
 970         return drain_latency | (prec_mult == high_precision ?
 971                                 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
 972 }
 973
 974 static int vlv_compute_wm(struct intel_crtc *crtc,
 975                           struct intel_plane *plane,
 976                           int fifo_size)
 977 {
 978         int clock, entries, pixel_size;
 979
 980         /*
 981          * FIXME the plane might have an fb
 982          * but be invisible (eg. due to clipping)
 983          */
 984         if (!crtc->active || !plane->base.state->fb)
 985                 return 0;
 986
 987         pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
 988         clock = crtc->config->base.adjusted_mode.crtc_clock;
 989
 990         entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
 991
 992         /*
 993          * Set up the watermark such that we don't start issuing memory
 994          * requests until we are within PND's max deadline value (256us).
 995          * Idea being to be idle as long as possible while still taking
 996          * advatange of PND's deadline scheduling. The limit of 8
 997          * cachelines (used when the FIFO will anyway drain in less time
 998          * than 256us) should match what we would be done if trickle
 999          * feed were enabled.
1000          */
1001         return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
1002 }
1003
1004 static bool vlv_compute_sr_wm(struct drm_device *dev,
1005                               struct vlv_wm_values *wm)
1006 {
1007         struct drm_i915_private *dev_priv = to_i915(dev);
1008         struct drm_crtc *crtc;
1009         enum pipe pipe = INVALID_PIPE;
1010         int num_planes = 0;
1011         int fifo_size = 0;
1012         struct intel_plane *plane;
1013
1014         wm->sr.cursor = wm->sr.plane = 0;
1015
1016         crtc = single_enabled_crtc(dev);
1017         /* maxfifo not supported on pipe C */
1018         if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1019                 pipe = to_intel_crtc(crtc)->pipe;
1020                 num_planes = !!wm->pipe[pipe].primary +
1021                         !!wm->pipe[pipe].sprite[0] +
1022                         !!wm->pipe[pipe].sprite[1];
1023                 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1024         }
1025
1026         if (fifo_size == 0 || num_planes > 1)
1027                 return false;
1028
1029         wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1030                                        to_intel_plane(crtc->cursor), 0x3f);
1031
1032         list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1033                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1034                         continue;
1035
1036                 if (plane->pipe != pipe)
1037                         continue;
1038
1039                 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1040                                               plane, fifo_size);
1041                 if (wm->sr.plane != 0)
1042                         break;
1043         }
1044
1045         return true;
1046 }
1047
1048 static void valleyview_update_wm(struct drm_crtc *crtc)
1049 {
1050         struct drm_device *dev = crtc->dev;
1051         struct drm_i915_private *dev_priv = dev->dev_private;
1052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1053         enum pipe pipe = intel_crtc->pipe;
1054         bool cxsr_enabled;
1055         struct vlv_wm_values wm = dev_priv->wm.vlv;
1056
1057         wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1058         wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1059                                                to_intel_plane(crtc->primary),
1060                                                vlv_get_fifo_size(dev, pipe, 0));
1061
1062         wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1063         wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1064                                               to_intel_plane(crtc->cursor),
1065                                               0x3f);
1066
1067         cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1068
1069         if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1070                 return;
1071
1072         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1073                       "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1074                       wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1075                       wm.sr.plane, wm.sr.cursor);
1076
1077         /*
1078          * FIXME DDR DVFS introduces massive memory latencies which
1079          * are not known to system agent so any deadline specified
1080          * by the display may not be respected. To support DDR DVFS
1081          * the watermark code needs to be rewritten to essentially
1082          * bypass deadline mechanism and rely solely on the
1083          * watermarks. For now disable DDR DVFS.
1084          */
1085         if (IS_CHERRYVIEW(dev_priv))
1086                 chv_set_memory_dvfs(dev_priv, false);
1087
1088         if (!cxsr_enabled)
1089                 intel_set_memory_cxsr(dev_priv, false);
1090
1091         vlv_write_wm_values(intel_crtc, &wm);
1092
1093         if (cxsr_enabled)
1094                 intel_set_memory_cxsr(dev_priv, true);
1095 }
1096
1097 static void valleyview_update_sprite_wm(struct drm_plane *plane,
1098                                         struct drm_crtc *crtc,
1099                                         uint32_t sprite_width,
1100                                         uint32_t sprite_height,
1101                                         int pixel_size,
1102                                         bool enabled, bool scaled)
1103 {
1104         struct drm_device *dev = crtc->dev;
1105         struct drm_i915_private *dev_priv = dev->dev_private;
1106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1107         enum pipe pipe = intel_crtc->pipe;
1108         int sprite = to_intel_plane(plane)->plane;
1109         bool cxsr_enabled;
1110         struct vlv_wm_values wm = dev_priv->wm.vlv;
1111
1112         if (enabled) {
1113                 wm.ddl[pipe].sprite[sprite] =
1114                         vlv_compute_drain_latency(crtc, plane);
1115
1116                 wm.pipe[pipe].sprite[sprite] =
1117                         vlv_compute_wm(intel_crtc,
1118                                        to_intel_plane(plane),
1119                                        vlv_get_fifo_size(dev, pipe, sprite+1));
1120         } else {
1121                 wm.ddl[pipe].sprite[sprite] = 0;
1122                 wm.pipe[pipe].sprite[sprite] = 0;
1123         }
1124
1125         cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1126
1127         if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1128                 return;
1129
1130         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1131                       "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1132                       sprite_name(pipe, sprite),
1133                       wm.pipe[pipe].sprite[sprite],
1134                       wm.sr.plane, wm.sr.cursor);
1135
1136         if (!cxsr_enabled)
1137                 intel_set_memory_cxsr(dev_priv, false);
1138
1139         vlv_write_wm_values(intel_crtc, &wm);
1140
1141         if (cxsr_enabled)
1142                 intel_set_memory_cxsr(dev_priv, true);
1143 }
1144
1145 #define single_plane_enabled(mask) is_power_of_2(mask)
1146
1147 static void g4x_update_wm(struct drm_crtc *crtc)
1148 {
1149         struct drm_device *dev = crtc->dev;
1150         static const int sr_latency_ns = 12000;
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1153         int plane_sr, cursor_sr;
1154         unsigned int enabled = 0;
1155         bool cxsr_enabled;
1156
1157         if (g4x_compute_wm0(dev, PIPE_A,
1158                             &g4x_wm_info, pessimal_latency_ns,
1159                             &g4x_cursor_wm_info, pessimal_latency_ns,
1160                             &planea_wm, &cursora_wm))
1161                 enabled |= 1 << PIPE_A;
1162
1163         if (g4x_compute_wm0(dev, PIPE_B,
1164                             &g4x_wm_info, pessimal_latency_ns,
1165                             &g4x_cursor_wm_info, pessimal_latency_ns,
1166                             &planeb_wm, &cursorb_wm))
1167                 enabled |= 1 << PIPE_B;
1168
1169         if (single_plane_enabled(enabled) &&
1170             g4x_compute_srwm(dev, ffs(enabled) - 1,
1171                              sr_latency_ns,
1172                              &g4x_wm_info,
1173                              &g4x_cursor_wm_info,
1174                              &plane_sr, &cursor_sr)) {
1175                 cxsr_enabled = true;
1176         } else {
1177                 cxsr_enabled = false;
1178                 intel_set_memory_cxsr(dev_priv, false);
1179                 plane_sr = cursor_sr = 0;
1180         }
1181
1182         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1183                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1184                       planea_wm, cursora_wm,
1185                       planeb_wm, cursorb_wm,
1186                       plane_sr, cursor_sr);
1187
1188         I915_WRITE(DSPFW1,
1189                    FW_WM(plane_sr, SR) |
1190                    FW_WM(cursorb_wm, CURSORB) |
1191                    FW_WM(planeb_wm, PLANEB) |
1192                    FW_WM(planea_wm, PLANEA));
1193         I915_WRITE(DSPFW2,
1194                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1195                    FW_WM(cursora_wm, CURSORA));
1196         /* HPLL off in SR has some issues on G4x... disable it */
1197         I915_WRITE(DSPFW3,
1198                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1199                    FW_WM(cursor_sr, CURSOR_SR));
1200
1201         if (cxsr_enabled)
1202                 intel_set_memory_cxsr(dev_priv, true);
1203 }
1204
1205 static void i965_update_wm(struct drm_crtc *unused_crtc)
1206 {
1207         struct drm_device *dev = unused_crtc->dev;
1208         struct drm_i915_private *dev_priv = dev->dev_private;
1209         struct drm_crtc *crtc;
1210         int srwm = 1;
1211         int cursor_sr = 16;
1212         bool cxsr_enabled;
1213
1214         /* Calc sr entries for one plane configs */
1215         crtc = single_enabled_crtc(dev);
1216         if (crtc) {
1217                 /* self-refresh has much higher latency */
1218                 static const int sr_latency_ns = 12000;
1219                 const struct drm_display_mode *adjusted_mode =
1220                         &to_intel_crtc(crtc)->config->base.adjusted_mode;
1221                 int clock = adjusted_mode->crtc_clock;
1222                 int htotal = adjusted_mode->crtc_htotal;
1223                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1224                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1225                 unsigned long line_time_us;
1226                 int entries;
1227
1228                 line_time_us = max(htotal * 1000 / clock, 1);
1229
1230                 /* Use ns/us then divide to preserve precision */
1231                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1232                         pixel_size * hdisplay;
1233                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1234                 srwm = I965_FIFO_SIZE - entries;
1235                 if (srwm < 0)
1236                         srwm = 1;
1237                 srwm &= 0x1ff;
1238                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1239                               entries, srwm);
1240
1241                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1242                         pixel_size * crtc->cursor->state->crtc_w;
1243                 entries = DIV_ROUND_UP(entries,
1244                                           i965_cursor_wm_info.cacheline_size);
1245                 cursor_sr = i965_cursor_wm_info.fifo_size -
1246                         (entries + i965_cursor_wm_info.guard_size);
1247
1248                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1249                         cursor_sr = i965_cursor_wm_info.max_wm;
1250
1251                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1252                               "cursor %d\n", srwm, cursor_sr);
1253
1254                 cxsr_enabled = true;
1255         } else {
1256                 cxsr_enabled = false;
1257                 /* Turn off self refresh if both pipes are enabled */
1258                 intel_set_memory_cxsr(dev_priv, false);
1259         }
1260
1261         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1262                       srwm);
1263
1264         /* 965 has limitations... */
1265         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1266                    FW_WM(8, CURSORB) |
1267                    FW_WM(8, PLANEB) |
1268                    FW_WM(8, PLANEA));
1269         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1270                    FW_WM(8, PLANEC_OLD));
1271         /* update cursor SR watermark */
1272         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1273
1274         if (cxsr_enabled)
1275                 intel_set_memory_cxsr(dev_priv, true);
1276 }
1277
1278 #undef FW_WM
1279
1280 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1281 {
1282         struct drm_device *dev = unused_crtc->dev;
1283         struct drm_i915_private *dev_priv = dev->dev_private;
1284         const struct intel_watermark_params *wm_info;
1285         uint32_t fwater_lo;
1286         uint32_t fwater_hi;
1287         int cwm, srwm = 1;
1288         int fifo_size;
1289         int planea_wm, planeb_wm;
1290         struct drm_crtc *crtc, *enabled = NULL;
1291
1292         if (IS_I945GM(dev))
1293                 wm_info = &i945_wm_info;
1294         else if (!IS_GEN2(dev))
1295                 wm_info = &i915_wm_info;
1296         else
1297                 wm_info = &i830_a_wm_info;
1298
1299         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1300         crtc = intel_get_crtc_for_plane(dev, 0);
1301         if (intel_crtc_active(crtc)) {
1302                 const struct drm_display_mode *adjusted_mode;
1303                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1304                 if (IS_GEN2(dev))
1305                         cpp = 4;
1306
1307                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1308                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1309                                                wm_info, fifo_size, cpp,
1310                                                pessimal_latency_ns);
1311                 enabled = crtc;
1312         } else {
1313                 planea_wm = fifo_size - wm_info->guard_size;
1314                 if (planea_wm > (long)wm_info->max_wm)
1315                         planea_wm = wm_info->max_wm;
1316         }
1317
1318         if (IS_GEN2(dev))
1319                 wm_info = &i830_bc_wm_info;
1320
1321         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1322         crtc = intel_get_crtc_for_plane(dev, 1);
1323         if (intel_crtc_active(crtc)) {
1324                 const struct drm_display_mode *adjusted_mode;
1325                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1326                 if (IS_GEN2(dev))
1327                         cpp = 4;
1328
1329                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1330                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1331                                                wm_info, fifo_size, cpp,
1332                                                pessimal_latency_ns);
1333                 if (enabled == NULL)
1334                         enabled = crtc;
1335                 else
1336                         enabled = NULL;
1337         } else {
1338                 planeb_wm = fifo_size - wm_info->guard_size;
1339                 if (planeb_wm > (long)wm_info->max_wm)
1340                         planeb_wm = wm_info->max_wm;
1341         }
1342
1343         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1344
1345         if (IS_I915GM(dev) && enabled) {
1346                 struct drm_i915_gem_object *obj;
1347
1348                 obj = intel_fb_obj(enabled->primary->state->fb);
1349
1350                 /* self-refresh seems busted with untiled */
1351                 if (obj->tiling_mode == I915_TILING_NONE)
1352                         enabled = NULL;
1353         }
1354
1355         /*
1356          * Overlay gets an aggressive default since video jitter is bad.
1357          */
1358         cwm = 2;
1359
1360         /* Play safe and disable self-refresh before adjusting watermarks. */
1361         intel_set_memory_cxsr(dev_priv, false);
1362
1363         /* Calc sr entries for one plane configs */
1364         if (HAS_FW_BLC(dev) && enabled) {
1365                 /* self-refresh has much higher latency */
1366                 static const int sr_latency_ns = 6000;
1367                 const struct drm_display_mode *adjusted_mode =
1368                         &to_intel_crtc(enabled)->config->base.adjusted_mode;
1369                 int clock = adjusted_mode->crtc_clock;
1370                 int htotal = adjusted_mode->crtc_htotal;
1371                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1372                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1373                 unsigned long line_time_us;
1374                 int entries;
1375
1376                 line_time_us = max(htotal * 1000 / clock, 1);
1377
1378                 /* Use ns/us then divide to preserve precision */
1379                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1380                         pixel_size * hdisplay;
1381                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1382                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1383                 srwm = wm_info->fifo_size - entries;
1384                 if (srwm < 0)
1385                         srwm = 1;
1386
1387                 if (IS_I945G(dev) || IS_I945GM(dev))
1388                         I915_WRITE(FW_BLC_SELF,
1389                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1390                 else if (IS_I915GM(dev))
1391                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1392         }
1393
1394         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1395                       planea_wm, planeb_wm, cwm, srwm);
1396
1397         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1398         fwater_hi = (cwm & 0x1f);
1399
1400         /* Set request length to 8 cachelines per fetch */
1401         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1402         fwater_hi = fwater_hi | (1 << 8);
1403
1404         I915_WRITE(FW_BLC, fwater_lo);
1405         I915_WRITE(FW_BLC2, fwater_hi);
1406
1407         if (enabled)
1408                 intel_set_memory_cxsr(dev_priv, true);
1409 }
1410
1411 static void i845_update_wm(struct drm_crtc *unused_crtc)
1412 {
1413         struct drm_device *dev = unused_crtc->dev;
1414         struct drm_i915_private *dev_priv = dev->dev_private;
1415         struct drm_crtc *crtc;
1416         const struct drm_display_mode *adjusted_mode;
1417         uint32_t fwater_lo;
1418         int planea_wm;
1419
1420         crtc = single_enabled_crtc(dev);
1421         if (crtc == NULL)
1422                 return;
1423
1424         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1425         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1426                                        &i845_wm_info,
1427                                        dev_priv->display.get_fifo_size(dev, 0),
1428                                        4, pessimal_latency_ns);
1429         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1430         fwater_lo |= (3<<8) | planea_wm;
1431
1432         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1433
1434         I915_WRITE(FW_BLC, fwater_lo);
1435 }
1436
1437 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1438                                     struct drm_crtc *crtc)
1439 {
1440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1441         uint32_t pixel_rate;
1442
1443         pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
1444
1445         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1446          * adjust the pixel_rate here. */
1447
1448         if (intel_crtc->config->pch_pfit.enabled) {
1449                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1450                 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
1451
1452                 pipe_w = intel_crtc->config->pipe_src_w;
1453                 pipe_h = intel_crtc->config->pipe_src_h;
1454                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1455                 pfit_h = pfit_size & 0xFFFF;
1456                 if (pipe_w < pfit_w)
1457                         pipe_w = pfit_w;
1458                 if (pipe_h < pfit_h)
1459                         pipe_h = pfit_h;
1460
1461                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1462                                      pfit_w * pfit_h);
1463         }
1464
1465         return pixel_rate;
1466 }
1467
1468 /* latency must be in 0.1us units. */
1469 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1470                                uint32_t latency)
1471 {
1472         uint64_t ret;
1473
1474         if (WARN(latency == 0, "Latency value missing\n"))
1475                 return UINT_MAX;
1476
1477         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1478         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1479
1480         return ret;
1481 }
1482
1483 /* latency must be in 0.1us units. */
1484 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1485                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1486                                uint32_t latency)
1487 {
1488         uint32_t ret;
1489
1490         if (WARN(latency == 0, "Latency value missing\n"))
1491                 return UINT_MAX;
1492
1493         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1494         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1495         ret = DIV_ROUND_UP(ret, 64) + 2;
1496         return ret;
1497 }
1498
1499 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1500                            uint8_t bytes_per_pixel)
1501 {
1502         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1503 }
1504
1505 struct skl_pipe_wm_parameters {
1506         bool active;
1507         uint32_t pipe_htotal;
1508         uint32_t pixel_rate; /* in KHz */
1509         struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1510         struct intel_plane_wm_parameters cursor;
1511 };
1512
1513 struct ilk_pipe_wm_parameters {
1514         bool active;
1515         uint32_t pipe_htotal;
1516         uint32_t pixel_rate;
1517         struct intel_plane_wm_parameters pri;
1518         struct intel_plane_wm_parameters spr;
1519         struct intel_plane_wm_parameters cur;
1520 };
1521
1522 struct ilk_wm_maximums {
1523         uint16_t pri;
1524         uint16_t spr;
1525         uint16_t cur;
1526         uint16_t fbc;
1527 };
1528
1529 /* used in computing the new watermarks state */
1530 struct intel_wm_config {
1531         unsigned int num_pipes_active;
1532         bool sprites_enabled;
1533         bool sprites_scaled;
1534 };
1535
1536 /*
1537  * For both WM_PIPE and WM_LP.
1538  * mem_value must be in 0.1us units.
1539  */
1540 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1541                                    uint32_t mem_value,
1542                                    bool is_lp)
1543 {
1544         uint32_t method1, method2;
1545
1546         if (!params->active || !params->pri.enabled)
1547                 return 0;
1548
1549         method1 = ilk_wm_method1(params->pixel_rate,
1550                                  params->pri.bytes_per_pixel,
1551                                  mem_value);
1552
1553         if (!is_lp)
1554                 return method1;
1555
1556         method2 = ilk_wm_method2(params->pixel_rate,
1557                                  params->pipe_htotal,
1558                                  params->pri.horiz_pixels,
1559                                  params->pri.bytes_per_pixel,
1560                                  mem_value);
1561
1562         return min(method1, method2);
1563 }
1564
1565 /*
1566  * For both WM_PIPE and WM_LP.
1567  * mem_value must be in 0.1us units.
1568  */
1569 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1570                                    uint32_t mem_value)
1571 {
1572         uint32_t method1, method2;
1573
1574         if (!params->active || !params->spr.enabled)
1575                 return 0;
1576
1577         method1 = ilk_wm_method1(params->pixel_rate,
1578                                  params->spr.bytes_per_pixel,
1579                                  mem_value);
1580         method2 = ilk_wm_method2(params->pixel_rate,
1581                                  params->pipe_htotal,
1582                                  params->spr.horiz_pixels,
1583                                  params->spr.bytes_per_pixel,
1584                                  mem_value);
1585         return min(method1, method2);
1586 }
1587
1588 /*
1589  * For both WM_PIPE and WM_LP.
1590  * mem_value must be in 0.1us units.
1591  */
1592 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1593                                    uint32_t mem_value)
1594 {
1595         if (!params->active || !params->cur.enabled)
1596                 return 0;
1597
1598         return ilk_wm_method2(params->pixel_rate,
1599                               params->pipe_htotal,
1600                               params->cur.horiz_pixels,
1601                               params->cur.bytes_per_pixel,
1602                               mem_value);
1603 }
1604
1605 /* Only for WM_LP. */
1606 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1607                                    uint32_t pri_val)
1608 {
1609         if (!params->active || !params->pri.enabled)
1610                 return 0;
1611
1612         return ilk_wm_fbc(pri_val,
1613                           params->pri.horiz_pixels,
1614                           params->pri.bytes_per_pixel);
1615 }
1616
1617 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1618 {
1619         if (INTEL_INFO(dev)->gen >= 8)
1620                 return 3072;
1621         else if (INTEL_INFO(dev)->gen >= 7)
1622                 return 768;
1623         else
1624                 return 512;
1625 }
1626
1627 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1628                                          int level, bool is_sprite)
1629 {
1630         if (INTEL_INFO(dev)->gen >= 8)
1631                 /* BDW primary/sprite plane watermarks */
1632                 return level == 0 ? 255 : 2047;
1633         else if (INTEL_INFO(dev)->gen >= 7)
1634                 /* IVB/HSW primary/sprite plane watermarks */
1635                 return level == 0 ? 127 : 1023;
1636         else if (!is_sprite)
1637                 /* ILK/SNB primary plane watermarks */
1638                 return level == 0 ? 127 : 511;
1639         else
1640                 /* ILK/SNB sprite plane watermarks */
1641                 return level == 0 ? 63 : 255;
1642 }
1643
1644 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1645                                           int level)
1646 {
1647         if (INTEL_INFO(dev)->gen >= 7)
1648                 return level == 0 ? 63 : 255;
1649         else
1650                 return level == 0 ? 31 : 63;
1651 }
1652
1653 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1654 {
1655         if (INTEL_INFO(dev)->gen >= 8)
1656                 return 31;
1657         else
1658                 return 15;
1659 }
1660
1661 /* Calculate the maximum primary/sprite plane watermark */
1662 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1663                                      int level,
1664                                      const struct intel_wm_config *config,
1665                                      enum intel_ddb_partitioning ddb_partitioning,
1666                                      bool is_sprite)
1667 {
1668         unsigned int fifo_size = ilk_display_fifo_size(dev);
1669
1670         /* if sprites aren't enabled, sprites get nothing */
1671         if (is_sprite && !config->sprites_enabled)
1672                 return 0;
1673
1674         /* HSW allows LP1+ watermarks even with multiple pipes */
1675         if (level == 0 || config->num_pipes_active > 1) {
1676                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1677
1678                 /*
1679                  * For some reason the non self refresh
1680                  * FIFO size is only half of the self
1681                  * refresh FIFO size on ILK/SNB.
1682                  */
1683                 if (INTEL_INFO(dev)->gen <= 6)
1684                         fifo_size /= 2;
1685         }
1686
1687         if (config->sprites_enabled) {
1688                 /* level 0 is always calculated with 1:1 split */
1689                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1690                         if (is_sprite)
1691                                 fifo_size *= 5;
1692                         fifo_size /= 6;
1693                 } else {
1694                         fifo_size /= 2;
1695                 }
1696         }
1697
1698         /* clamp to max that the registers can hold */
1699         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1700 }
1701
1702 /* Calculate the maximum cursor plane watermark */
1703 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1704                                       int level,
1705                                       const struct intel_wm_config *config)
1706 {
1707         /* HSW LP1+ watermarks w/ multiple pipes */
1708         if (level > 0 && config->num_pipes_active > 1)
1709                 return 64;
1710
1711         /* otherwise just report max that registers can hold */
1712         return ilk_cursor_wm_reg_max(dev, level);
1713 }
1714
1715 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1716                                     int level,
1717                                     const struct intel_wm_config *config,
1718                                     enum intel_ddb_partitioning ddb_partitioning,
1719                                     struct ilk_wm_maximums *max)
1720 {
1721         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1722         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1723         max->cur = ilk_cursor_wm_max(dev, level, config);
1724         max->fbc = ilk_fbc_wm_reg_max(dev);
1725 }
1726
1727 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1728                                         int level,
1729                                         struct ilk_wm_maximums *max)
1730 {
1731         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1732         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1733         max->cur = ilk_cursor_wm_reg_max(dev, level);
1734         max->fbc = ilk_fbc_wm_reg_max(dev);
1735 }
1736
1737 static bool ilk_validate_wm_level(int level,
1738                                   const struct ilk_wm_maximums *max,
1739                                   struct intel_wm_level *result)
1740 {
1741         bool ret;
1742
1743         /* already determined to be invalid? */
1744         if (!result->enable)
1745                 return false;
1746
1747         result->enable = result->pri_val <= max->pri &&
1748                          result->spr_val <= max->spr &&
1749                          result->cur_val <= max->cur;
1750
1751         ret = result->enable;
1752
1753         /*
1754          * HACK until we can pre-compute everything,
1755          * and thus fail gracefully if LP0 watermarks
1756          * are exceeded...
1757          */
1758         if (level == 0 && !result->enable) {
1759                 if (result->pri_val > max->pri)
1760                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1761                                       level, result->pri_val, max->pri);
1762                 if (result->spr_val > max->spr)
1763                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1764                                       level, result->spr_val, max->spr);
1765                 if (result->cur_val > max->cur)
1766                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1767                                       level, result->cur_val, max->cur);
1768
1769                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1770                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1771                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1772                 result->enable = true;
1773         }
1774
1775         return ret;
1776 }
1777
1778 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1779                                  int level,
1780                                  const struct ilk_pipe_wm_parameters *p,
1781                                  struct intel_wm_level *result)
1782 {
1783         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1784         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1785         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1786
1787         /* WM1+ latency values stored in 0.5us units */
1788         if (level > 0) {
1789                 pri_latency *= 5;
1790                 spr_latency *= 5;
1791                 cur_latency *= 5;
1792         }
1793
1794         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1795         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1796         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1797         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1798         result->enable = true;
1799 }
1800
1801 static uint32_t
1802 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1803 {
1804         struct drm_i915_private *dev_priv = dev->dev_private;
1805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806         struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
1807         u32 linetime, ips_linetime;
1808
1809         if (!intel_crtc->active)
1810                 return 0;
1811
1812         /* The WM are computed with base on how long it takes to fill a single
1813          * row at the given clock rate, multiplied by 8.
1814          * */
1815         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1816                                      mode->crtc_clock);
1817         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1818                                          dev_priv->display.get_display_clock_speed(dev_priv->dev));
1819
1820         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1821                PIPE_WM_LINETIME_TIME(linetime);
1822 }
1823
1824 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
1825 {
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827
1828         if (IS_GEN9(dev)) {
1829                 uint32_t val;
1830                 int ret, i;
1831                 int level, max_level = ilk_wm_max_level(dev);
1832
1833                 /* read the first set of memory latencies[0:3] */
1834                 val = 0; /* data0 to be programmed to 0 for first set */
1835                 mutex_lock(&dev_priv->rps.hw_lock);
1836                 ret = sandybridge_pcode_read(dev_priv,
1837                                              GEN9_PCODE_READ_MEM_LATENCY,
1838                                              &val);
1839                 mutex_unlock(&dev_priv->rps.hw_lock);
1840
1841                 if (ret) {
1842                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1843                         return;
1844                 }
1845
1846                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1847                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1848                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1849                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1850                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1851                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1852                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1853
1854                 /* read the second set of memory latencies[4:7] */
1855                 val = 1; /* data0 to be programmed to 1 for second set */
1856                 mutex_lock(&dev_priv->rps.hw_lock);
1857                 ret = sandybridge_pcode_read(dev_priv,
1858                                              GEN9_PCODE_READ_MEM_LATENCY,
1859                                              &val);
1860                 mutex_unlock(&dev_priv->rps.hw_lock);
1861                 if (ret) {
1862                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1863                         return;
1864                 }
1865
1866                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1867                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1868                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1869                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1870                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1871                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1872                                 GEN9_MEM_LATENCY_LEVEL_MASK;
1873
1874                 /*
1875                  * WaWmMemoryReadLatency:skl
1876                  *
1877                  * punit doesn't take into account the read latency so we need
1878                  * to add 2us to the various latency levels we retrieve from
1879                  * the punit.
1880                  *   - W0 is a bit special in that it's the only level that
1881                  *   can't be disabled if we want to have display working, so
1882                  *   we always add 2us there.
1883                  *   - For levels >=1, punit returns 0us latency when they are
1884                  *   disabled, so we respect that and don't add 2us then
1885                  *
1886                  * Additionally, if a level n (n > 1) has a 0us latency, all
1887                  * levels m (m >= n) need to be disabled. We make sure to
1888                  * sanitize the values out of the punit to satisfy this
1889                  * requirement.
1890                  */
1891                 wm[0] += 2;
1892                 for (level = 1; level <= max_level; level++)
1893                         if (wm[level] != 0)
1894                                 wm[level] += 2;
1895                         else {
1896                                 for (i = level + 1; i <= max_level; i++)
1897                                         wm[i] = 0;
1898
1899                                 break;
1900                         }
1901         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1902                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1903
1904                 wm[0] = (sskpd >> 56) & 0xFF;
1905                 if (wm[0] == 0)
1906                         wm[0] = sskpd & 0xF;
1907                 wm[1] = (sskpd >> 4) & 0xFF;
1908                 wm[2] = (sskpd >> 12) & 0xFF;
1909                 wm[3] = (sskpd >> 20) & 0x1FF;
1910                 wm[4] = (sskpd >> 32) & 0x1FF;
1911         } else if (INTEL_INFO(dev)->gen >= 6) {
1912                 uint32_t sskpd = I915_READ(MCH_SSKPD);
1913
1914                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1915                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1916                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1917                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
1918         } else if (INTEL_INFO(dev)->gen >= 5) {
1919                 uint32_t mltr = I915_READ(MLTR_ILK);
1920
1921                 /* ILK primary LP0 latency is 700 ns */
1922                 wm[0] = 7;
1923                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1924                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
1925         }
1926 }
1927
1928 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1929 {
1930         /* ILK sprite LP0 latency is 1300 ns */
1931         if (INTEL_INFO(dev)->gen == 5)
1932                 wm[0] = 13;
1933 }
1934
1935 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1936 {
1937         /* ILK cursor LP0 latency is 1300 ns */
1938         if (INTEL_INFO(dev)->gen == 5)
1939                 wm[0] = 13;
1940
1941         /* WaDoubleCursorLP3Latency:ivb */
1942         if (IS_IVYBRIDGE(dev))
1943                 wm[3] *= 2;
1944 }
1945
1946 int ilk_wm_max_level(const struct drm_device *dev)
1947 {
1948         /* how many WM levels are we expecting */
1949         if (INTEL_INFO(dev)->gen >= 9)
1950                 return 7;
1951         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1952                 return 4;
1953         else if (INTEL_INFO(dev)->gen >= 6)
1954                 return 3;
1955         else
1956                 return 2;
1957 }
1958
1959 static void intel_print_wm_latency(struct drm_device *dev,
1960                                    const char *name,
1961                                    const uint16_t wm[8])
1962 {
1963         int level, max_level = ilk_wm_max_level(dev);
1964
1965         for (level = 0; level <= max_level; level++) {
1966                 unsigned int latency = wm[level];
1967
1968                 if (latency == 0) {
1969                         DRM_ERROR("%s WM%d latency not provided\n",
1970                                   name, level);
1971                         continue;
1972                 }
1973
1974                 /*
1975                  * - latencies are in us on gen9.
1976                  * - before then, WM1+ latency values are in 0.5us units
1977                  */
1978                 if (IS_GEN9(dev))
1979                         latency *= 10;
1980                 else if (level > 0)
1981                         latency *= 5;
1982
1983                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1984                               name, level, wm[level],
1985                               latency / 10, latency % 10);
1986         }
1987 }
1988
1989 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1990                                     uint16_t wm[5], uint16_t min)
1991 {
1992         int level, max_level = ilk_wm_max_level(dev_priv->dev);
1993
1994         if (wm[0] >= min)
1995                 return false;
1996
1997         wm[0] = max(wm[0], min);
1998         for (level = 1; level <= max_level; level++)
1999                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2000
2001         return true;
2002 }
2003
2004 static void snb_wm_latency_quirk(struct drm_device *dev)
2005 {
2006         struct drm_i915_private *dev_priv = dev->dev_private;
2007         bool changed;
2008
2009         /*
2010          * The BIOS provided WM memory latency values are often
2011          * inadequate for high resolution displays. Adjust them.
2012          */
2013         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2014                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2015                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2016
2017         if (!changed)
2018                 return;
2019
2020         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2021         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2022         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2023         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2024 }
2025
2026 static void ilk_setup_wm_latency(struct drm_device *dev)
2027 {
2028         struct drm_i915_private *dev_priv = dev->dev_private;
2029
2030         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2031
2032         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2033                sizeof(dev_priv->wm.pri_latency));
2034         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2035                sizeof(dev_priv->wm.pri_latency));
2036
2037         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2038         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2039
2040         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2041         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2042         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2043
2044         if (IS_GEN6(dev))
2045                 snb_wm_latency_quirk(dev);
2046 }
2047
2048 static void skl_setup_wm_latency(struct drm_device *dev)
2049 {
2050         struct drm_i915_private *dev_priv = dev->dev_private;
2051
2052         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2053         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2054 }
2055
2056 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2057                                       struct ilk_pipe_wm_parameters *p)
2058 {
2059         struct drm_device *dev = crtc->dev;
2060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2061         enum pipe pipe = intel_crtc->pipe;
2062         struct drm_plane *plane;
2063
2064         if (!intel_crtc->active)
2065                 return;
2066
2067         p->active = true;
2068         p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2069         p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2070
2071         if (crtc->primary->state->fb) {
2072                 p->pri.enabled = true;
2073                 p->pri.bytes_per_pixel =
2074                         crtc->primary->state->fb->bits_per_pixel / 8;
2075         } else {
2076                 p->pri.enabled = false;
2077                 p->pri.bytes_per_pixel = 0;
2078         }
2079
2080         if (crtc->cursor->state->fb) {
2081                 p->cur.enabled = true;
2082                 p->cur.bytes_per_pixel = 4;
2083         } else {
2084                 p->cur.enabled = false;
2085                 p->cur.bytes_per_pixel = 0;
2086         }
2087         p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2088         p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2089
2090         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2091                 struct intel_plane *intel_plane = to_intel_plane(plane);
2092
2093                 if (intel_plane->pipe == pipe) {
2094                         p->spr = intel_plane->wm;
2095                         break;
2096                 }
2097         }
2098 }
2099
2100 static void ilk_compute_wm_config(struct drm_device *dev,
2101                                   struct intel_wm_config *config)
2102 {
2103         struct intel_crtc *intel_crtc;
2104
2105         /* Compute the currently _active_ config */
2106         for_each_intel_crtc(dev, intel_crtc) {
2107                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2108
2109                 if (!wm->pipe_enabled)
2110                         continue;
2111
2112                 config->sprites_enabled |= wm->sprites_enabled;
2113                 config->sprites_scaled |= wm->sprites_scaled;
2114                 config->num_pipes_active++;
2115         }
2116 }
2117
2118 /* Compute new watermarks for the pipe */
2119 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2120                                   const struct ilk_pipe_wm_parameters *params,
2121                                   struct intel_pipe_wm *pipe_wm)
2122 {
2123         struct drm_device *dev = crtc->dev;
2124         const struct drm_i915_private *dev_priv = dev->dev_private;
2125         int level, max_level = ilk_wm_max_level(dev);
2126         /* LP0 watermark maximums depend on this pipe alone */
2127         struct intel_wm_config config = {
2128                 .num_pipes_active = 1,
2129                 .sprites_enabled = params->spr.enabled,
2130                 .sprites_scaled = params->spr.scaled,
2131         };
2132         struct ilk_wm_maximums max;
2133
2134         pipe_wm->pipe_enabled = params->active;
2135         pipe_wm->sprites_enabled = params->spr.enabled;
2136         pipe_wm->sprites_scaled = params->spr.scaled;
2137
2138         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2139         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2140                 max_level = 1;
2141
2142         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2143         if (params->spr.scaled)
2144                 max_level = 0;
2145
2146         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2147
2148         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2149                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2150
2151         /* LP0 watermarks always use 1/2 DDB partitioning */
2152         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2153
2154         /* At least LP0 must be valid */
2155         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2156                 return false;
2157
2158         ilk_compute_wm_reg_maximums(dev, 1, &max);
2159
2160         for (level = 1; level <= max_level; level++) {
2161                 struct intel_wm_level wm = {};
2162
2163                 ilk_compute_wm_level(dev_priv, level, params, &wm);
2164
2165                 /*
2166                  * Disable any watermark level that exceeds the
2167                  * register maximums since such watermarks are
2168                  * always invalid.
2169                  */
2170                 if (!ilk_validate_wm_level(level, &max, &wm))
2171                         break;
2172
2173                 pipe_wm->wm[level] = wm;
2174         }
2175
2176         return true;
2177 }
2178
2179 /*
2180  * Merge the watermarks from all active pipes for a specific level.
2181  */
2182 static void ilk_merge_wm_level(struct drm_device *dev,
2183                                int level,
2184                                struct intel_wm_level *ret_wm)
2185 {
2186         const struct intel_crtc *intel_crtc;
2187
2188         ret_wm->enable = true;
2189
2190         for_each_intel_crtc(dev, intel_crtc) {
2191                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2192                 const struct intel_wm_level *wm = &active->wm[level];
2193
2194                 if (!active->pipe_enabled)
2195                         continue;
2196
2197                 /*
2198                  * The watermark values may have been used in the past,
2199                  * so we must maintain them in the registers for some
2200                  * time even if the level is now disabled.
2201                  */
2202                 if (!wm->enable)
2203                         ret_wm->enable = false;
2204
2205                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2206                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2207                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2208                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2209         }
2210 }
2211
2212 /*
2213  * Merge all low power watermarks for all active pipes.
2214  */
2215 static void ilk_wm_merge(struct drm_device *dev,
2216                          const struct intel_wm_config *config,
2217                          const struct ilk_wm_maximums *max,
2218                          struct intel_pipe_wm *merged)
2219 {
2220         int level, max_level = ilk_wm_max_level(dev);
2221         int last_enabled_level = max_level;
2222
2223         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2224         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2225             config->num_pipes_active > 1)
2226                 return;
2227
2228         /* ILK: FBC WM must be disabled always */
2229         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2230
2231         /* merge each WM1+ level */
2232         for (level = 1; level <= max_level; level++) {
2233                 struct intel_wm_level *wm = &merged->wm[level];
2234
2235                 ilk_merge_wm_level(dev, level, wm);
2236
2237                 if (level > last_enabled_level)
2238                         wm->enable = false;
2239                 else if (!ilk_validate_wm_level(level, max, wm))
2240                         /* make sure all following levels get disabled */
2241                         last_enabled_level = level - 1;
2242
2243                 /*
2244                  * The spec says it is preferred to disable
2245                  * FBC WMs instead of disabling a WM level.
2246                  */
2247                 if (wm->fbc_val > max->fbc) {
2248                         if (wm->enable)
2249                                 merged->fbc_wm_enabled = false;
2250                         wm->fbc_val = 0;
2251                 }
2252         }
2253
2254         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2255         /*
2256          * FIXME this is racy. FBC might get enabled later.
2257          * What we should check here is whether FBC can be
2258          * enabled sometime later.
2259          */
2260         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2261                 for (level = 2; level <= max_level; level++) {
2262                         struct intel_wm_level *wm = &merged->wm[level];
2263
2264                         wm->enable = false;
2265                 }
2266         }
2267 }
2268
2269 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2270 {
2271         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2272         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2273 }
2274
2275 /* The value we need to program into the WM_LPx latency field */
2276 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2277 {
2278         struct drm_i915_private *dev_priv = dev->dev_private;
2279
2280         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2281                 return 2 * level;
2282         else
2283                 return dev_priv->wm.pri_latency[level];
2284 }
2285
2286 static void ilk_compute_wm_results(struct drm_device *dev,
2287                                    const struct intel_pipe_wm *merged,
2288                                    enum intel_ddb_partitioning partitioning,
2289                                    struct ilk_wm_values *results)
2290 {
2291         struct intel_crtc *intel_crtc;
2292         int level, wm_lp;
2293
2294         results->enable_fbc_wm = merged->fbc_wm_enabled;
2295         results->partitioning = partitioning;
2296
2297         /* LP1+ register values */
2298         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2299                 const struct intel_wm_level *r;
2300
2301                 level = ilk_wm_lp_to_level(wm_lp, merged);
2302
2303                 r = &merged->wm[level];
2304
2305                 /*
2306                  * Maintain the watermark values even if the level is
2307                  * disabled. Doing otherwise could cause underruns.
2308                  */
2309                 results->wm_lp[wm_lp - 1] =
2310                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2311                         (r->pri_val << WM1_LP_SR_SHIFT) |
2312                         r->cur_val;
2313
2314                 if (r->enable)
2315                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2316
2317                 if (INTEL_INFO(dev)->gen >= 8)
2318                         results->wm_lp[wm_lp - 1] |=
2319                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2320                 else
2321                         results->wm_lp[wm_lp - 1] |=
2322                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2323
2324                 /*
2325                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2326                  * level is disabled. Doing otherwise could cause underruns.
2327                  */
2328                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2329                         WARN_ON(wm_lp != 1);
2330                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2331                 } else
2332                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2333         }
2334
2335         /* LP0 register values */
2336         for_each_intel_crtc(dev, intel_crtc) {
2337                 enum pipe pipe = intel_crtc->pipe;
2338                 const struct intel_wm_level *r =
2339                         &intel_crtc->wm.active.wm[0];
2340
2341                 if (WARN_ON(!r->enable))
2342                         continue;
2343
2344                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2345
2346                 results->wm_pipe[pipe] =
2347                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2348                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2349                         r->cur_val;
2350         }
2351 }
2352
2353 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2354  * case both are at the same level. Prefer r1 in case they're the same. */
2355 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2356                                                   struct intel_pipe_wm *r1,
2357                                                   struct intel_pipe_wm *r2)
2358 {
2359         int level, max_level = ilk_wm_max_level(dev);
2360         int level1 = 0, level2 = 0;
2361
2362         for (level = 1; level <= max_level; level++) {
2363                 if (r1->wm[level].enable)
2364                         level1 = level;
2365                 if (r2->wm[level].enable)
2366                         level2 = level;
2367         }
2368
2369         if (level1 == level2) {
2370                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2371                         return r2;
2372                 else
2373                         return r1;
2374         } else if (level1 > level2) {
2375                 return r1;
2376         } else {
2377                 return r2;
2378         }
2379 }
2380
2381 /* dirty bits used to track which watermarks need changes */
2382 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2383 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2384 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2385 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2386 #define WM_DIRTY_FBC (1 << 24)
2387 #define WM_DIRTY_DDB (1 << 25)
2388
2389 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2390                                          const struct ilk_wm_values *old,
2391                                          const struct ilk_wm_values *new)
2392 {
2393         unsigned int dirty = 0;
2394         enum pipe pipe;
2395         int wm_lp;
2396
2397         for_each_pipe(dev_priv, pipe) {
2398                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2399                         dirty |= WM_DIRTY_LINETIME(pipe);
2400                         /* Must disable LP1+ watermarks too */
2401                         dirty |= WM_DIRTY_LP_ALL;
2402                 }
2403
2404                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2405                         dirty |= WM_DIRTY_PIPE(pipe);
2406                         /* Must disable LP1+ watermarks too */
2407                         dirty |= WM_DIRTY_LP_ALL;
2408                 }
2409         }
2410
2411         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2412                 dirty |= WM_DIRTY_FBC;
2413                 /* Must disable LP1+ watermarks too */
2414                 dirty |= WM_DIRTY_LP_ALL;
2415         }
2416
2417         if (old->partitioning != new->partitioning) {
2418                 dirty |= WM_DIRTY_DDB;
2419                 /* Must disable LP1+ watermarks too */
2420                 dirty |= WM_DIRTY_LP_ALL;
2421         }
2422
2423         /* LP1+ watermarks already deemed dirty, no need to continue */
2424         if (dirty & WM_DIRTY_LP_ALL)
2425                 return dirty;
2426
2427         /* Find the lowest numbered LP1+ watermark in need of an update... */
2428         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2429                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2430                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2431                         break;
2432         }
2433
2434         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2435         for (; wm_lp <= 3; wm_lp++)
2436                 dirty |= WM_DIRTY_LP(wm_lp);
2437
2438         return dirty;
2439 }
2440
2441 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2442                                unsigned int dirty)
2443 {
2444         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2445         bool changed = false;
2446
2447         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2448                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2449                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2450                 changed = true;
2451         }
2452         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2453                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2454                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2455                 changed = true;
2456         }
2457         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2458                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2459                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2460                 changed = true;
2461         }
2462
2463         /*
2464          * Don't touch WM1S_LP_EN here.
2465          * Doing so could cause underruns.
2466          */
2467
2468         return changed;
2469 }
2470
2471 /*
2472  * The spec says we shouldn't write when we don't need, because every write
2473  * causes WMs to be re-evaluated, expending some power.
2474  */
2475 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2476                                 struct ilk_wm_values *results)
2477 {
2478         struct drm_device *dev = dev_priv->dev;
2479         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2480         unsigned int dirty;
2481         uint32_t val;
2482
2483         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2484         if (!dirty)
2485                 return;
2486
2487         _ilk_disable_lp_wm(dev_priv, dirty);
2488
2489         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2490                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2491         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2492                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2493         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2494                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2495
2496         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2497                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2498         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2499                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2500         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2501                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2502
2503         if (dirty & WM_DIRTY_DDB) {
2504                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2505                         val = I915_READ(WM_MISC);
2506                         if (results->partitioning == INTEL_DDB_PART_1_2)
2507                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2508                         else
2509                                 val |= WM_MISC_DATA_PARTITION_5_6;
2510                         I915_WRITE(WM_MISC, val);
2511                 } else {
2512                         val = I915_READ(DISP_ARB_CTL2);
2513                         if (results->partitioning == INTEL_DDB_PART_1_2)
2514                                 val &= ~DISP_DATA_PARTITION_5_6;
2515                         else
2516                                 val |= DISP_DATA_PARTITION_5_6;
2517                         I915_WRITE(DISP_ARB_CTL2, val);
2518                 }
2519         }
2520
2521         if (dirty & WM_DIRTY_FBC) {
2522                 val = I915_READ(DISP_ARB_CTL);
2523                 if (results->enable_fbc_wm)
2524                         val &= ~DISP_FBC_WM_DIS;
2525                 else
2526                         val |= DISP_FBC_WM_DIS;
2527                 I915_WRITE(DISP_ARB_CTL, val);
2528         }
2529
2530         if (dirty & WM_DIRTY_LP(1) &&
2531             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2532                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2533
2534         if (INTEL_INFO(dev)->gen >= 7) {
2535                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2536                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2537                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2538                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2539         }
2540
2541         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2542                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2543         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2544                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2545         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2546                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2547
2548         dev_priv->wm.hw = *results;
2549 }
2550
2551 static bool ilk_disable_lp_wm(struct drm_device *dev)
2552 {
2553         struct drm_i915_private *dev_priv = dev->dev_private;
2554
2555         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2556 }
2557
2558 /*
2559  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2560  * different active planes.
2561  */
2562
2563 #define SKL_DDB_SIZE            896     /* in blocks */
2564 #define BXT_DDB_SIZE            512
2565
2566 static void
2567 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2568                                    struct drm_crtc *for_crtc,
2569                                    const struct intel_wm_config *config,
2570                                    const struct skl_pipe_wm_parameters *params,
2571                                    struct skl_ddb_entry *alloc /* out */)
2572 {
2573         struct drm_crtc *crtc;
2574         unsigned int pipe_size, ddb_size;
2575         int nth_active_pipe;
2576
2577         if (!params->active) {
2578                 alloc->start = 0;
2579                 alloc->end = 0;
2580                 return;
2581         }
2582
2583         if (IS_BROXTON(dev))
2584                 ddb_size = BXT_DDB_SIZE;
2585         else
2586                 ddb_size = SKL_DDB_SIZE;
2587
2588         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2589
2590         nth_active_pipe = 0;
2591         for_each_crtc(dev, crtc) {
2592                 if (!to_intel_crtc(crtc)->active)
2593                         continue;
2594
2595                 if (crtc == for_crtc)
2596                         break;
2597
2598                 nth_active_pipe++;
2599         }
2600
2601         pipe_size = ddb_size / config->num_pipes_active;
2602         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2603         alloc->end = alloc->start + pipe_size;
2604 }
2605
2606 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2607 {
2608         if (config->num_pipes_active == 1)
2609                 return 32;
2610
2611         return 8;
2612 }
2613
2614 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2615 {
2616         entry->start = reg & 0x3ff;
2617         entry->end = (reg >> 16) & 0x3ff;
2618         if (entry->end)
2619                 entry->end += 1;
2620 }
2621
2622 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2623                           struct skl_ddb_allocation *ddb /* out */)
2624 {
2625         enum pipe pipe;
2626         int plane;
2627         u32 val;
2628
2629         for_each_pipe(dev_priv, pipe) {
2630                 for_each_plane(dev_priv, pipe, plane) {
2631                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2632                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2633                                                    val);
2634                 }
2635
2636                 val = I915_READ(CUR_BUF_CFG(pipe));
2637                 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2638         }
2639 }
2640
2641 static unsigned int
2642 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2643 {
2644
2645         /* for planar format */
2646         if (p->y_bytes_per_pixel) {
2647                 if (y)  /* y-plane data rate */
2648                         return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2649                 else    /* uv-plane data rate */
2650                         return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2651         }
2652
2653         /* for packed formats */
2654         return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2655 }
2656
2657 /*
2658  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2659  * a 8192x4096@32bpp framebuffer:
2660  *   3 * 4096 * 8192  * 4 < 2^32
2661  */
2662 static unsigned int
2663 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2664                                  const struct skl_pipe_wm_parameters *params)
2665 {
2666         unsigned int total_data_rate = 0;
2667         int plane;
2668
2669         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2670                 const struct intel_plane_wm_parameters *p;
2671
2672                 p = &params->plane[plane];
2673                 if (!p->enabled)
2674                         continue;
2675
2676                 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2677                 if (p->y_bytes_per_pixel) {
2678                         total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2679                 }
2680         }
2681
2682         return total_data_rate;
2683 }
2684
2685 static void
2686 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2687                       const struct intel_wm_config *config,
2688                       const struct skl_pipe_wm_parameters *params,
2689                       struct skl_ddb_allocation *ddb /* out */)
2690 {
2691         struct drm_device *dev = crtc->dev;
2692         struct drm_i915_private *dev_priv = dev->dev_private;
2693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2694         enum pipe pipe = intel_crtc->pipe;
2695         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2696         uint16_t alloc_size, start, cursor_blocks;
2697         uint16_t minimum[I915_MAX_PLANES];
2698         uint16_t y_minimum[I915_MAX_PLANES];
2699         unsigned int total_data_rate;
2700         int plane;
2701
2702         skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2703         alloc_size = skl_ddb_entry_size(alloc);
2704         if (alloc_size == 0) {
2705                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2706                 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2707                 return;
2708         }
2709
2710         cursor_blocks = skl_cursor_allocation(config);
2711         ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2712         ddb->cursor[pipe].end = alloc->end;
2713
2714         alloc_size -= cursor_blocks;
2715         alloc->end -= cursor_blocks;
2716
2717         /* 1. Allocate the mininum required blocks for each active plane */
2718         for_each_plane(dev_priv, pipe, plane) {
2719                 const struct intel_plane_wm_parameters *p;
2720
2721                 p = &params->plane[plane];
2722                 if (!p->enabled)
2723                         continue;
2724
2725                 minimum[plane] = 8;
2726                 alloc_size -= minimum[plane];
2727                 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2728                 alloc_size -= y_minimum[plane];
2729         }
2730
2731         /*
2732          * 2. Distribute the remaining space in proportion to the amount of
2733          * data each plane needs to fetch from memory.
2734          *
2735          * FIXME: we may not allocate every single block here.
2736          */
2737         total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2738
2739         start = alloc->start;
2740         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2741                 const struct intel_plane_wm_parameters *p;
2742                 unsigned int data_rate, y_data_rate;
2743                 uint16_t plane_blocks, y_plane_blocks = 0;
2744
2745                 p = &params->plane[plane];
2746                 if (!p->enabled)
2747                         continue;
2748
2749                 data_rate = skl_plane_relative_data_rate(p, 0);
2750
2751                 /*
2752                  * allocation for (packed formats) or (uv-plane part of planar format):
2753                  * promote the expression to 64 bits to avoid overflowing, the
2754                  * result is < available as data_rate / total_data_rate < 1
2755                  */
2756                 plane_blocks = minimum[plane];
2757                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2758                                         total_data_rate);
2759
2760                 ddb->plane[pipe][plane].start = start;
2761                 ddb->plane[pipe][plane].end = start + plane_blocks;
2762
2763                 start += plane_blocks;
2764
2765                 /*
2766                  * allocation for y_plane part of planar format:
2767                  */
2768                 if (p->y_bytes_per_pixel) {
2769                         y_data_rate = skl_plane_relative_data_rate(p, 1);
2770                         y_plane_blocks = y_minimum[plane];
2771                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2772                                                 total_data_rate);
2773
2774                         ddb->y_plane[pipe][plane].start = start;
2775                         ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2776
2777                         start += y_plane_blocks;
2778                 }
2779
2780         }
2781
2782 }
2783
2784 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2785 {
2786         /* TODO: Take into account the scalers once we support them */
2787         return config->base.adjusted_mode.crtc_clock;
2788 }
2789
2790 /*
2791  * The max latency should be 257 (max the punit can code is 255 and we add 2us
2792  * for the read latency) and bytes_per_pixel should always be <= 8, so that
2793  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2794  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2795 */
2796 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2797                                uint32_t latency)
2798 {
2799         uint32_t wm_intermediate_val, ret;
2800
2801         if (latency == 0)
2802                 return UINT_MAX;
2803
2804         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2805         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2806
2807         return ret;
2808 }
2809
2810 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2811                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2812                                uint64_t tiling, uint32_t latency)
2813 {
2814         uint32_t ret;
2815         uint32_t plane_bytes_per_line, plane_blocks_per_line;
2816         uint32_t wm_intermediate_val;
2817
2818         if (latency == 0)
2819                 return UINT_MAX;
2820
2821         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
2822
2823         if (tiling == I915_FORMAT_MOD_Y_TILED ||
2824             tiling == I915_FORMAT_MOD_Yf_TILED) {
2825                 plane_bytes_per_line *= 4;
2826                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2827                 plane_blocks_per_line /= 4;
2828         } else {
2829                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2830         }
2831
2832         wm_intermediate_val = latency * pixel_rate;
2833         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
2834                                 plane_blocks_per_line;
2835
2836         return ret;
2837 }
2838
2839 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2840                                        const struct intel_crtc *intel_crtc)
2841 {
2842         struct drm_device *dev = intel_crtc->base.dev;
2843         struct drm_i915_private *dev_priv = dev->dev_private;
2844         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2845         enum pipe pipe = intel_crtc->pipe;
2846
2847         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2848                    sizeof(new_ddb->plane[pipe])))
2849                 return true;
2850
2851         if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2852                     sizeof(new_ddb->cursor[pipe])))
2853                 return true;
2854
2855         return false;
2856 }
2857
2858 static void skl_compute_wm_global_parameters(struct drm_device *dev,
2859                                              struct intel_wm_config *config)
2860 {
2861         struct drm_crtc *crtc;
2862         struct drm_plane *plane;
2863
2864         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2865                 config->num_pipes_active += to_intel_crtc(crtc)->active;
2866
2867         /* FIXME: I don't think we need those two global parameters on SKL */
2868         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2869                 struct intel_plane *intel_plane = to_intel_plane(plane);
2870
2871                 config->sprites_enabled |= intel_plane->wm.enabled;
2872                 config->sprites_scaled |= intel_plane->wm.scaled;
2873         }
2874 }
2875
2876 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2877                                            struct skl_pipe_wm_parameters *p)
2878 {
2879         struct drm_device *dev = crtc->dev;
2880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2881         enum pipe pipe = intel_crtc->pipe;
2882         struct drm_plane *plane;
2883         struct drm_framebuffer *fb;
2884         int i = 1; /* Index for sprite planes start */
2885
2886         p->active = intel_crtc->active;
2887         if (p->active) {
2888                 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2889                 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2890
2891                 fb = crtc->primary->state->fb;
2892                 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
2893                 if (fb) {
2894                         p->plane[0].enabled = true;
2895                         p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2896                                 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
2897                         p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2898                                 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
2899                         p->plane[0].tiling = fb->modifier[0];
2900                 } else {
2901                         p->plane[0].enabled = false;
2902                         p->plane[0].bytes_per_pixel = 0;
2903                         p->plane[0].y_bytes_per_pixel = 0;
2904                         p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2905                 }
2906                 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2907                 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
2908                 p->plane[0].rotation = crtc->primary->state->rotation;
2909
2910                 fb = crtc->cursor->state->fb;
2911                 p->cursor.y_bytes_per_pixel = 0;
2912                 if (fb) {
2913                         p->cursor.enabled = true;
2914                         p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2915                         p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2916                         p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2917                 } else {
2918                         p->cursor.enabled = false;
2919                         p->cursor.bytes_per_pixel = 0;
2920                         p->cursor.horiz_pixels = 64;
2921                         p->cursor.vert_pixels = 64;
2922                 }
2923         }
2924
2925         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2926                 struct intel_plane *intel_plane = to_intel_plane(plane);
2927
2928                 if (intel_plane->pipe == pipe &&
2929                         plane->type == DRM_PLANE_TYPE_OVERLAY)
2930                         p->plane[i++] = intel_plane->wm;
2931         }
2932 }
2933
2934 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2935                                  struct skl_pipe_wm_parameters *p,
2936                                  struct intel_plane_wm_parameters *p_params,
2937                                  uint16_t ddb_allocation,
2938                                  int level,
2939                                  uint16_t *out_blocks, /* out */
2940                                  uint8_t *out_lines /* out */)
2941 {
2942         uint32_t latency = dev_priv->wm.skl_latency[level];
2943         uint32_t method1, method2;
2944         uint32_t plane_bytes_per_line, plane_blocks_per_line;
2945         uint32_t res_blocks, res_lines;
2946         uint32_t selected_result;
2947         uint8_t bytes_per_pixel;
2948
2949         if (latency == 0 || !p->active || !p_params->enabled)
2950                 return false;
2951
2952         bytes_per_pixel = p_params->y_bytes_per_pixel ?
2953                 p_params->y_bytes_per_pixel :
2954                 p_params->bytes_per_pixel;
2955         method1 = skl_wm_method1(p->pixel_rate,
2956                                  bytes_per_pixel,
2957                                  latency);
2958         method2 = skl_wm_method2(p->pixel_rate,
2959                                  p->pipe_htotal,
2960                                  p_params->horiz_pixels,
2961                                  bytes_per_pixel,
2962                                  p_params->tiling,
2963                                  latency);
2964
2965         plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
2966         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2967
2968         if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2969             p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
2970                 uint32_t min_scanlines = 4;
2971                 uint32_t y_tile_minimum;
2972                 if (intel_rotation_90_or_270(p_params->rotation)) {
2973                         switch (p_params->bytes_per_pixel) {
2974                         case 1:
2975                                 min_scanlines = 16;
2976                                 break;
2977                         case 2:
2978                                 min_scanlines = 8;
2979                                 break;
2980                         case 8:
2981                                 WARN(1, "Unsupported pixel depth for rotation");
2982                         }
2983                 }
2984                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
2985                 selected_result = max(method2, y_tile_minimum);
2986         } else {
2987                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2988                         selected_result = min(method1, method2);
2989                 else
2990                         selected_result = method1;
2991         }
2992
2993         res_blocks = selected_result + 1;
2994         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
2995
2996         if (level >= 1 && level <= 7) {
2997                 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2998                     p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2999                         res_lines += 4;
3000                 else
3001                         res_blocks++;
3002         }
3003
3004         if (res_blocks >= ddb_allocation || res_lines > 31)
3005                 return false;
3006
3007         *out_blocks = res_blocks;
3008         *out_lines = res_lines;
3009
3010         return true;
3011 }
3012
3013 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3014                                  struct skl_ddb_allocation *ddb,
3015                                  struct skl_pipe_wm_parameters *p,
3016                                  enum pipe pipe,
3017                                  int level,
3018                                  int num_planes,
3019                                  struct skl_wm_level *result)
3020 {
3021         uint16_t ddb_blocks;
3022         int i;
3023
3024         for (i = 0; i < num_planes; i++) {
3025                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3026
3027                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3028                                                 p, &p->plane[i],
3029                                                 ddb_blocks,
3030                                                 level,
3031                                                 &result->plane_res_b[i],
3032                                                 &result->plane_res_l[i]);
3033         }
3034
3035         ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3036         result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3037                                                  ddb_blocks, level,
3038                                                  &result->cursor_res_b,
3039                                                  &result->cursor_res_l);
3040 }
3041
3042 static uint32_t
3043 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3044 {
3045         if (!to_intel_crtc(crtc)->active)
3046                 return 0;
3047
3048         return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3049
3050 }
3051
3052 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3053                                       struct skl_pipe_wm_parameters *params,
3054                                       struct skl_wm_level *trans_wm /* out */)
3055 {
3056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3057         int i;
3058
3059         if (!params->active)
3060                 return;
3061
3062         /* Until we know more, just disable transition WMs */
3063         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3064                 trans_wm->plane_en[i] = false;
3065         trans_wm->cursor_en = false;
3066 }
3067
3068 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3069                                 struct skl_ddb_allocation *ddb,
3070                                 struct skl_pipe_wm_parameters *params,
3071                                 struct skl_pipe_wm *pipe_wm)
3072 {
3073         struct drm_device *dev = crtc->dev;
3074         const struct drm_i915_private *dev_priv = dev->dev_private;
3075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076         int level, max_level = ilk_wm_max_level(dev);
3077
3078         for (level = 0; level <= max_level; level++) {
3079                 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3080                                      level, intel_num_planes(intel_crtc),
3081                                      &pipe_wm->wm[level]);
3082         }
3083         pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3084
3085         skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3086 }
3087
3088 static void skl_compute_wm_results(struct drm_device *dev,
3089                                    struct skl_pipe_wm_parameters *p,
3090                                    struct skl_pipe_wm *p_wm,
3091                                    struct skl_wm_values *r,
3092                                    struct intel_crtc *intel_crtc)
3093 {
3094         int level, max_level = ilk_wm_max_level(dev);
3095         enum pipe pipe = intel_crtc->pipe;
3096         uint32_t temp;
3097         int i;
3098
3099         for (level = 0; level <= max_level; level++) {
3100                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3101                         temp = 0;
3102
3103                         temp |= p_wm->wm[level].plane_res_l[i] <<
3104                                         PLANE_WM_LINES_SHIFT;
3105                         temp |= p_wm->wm[level].plane_res_b[i];
3106                         if (p_wm->wm[level].plane_en[i])
3107                                 temp |= PLANE_WM_EN;
3108
3109                         r->plane[pipe][i][level] = temp;
3110                 }
3111
3112                 temp = 0;
3113
3114                 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3115                 temp |= p_wm->wm[level].cursor_res_b;
3116
3117                 if (p_wm->wm[level].cursor_en)
3118                         temp |= PLANE_WM_EN;
3119
3120                 r->cursor[pipe][level] = temp;
3121
3122         }
3123
3124         /* transition WMs */
3125         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3126                 temp = 0;
3127                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3128                 temp |= p_wm->trans_wm.plane_res_b[i];
3129                 if (p_wm->trans_wm.plane_en[i])
3130                         temp |= PLANE_WM_EN;
3131
3132                 r->plane_trans[pipe][i] = temp;
3133         }
3134
3135         temp = 0;
3136         temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3137         temp |= p_wm->trans_wm.cursor_res_b;
3138         if (p_wm->trans_wm.cursor_en)
3139                 temp |= PLANE_WM_EN;
3140
3141         r->cursor_trans[pipe] = temp;
3142
3143         r->wm_linetime[pipe] = p_wm->linetime;
3144 }
3145
3146 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3147                                 const struct skl_ddb_entry *entry)
3148 {
3149         if (entry->end)
3150                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3151         else
3152                 I915_WRITE(reg, 0);
3153 }
3154
3155 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3156                                 const struct skl_wm_values *new)
3157 {
3158         struct drm_device *dev = dev_priv->dev;
3159         struct intel_crtc *crtc;
3160
3161         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3162                 int i, level, max_level = ilk_wm_max_level(dev);
3163                 enum pipe pipe = crtc->pipe;
3164
3165                 if (!new->dirty[pipe])
3166                         continue;
3167
3168                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3169
3170                 for (level = 0; level <= max_level; level++) {
3171                         for (i = 0; i < intel_num_planes(crtc); i++)
3172                                 I915_WRITE(PLANE_WM(pipe, i, level),
3173                                            new->plane[pipe][i][level]);
3174                         I915_WRITE(CUR_WM(pipe, level),
3175                                    new->cursor[pipe][level]);
3176                 }
3177                 for (i = 0; i < intel_num_planes(crtc); i++)
3178                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3179                                    new->plane_trans[pipe][i]);
3180                 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3181
3182                 for (i = 0; i < intel_num_planes(crtc); i++) {
3183                         skl_ddb_entry_write(dev_priv,
3184                                             PLANE_BUF_CFG(pipe, i),
3185                                             &new->ddb.plane[pipe][i]);
3186                         skl_ddb_entry_write(dev_priv,
3187                                             PLANE_NV12_BUF_CFG(pipe, i),
3188                                             &new->ddb.y_plane[pipe][i]);
3189                 }
3190
3191                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3192                                     &new->ddb.cursor[pipe]);
3193         }
3194 }
3195
3196 /*
3197  * When setting up a new DDB allocation arrangement, we need to correctly
3198  * sequence the times at which the new allocations for the pipes are taken into
3199  * account or we'll have pipes fetching from space previously allocated to
3200  * another pipe.
3201  *
3202  * Roughly the sequence looks like:
3203  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3204  *     overlapping with a previous light-up pipe (another way to put it is:
3205  *     pipes with their new allocation strickly included into their old ones).
3206  *  2. re-allocate the other pipes that get their allocation reduced
3207  *  3. allocate the pipes having their allocation increased
3208  *
3209  * Steps 1. and 2. are here to take care of the following case:
3210  * - Initially DDB looks like this:
3211  *     |   B    |   C    |
3212  * - enable pipe A.
3213  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3214  *   allocation
3215  *     |  A  |  B  |  C  |
3216  *
3217  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3218  */
3219
3220 static void
3221 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3222 {
3223         int plane;
3224
3225         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3226
3227         for_each_plane(dev_priv, pipe, plane) {
3228                 I915_WRITE(PLANE_SURF(pipe, plane),
3229                            I915_READ(PLANE_SURF(pipe, plane)));
3230         }
3231         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3232 }
3233
3234 static bool
3235 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3236                             const struct skl_ddb_allocation *new,
3237                             enum pipe pipe)
3238 {
3239         uint16_t old_size, new_size;
3240
3241         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3242         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3243
3244         return old_size != new_size &&
3245                new->pipe[pipe].start >= old->pipe[pipe].start &&
3246                new->pipe[pipe].end <= old->pipe[pipe].end;
3247 }
3248
3249 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3250                                 struct skl_wm_values *new_values)
3251 {
3252         struct drm_device *dev = dev_priv->dev;
3253         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3254         bool reallocated[I915_MAX_PIPES] = {};
3255         struct intel_crtc *crtc;
3256         enum pipe pipe;
3257
3258         new_ddb = &new_values->ddb;
3259         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3260
3261         /*
3262          * First pass: flush the pipes with the new allocation contained into
3263          * the old space.
3264          *
3265          * We'll wait for the vblank on those pipes to ensure we can safely
3266          * re-allocate the freed space without this pipe fetching from it.
3267          */
3268         for_each_intel_crtc(dev, crtc) {
3269                 if (!crtc->active)
3270                         continue;
3271
3272                 pipe = crtc->pipe;
3273
3274                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3275                         continue;
3276
3277                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3278                 intel_wait_for_vblank(dev, pipe);
3279
3280                 reallocated[pipe] = true;
3281         }
3282
3283
3284         /*
3285          * Second pass: flush the pipes that are having their allocation
3286          * reduced, but overlapping with a previous allocation.
3287          *
3288          * Here as well we need to wait for the vblank to make sure the freed
3289          * space is not used anymore.
3290          */
3291         for_each_intel_crtc(dev, crtc) {
3292                 if (!crtc->active)
3293                         continue;
3294
3295                 pipe = crtc->pipe;
3296
3297                 if (reallocated[pipe])
3298                         continue;
3299
3300                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3301                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3302                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3303                         intel_wait_for_vblank(dev, pipe);
3304                         reallocated[pipe] = true;
3305                 }
3306         }
3307
3308         /*
3309          * Third pass: flush the pipes that got more space allocated.
3310          *
3311          * We don't need to actively wait for the update here, next vblank
3312          * will just get more DDB space with the correct WM values.
3313          */
3314         for_each_intel_crtc(dev, crtc) {
3315                 if (!crtc->active)
3316                         continue;
3317
3318                 pipe = crtc->pipe;
3319
3320                 /*
3321                  * At this point, only the pipes more space than before are
3322                  * left to re-allocate.
3323                  */
3324                 if (reallocated[pipe])
3325                         continue;
3326
3327                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3328         }
3329 }
3330
3331 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3332                                struct skl_pipe_wm_parameters *params,
3333                                struct intel_wm_config *config,
3334                                struct skl_ddb_allocation *ddb, /* out */
3335                                struct skl_pipe_wm *pipe_wm /* out */)
3336 {
3337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338
3339         skl_compute_wm_pipe_parameters(crtc, params);
3340         skl_allocate_pipe_ddb(crtc, config, params, ddb);
3341         skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3342
3343         if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3344                 return false;
3345
3346         intel_crtc->wm.skl_active = *pipe_wm;
3347
3348         return true;
3349 }
3350
3351 static void skl_update_other_pipe_wm(struct drm_device *dev,
3352                                      struct drm_crtc *crtc,
3353                                      struct intel_wm_config *config,
3354                                      struct skl_wm_values *r)
3355 {
3356         struct intel_crtc *intel_crtc;
3357         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3358
3359         /*
3360          * If the WM update hasn't changed the allocation for this_crtc (the
3361          * crtc we are currently computing the new WM values for), other
3362          * enabled crtcs will keep the same allocation and we don't need to
3363          * recompute anything for them.
3364          */
3365         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3366                 return;
3367
3368         /*
3369          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3370          * other active pipes need new DDB allocation and WM values.
3371          */
3372         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3373                                 base.head) {
3374                 struct skl_pipe_wm_parameters params = {};
3375                 struct skl_pipe_wm pipe_wm = {};
3376                 bool wm_changed;
3377
3378                 if (this_crtc->pipe == intel_crtc->pipe)
3379                         continue;
3380
3381                 if (!intel_crtc->active)
3382                         continue;
3383
3384                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3385                                                 &params, config,
3386                                                 &r->ddb, &pipe_wm);
3387
3388                 /*
3389                  * If we end up re-computing the other pipe WM values, it's
3390                  * because it was really needed, so we expect the WM values to
3391                  * be different.
3392                  */
3393                 WARN_ON(!wm_changed);
3394
3395                 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3396                 r->dirty[intel_crtc->pipe] = true;
3397         }
3398 }
3399
3400 static void skl_update_wm(struct drm_crtc *crtc)
3401 {
3402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3403         struct drm_device *dev = crtc->dev;
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         struct skl_pipe_wm_parameters params = {};
3406         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3407         struct skl_pipe_wm pipe_wm = {};
3408         struct intel_wm_config config = {};
3409
3410         memset(results, 0, sizeof(*results));
3411
3412         skl_compute_wm_global_parameters(dev, &config);
3413
3414         if (!skl_update_pipe_wm(crtc, &params, &config,
3415                                 &results->ddb, &pipe_wm))
3416                 return;
3417
3418         skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3419         results->dirty[intel_crtc->pipe] = true;
3420
3421         skl_update_other_pipe_wm(dev, crtc, &config, results);
3422         skl_write_wm_values(dev_priv, results);
3423         skl_flush_wm_values(dev_priv, results);
3424
3425         /* store the new configuration */
3426         dev_priv->wm.skl_hw = *results;
3427 }
3428
3429 static void
3430 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3431                      uint32_t sprite_width, uint32_t sprite_height,
3432                      int pixel_size, bool enabled, bool scaled)
3433 {
3434         struct intel_plane *intel_plane = to_intel_plane(plane);
3435         struct drm_framebuffer *fb = plane->state->fb;
3436
3437         intel_plane->wm.enabled = enabled;
3438         intel_plane->wm.scaled = scaled;
3439         intel_plane->wm.horiz_pixels = sprite_width;
3440         intel_plane->wm.vert_pixels = sprite_height;
3441         intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3442
3443         /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3444         intel_plane->wm.bytes_per_pixel =
3445                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3446                 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3447         intel_plane->wm.y_bytes_per_pixel =
3448                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3449                 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3450
3451         /*
3452          * Framebuffer can be NULL on plane disable, but it does not
3453          * matter for watermarks if we assume no tiling in that case.
3454          */
3455         if (fb)
3456                 intel_plane->wm.tiling = fb->modifier[0];
3457         intel_plane->wm.rotation = plane->state->rotation;
3458
3459         skl_update_wm(crtc);
3460 }
3461
3462 static void ilk_update_wm(struct drm_crtc *crtc)
3463 {
3464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3465         struct drm_device *dev = crtc->dev;
3466         struct drm_i915_private *dev_priv = dev->dev_private;
3467         struct ilk_wm_maximums max;
3468         struct ilk_pipe_wm_parameters params = {};
3469         struct ilk_wm_values results = {};
3470         enum intel_ddb_partitioning partitioning;
3471         struct intel_pipe_wm pipe_wm = {};
3472         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3473         struct intel_wm_config config = {};
3474
3475         ilk_compute_wm_parameters(crtc, &params);
3476
3477         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3478
3479         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3480                 return;
3481
3482         intel_crtc->wm.active = pipe_wm;
3483
3484         ilk_compute_wm_config(dev, &config);
3485
3486         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3487         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3488
3489         /* 5/6 split only in single pipe config on IVB+ */
3490         if (INTEL_INFO(dev)->gen >= 7 &&
3491             config.num_pipes_active == 1 && config.sprites_enabled) {
3492                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3493                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3494
3495                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3496         } else {
3497                 best_lp_wm = &lp_wm_1_2;
3498         }
3499
3500         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3501                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3502
3503         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3504
3505         ilk_write_wm_values(dev_priv, &results);
3506 }
3507
3508 static void
3509 ilk_update_sprite_wm(struct drm_plane *plane,
3510                      struct drm_crtc *crtc,
3511                      uint32_t sprite_width, uint32_t sprite_height,
3512                      int pixel_size, bool enabled, bool scaled)
3513 {
3514         struct drm_device *dev = plane->dev;
3515         struct intel_plane *intel_plane = to_intel_plane(plane);
3516
3517         intel_plane->wm.enabled = enabled;
3518         intel_plane->wm.scaled = scaled;
3519         intel_plane->wm.horiz_pixels = sprite_width;
3520         intel_plane->wm.vert_pixels = sprite_width;
3521         intel_plane->wm.bytes_per_pixel = pixel_size;
3522
3523         /*
3524          * IVB workaround: must disable low power watermarks for at least
3525          * one frame before enabling scaling.  LP watermarks can be re-enabled
3526          * when scaling is disabled.
3527          *
3528          * WaCxSRDisabledForSpriteScaling:ivb
3529          */
3530         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3531                 intel_wait_for_vblank(dev, intel_plane->pipe);
3532
3533         ilk_update_wm(crtc);
3534 }
3535
3536 static void skl_pipe_wm_active_state(uint32_t val,
3537                                      struct skl_pipe_wm *active,
3538                                      bool is_transwm,
3539                                      bool is_cursor,
3540                                      int i,
3541                                      int level)
3542 {
3543         bool is_enabled = (val & PLANE_WM_EN) != 0;
3544
3545         if (!is_transwm) {
3546                 if (!is_cursor) {
3547                         active->wm[level].plane_en[i] = is_enabled;
3548                         active->wm[level].plane_res_b[i] =
3549                                         val & PLANE_WM_BLOCKS_MASK;
3550                         active->wm[level].plane_res_l[i] =
3551                                         (val >> PLANE_WM_LINES_SHIFT) &
3552                                                 PLANE_WM_LINES_MASK;
3553                 } else {
3554                         active->wm[level].cursor_en = is_enabled;
3555                         active->wm[level].cursor_res_b =
3556                                         val & PLANE_WM_BLOCKS_MASK;
3557                         active->wm[level].cursor_res_l =
3558                                         (val >> PLANE_WM_LINES_SHIFT) &
3559                                                 PLANE_WM_LINES_MASK;
3560                 }
3561         } else {
3562                 if (!is_cursor) {
3563                         active->trans_wm.plane_en[i] = is_enabled;
3564                         active->trans_wm.plane_res_b[i] =
3565                                         val & PLANE_WM_BLOCKS_MASK;
3566                         active->trans_wm.plane_res_l[i] =
3567                                         (val >> PLANE_WM_LINES_SHIFT) &
3568                                                 PLANE_WM_LINES_MASK;
3569                 } else {
3570                         active->trans_wm.cursor_en = is_enabled;
3571                         active->trans_wm.cursor_res_b =
3572                                         val & PLANE_WM_BLOCKS_MASK;
3573                         active->trans_wm.cursor_res_l =
3574                                         (val >> PLANE_WM_LINES_SHIFT) &
3575                                                 PLANE_WM_LINES_MASK;
3576                 }
3577         }
3578 }
3579
3580 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3581 {
3582         struct drm_device *dev = crtc->dev;
3583         struct drm_i915_private *dev_priv = dev->dev_private;
3584         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586         struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3587         enum pipe pipe = intel_crtc->pipe;
3588         int level, i, max_level;
3589         uint32_t temp;
3590
3591         max_level = ilk_wm_max_level(dev);
3592
3593         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3594
3595         for (level = 0; level <= max_level; level++) {
3596                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3597                         hw->plane[pipe][i][level] =
3598                                         I915_READ(PLANE_WM(pipe, i, level));
3599                 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3600         }
3601
3602         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3603                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3604         hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3605
3606         if (!intel_crtc->active)
3607                 return;
3608
3609         hw->dirty[pipe] = true;
3610
3611         active->linetime = hw->wm_linetime[pipe];
3612
3613         for (level = 0; level <= max_level; level++) {
3614                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3615                         temp = hw->plane[pipe][i][level];
3616                         skl_pipe_wm_active_state(temp, active, false,
3617                                                 false, i, level);
3618                 }
3619                 temp = hw->cursor[pipe][level];
3620                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3621         }
3622
3623         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3624                 temp = hw->plane_trans[pipe][i];
3625                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3626         }
3627
3628         temp = hw->cursor_trans[pipe];
3629         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3630 }
3631
3632 void skl_wm_get_hw_state(struct drm_device *dev)
3633 {
3634         struct drm_i915_private *dev_priv = dev->dev_private;
3635         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3636         struct drm_crtc *crtc;
3637
3638         skl_ddb_get_hw_state(dev_priv, ddb);
3639         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3640                 skl_pipe_wm_get_hw_state(crtc);
3641 }
3642
3643 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3644 {
3645         struct drm_device *dev = crtc->dev;
3646         struct drm_i915_private *dev_priv = dev->dev_private;
3647         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3650         enum pipe pipe = intel_crtc->pipe;
3651         static const unsigned int wm0_pipe_reg[] = {
3652                 [PIPE_A] = WM0_PIPEA_ILK,
3653                 [PIPE_B] = WM0_PIPEB_ILK,
3654                 [PIPE_C] = WM0_PIPEC_IVB,
3655         };
3656
3657         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3658         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3659                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3660
3661         active->pipe_enabled = intel_crtc->active;
3662
3663         if (active->pipe_enabled) {
3664                 u32 tmp = hw->wm_pipe[pipe];
3665
3666                 /*
3667                  * For active pipes LP0 watermark is marked as
3668                  * enabled, and LP1+ watermaks as disabled since
3669                  * we can't really reverse compute them in case
3670                  * multiple pipes are active.
3671                  */
3672                 active->wm[0].enable = true;
3673                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3674                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3675                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3676                 active->linetime = hw->wm_linetime[pipe];
3677         } else {
3678                 int level, max_level = ilk_wm_max_level(dev);
3679
3680                 /*
3681                  * For inactive pipes, all watermark levels
3682                  * should be marked as enabled but zeroed,
3683                  * which is what we'd compute them to.
3684                  */
3685                 for (level = 0; level <= max_level; level++)
3686                         active->wm[level].enable = true;
3687         }
3688 }
3689
3690 void ilk_wm_get_hw_state(struct drm_device *dev)
3691 {
3692         struct drm_i915_private *dev_priv = dev->dev_private;
3693         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3694         struct drm_crtc *crtc;
3695
3696         for_each_crtc(dev, crtc)
3697                 ilk_pipe_wm_get_hw_state(crtc);
3698
3699         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3700         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3701         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3702
3703         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3704         if (INTEL_INFO(dev)->gen >= 7) {
3705                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3706                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3707         }
3708
3709         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3710                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3711                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3712         else if (IS_IVYBRIDGE(dev))
3713                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3714                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3715
3716         hw->enable_fbc_wm =
3717                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3718 }
3719
3720 /**
3721  * intel_update_watermarks - update FIFO watermark values based on current modes
3722  *
3723  * Calculate watermark values for the various WM regs based on current mode
3724  * and plane configuration.
3725  *
3726  * There are several cases to deal with here:
3727  *   - normal (i.e. non-self-refresh)
3728  *   - self-refresh (SR) mode
3729  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3730  *   - lines are small relative to FIFO size (buffer can hold more than 2
3731  *     lines), so need to account for TLB latency
3732  *
3733  *   The normal calculation is:
3734  *     watermark = dotclock * bytes per pixel * latency
3735  *   where latency is platform & configuration dependent (we assume pessimal
3736  *   values here).
3737  *
3738  *   The SR calculation is:
3739  *     watermark = (trunc(latency/line time)+1) * surface width *
3740  *       bytes per pixel
3741  *   where
3742  *     line time = htotal / dotclock
3743  *     surface width = hdisplay for normal plane and 64 for cursor
3744  *   and latency is assumed to be high, as above.
3745  *
3746  * The final value programmed to the register should always be rounded up,
3747  * and include an extra 2 entries to account for clock crossings.
3748  *
3749  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3750  * to set the non-SR watermarks to 8.
3751  */
3752 void intel_update_watermarks(struct drm_crtc *crtc)
3753 {
3754         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3755
3756         if (dev_priv->display.update_wm)
3757                 dev_priv->display.update_wm(crtc);
3758 }
3759
3760 void intel_update_sprite_watermarks(struct drm_plane *plane,
3761                                     struct drm_crtc *crtc,
3762                                     uint32_t sprite_width,
3763                                     uint32_t sprite_height,
3764                                     int pixel_size,
3765                                     bool enabled, bool scaled)
3766 {
3767         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3768
3769         if (dev_priv->display.update_sprite_wm)
3770                 dev_priv->display.update_sprite_wm(plane, crtc,
3771                                                    sprite_width, sprite_height,
3772                                                    pixel_size, enabled, scaled);
3773 }
3774
3775 /**
3776  * Lock protecting IPS related data structures
3777  */
3778 DEFINE_SPINLOCK(mchdev_lock);
3779
3780 /* Global for IPS driver to get at the current i915 device. Protected by
3781  * mchdev_lock. */
3782 static struct drm_i915_private *i915_mch_dev;
3783
3784 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3785 {
3786         struct drm_i915_private *dev_priv = dev->dev_private;
3787         u16 rgvswctl;
3788
3789         assert_spin_locked(&mchdev_lock);
3790
3791         rgvswctl = I915_READ16(MEMSWCTL);
3792         if (rgvswctl & MEMCTL_CMD_STS) {
3793                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3794                 return false; /* still busy with another command */
3795         }
3796
3797         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3798                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3799         I915_WRITE16(MEMSWCTL, rgvswctl);
3800         POSTING_READ16(MEMSWCTL);
3801
3802         rgvswctl |= MEMCTL_CMD_STS;
3803         I915_WRITE16(MEMSWCTL, rgvswctl);
3804
3805         return true;
3806 }
3807
3808 static void ironlake_enable_drps(struct drm_device *dev)
3809 {
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811         u32 rgvmodectl = I915_READ(MEMMODECTL);
3812         u8 fmax, fmin, fstart, vstart;
3813
3814         spin_lock_irq(&mchdev_lock);
3815
3816         /* Enable temp reporting */
3817         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3818         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3819
3820         /* 100ms RC evaluation intervals */
3821         I915_WRITE(RCUPEI, 100000);
3822         I915_WRITE(RCDNEI, 100000);
3823
3824         /* Set max/min thresholds to 90ms and 80ms respectively */
3825         I915_WRITE(RCBMAXAVG, 90000);
3826         I915_WRITE(RCBMINAVG, 80000);
3827
3828         I915_WRITE(MEMIHYST, 1);
3829
3830         /* Set up min, max, and cur for interrupt handling */
3831         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3832         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3833         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3834                 MEMMODE_FSTART_SHIFT;
3835
3836         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3837                 PXVFREQ_PX_SHIFT;
3838
3839         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3840         dev_priv->ips.fstart = fstart;
3841
3842         dev_priv->ips.max_delay = fstart;
3843         dev_priv->ips.min_delay = fmin;
3844         dev_priv->ips.cur_delay = fstart;
3845
3846         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3847                          fmax, fmin, fstart);
3848
3849         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3850
3851         /*
3852          * Interrupts will be enabled in ironlake_irq_postinstall
3853          */
3854
3855         I915_WRITE(VIDSTART, vstart);
3856         POSTING_READ(VIDSTART);
3857
3858         rgvmodectl |= MEMMODE_SWMODE_EN;
3859         I915_WRITE(MEMMODECTL, rgvmodectl);
3860
3861         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3862                 DRM_ERROR("stuck trying to change perf mode\n");
3863         mdelay(1);
3864
3865         ironlake_set_drps(dev, fstart);
3866
3867         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3868                 I915_READ(0x112e0);
3869         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3870         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3871         dev_priv->ips.last_time2 = ktime_get_raw_ns();
3872
3873         spin_unlock_irq(&mchdev_lock);
3874 }
3875
3876 static void ironlake_disable_drps(struct drm_device *dev)
3877 {
3878         struct drm_i915_private *dev_priv = dev->dev_private;
3879         u16 rgvswctl;
3880
3881         spin_lock_irq(&mchdev_lock);
3882
3883         rgvswctl = I915_READ16(MEMSWCTL);
3884
3885         /* Ack interrupts, disable EFC interrupt */
3886         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3887         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3888         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3889         I915_WRITE(DEIIR, DE_PCU_EVENT);
3890         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3891
3892         /* Go back to the starting frequency */
3893         ironlake_set_drps(dev, dev_priv->ips.fstart);
3894         mdelay(1);
3895         rgvswctl |= MEMCTL_CMD_STS;
3896         I915_WRITE(MEMSWCTL, rgvswctl);
3897         mdelay(1);
3898
3899         spin_unlock_irq(&mchdev_lock);
3900 }
3901
3902 /* There's a funny hw issue where the hw returns all 0 when reading from
3903  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3904  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3905  * all limits and the gpu stuck at whatever frequency it is at atm).
3906  */
3907 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3908 {
3909         u32 limits;
3910
3911         /* Only set the down limit when we've reached the lowest level to avoid
3912          * getting more interrupts, otherwise leave this clear. This prevents a
3913          * race in the hw when coming out of rc6: There's a tiny window where
3914          * the hw runs at the minimal clock before selecting the desired
3915          * frequency, if the down threshold expires in that window we will not
3916          * receive a down interrupt. */
3917         if (IS_GEN9(dev_priv->dev)) {
3918                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3919                 if (val <= dev_priv->rps.min_freq_softlimit)
3920                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3921         } else {
3922                 limits = dev_priv->rps.max_freq_softlimit << 24;
3923                 if (val <= dev_priv->rps.min_freq_softlimit)
3924                         limits |= dev_priv->rps.min_freq_softlimit << 16;
3925         }
3926
3927         return limits;
3928 }
3929
3930 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3931 {
3932         int new_power;
3933         u32 threshold_up = 0, threshold_down = 0; /* in % */
3934         u32 ei_up = 0, ei_down = 0;
3935
3936         new_power = dev_priv->rps.power;
3937         switch (dev_priv->rps.power) {
3938         case LOW_POWER:
3939                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3940                         new_power = BETWEEN;
3941                 break;
3942
3943         case BETWEEN:
3944                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3945                         new_power = LOW_POWER;
3946                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3947                         new_power = HIGH_POWER;
3948                 break;
3949
3950         case HIGH_POWER:
3951                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3952                         new_power = BETWEEN;
3953                 break;
3954         }
3955         /* Max/min bins are special */
3956         if (val <= dev_priv->rps.min_freq_softlimit)
3957                 new_power = LOW_POWER;
3958         if (val >= dev_priv->rps.max_freq_softlimit)
3959                 new_power = HIGH_POWER;
3960         if (new_power == dev_priv->rps.power)
3961                 return;
3962
3963         /* Note the units here are not exactly 1us, but 1280ns. */
3964         switch (new_power) {
3965         case LOW_POWER:
3966                 /* Upclock if more than 95% busy over 16ms */
3967                 ei_up = 16000;
3968                 threshold_up = 95;
3969
3970                 /* Downclock if less than 85% busy over 32ms */
3971                 ei_down = 32000;
3972                 threshold_down = 85;
3973                 break;
3974
3975         case BETWEEN:
3976                 /* Upclock if more than 90% busy over 13ms */
3977                 ei_up = 13000;
3978                 threshold_up = 90;
3979
3980                 /* Downclock if less than 75% busy over 32ms */
3981                 ei_down = 32000;
3982                 threshold_down = 75;
3983                 break;
3984
3985         case HIGH_POWER:
3986                 /* Upclock if more than 85% busy over 10ms */
3987                 ei_up = 10000;
3988                 threshold_up = 85;
3989
3990                 /* Downclock if less than 60% busy over 32ms */
3991                 ei_down = 32000;
3992                 threshold_down = 60;
3993                 break;
3994         }
3995
3996         I915_WRITE(GEN6_RP_UP_EI,
3997                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3998         I915_WRITE(GEN6_RP_UP_THRESHOLD,
3999                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4000
4001         I915_WRITE(GEN6_RP_DOWN_EI,
4002                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4003         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4004                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4005
4006          I915_WRITE(GEN6_RP_CONTROL,
4007                     GEN6_RP_MEDIA_TURBO |
4008                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4009                     GEN6_RP_MEDIA_IS_GFX |
4010                     GEN6_RP_ENABLE |
4011                     GEN6_RP_UP_BUSY_AVG |
4012                     GEN6_RP_DOWN_IDLE_AVG);
4013
4014         dev_priv->rps.power = new_power;
4015         dev_priv->rps.up_threshold = threshold_up;
4016         dev_priv->rps.down_threshold = threshold_down;
4017         dev_priv->rps.last_adj = 0;
4018 }
4019
4020 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4021 {
4022         u32 mask = 0;
4023
4024         if (val > dev_priv->rps.min_freq_softlimit)
4025                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4026         if (val < dev_priv->rps.max_freq_softlimit)
4027                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4028
4029         mask &= dev_priv->pm_rps_events;
4030
4031         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4032 }
4033
4034 /* gen6_set_rps is called to update the frequency request, but should also be
4035  * called when the range (min_delay and max_delay) is modified so that we can
4036  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4037 static void gen6_set_rps(struct drm_device *dev, u8 val)
4038 {
4039         struct drm_i915_private *dev_priv = dev->dev_private;
4040
4041         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4042         WARN_ON(val > dev_priv->rps.max_freq);
4043         WARN_ON(val < dev_priv->rps.min_freq);
4044
4045         /* min/max delay may still have been modified so be sure to
4046          * write the limits value.
4047          */
4048         if (val != dev_priv->rps.cur_freq) {
4049                 gen6_set_rps_thresholds(dev_priv, val);
4050
4051                 if (IS_GEN9(dev))
4052                         I915_WRITE(GEN6_RPNSWREQ,
4053                                    GEN9_FREQUENCY(val));
4054                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4055                         I915_WRITE(GEN6_RPNSWREQ,
4056                                    HSW_FREQUENCY(val));
4057                 else
4058                         I915_WRITE(GEN6_RPNSWREQ,
4059                                    GEN6_FREQUENCY(val) |
4060                                    GEN6_OFFSET(0) |
4061                                    GEN6_AGGRESSIVE_TURBO);
4062         }
4063
4064         /* Make sure we continue to get interrupts
4065          * until we hit the minimum or maximum frequencies.
4066          */
4067         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4068         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4069
4070         POSTING_READ(GEN6_RPNSWREQ);
4071
4072         dev_priv->rps.cur_freq = val;
4073         trace_intel_gpu_freq_change(val * 50);
4074 }
4075
4076 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4077 {
4078         struct drm_i915_private *dev_priv = dev->dev_private;
4079
4080         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4081         WARN_ON(val > dev_priv->rps.max_freq);
4082         WARN_ON(val < dev_priv->rps.min_freq);
4083
4084         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4085                       "Odd GPU freq value\n"))
4086                 val &= ~1;
4087
4088         if (val != dev_priv->rps.cur_freq) {
4089                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4090                 if (!IS_CHERRYVIEW(dev_priv))
4091                         gen6_set_rps_thresholds(dev_priv, val);
4092         }
4093
4094         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4095
4096         dev_priv->rps.cur_freq = val;
4097         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4098 }
4099
4100 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4101  *
4102  * * If Gfx is Idle, then
4103  * 1. Forcewake Media well.
4104  * 2. Request idle freq.
4105  * 3. Release Forcewake of Media well.
4106 */
4107 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4108 {
4109         u32 val = dev_priv->rps.idle_freq;
4110
4111         if (dev_priv->rps.cur_freq <= val)
4112                 return;
4113
4114         /* Wake up the media well, as that takes a lot less
4115          * power than the Render well. */
4116         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4117         valleyview_set_rps(dev_priv->dev, val);
4118         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4119 }
4120
4121 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4122 {
4123         mutex_lock(&dev_priv->rps.hw_lock);
4124         if (dev_priv->rps.enabled) {
4125                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4126                         gen6_rps_reset_ei(dev_priv);
4127                 I915_WRITE(GEN6_PMINTRMSK,
4128                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4129         }
4130         mutex_unlock(&dev_priv->rps.hw_lock);
4131 }
4132
4133 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4134 {
4135         struct drm_device *dev = dev_priv->dev;
4136
4137         mutex_lock(&dev_priv->rps.hw_lock);
4138         if (dev_priv->rps.enabled) {
4139                 if (IS_VALLEYVIEW(dev))
4140                         vlv_set_rps_idle(dev_priv);
4141                 else
4142                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4143                 dev_priv->rps.last_adj = 0;
4144                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4145         }
4146
4147         while (!list_empty(&dev_priv->rps.clients))
4148                 list_del_init(dev_priv->rps.clients.next);
4149         mutex_unlock(&dev_priv->rps.hw_lock);
4150 }
4151
4152 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4153                     struct drm_i915_file_private *file_priv)
4154 {
4155         u32 val;
4156
4157         mutex_lock(&dev_priv->rps.hw_lock);
4158         val = dev_priv->rps.max_freq_softlimit;
4159         if (dev_priv->rps.enabled &&
4160             dev_priv->mm.busy &&
4161             dev_priv->rps.cur_freq < val &&
4162             (file_priv == NULL || list_empty(&file_priv->rps_boost))) {
4163                 intel_set_rps(dev_priv->dev, val);
4164                 dev_priv->rps.last_adj = 0;
4165
4166                 if (file_priv != NULL) {
4167                         list_add(&file_priv->rps_boost, &dev_priv->rps.clients);
4168                         file_priv->rps_boosts++;
4169                 } else
4170                         dev_priv->rps.boosts++;
4171         }
4172         mutex_unlock(&dev_priv->rps.hw_lock);
4173 }
4174
4175 void intel_set_rps(struct drm_device *dev, u8 val)
4176 {
4177         if (IS_VALLEYVIEW(dev))
4178                 valleyview_set_rps(dev, val);
4179         else
4180                 gen6_set_rps(dev, val);
4181 }
4182
4183 static void gen9_disable_rps(struct drm_device *dev)
4184 {
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186
4187         I915_WRITE(GEN6_RC_CONTROL, 0);
4188         I915_WRITE(GEN9_PG_ENABLE, 0);
4189 }
4190
4191 static void gen6_disable_rps(struct drm_device *dev)
4192 {
4193         struct drm_i915_private *dev_priv = dev->dev_private;
4194
4195         I915_WRITE(GEN6_RC_CONTROL, 0);
4196         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4197 }
4198
4199 static void cherryview_disable_rps(struct drm_device *dev)
4200 {
4201         struct drm_i915_private *dev_priv = dev->dev_private;
4202
4203         I915_WRITE(GEN6_RC_CONTROL, 0);
4204 }
4205
4206 static void valleyview_disable_rps(struct drm_device *dev)
4207 {
4208         struct drm_i915_private *dev_priv = dev->dev_private;
4209
4210         /* we're doing forcewake before Disabling RC6,
4211          * This what the BIOS expects when going into suspend */
4212         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4213
4214         I915_WRITE(GEN6_RC_CONTROL, 0);
4215
4216         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4217 }
4218
4219 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4220 {
4221         if (IS_VALLEYVIEW(dev)) {
4222                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4223                         mode = GEN6_RC_CTL_RC6_ENABLE;
4224                 else
4225                         mode = 0;
4226         }
4227         if (HAS_RC6p(dev))
4228                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4229                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4230                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4231                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4232
4233         else
4234                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4235                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4236 }
4237
4238 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4239 {
4240         /* No RC6 before Ironlake */
4241         if (INTEL_INFO(dev)->gen < 5)
4242                 return 0;
4243
4244         /* RC6 is only on Ironlake mobile not on desktop */
4245         if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4246                 return 0;
4247
4248         /* Respect the kernel parameter if it is set */
4249         if (enable_rc6 >= 0) {
4250                 int mask;
4251
4252                 if (HAS_RC6p(dev))
4253                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4254                                INTEL_RC6pp_ENABLE;
4255                 else
4256                         mask = INTEL_RC6_ENABLE;
4257
4258                 if ((enable_rc6 & mask) != enable_rc6)
4259                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4260                                       enable_rc6 & mask, enable_rc6, mask);
4261
4262                 return enable_rc6 & mask;
4263         }
4264
4265         /* Disable RC6 on Ironlake */
4266         if (INTEL_INFO(dev)->gen == 5)
4267                 return 0;
4268
4269         if (IS_IVYBRIDGE(dev))
4270                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4271
4272         return INTEL_RC6_ENABLE;
4273 }
4274
4275 int intel_enable_rc6(const struct drm_device *dev)
4276 {
4277         return i915.enable_rc6;
4278 }
4279
4280 static void gen6_init_rps_frequencies(struct drm_device *dev)
4281 {
4282         struct drm_i915_private *dev_priv = dev->dev_private;
4283         uint32_t rp_state_cap;
4284         u32 ddcc_status = 0;
4285         int ret;
4286
4287         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4288         /* All of these values are in units of 50MHz */
4289         dev_priv->rps.cur_freq          = 0;
4290         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4291         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
4292         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
4293         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
4294         if (IS_SKYLAKE(dev)) {
4295                 /* Store the frequency values in 16.66 MHZ units, which is
4296                    the natural hardware unit for SKL */
4297                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4298                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4299                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4300         }
4301         /* hw_max = RP0 until we check for overclocking */
4302         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4303
4304         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4305         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4306                 ret = sandybridge_pcode_read(dev_priv,
4307                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4308                                         &ddcc_status);
4309                 if (0 == ret)
4310                         dev_priv->rps.efficient_freq =
4311                                 clamp_t(u8,
4312                                         ((ddcc_status >> 8) & 0xff),
4313                                         dev_priv->rps.min_freq,
4314                                         dev_priv->rps.max_freq);
4315         }
4316
4317         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4318
4319         /* Preserve min/max settings in case of re-init */
4320         if (dev_priv->rps.max_freq_softlimit == 0)
4321                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4322
4323         if (dev_priv->rps.min_freq_softlimit == 0) {
4324                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4325                         dev_priv->rps.min_freq_softlimit =
4326                                 max_t(int, dev_priv->rps.efficient_freq,
4327                                       intel_freq_opcode(dev_priv, 450));
4328                 else
4329                         dev_priv->rps.min_freq_softlimit =
4330                                 dev_priv->rps.min_freq;
4331         }
4332 }
4333
4334 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4335 static void gen9_enable_rps(struct drm_device *dev)
4336 {
4337         struct drm_i915_private *dev_priv = dev->dev_private;
4338
4339         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4340
4341         gen6_init_rps_frequencies(dev);
4342
4343         /* Program defaults and thresholds for RPS*/
4344         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4345                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4346
4347         /* 1 second timeout*/
4348         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4349                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4350
4351         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4352
4353         /* Leaning on the below call to gen6_set_rps to program/setup the
4354          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4355          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4356         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4357         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4358
4359         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4360 }
4361
4362 static void gen9_enable_rc6(struct drm_device *dev)
4363 {
4364         struct drm_i915_private *dev_priv = dev->dev_private;
4365         struct intel_engine_cs *ring;
4366         uint32_t rc6_mask = 0;
4367         int unused;
4368
4369         /* 1a: Software RC state - RC0 */
4370         I915_WRITE(GEN6_RC_STATE, 0);
4371
4372         /* 1b: Get forcewake during program sequence. Although the driver
4373          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4374         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4375
4376         /* 2a: Disable RC states. */
4377         I915_WRITE(GEN6_RC_CONTROL, 0);
4378
4379         /* 2b: Program RC6 thresholds.*/
4380         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4381         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4382         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4383         for_each_ring(ring, dev_priv, unused)
4384                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4385         I915_WRITE(GEN6_RC_SLEEP, 0);
4386         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4387
4388         /* 2c: Program Coarse Power Gating Policies. */
4389         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4390         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4391
4392         /* 3a: Enable RC6 */
4393         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4394                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4395         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4396                         "on" : "off");
4397         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4398                                    GEN6_RC_CTL_EI_MODE(1) |
4399                                    rc6_mask);
4400
4401         /*
4402          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4403          * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4404          */
4405         I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4406                         GEN9_MEDIA_PG_ENABLE : 0);
4407
4408
4409         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4410
4411 }
4412
4413 static void gen8_enable_rps(struct drm_device *dev)
4414 {
4415         struct drm_i915_private *dev_priv = dev->dev_private;
4416         struct intel_engine_cs *ring;
4417         uint32_t rc6_mask = 0;
4418         int unused;
4419
4420         /* 1a: Software RC state - RC0 */
4421         I915_WRITE(GEN6_RC_STATE, 0);
4422
4423         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4424          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4425         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4426
4427         /* 2a: Disable RC states. */
4428         I915_WRITE(GEN6_RC_CONTROL, 0);
4429
4430         /* Initialize rps frequencies */
4431         gen6_init_rps_frequencies(dev);
4432
4433         /* 2b: Program RC6 thresholds.*/
4434         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4435         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4436         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4437         for_each_ring(ring, dev_priv, unused)
4438                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4439         I915_WRITE(GEN6_RC_SLEEP, 0);
4440         if (IS_BROADWELL(dev))
4441                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4442         else
4443                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4444
4445         /* 3: Enable RC6 */
4446         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4447                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4448         intel_print_rc6_info(dev, rc6_mask);
4449         if (IS_BROADWELL(dev))
4450                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4451                                 GEN7_RC_CTL_TO_MODE |
4452                                 rc6_mask);
4453         else
4454                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4455                                 GEN6_RC_CTL_EI_MODE(1) |
4456                                 rc6_mask);
4457
4458         /* 4 Program defaults and thresholds for RPS*/
4459         I915_WRITE(GEN6_RPNSWREQ,
4460                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4461         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4462                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4463         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4464         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4465
4466         /* Docs recommend 900MHz, and 300 MHz respectively */
4467         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4468                    dev_priv->rps.max_freq_softlimit << 24 |
4469                    dev_priv->rps.min_freq_softlimit << 16);
4470
4471         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4472         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4473         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4474         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4475
4476         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4477
4478         /* 5: Enable RPS */
4479         I915_WRITE(GEN6_RP_CONTROL,
4480                    GEN6_RP_MEDIA_TURBO |
4481                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4482                    GEN6_RP_MEDIA_IS_GFX |
4483                    GEN6_RP_ENABLE |
4484                    GEN6_RP_UP_BUSY_AVG |
4485                    GEN6_RP_DOWN_IDLE_AVG);
4486
4487         /* 6: Ring frequency + overclocking (our driver does this later */
4488
4489         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4490         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4491
4492         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4493 }
4494
4495 static void gen6_enable_rps(struct drm_device *dev)
4496 {
4497         struct drm_i915_private *dev_priv = dev->dev_private;
4498         struct intel_engine_cs *ring;
4499         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4500         u32 gtfifodbg;
4501         int rc6_mode;
4502         int i, ret;
4503
4504         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4505
4506         /* Here begins a magic sequence of register writes to enable
4507          * auto-downclocking.
4508          *
4509          * Perhaps there might be some value in exposing these to
4510          * userspace...
4511          */
4512         I915_WRITE(GEN6_RC_STATE, 0);
4513
4514         /* Clear the DBG now so we don't confuse earlier errors */
4515         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4516                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4517                 I915_WRITE(GTFIFODBG, gtfifodbg);
4518         }
4519
4520         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4521
4522         /* Initialize rps frequencies */
4523         gen6_init_rps_frequencies(dev);
4524
4525         /* disable the counters and set deterministic thresholds */
4526         I915_WRITE(GEN6_RC_CONTROL, 0);
4527
4528         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4529         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4530         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4531         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4532         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4533
4534         for_each_ring(ring, dev_priv, i)
4535                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4536
4537         I915_WRITE(GEN6_RC_SLEEP, 0);
4538         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4539         if (IS_IVYBRIDGE(dev))
4540                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4541         else
4542                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4543         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4544         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4545
4546         /* Check if we are enabling RC6 */
4547         rc6_mode = intel_enable_rc6(dev_priv->dev);
4548         if (rc6_mode & INTEL_RC6_ENABLE)
4549                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4550
4551         /* We don't use those on Haswell */
4552         if (!IS_HASWELL(dev)) {
4553                 if (rc6_mode & INTEL_RC6p_ENABLE)
4554                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4555
4556                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4557                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4558         }
4559
4560         intel_print_rc6_info(dev, rc6_mask);
4561
4562         I915_WRITE(GEN6_RC_CONTROL,
4563                    rc6_mask |
4564                    GEN6_RC_CTL_EI_MODE(1) |
4565                    GEN6_RC_CTL_HW_ENABLE);
4566
4567         /* Power down if completely idle for over 50ms */
4568         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4569         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4570
4571         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4572         if (ret)
4573                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4574
4575         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4576         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4577                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4578                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4579                                  (pcu_mbox & 0xff) * 50);
4580                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4581         }
4582
4583         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4584         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4585
4586         rc6vids = 0;
4587         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4588         if (IS_GEN6(dev) && ret) {
4589                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4590         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4591                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4592                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4593                 rc6vids &= 0xffff00;
4594                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4595                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4596                 if (ret)
4597                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4598         }
4599
4600         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4601 }
4602
4603 static void __gen6_update_ring_freq(struct drm_device *dev)
4604 {
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         int min_freq = 15;
4607         unsigned int gpu_freq;
4608         unsigned int max_ia_freq, min_ring_freq;
4609         int scaling_factor = 180;
4610         struct cpufreq_policy *policy;
4611
4612         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4613
4614         policy = cpufreq_cpu_get(0);
4615         if (policy) {
4616                 max_ia_freq = policy->cpuinfo.max_freq;
4617                 cpufreq_cpu_put(policy);
4618         } else {
4619                 /*
4620                  * Default to measured freq if none found, PCU will ensure we
4621                  * don't go over
4622                  */
4623                 max_ia_freq = tsc_khz;
4624         }
4625
4626         /* Convert from kHz to MHz */
4627         max_ia_freq /= 1000;
4628
4629         min_ring_freq = I915_READ(DCLK) & 0xf;
4630         /* convert DDR frequency from units of 266.6MHz to bandwidth */
4631         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4632
4633         /*
4634          * For each potential GPU frequency, load a ring frequency we'd like
4635          * to use for memory access.  We do this by specifying the IA frequency
4636          * the PCU should use as a reference to determine the ring frequency.
4637          */
4638         for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
4639              gpu_freq--) {
4640                 int diff = dev_priv->rps.max_freq - gpu_freq;
4641                 unsigned int ia_freq = 0, ring_freq = 0;
4642
4643                 if (INTEL_INFO(dev)->gen >= 8) {
4644                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
4645                         ring_freq = max(min_ring_freq, gpu_freq);
4646                 } else if (IS_HASWELL(dev)) {
4647                         ring_freq = mult_frac(gpu_freq, 5, 4);
4648                         ring_freq = max(min_ring_freq, ring_freq);
4649                         /* leave ia_freq as the default, chosen by cpufreq */
4650                 } else {
4651                         /* On older processors, there is no separate ring
4652                          * clock domain, so in order to boost the bandwidth
4653                          * of the ring, we need to upclock the CPU (ia_freq).
4654                          *
4655                          * For GPU frequencies less than 750MHz,
4656                          * just use the lowest ring freq.
4657                          */
4658                         if (gpu_freq < min_freq)
4659                                 ia_freq = 800;
4660                         else
4661                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4662                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4663                 }
4664
4665                 sandybridge_pcode_write(dev_priv,
4666                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4667                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4668                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4669                                         gpu_freq);
4670         }
4671 }
4672
4673 void gen6_update_ring_freq(struct drm_device *dev)
4674 {
4675         struct drm_i915_private *dev_priv = dev->dev_private;
4676
4677         if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4678                 return;
4679
4680         mutex_lock(&dev_priv->rps.hw_lock);
4681         __gen6_update_ring_freq(dev);
4682         mutex_unlock(&dev_priv->rps.hw_lock);
4683 }
4684
4685 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4686 {
4687         struct drm_device *dev = dev_priv->dev;
4688         u32 val, rp0;
4689
4690         if (dev->pdev->revision >= 0x20) {
4691                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4692
4693                 switch (INTEL_INFO(dev)->eu_total) {
4694                 case 8:
4695                                 /* (2 * 4) config */
4696                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4697                                 break;
4698                 case 12:
4699                                 /* (2 * 6) config */
4700                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4701                                 break;
4702                 case 16:
4703                                 /* (2 * 8) config */
4704                 default:
4705                                 /* Setting (2 * 8) Min RP0 for any other combination */
4706                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4707                                 break;
4708                 }
4709                 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4710         } else {
4711                 /* For pre-production hardware */
4712                 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4713                 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4714                        PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4715         }
4716         return rp0;
4717 }
4718
4719 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4720 {
4721         u32 val, rpe;
4722
4723         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4724         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4725
4726         return rpe;
4727 }
4728
4729 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4730 {
4731         struct drm_device *dev = dev_priv->dev;
4732         u32 val, rp1;
4733
4734         if (dev->pdev->revision >= 0x20) {
4735                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4736                 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4737         } else {
4738                 /* For pre-production hardware */
4739                 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4740                 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4741                        PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4742         }
4743         return rp1;
4744 }
4745
4746 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4747 {
4748         u32 val, rp1;
4749
4750         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4751
4752         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4753
4754         return rp1;
4755 }
4756
4757 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4758 {
4759         u32 val, rp0;
4760
4761         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4762
4763         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4764         /* Clamp to max */
4765         rp0 = min_t(u32, rp0, 0xea);
4766
4767         return rp0;
4768 }
4769
4770 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4771 {
4772         u32 val, rpe;
4773
4774         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4775         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4776         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4777         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4778
4779         return rpe;
4780 }
4781
4782 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4783 {
4784         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4785 }
4786
4787 /* Check that the pctx buffer wasn't move under us. */
4788 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4789 {
4790         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4791
4792         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4793                              dev_priv->vlv_pctx->stolen->start);
4794 }
4795
4796
4797 /* Check that the pcbr address is not empty. */
4798 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4799 {
4800         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4801
4802         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4803 }
4804
4805 static void cherryview_setup_pctx(struct drm_device *dev)
4806 {
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         unsigned long pctx_paddr, paddr;
4809         struct i915_gtt *gtt = &dev_priv->gtt;
4810         u32 pcbr;
4811         int pctx_size = 32*1024;
4812
4813         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4814
4815         pcbr = I915_READ(VLV_PCBR);
4816         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4817                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4818                 paddr = (dev_priv->mm.stolen_base +
4819                          (gtt->stolen_size - pctx_size));
4820
4821                 pctx_paddr = (paddr & (~4095));
4822                 I915_WRITE(VLV_PCBR, pctx_paddr);
4823         }
4824
4825         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
4826 }
4827
4828 static void valleyview_setup_pctx(struct drm_device *dev)
4829 {
4830         struct drm_i915_private *dev_priv = dev->dev_private;
4831         struct drm_i915_gem_object *pctx;
4832         unsigned long pctx_paddr;
4833         u32 pcbr;
4834         int pctx_size = 24*1024;
4835
4836         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4837
4838         pcbr = I915_READ(VLV_PCBR);
4839         if (pcbr) {
4840                 /* BIOS set it up already, grab the pre-alloc'd space */
4841                 int pcbr_offset;
4842
4843                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4844                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4845                                                                       pcbr_offset,
4846                                                                       I915_GTT_OFFSET_NONE,
4847                                                                       pctx_size);
4848                 goto out;
4849         }
4850
4851         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4852
4853         /*
4854          * From the Gunit register HAS:
4855          * The Gfx driver is expected to program this register and ensure
4856          * proper allocation within Gfx stolen memory.  For example, this
4857          * register should be programmed such than the PCBR range does not
4858          * overlap with other ranges, such as the frame buffer, protected
4859          * memory, or any other relevant ranges.
4860          */
4861         pctx = i915_gem_object_create_stolen(dev, pctx_size);
4862         if (!pctx) {
4863                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4864                 return;
4865         }
4866
4867         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4868         I915_WRITE(VLV_PCBR, pctx_paddr);
4869
4870 out:
4871         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
4872         dev_priv->vlv_pctx = pctx;
4873 }
4874
4875 static void valleyview_cleanup_pctx(struct drm_device *dev)
4876 {
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878
4879         if (WARN_ON(!dev_priv->vlv_pctx))
4880                 return;
4881
4882         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4883         dev_priv->vlv_pctx = NULL;
4884 }
4885
4886 static void valleyview_init_gt_powersave(struct drm_device *dev)
4887 {
4888         struct drm_i915_private *dev_priv = dev->dev_private;
4889         u32 val;
4890
4891         valleyview_setup_pctx(dev);
4892
4893         mutex_lock(&dev_priv->rps.hw_lock);
4894
4895         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4896         switch ((val >> 6) & 3) {
4897         case 0:
4898         case 1:
4899                 dev_priv->mem_freq = 800;
4900                 break;
4901         case 2:
4902                 dev_priv->mem_freq = 1066;
4903                 break;
4904         case 3:
4905                 dev_priv->mem_freq = 1333;
4906                 break;
4907         }
4908         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
4909
4910         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4911         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4912         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4913                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4914                          dev_priv->rps.max_freq);
4915
4916         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4917         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4918                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4919                          dev_priv->rps.efficient_freq);
4920
4921         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4922         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4923                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4924                          dev_priv->rps.rp1_freq);
4925
4926         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4927         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4928                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4929                          dev_priv->rps.min_freq);
4930
4931         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4932
4933         /* Preserve min/max settings in case of re-init */
4934         if (dev_priv->rps.max_freq_softlimit == 0)
4935                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4936
4937         if (dev_priv->rps.min_freq_softlimit == 0)
4938                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4939
4940         mutex_unlock(&dev_priv->rps.hw_lock);
4941 }
4942
4943 static void cherryview_init_gt_powersave(struct drm_device *dev)
4944 {
4945         struct drm_i915_private *dev_priv = dev->dev_private;
4946         u32 val;
4947
4948         cherryview_setup_pctx(dev);
4949
4950         mutex_lock(&dev_priv->rps.hw_lock);
4951
4952         mutex_lock(&dev_priv->dpio_lock);
4953         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4954         mutex_unlock(&dev_priv->dpio_lock);
4955
4956         switch ((val >> 2) & 0x7) {
4957         case 0:
4958         case 1:
4959                 dev_priv->rps.cz_freq = 200;
4960                 dev_priv->mem_freq = 1600;
4961                 break;
4962         case 2:
4963                 dev_priv->rps.cz_freq = 267;
4964                 dev_priv->mem_freq = 1600;
4965                 break;
4966         case 3:
4967                 dev_priv->rps.cz_freq = 333;
4968                 dev_priv->mem_freq = 2000;
4969                 break;
4970         case 4:
4971                 dev_priv->rps.cz_freq = 320;
4972                 dev_priv->mem_freq = 1600;
4973                 break;
4974         case 5:
4975                 dev_priv->rps.cz_freq = 400;
4976                 dev_priv->mem_freq = 1600;
4977                 break;
4978         }
4979         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
4980
4981         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4982         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4983         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4984                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4985                          dev_priv->rps.max_freq);
4986
4987         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4988         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4989                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4990                          dev_priv->rps.efficient_freq);
4991
4992         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4993         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4994                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4995                          dev_priv->rps.rp1_freq);
4996
4997         /* PUnit validated range is only [RPe, RP0] */
4998         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
4999         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5000                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5001                          dev_priv->rps.min_freq);
5002
5003         WARN_ONCE((dev_priv->rps.max_freq |
5004                    dev_priv->rps.efficient_freq |
5005                    dev_priv->rps.rp1_freq |
5006                    dev_priv->rps.min_freq) & 1,
5007                   "Odd GPU freq values\n");
5008
5009         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5010
5011         /* Preserve min/max settings in case of re-init */
5012         if (dev_priv->rps.max_freq_softlimit == 0)
5013                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5014
5015         if (dev_priv->rps.min_freq_softlimit == 0)
5016                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5017
5018         mutex_unlock(&dev_priv->rps.hw_lock);
5019 }
5020
5021 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5022 {
5023         valleyview_cleanup_pctx(dev);
5024 }
5025
5026 static void cherryview_enable_rps(struct drm_device *dev)
5027 {
5028         struct drm_i915_private *dev_priv = dev->dev_private;
5029         struct intel_engine_cs *ring;
5030         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5031         int i;
5032
5033         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5034
5035         gtfifodbg = I915_READ(GTFIFODBG);
5036         if (gtfifodbg) {
5037                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5038                                  gtfifodbg);
5039                 I915_WRITE(GTFIFODBG, gtfifodbg);
5040         }
5041
5042         cherryview_check_pctx(dev_priv);
5043
5044         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5045          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5046         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5047
5048         /*  Disable RC states. */
5049         I915_WRITE(GEN6_RC_CONTROL, 0);
5050
5051         /* 2a: Program RC6 thresholds.*/
5052         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5053         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5054         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5055
5056         for_each_ring(ring, dev_priv, i)
5057                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5058         I915_WRITE(GEN6_RC_SLEEP, 0);
5059
5060         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5061         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5062
5063         /* allows RC6 residency counter to work */
5064         I915_WRITE(VLV_COUNTER_CONTROL,
5065                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5066                                       VLV_MEDIA_RC6_COUNT_EN |
5067                                       VLV_RENDER_RC6_COUNT_EN));
5068
5069         /* For now we assume BIOS is allocating and populating the PCBR  */
5070         pcbr = I915_READ(VLV_PCBR);
5071
5072         /* 3: Enable RC6 */
5073         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5074                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5075                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5076
5077         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5078
5079         /* 4 Program defaults and thresholds for RPS*/
5080         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5081         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5082         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5083         I915_WRITE(GEN6_RP_UP_EI, 66000);
5084         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5085
5086         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5087
5088         /* 5: Enable RPS */
5089         I915_WRITE(GEN6_RP_CONTROL,
5090                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5091                    GEN6_RP_MEDIA_IS_GFX |
5092                    GEN6_RP_ENABLE |
5093                    GEN6_RP_UP_BUSY_AVG |
5094                    GEN6_RP_DOWN_IDLE_AVG);
5095
5096         /* Setting Fixed Bias */
5097         val = VLV_OVERRIDE_EN |
5098                   VLV_SOC_TDP_EN |
5099                   CHV_BIAS_CPU_50_SOC_50;
5100         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5101
5102         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5103
5104         /* RPS code assumes GPLL is used */
5105         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5106
5107         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5108         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5109
5110         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5111         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5112                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5113                          dev_priv->rps.cur_freq);
5114
5115         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5116                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5117                          dev_priv->rps.efficient_freq);
5118
5119         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5120
5121         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5122 }
5123
5124 static void valleyview_enable_rps(struct drm_device *dev)
5125 {
5126         struct drm_i915_private *dev_priv = dev->dev_private;
5127         struct intel_engine_cs *ring;
5128         u32 gtfifodbg, val, rc6_mode = 0;
5129         int i;
5130
5131         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5132
5133         valleyview_check_pctx(dev_priv);
5134
5135         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5136                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5137                                  gtfifodbg);
5138                 I915_WRITE(GTFIFODBG, gtfifodbg);
5139         }
5140
5141         /* If VLV, Forcewake all wells, else re-direct to regular path */
5142         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5143
5144         /*  Disable RC states. */
5145         I915_WRITE(GEN6_RC_CONTROL, 0);
5146
5147         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5148         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5149         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5150         I915_WRITE(GEN6_RP_UP_EI, 66000);
5151         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5152
5153         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5154
5155         I915_WRITE(GEN6_RP_CONTROL,
5156                    GEN6_RP_MEDIA_TURBO |
5157                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5158                    GEN6_RP_MEDIA_IS_GFX |
5159                    GEN6_RP_ENABLE |
5160                    GEN6_RP_UP_BUSY_AVG |
5161                    GEN6_RP_DOWN_IDLE_CONT);
5162
5163         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5164         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5165         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5166
5167         for_each_ring(ring, dev_priv, i)
5168                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5169
5170         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5171
5172         /* allows RC6 residency counter to work */
5173         I915_WRITE(VLV_COUNTER_CONTROL,
5174                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5175                                       VLV_RENDER_RC0_COUNT_EN |
5176                                       VLV_MEDIA_RC6_COUNT_EN |
5177                                       VLV_RENDER_RC6_COUNT_EN));
5178
5179         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5180                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5181
5182         intel_print_rc6_info(dev, rc6_mode);
5183
5184         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5185
5186         /* Setting Fixed Bias */
5187         val = VLV_OVERRIDE_EN |
5188                   VLV_SOC_TDP_EN |
5189                   VLV_BIAS_CPU_125_SOC_875;
5190         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5191
5192         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5193
5194         /* RPS code assumes GPLL is used */
5195         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5196
5197         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
5198         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5199
5200         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5201         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5202                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5203                          dev_priv->rps.cur_freq);
5204
5205         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5206                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5207                          dev_priv->rps.efficient_freq);
5208
5209         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5210
5211         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5212 }
5213
5214 static unsigned long intel_pxfreq(u32 vidfreq)
5215 {
5216         unsigned long freq;
5217         int div = (vidfreq & 0x3f0000) >> 16;
5218         int post = (vidfreq & 0x3000) >> 12;
5219         int pre = (vidfreq & 0x7);
5220
5221         if (!pre)
5222                 return 0;
5223
5224         freq = ((div * 133333) / ((1<<post) * pre));
5225
5226         return freq;
5227 }
5228
5229 static const struct cparams {
5230         u16 i;
5231         u16 t;
5232         u16 m;
5233         u16 c;
5234 } cparams[] = {
5235         { 1, 1333, 301, 28664 },
5236         { 1, 1066, 294, 24460 },
5237         { 1, 800, 294, 25192 },
5238         { 0, 1333, 276, 27605 },
5239         { 0, 1066, 276, 27605 },
5240         { 0, 800, 231, 23784 },
5241 };
5242
5243 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5244 {
5245         u64 total_count, diff, ret;
5246         u32 count1, count2, count3, m = 0, c = 0;
5247         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5248         int i;
5249
5250         assert_spin_locked(&mchdev_lock);
5251
5252         diff1 = now - dev_priv->ips.last_time1;
5253
5254         /* Prevent division-by-zero if we are asking too fast.
5255          * Also, we don't get interesting results if we are polling
5256          * faster than once in 10ms, so just return the saved value
5257          * in such cases.
5258          */
5259         if (diff1 <= 10)
5260                 return dev_priv->ips.chipset_power;
5261
5262         count1 = I915_READ(DMIEC);
5263         count2 = I915_READ(DDREC);
5264         count3 = I915_READ(CSIEC);
5265
5266         total_count = count1 + count2 + count3;
5267
5268         /* FIXME: handle per-counter overflow */
5269         if (total_count < dev_priv->ips.last_count1) {
5270                 diff = ~0UL - dev_priv->ips.last_count1;
5271                 diff += total_count;
5272         } else {
5273                 diff = total_count - dev_priv->ips.last_count1;
5274         }
5275
5276         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5277                 if (cparams[i].i == dev_priv->ips.c_m &&
5278                     cparams[i].t == dev_priv->ips.r_t) {
5279                         m = cparams[i].m;
5280                         c = cparams[i].c;
5281                         break;
5282                 }
5283         }
5284
5285         diff = div_u64(diff, diff1);
5286         ret = ((m * diff) + c);
5287         ret = div_u64(ret, 10);
5288
5289         dev_priv->ips.last_count1 = total_count;
5290         dev_priv->ips.last_time1 = now;
5291
5292         dev_priv->ips.chipset_power = ret;
5293
5294         return ret;
5295 }
5296
5297 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5298 {
5299         struct drm_device *dev = dev_priv->dev;
5300         unsigned long val;
5301
5302         if (INTEL_INFO(dev)->gen != 5)
5303                 return 0;
5304
5305         spin_lock_irq(&mchdev_lock);
5306
5307         val = __i915_chipset_val(dev_priv);
5308
5309         spin_unlock_irq(&mchdev_lock);
5310
5311         return val;
5312 }
5313
5314 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5315 {
5316         unsigned long m, x, b;
5317         u32 tsfs;
5318
5319         tsfs = I915_READ(TSFS);
5320
5321         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5322         x = I915_READ8(TR1);
5323
5324         b = tsfs & TSFS_INTR_MASK;
5325
5326         return ((m * x) / 127) - b;
5327 }
5328
5329 static int _pxvid_to_vd(u8 pxvid)
5330 {
5331         if (pxvid == 0)
5332                 return 0;
5333
5334         if (pxvid >= 8 && pxvid < 31)
5335                 pxvid = 31;
5336
5337         return (pxvid + 2) * 125;
5338 }
5339
5340 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5341 {
5342         struct drm_device *dev = dev_priv->dev;
5343         const int vd = _pxvid_to_vd(pxvid);
5344         const int vm = vd - 1125;
5345
5346         if (INTEL_INFO(dev)->is_mobile)
5347                 return vm > 0 ? vm : 0;
5348
5349         return vd;
5350 }
5351
5352 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5353 {
5354         u64 now, diff, diffms;
5355         u32 count;
5356
5357         assert_spin_locked(&mchdev_lock);
5358
5359         now = ktime_get_raw_ns();
5360         diffms = now - dev_priv->ips.last_time2;
5361         do_div(diffms, NSEC_PER_MSEC);
5362
5363         /* Don't divide by 0 */
5364         if (!diffms)
5365                 return;
5366
5367         count = I915_READ(GFXEC);
5368
5369         if (count < dev_priv->ips.last_count2) {
5370                 diff = ~0UL - dev_priv->ips.last_count2;
5371                 diff += count;
5372         } else {
5373                 diff = count - dev_priv->ips.last_count2;
5374         }
5375
5376         dev_priv->ips.last_count2 = count;
5377         dev_priv->ips.last_time2 = now;
5378
5379         /* More magic constants... */
5380         diff = diff * 1181;
5381         diff = div_u64(diff, diffms * 10);
5382         dev_priv->ips.gfx_power = diff;
5383 }
5384
5385 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5386 {
5387         struct drm_device *dev = dev_priv->dev;
5388
5389         if (INTEL_INFO(dev)->gen != 5)
5390                 return;
5391
5392         spin_lock_irq(&mchdev_lock);
5393
5394         __i915_update_gfx_val(dev_priv);
5395
5396         spin_unlock_irq(&mchdev_lock);
5397 }
5398
5399 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5400 {
5401         unsigned long t, corr, state1, corr2, state2;
5402         u32 pxvid, ext_v;
5403
5404         assert_spin_locked(&mchdev_lock);
5405
5406         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
5407         pxvid = (pxvid >> 24) & 0x7f;
5408         ext_v = pvid_to_extvid(dev_priv, pxvid);
5409
5410         state1 = ext_v;
5411
5412         t = i915_mch_val(dev_priv);
5413
5414         /* Revel in the empirically derived constants */
5415
5416         /* Correction factor in 1/100000 units */
5417         if (t > 80)
5418                 corr = ((t * 2349) + 135940);
5419         else if (t >= 50)
5420                 corr = ((t * 964) + 29317);
5421         else /* < 50 */
5422                 corr = ((t * 301) + 1004);
5423
5424         corr = corr * ((150142 * state1) / 10000 - 78642);
5425         corr /= 100000;
5426         corr2 = (corr * dev_priv->ips.corr);
5427
5428         state2 = (corr2 * state1) / 10000;
5429         state2 /= 100; /* convert to mW */
5430
5431         __i915_update_gfx_val(dev_priv);
5432
5433         return dev_priv->ips.gfx_power + state2;
5434 }
5435
5436 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5437 {
5438         struct drm_device *dev = dev_priv->dev;
5439         unsigned long val;
5440
5441         if (INTEL_INFO(dev)->gen != 5)
5442                 return 0;
5443
5444         spin_lock_irq(&mchdev_lock);
5445
5446         val = __i915_gfx_val(dev_priv);
5447
5448         spin_unlock_irq(&mchdev_lock);
5449
5450         return val;
5451 }
5452
5453 /**
5454  * i915_read_mch_val - return value for IPS use
5455  *
5456  * Calculate and return a value for the IPS driver to use when deciding whether
5457  * we have thermal and power headroom to increase CPU or GPU power budget.
5458  */
5459 unsigned long i915_read_mch_val(void)
5460 {
5461         struct drm_i915_private *dev_priv;
5462         unsigned long chipset_val, graphics_val, ret = 0;
5463
5464         spin_lock_irq(&mchdev_lock);
5465         if (!i915_mch_dev)
5466                 goto out_unlock;
5467         dev_priv = i915_mch_dev;
5468
5469         chipset_val = __i915_chipset_val(dev_priv);
5470         graphics_val = __i915_gfx_val(dev_priv);
5471
5472         ret = chipset_val + graphics_val;
5473
5474 out_unlock:
5475         spin_unlock_irq(&mchdev_lock);
5476
5477         return ret;
5478 }
5479 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5480
5481 /**
5482  * i915_gpu_raise - raise GPU frequency limit
5483  *
5484  * Raise the limit; IPS indicates we have thermal headroom.
5485  */
5486 bool i915_gpu_raise(void)
5487 {
5488         struct drm_i915_private *dev_priv;
5489         bool ret = true;
5490
5491         spin_lock_irq(&mchdev_lock);
5492         if (!i915_mch_dev) {
5493                 ret = false;
5494                 goto out_unlock;
5495         }
5496         dev_priv = i915_mch_dev;
5497
5498         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5499                 dev_priv->ips.max_delay--;
5500
5501 out_unlock:
5502         spin_unlock_irq(&mchdev_lock);
5503
5504         return ret;
5505 }
5506 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5507
5508 /**
5509  * i915_gpu_lower - lower GPU frequency limit
5510  *
5511  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5512  * frequency maximum.
5513  */
5514 bool i915_gpu_lower(void)
5515 {
5516         struct drm_i915_private *dev_priv;
5517         bool ret = true;
5518
5519         spin_lock_irq(&mchdev_lock);
5520         if (!i915_mch_dev) {
5521                 ret = false;
5522                 goto out_unlock;
5523         }
5524         dev_priv = i915_mch_dev;
5525
5526         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5527                 dev_priv->ips.max_delay++;
5528
5529 out_unlock:
5530         spin_unlock_irq(&mchdev_lock);
5531
5532         return ret;
5533 }
5534 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5535
5536 /**
5537  * i915_gpu_busy - indicate GPU business to IPS
5538  *
5539  * Tell the IPS driver whether or not the GPU is busy.
5540  */
5541 bool i915_gpu_busy(void)
5542 {
5543         struct drm_i915_private *dev_priv;
5544         struct intel_engine_cs *ring;
5545         bool ret = false;
5546         int i;
5547
5548         spin_lock_irq(&mchdev_lock);
5549         if (!i915_mch_dev)
5550                 goto out_unlock;
5551         dev_priv = i915_mch_dev;
5552
5553         for_each_ring(ring, dev_priv, i)
5554                 ret |= !list_empty(&ring->request_list);
5555
5556 out_unlock:
5557         spin_unlock_irq(&mchdev_lock);
5558
5559         return ret;
5560 }
5561 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5562
5563 /**
5564  * i915_gpu_turbo_disable - disable graphics turbo
5565  *
5566  * Disable graphics turbo by resetting the max frequency and setting the
5567  * current frequency to the default.
5568  */
5569 bool i915_gpu_turbo_disable(void)
5570 {
5571         struct drm_i915_private *dev_priv;
5572         bool ret = true;
5573
5574         spin_lock_irq(&mchdev_lock);
5575         if (!i915_mch_dev) {
5576                 ret = false;
5577                 goto out_unlock;
5578         }
5579         dev_priv = i915_mch_dev;
5580
5581         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5582
5583         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5584                 ret = false;
5585
5586 out_unlock:
5587         spin_unlock_irq(&mchdev_lock);
5588
5589         return ret;
5590 }
5591 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5592
5593 /**
5594  * Tells the intel_ips driver that the i915 driver is now loaded, if
5595  * IPS got loaded first.
5596  *
5597  * This awkward dance is so that neither module has to depend on the
5598  * other in order for IPS to do the appropriate communication of
5599  * GPU turbo limits to i915.
5600  */
5601 static void
5602 ips_ping_for_i915_load(void)
5603 {
5604         void (*link)(void);
5605
5606         link = symbol_get(ips_link_to_i915_driver);
5607         if (link) {
5608                 link();
5609                 symbol_put(ips_link_to_i915_driver);
5610         }
5611 }
5612
5613 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5614 {
5615         /* We only register the i915 ips part with intel-ips once everything is
5616          * set up, to avoid intel-ips sneaking in and reading bogus values. */
5617         spin_lock_irq(&mchdev_lock);
5618         i915_mch_dev = dev_priv;
5619         spin_unlock_irq(&mchdev_lock);
5620
5621         ips_ping_for_i915_load();
5622 }
5623
5624 void intel_gpu_ips_teardown(void)
5625 {
5626         spin_lock_irq(&mchdev_lock);
5627         i915_mch_dev = NULL;
5628         spin_unlock_irq(&mchdev_lock);
5629 }
5630
5631 static void intel_init_emon(struct drm_device *dev)
5632 {
5633         struct drm_i915_private *dev_priv = dev->dev_private;
5634         u32 lcfuse;
5635         u8 pxw[16];
5636         int i;
5637
5638         /* Disable to program */
5639         I915_WRITE(ECR, 0);
5640         POSTING_READ(ECR);
5641
5642         /* Program energy weights for various events */
5643         I915_WRITE(SDEW, 0x15040d00);
5644         I915_WRITE(CSIEW0, 0x007f0000);
5645         I915_WRITE(CSIEW1, 0x1e220004);
5646         I915_WRITE(CSIEW2, 0x04000004);
5647
5648         for (i = 0; i < 5; i++)
5649                 I915_WRITE(PEW + (i * 4), 0);
5650         for (i = 0; i < 3; i++)
5651                 I915_WRITE(DEW + (i * 4), 0);
5652
5653         /* Program P-state weights to account for frequency power adjustment */
5654         for (i = 0; i < 16; i++) {
5655                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5656                 unsigned long freq = intel_pxfreq(pxvidfreq);
5657                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5658                         PXVFREQ_PX_SHIFT;
5659                 unsigned long val;
5660
5661                 val = vid * vid;
5662                 val *= (freq / 1000);
5663                 val *= 255;
5664                 val /= (127*127*900);
5665                 if (val > 0xff)
5666                         DRM_ERROR("bad pxval: %ld\n", val);
5667                 pxw[i] = val;
5668         }
5669         /* Render standby states get 0 weight */
5670         pxw[14] = 0;
5671         pxw[15] = 0;
5672
5673         for (i = 0; i < 4; i++) {
5674                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5675                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5676                 I915_WRITE(PXW + (i * 4), val);
5677         }
5678
5679         /* Adjust magic regs to magic values (more experimental results) */
5680         I915_WRITE(OGW0, 0);
5681         I915_WRITE(OGW1, 0);
5682         I915_WRITE(EG0, 0x00007f00);
5683         I915_WRITE(EG1, 0x0000000e);
5684         I915_WRITE(EG2, 0x000e0000);
5685         I915_WRITE(EG3, 0x68000300);
5686         I915_WRITE(EG4, 0x42000000);
5687         I915_WRITE(EG5, 0x00140031);
5688         I915_WRITE(EG6, 0);
5689         I915_WRITE(EG7, 0);
5690
5691         for (i = 0; i < 8; i++)
5692                 I915_WRITE(PXWL + (i * 4), 0);
5693
5694         /* Enable PMON + select events */
5695         I915_WRITE(ECR, 0x80000019);
5696
5697         lcfuse = I915_READ(LCFUSE02);
5698
5699         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5700 }
5701
5702 void intel_init_gt_powersave(struct drm_device *dev)
5703 {
5704         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5705
5706         if (IS_CHERRYVIEW(dev))
5707                 cherryview_init_gt_powersave(dev);
5708         else if (IS_VALLEYVIEW(dev))
5709                 valleyview_init_gt_powersave(dev);
5710 }
5711
5712 void intel_cleanup_gt_powersave(struct drm_device *dev)
5713 {
5714         if (IS_CHERRYVIEW(dev))
5715                 return;
5716         else if (IS_VALLEYVIEW(dev))
5717                 valleyview_cleanup_gt_powersave(dev);
5718 }
5719
5720 static void gen6_suspend_rps(struct drm_device *dev)
5721 {
5722         struct drm_i915_private *dev_priv = dev->dev_private;
5723
5724         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5725
5726         gen6_disable_rps_interrupts(dev);
5727 }
5728
5729 /**
5730  * intel_suspend_gt_powersave - suspend PM work and helper threads
5731  * @dev: drm device
5732  *
5733  * We don't want to disable RC6 or other features here, we just want
5734  * to make sure any work we've queued has finished and won't bother
5735  * us while we're suspended.
5736  */
5737 void intel_suspend_gt_powersave(struct drm_device *dev)
5738 {
5739         struct drm_i915_private *dev_priv = dev->dev_private;
5740
5741         if (INTEL_INFO(dev)->gen < 6)
5742                 return;
5743
5744         gen6_suspend_rps(dev);
5745
5746         /* Force GPU to min freq during suspend */
5747         gen6_rps_idle(dev_priv);
5748 }
5749
5750 void intel_disable_gt_powersave(struct drm_device *dev)
5751 {
5752         struct drm_i915_private *dev_priv = dev->dev_private;
5753
5754         if (IS_IRONLAKE_M(dev)) {
5755                 ironlake_disable_drps(dev);
5756         } else if (INTEL_INFO(dev)->gen >= 6) {
5757                 intel_suspend_gt_powersave(dev);
5758
5759                 mutex_lock(&dev_priv->rps.hw_lock);
5760                 if (INTEL_INFO(dev)->gen >= 9)
5761                         gen9_disable_rps(dev);
5762                 else if (IS_CHERRYVIEW(dev))
5763                         cherryview_disable_rps(dev);
5764                 else if (IS_VALLEYVIEW(dev))
5765                         valleyview_disable_rps(dev);
5766                 else
5767                         gen6_disable_rps(dev);
5768
5769                 dev_priv->rps.enabled = false;
5770                 mutex_unlock(&dev_priv->rps.hw_lock);
5771         }
5772 }
5773
5774 static void intel_gen6_powersave_work(struct work_struct *work)
5775 {
5776         struct drm_i915_private *dev_priv =
5777                 container_of(work, struct drm_i915_private,
5778                              rps.delayed_resume_work.work);
5779         struct drm_device *dev = dev_priv->dev;
5780
5781         mutex_lock(&dev_priv->rps.hw_lock);
5782
5783         gen6_reset_rps_interrupts(dev);
5784
5785         if (IS_CHERRYVIEW(dev)) {
5786                 cherryview_enable_rps(dev);
5787         } else if (IS_VALLEYVIEW(dev)) {
5788                 valleyview_enable_rps(dev);
5789         } else if (INTEL_INFO(dev)->gen >= 9) {
5790                 gen9_enable_rc6(dev);
5791                 gen9_enable_rps(dev);
5792                 __gen6_update_ring_freq(dev);
5793         } else if (IS_BROADWELL(dev)) {
5794                 gen8_enable_rps(dev);
5795                 __gen6_update_ring_freq(dev);
5796         } else {
5797                 gen6_enable_rps(dev);
5798                 __gen6_update_ring_freq(dev);
5799         }
5800
5801         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5802         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5803
5804         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5805         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5806
5807         dev_priv->rps.enabled = true;
5808
5809         gen6_enable_rps_interrupts(dev);
5810
5811         mutex_unlock(&dev_priv->rps.hw_lock);
5812
5813         intel_runtime_pm_put(dev_priv);
5814 }
5815
5816 void intel_enable_gt_powersave(struct drm_device *dev)
5817 {
5818         struct drm_i915_private *dev_priv = dev->dev_private;
5819
5820         /* Powersaving is controlled by the host when inside a VM */
5821         if (intel_vgpu_active(dev))
5822                 return;
5823
5824         if (IS_IRONLAKE_M(dev)) {
5825                 mutex_lock(&dev->struct_mutex);
5826                 ironlake_enable_drps(dev);
5827                 intel_init_emon(dev);
5828                 mutex_unlock(&dev->struct_mutex);
5829         } else if (INTEL_INFO(dev)->gen >= 6) {
5830                 /*
5831                  * PCU communication is slow and this doesn't need to be
5832                  * done at any specific time, so do this out of our fast path
5833                  * to make resume and init faster.
5834                  *
5835                  * We depend on the HW RC6 power context save/restore
5836                  * mechanism when entering D3 through runtime PM suspend. So
5837                  * disable RPM until RPS/RC6 is properly setup. We can only
5838                  * get here via the driver load/system resume/runtime resume
5839                  * paths, so the _noresume version is enough (and in case of
5840                  * runtime resume it's necessary).
5841                  */
5842                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5843                                            round_jiffies_up_relative(HZ)))
5844                         intel_runtime_pm_get_noresume(dev_priv);
5845         }
5846 }
5847
5848 void intel_reset_gt_powersave(struct drm_device *dev)
5849 {
5850         struct drm_i915_private *dev_priv = dev->dev_private;
5851
5852         if (INTEL_INFO(dev)->gen < 6)
5853                 return;
5854
5855         gen6_suspend_rps(dev);
5856         dev_priv->rps.enabled = false;
5857 }
5858
5859 static void ibx_init_clock_gating(struct drm_device *dev)
5860 {
5861         struct drm_i915_private *dev_priv = dev->dev_private;
5862
5863         /*
5864          * On Ibex Peak and Cougar Point, we need to disable clock
5865          * gating for the panel power sequencer or it will fail to
5866          * start up when no ports are active.
5867          */
5868         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5869 }
5870
5871 static void g4x_disable_trickle_feed(struct drm_device *dev)
5872 {
5873         struct drm_i915_private *dev_priv = dev->dev_private;
5874         int pipe;
5875
5876         for_each_pipe(dev_priv, pipe) {
5877                 I915_WRITE(DSPCNTR(pipe),
5878                            I915_READ(DSPCNTR(pipe)) |
5879                            DISPPLANE_TRICKLE_FEED_DISABLE);
5880                 intel_flush_primary_plane(dev_priv, pipe);
5881         }
5882 }
5883
5884 static void ilk_init_lp_watermarks(struct drm_device *dev)
5885 {
5886         struct drm_i915_private *dev_priv = dev->dev_private;
5887
5888         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5889         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5890         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5891
5892         /*
5893          * Don't touch WM1S_LP_EN here.
5894          * Doing so could cause underruns.
5895          */
5896 }
5897
5898 static void ironlake_init_clock_gating(struct drm_device *dev)
5899 {
5900         struct drm_i915_private *dev_priv = dev->dev_private;
5901         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5902
5903         /*
5904          * Required for FBC
5905          * WaFbcDisableDpfcClockGating:ilk
5906          */
5907         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5908                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5909                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
5910
5911         I915_WRITE(PCH_3DCGDIS0,
5912                    MARIUNIT_CLOCK_GATE_DISABLE |
5913                    SVSMUNIT_CLOCK_GATE_DISABLE);
5914         I915_WRITE(PCH_3DCGDIS1,
5915                    VFMUNIT_CLOCK_GATE_DISABLE);
5916
5917         /*
5918          * According to the spec the following bits should be set in
5919          * order to enable memory self-refresh
5920          * The bit 22/21 of 0x42004
5921          * The bit 5 of 0x42020
5922          * The bit 15 of 0x45000
5923          */
5924         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5925                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
5926                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5927         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5928         I915_WRITE(DISP_ARB_CTL,
5929                    (I915_READ(DISP_ARB_CTL) |
5930                     DISP_FBC_WM_DIS));
5931
5932         ilk_init_lp_watermarks(dev);
5933
5934         /*
5935          * Based on the document from hardware guys the following bits
5936          * should be set unconditionally in order to enable FBC.
5937          * The bit 22 of 0x42000
5938          * The bit 22 of 0x42004
5939          * The bit 7,8,9 of 0x42020.
5940          */
5941         if (IS_IRONLAKE_M(dev)) {
5942                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5943                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5944                            I915_READ(ILK_DISPLAY_CHICKEN1) |
5945                            ILK_FBCQ_DIS);
5946                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5947                            I915_READ(ILK_DISPLAY_CHICKEN2) |
5948                            ILK_DPARB_GATE);
5949         }
5950
5951         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5952
5953         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5954                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5955                    ILK_ELPIN_409_SELECT);
5956         I915_WRITE(_3D_CHICKEN2,
5957                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5958                    _3D_CHICKEN2_WM_READ_PIPELINED);
5959
5960         /* WaDisableRenderCachePipelinedFlush:ilk */
5961         I915_WRITE(CACHE_MODE_0,
5962                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5963
5964         /* WaDisable_RenderCache_OperationalFlush:ilk */
5965         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5966
5967         g4x_disable_trickle_feed(dev);
5968
5969         ibx_init_clock_gating(dev);
5970 }
5971
5972 static void cpt_init_clock_gating(struct drm_device *dev)
5973 {
5974         struct drm_i915_private *dev_priv = dev->dev_private;
5975         int pipe;
5976         uint32_t val;
5977
5978         /*
5979          * On Ibex Peak and Cougar Point, we need to disable clock
5980          * gating for the panel power sequencer or it will fail to
5981          * start up when no ports are active.
5982          */
5983         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5984                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5985                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
5986         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5987                    DPLS_EDP_PPS_FIX_DIS);
5988         /* The below fixes the weird display corruption, a few pixels shifted
5989          * downward, on (only) LVDS of some HP laptops with IVY.
5990          */
5991         for_each_pipe(dev_priv, pipe) {
5992                 val = I915_READ(TRANS_CHICKEN2(pipe));
5993                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5994                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5995                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
5996                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5997                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5998                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5999                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6000                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6001         }
6002         /* WADP0ClockGatingDisable */
6003         for_each_pipe(dev_priv, pipe) {
6004                 I915_WRITE(TRANS_CHICKEN1(pipe),
6005                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6006         }
6007 }
6008
6009 static void gen6_check_mch_setup(struct drm_device *dev)
6010 {
6011         struct drm_i915_private *dev_priv = dev->dev_private;
6012         uint32_t tmp;
6013
6014         tmp = I915_READ(MCH_SSKPD);
6015         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6016                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6017                               tmp);
6018 }
6019
6020 static void gen6_init_clock_gating(struct drm_device *dev)
6021 {
6022         struct drm_i915_private *dev_priv = dev->dev_private;
6023         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6024
6025         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6026
6027         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6028                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6029                    ILK_ELPIN_409_SELECT);
6030
6031         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6032         I915_WRITE(_3D_CHICKEN,
6033                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6034
6035         /* WaDisable_RenderCache_OperationalFlush:snb */
6036         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6037
6038         /*
6039          * BSpec recoomends 8x4 when MSAA is used,
6040          * however in practice 16x4 seems fastest.
6041          *
6042          * Note that PS/WM thread counts depend on the WIZ hashing
6043          * disable bit, which we don't touch here, but it's good
6044          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6045          */
6046         I915_WRITE(GEN6_GT_MODE,
6047                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6048
6049         ilk_init_lp_watermarks(dev);
6050
6051         I915_WRITE(CACHE_MODE_0,
6052                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6053
6054         I915_WRITE(GEN6_UCGCTL1,
6055                    I915_READ(GEN6_UCGCTL1) |
6056                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6057                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6058
6059         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6060          * gating disable must be set.  Failure to set it results in
6061          * flickering pixels due to Z write ordering failures after
6062          * some amount of runtime in the Mesa "fire" demo, and Unigine
6063          * Sanctuary and Tropics, and apparently anything else with
6064          * alpha test or pixel discard.
6065          *
6066          * According to the spec, bit 11 (RCCUNIT) must also be set,
6067          * but we didn't debug actual testcases to find it out.
6068          *
6069          * WaDisableRCCUnitClockGating:snb
6070          * WaDisableRCPBUnitClockGating:snb
6071          */
6072         I915_WRITE(GEN6_UCGCTL2,
6073                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6074                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6075
6076         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6077         I915_WRITE(_3D_CHICKEN3,
6078                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6079
6080         /*
6081          * Bspec says:
6082          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6083          * 3DSTATE_SF number of SF output attributes is more than 16."
6084          */
6085         I915_WRITE(_3D_CHICKEN3,
6086                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6087
6088         /*
6089          * According to the spec the following bits should be
6090          * set in order to enable memory self-refresh and fbc:
6091          * The bit21 and bit22 of 0x42000
6092          * The bit21 and bit22 of 0x42004
6093          * The bit5 and bit7 of 0x42020
6094          * The bit14 of 0x70180
6095          * The bit14 of 0x71180
6096          *
6097          * WaFbcAsynchFlipDisableFbcQueue:snb
6098          */
6099         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6100                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6101                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6102         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6103                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6104                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6105         I915_WRITE(ILK_DSPCLK_GATE_D,
6106                    I915_READ(ILK_DSPCLK_GATE_D) |
6107                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6108                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6109
6110         g4x_disable_trickle_feed(dev);
6111
6112         cpt_init_clock_gating(dev);
6113
6114         gen6_check_mch_setup(dev);
6115 }
6116
6117 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6118 {
6119         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6120
6121         /*
6122          * WaVSThreadDispatchOverride:ivb,vlv
6123          *
6124          * This actually overrides the dispatch
6125          * mode for all thread types.
6126          */
6127         reg &= ~GEN7_FF_SCHED_MASK;
6128         reg |= GEN7_FF_TS_SCHED_HW;
6129         reg |= GEN7_FF_VS_SCHED_HW;
6130         reg |= GEN7_FF_DS_SCHED_HW;
6131
6132         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6133 }
6134
6135 static void lpt_init_clock_gating(struct drm_device *dev)
6136 {
6137         struct drm_i915_private *dev_priv = dev->dev_private;
6138
6139         /*
6140          * TODO: this bit should only be enabled when really needed, then
6141          * disabled when not needed anymore in order to save power.
6142          */
6143         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6144                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6145                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6146                            PCH_LP_PARTITION_LEVEL_DISABLE);
6147
6148         /* WADPOClockGatingDisable:hsw */
6149         I915_WRITE(_TRANSA_CHICKEN1,
6150                    I915_READ(_TRANSA_CHICKEN1) |
6151                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6152 }
6153
6154 static void lpt_suspend_hw(struct drm_device *dev)
6155 {
6156         struct drm_i915_private *dev_priv = dev->dev_private;
6157
6158         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6159                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6160
6161                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6162                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6163         }
6164 }
6165
6166 static void broadwell_init_clock_gating(struct drm_device *dev)
6167 {
6168         struct drm_i915_private *dev_priv = dev->dev_private;
6169         enum pipe pipe;
6170
6171         I915_WRITE(WM3_LP_ILK, 0);
6172         I915_WRITE(WM2_LP_ILK, 0);
6173         I915_WRITE(WM1_LP_ILK, 0);
6174
6175         /* WaSwitchSolVfFArbitrationPriority:bdw */
6176         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6177
6178         /* WaPsrDPAMaskVBlankInSRD:bdw */
6179         I915_WRITE(CHICKEN_PAR1_1,
6180                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6181
6182         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6183         for_each_pipe(dev_priv, pipe) {
6184                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6185                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6186                            BDW_DPRS_MASK_VBLANK_SRD);
6187         }
6188
6189         /* WaVSRefCountFullforceMissDisable:bdw */
6190         /* WaDSRefCountFullforceMissDisable:bdw */
6191         I915_WRITE(GEN7_FF_THREAD_MODE,
6192                    I915_READ(GEN7_FF_THREAD_MODE) &
6193                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6194
6195         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6196                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6197
6198         /* WaDisableSDEUnitClockGating:bdw */
6199         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6200                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6201
6202         lpt_init_clock_gating(dev);
6203 }
6204
6205 static void haswell_init_clock_gating(struct drm_device *dev)
6206 {
6207         struct drm_i915_private *dev_priv = dev->dev_private;
6208
6209         ilk_init_lp_watermarks(dev);
6210
6211         /* L3 caching of data atomics doesn't work -- disable it. */
6212         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6213         I915_WRITE(HSW_ROW_CHICKEN3,
6214                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6215
6216         /* This is required by WaCatErrorRejectionIssue:hsw */
6217         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6218                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6219                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6220
6221         /* WaVSRefCountFullforceMissDisable:hsw */
6222         I915_WRITE(GEN7_FF_THREAD_MODE,
6223                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6224
6225         /* WaDisable_RenderCache_OperationalFlush:hsw */
6226         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6227
6228         /* enable HiZ Raw Stall Optimization */
6229         I915_WRITE(CACHE_MODE_0_GEN7,
6230                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6231
6232         /* WaDisable4x2SubspanOptimization:hsw */
6233         I915_WRITE(CACHE_MODE_1,
6234                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6235
6236         /*
6237          * BSpec recommends 8x4 when MSAA is used,
6238          * however in practice 16x4 seems fastest.
6239          *
6240          * Note that PS/WM thread counts depend on the WIZ hashing
6241          * disable bit, which we don't touch here, but it's good
6242          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6243          */
6244         I915_WRITE(GEN7_GT_MODE,
6245                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6246
6247         /* WaSampleCChickenBitEnable:hsw */
6248         I915_WRITE(HALF_SLICE_CHICKEN3,
6249                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6250
6251         /* WaSwitchSolVfFArbitrationPriority:hsw */
6252         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6253
6254         /* WaRsPkgCStateDisplayPMReq:hsw */
6255         I915_WRITE(CHICKEN_PAR1_1,
6256                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6257
6258         lpt_init_clock_gating(dev);
6259 }
6260
6261 static void ivybridge_init_clock_gating(struct drm_device *dev)
6262 {
6263         struct drm_i915_private *dev_priv = dev->dev_private;
6264         uint32_t snpcr;
6265
6266         ilk_init_lp_watermarks(dev);
6267
6268         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6269
6270         /* WaDisableEarlyCull:ivb */
6271         I915_WRITE(_3D_CHICKEN3,
6272                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6273
6274         /* WaDisableBackToBackFlipFix:ivb */
6275         I915_WRITE(IVB_CHICKEN3,
6276                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6277                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6278
6279         /* WaDisablePSDDualDispatchEnable:ivb */
6280         if (IS_IVB_GT1(dev))
6281                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6282                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6283
6284         /* WaDisable_RenderCache_OperationalFlush:ivb */
6285         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6286
6287         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6288         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6289                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6290
6291         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6292         I915_WRITE(GEN7_L3CNTLREG1,
6293                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6294         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6295                    GEN7_WA_L3_CHICKEN_MODE);
6296         if (IS_IVB_GT1(dev))
6297                 I915_WRITE(GEN7_ROW_CHICKEN2,
6298                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6299         else {
6300                 /* must write both registers */
6301                 I915_WRITE(GEN7_ROW_CHICKEN2,
6302                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6303                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6304                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6305         }
6306
6307         /* WaForceL3Serialization:ivb */
6308         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6309                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6310
6311         /*
6312          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6313          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6314          */
6315         I915_WRITE(GEN6_UCGCTL2,
6316                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6317
6318         /* This is required by WaCatErrorRejectionIssue:ivb */
6319         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6320                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6321                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6322
6323         g4x_disable_trickle_feed(dev);
6324
6325         gen7_setup_fixed_func_scheduler(dev_priv);
6326
6327         if (0) { /* causes HiZ corruption on ivb:gt1 */
6328                 /* enable HiZ Raw Stall Optimization */
6329                 I915_WRITE(CACHE_MODE_0_GEN7,
6330                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6331         }
6332
6333         /* WaDisable4x2SubspanOptimization:ivb */
6334         I915_WRITE(CACHE_MODE_1,
6335                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6336
6337         /*
6338          * BSpec recommends 8x4 when MSAA is used,
6339          * however in practice 16x4 seems fastest.
6340          *
6341          * Note that PS/WM thread counts depend on the WIZ hashing
6342          * disable bit, which we don't touch here, but it's good
6343          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6344          */
6345         I915_WRITE(GEN7_GT_MODE,
6346                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6347
6348         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6349         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6350         snpcr |= GEN6_MBC_SNPCR_MED;
6351         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6352
6353         if (!HAS_PCH_NOP(dev))
6354                 cpt_init_clock_gating(dev);
6355
6356         gen6_check_mch_setup(dev);
6357 }
6358
6359 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6360 {
6361         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6362
6363         /*
6364          * Disable trickle feed and enable pnd deadline calculation
6365          */
6366         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6367         I915_WRITE(CBR1_VLV, 0);
6368 }
6369
6370 static void valleyview_init_clock_gating(struct drm_device *dev)
6371 {
6372         struct drm_i915_private *dev_priv = dev->dev_private;
6373
6374         vlv_init_display_clock_gating(dev_priv);
6375
6376         /* WaDisableEarlyCull:vlv */
6377         I915_WRITE(_3D_CHICKEN3,
6378                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6379
6380         /* WaDisableBackToBackFlipFix:vlv */
6381         I915_WRITE(IVB_CHICKEN3,
6382                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6383                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6384
6385         /* WaPsdDispatchEnable:vlv */
6386         /* WaDisablePSDDualDispatchEnable:vlv */
6387         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6388                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6389                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6390
6391         /* WaDisable_RenderCache_OperationalFlush:vlv */
6392         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6393
6394         /* WaForceL3Serialization:vlv */
6395         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6396                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6397
6398         /* WaDisableDopClockGating:vlv */
6399         I915_WRITE(GEN7_ROW_CHICKEN2,
6400                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6401
6402         /* This is required by WaCatErrorRejectionIssue:vlv */
6403         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6404                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6405                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6406
6407         gen7_setup_fixed_func_scheduler(dev_priv);
6408
6409         /*
6410          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6411          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6412          */
6413         I915_WRITE(GEN6_UCGCTL2,
6414                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6415
6416         /* WaDisableL3Bank2xClockGate:vlv
6417          * Disabling L3 clock gating- MMIO 940c[25] = 1
6418          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6419         I915_WRITE(GEN7_UCGCTL4,
6420                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6421
6422         /*
6423          * BSpec says this must be set, even though
6424          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6425          */
6426         I915_WRITE(CACHE_MODE_1,
6427                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6428
6429         /*
6430          * BSpec recommends 8x4 when MSAA is used,
6431          * however in practice 16x4 seems fastest.
6432          *
6433          * Note that PS/WM thread counts depend on the WIZ hashing
6434          * disable bit, which we don't touch here, but it's good
6435          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6436          */
6437         I915_WRITE(GEN7_GT_MODE,
6438                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6439
6440         /*
6441          * WaIncreaseL3CreditsForVLVB0:vlv
6442          * This is the hardware default actually.
6443          */
6444         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6445
6446         /*
6447          * WaDisableVLVClockGating_VBIIssue:vlv
6448          * Disable clock gating on th GCFG unit to prevent a delay
6449          * in the reporting of vblank events.
6450          */
6451         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6452 }
6453
6454 static void cherryview_init_clock_gating(struct drm_device *dev)
6455 {
6456         struct drm_i915_private *dev_priv = dev->dev_private;
6457
6458         vlv_init_display_clock_gating(dev_priv);
6459
6460         /* WaVSRefCountFullforceMissDisable:chv */
6461         /* WaDSRefCountFullforceMissDisable:chv */
6462         I915_WRITE(GEN7_FF_THREAD_MODE,
6463                    I915_READ(GEN7_FF_THREAD_MODE) &
6464                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6465
6466         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6467         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6468                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6469
6470         /* WaDisableCSUnitClockGating:chv */
6471         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6472                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6473
6474         /* WaDisableSDEUnitClockGating:chv */
6475         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6476                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6477 }
6478
6479 static void g4x_init_clock_gating(struct drm_device *dev)
6480 {
6481         struct drm_i915_private *dev_priv = dev->dev_private;
6482         uint32_t dspclk_gate;
6483
6484         I915_WRITE(RENCLK_GATE_D1, 0);
6485         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6486                    GS_UNIT_CLOCK_GATE_DISABLE |
6487                    CL_UNIT_CLOCK_GATE_DISABLE);
6488         I915_WRITE(RAMCLK_GATE_D, 0);
6489         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6490                 OVRUNIT_CLOCK_GATE_DISABLE |
6491                 OVCUNIT_CLOCK_GATE_DISABLE;
6492         if (IS_GM45(dev))
6493                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6494         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6495
6496         /* WaDisableRenderCachePipelinedFlush */
6497         I915_WRITE(CACHE_MODE_0,
6498                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6499
6500         /* WaDisable_RenderCache_OperationalFlush:g4x */
6501         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6502
6503         g4x_disable_trickle_feed(dev);
6504 }
6505
6506 static void crestline_init_clock_gating(struct drm_device *dev)
6507 {
6508         struct drm_i915_private *dev_priv = dev->dev_private;
6509
6510         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6511         I915_WRITE(RENCLK_GATE_D2, 0);
6512         I915_WRITE(DSPCLK_GATE_D, 0);
6513         I915_WRITE(RAMCLK_GATE_D, 0);
6514         I915_WRITE16(DEUC, 0);
6515         I915_WRITE(MI_ARB_STATE,
6516                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6517
6518         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6519         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6520 }
6521
6522 static void broadwater_init_clock_gating(struct drm_device *dev)
6523 {
6524         struct drm_i915_private *dev_priv = dev->dev_private;
6525
6526         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6527                    I965_RCC_CLOCK_GATE_DISABLE |
6528                    I965_RCPB_CLOCK_GATE_DISABLE |
6529                    I965_ISC_CLOCK_GATE_DISABLE |
6530                    I965_FBC_CLOCK_GATE_DISABLE);
6531         I915_WRITE(RENCLK_GATE_D2, 0);
6532         I915_WRITE(MI_ARB_STATE,
6533                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6534
6535         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6536         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6537 }
6538
6539 static void gen3_init_clock_gating(struct drm_device *dev)
6540 {
6541         struct drm_i915_private *dev_priv = dev->dev_private;
6542         u32 dstate = I915_READ(D_STATE);
6543
6544         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6545                 DSTATE_DOT_CLOCK_GATING;
6546         I915_WRITE(D_STATE, dstate);
6547
6548         if (IS_PINEVIEW(dev))
6549                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6550
6551         /* IIR "flip pending" means done if this bit is set */
6552         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6553
6554         /* interrupts should cause a wake up from C3 */
6555         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6556
6557         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6558         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6559
6560         I915_WRITE(MI_ARB_STATE,
6561                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6562 }
6563
6564 static void i85x_init_clock_gating(struct drm_device *dev)
6565 {
6566         struct drm_i915_private *dev_priv = dev->dev_private;
6567
6568         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6569
6570         /* interrupts should cause a wake up from C3 */
6571         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6572                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6573
6574         I915_WRITE(MEM_MODE,
6575                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6576 }
6577
6578 static void i830_init_clock_gating(struct drm_device *dev)
6579 {
6580         struct drm_i915_private *dev_priv = dev->dev_private;
6581
6582         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6583
6584         I915_WRITE(MEM_MODE,
6585                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6586                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6587 }
6588
6589 void intel_init_clock_gating(struct drm_device *dev)
6590 {
6591         struct drm_i915_private *dev_priv = dev->dev_private;
6592
6593         if (dev_priv->display.init_clock_gating)
6594                 dev_priv->display.init_clock_gating(dev);
6595 }
6596
6597 void intel_suspend_hw(struct drm_device *dev)
6598 {
6599         if (HAS_PCH_LPT(dev))
6600                 lpt_suspend_hw(dev);
6601 }
6602
6603 /* Set up chip specific power management-related functions */
6604 void intel_init_pm(struct drm_device *dev)
6605 {
6606         struct drm_i915_private *dev_priv = dev->dev_private;
6607
6608         intel_fbc_init(dev_priv);
6609
6610         /* For cxsr */
6611         if (IS_PINEVIEW(dev))
6612                 i915_pineview_get_mem_freq(dev);
6613         else if (IS_GEN5(dev))
6614                 i915_ironlake_get_mem_freq(dev);
6615
6616         /* For FIFO watermark updates */
6617         if (INTEL_INFO(dev)->gen >= 9) {
6618                 skl_setup_wm_latency(dev);
6619
6620                 if (IS_BROXTON(dev))
6621                         dev_priv->display.init_clock_gating =
6622                                 bxt_init_clock_gating;
6623                 else if (IS_SKYLAKE(dev))
6624                         dev_priv->display.init_clock_gating =
6625                                 skl_init_clock_gating;
6626                 dev_priv->display.update_wm = skl_update_wm;
6627                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
6628         } else if (HAS_PCH_SPLIT(dev)) {
6629                 ilk_setup_wm_latency(dev);
6630
6631                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6632                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6633                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6634                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6635                         dev_priv->display.update_wm = ilk_update_wm;
6636                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6637                 } else {
6638                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6639                                       "Disable CxSR\n");
6640                 }
6641
6642                 if (IS_GEN5(dev))
6643                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6644                 else if (IS_GEN6(dev))
6645                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6646                 else if (IS_IVYBRIDGE(dev))
6647                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6648                 else if (IS_HASWELL(dev))
6649                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6650                 else if (INTEL_INFO(dev)->gen == 8)
6651                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
6652         } else if (IS_CHERRYVIEW(dev)) {
6653                 dev_priv->display.update_wm = valleyview_update_wm;
6654                 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6655                 dev_priv->display.init_clock_gating =
6656                         cherryview_init_clock_gating;
6657         } else if (IS_VALLEYVIEW(dev)) {
6658                 dev_priv->display.update_wm = valleyview_update_wm;
6659                 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
6660                 dev_priv->display.init_clock_gating =
6661                         valleyview_init_clock_gating;
6662         } else if (IS_PINEVIEW(dev)) {
6663                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6664                                             dev_priv->is_ddr3,
6665                                             dev_priv->fsb_freq,
6666                                             dev_priv->mem_freq)) {
6667                         DRM_INFO("failed to find known CxSR latency "
6668                                  "(found ddr%s fsb freq %d, mem freq %d), "
6669                                  "disabling CxSR\n",
6670                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6671                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6672                         /* Disable CxSR and never update its watermark again */
6673                         intel_set_memory_cxsr(dev_priv, false);
6674                         dev_priv->display.update_wm = NULL;
6675                 } else
6676                         dev_priv->display.update_wm = pineview_update_wm;
6677                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6678         } else if (IS_G4X(dev)) {
6679                 dev_priv->display.update_wm = g4x_update_wm;
6680                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6681         } else if (IS_GEN4(dev)) {
6682                 dev_priv->display.update_wm = i965_update_wm;
6683                 if (IS_CRESTLINE(dev))
6684                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6685                 else if (IS_BROADWATER(dev))
6686                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6687         } else if (IS_GEN3(dev)) {
6688                 dev_priv->display.update_wm = i9xx_update_wm;
6689                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6690                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6691         } else if (IS_GEN2(dev)) {
6692                 if (INTEL_INFO(dev)->num_pipes == 1) {
6693                         dev_priv->display.update_wm = i845_update_wm;
6694                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6695                 } else {
6696                         dev_priv->display.update_wm = i9xx_update_wm;
6697                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6698                 }
6699
6700                 if (IS_I85X(dev) || IS_I865G(dev))
6701                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6702                 else
6703                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
6704         } else {
6705                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6706         }
6707 }
6708
6709 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
6710 {
6711         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6712
6713         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6714                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6715                 return -EAGAIN;
6716         }
6717
6718         I915_WRITE(GEN6_PCODE_DATA, *val);
6719         I915_WRITE(GEN6_PCODE_DATA1, 0);
6720         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6721
6722         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6723                      500)) {
6724                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6725                 return -ETIMEDOUT;
6726         }
6727
6728         *val = I915_READ(GEN6_PCODE_DATA);
6729         I915_WRITE(GEN6_PCODE_DATA, 0);
6730
6731         return 0;
6732 }
6733
6734 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
6735 {
6736         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6737
6738         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6739                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6740                 return -EAGAIN;
6741         }
6742
6743         I915_WRITE(GEN6_PCODE_DATA, val);
6744         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6745
6746         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6747                      500)) {
6748                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6749                 return -ETIMEDOUT;
6750         }
6751
6752         I915_WRITE(GEN6_PCODE_DATA, 0);
6753
6754         return 0;
6755 }
6756
6757 static int vlv_gpu_freq_div(unsigned int czclk_freq)
6758 {
6759         switch (czclk_freq) {
6760         case 200:
6761                 return 10;
6762         case 267:
6763                 return 12;
6764         case 320:
6765         case 333:
6766                 return 16;
6767         case 400:
6768                 return 20;
6769         default:
6770                 return -1;
6771         }
6772 }
6773
6774 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6775 {
6776         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6777
6778         div = vlv_gpu_freq_div(czclk_freq);
6779         if (div < 0)
6780                 return div;
6781
6782         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
6783 }
6784
6785 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
6786 {
6787         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6788
6789         mul = vlv_gpu_freq_div(czclk_freq);
6790         if (mul < 0)
6791                 return mul;
6792
6793         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
6794 }
6795
6796 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6797 {
6798         int div, czclk_freq = dev_priv->rps.cz_freq;
6799
6800         div = vlv_gpu_freq_div(czclk_freq) / 2;
6801         if (div < 0)
6802                 return div;
6803
6804         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
6805 }
6806
6807 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6808 {
6809         int mul, czclk_freq = dev_priv->rps.cz_freq;
6810
6811         mul = vlv_gpu_freq_div(czclk_freq) / 2;
6812         if (mul < 0)
6813                 return mul;
6814
6815         /* CHV needs even values */
6816         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
6817 }
6818
6819 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
6820 {
6821         if (IS_GEN9(dev_priv->dev))
6822                 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6823         else if (IS_CHERRYVIEW(dev_priv->dev))
6824                 return chv_gpu_freq(dev_priv, val);
6825         else if (IS_VALLEYVIEW(dev_priv->dev))
6826                 return byt_gpu_freq(dev_priv, val);
6827         else
6828                 return val * GT_FREQUENCY_MULTIPLIER;
6829 }
6830
6831 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6832 {
6833         if (IS_GEN9(dev_priv->dev))
6834                 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6835         else if (IS_CHERRYVIEW(dev_priv->dev))
6836                 return chv_freq_opcode(dev_priv, val);
6837         else if (IS_VALLEYVIEW(dev_priv->dev))
6838                 return byt_freq_opcode(dev_priv, val);
6839         else
6840                 return val / GT_FREQUENCY_MULTIPLIER;
6841 }
6842
6843 struct request_boost {
6844         struct work_struct work;
6845         struct drm_i915_gem_request *req;
6846 };
6847
6848 static void __intel_rps_boost_work(struct work_struct *work)
6849 {
6850         struct request_boost *boost = container_of(work, struct request_boost, work);
6851
6852         if (!i915_gem_request_completed(boost->req, true))
6853                 gen6_rps_boost(to_i915(boost->req->ring->dev), NULL);
6854
6855         i915_gem_request_unreference__unlocked(boost->req);
6856         kfree(boost);
6857 }
6858
6859 void intel_queue_rps_boost_for_request(struct drm_device *dev,
6860                                        struct drm_i915_gem_request *req)
6861 {
6862         struct request_boost *boost;
6863
6864         if (req == NULL || INTEL_INFO(dev)->gen < 6)
6865                 return;
6866
6867         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
6868         if (boost == NULL)
6869                 return;
6870
6871         i915_gem_request_reference(req);
6872         boost->req = req;
6873
6874         INIT_WORK(&boost->work, __intel_rps_boost_work);
6875         queue_work(to_i915(dev)->wq, &boost->work);
6876 }
6877
6878 void intel_pm_setup(struct drm_device *dev)
6879 {
6880         struct drm_i915_private *dev_priv = dev->dev_private;
6881
6882         mutex_init(&dev_priv->rps.hw_lock);
6883
6884         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6885                           intel_gen6_powersave_work);
6886         INIT_LIST_HEAD(&dev_priv->rps.clients);
6887         INIT_LIST_HEAD(&dev_priv->rps.semaphores.rps_boost);
6888         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.rps_boost);
6889
6890         dev_priv->pm.suspended = false;
6891 }